Decoding method, system-on-chip and decoding device comprising system-on-chip

Abstract

The invention discloses a decoding method, a system-on-chip and a decoding device comprising the system-on-chip. The decoding method includes reading first input data including information about a first encoded bitstream buffer address from an input data buffer, reading first DPB data including information about a first DPB address from a DPB data buffer, a first decoded picture is generated by decoding the first encoded bitstream stored in the first encoded bitstream buffer address, and the first decoded picture is stored in the first DPB address.

Description

[0001] This application claims the priority and benefit of Korean Patent Application No. 10-2023-0169865, filed with the Korean Intellectual Property Office on November 29, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a decoding method, a system-on-chip, and a decoding apparatus including the system-on-chip. Background Art

[0003] Electronic devices (such as smartphones, tablet PCs, laptop computers, desktop computers, and digital cameras) may be equipped with digital video functions. These electronic devices may effectively transmit, receive, encode, decode, and / or store digital video information by implementing video compression techniques.

[0004] As the demand for high-definition video increases, electronic devices need to process a large amount of digital video information. Since encoding or decoding digital video information takes a long time, research is being conducted to reduce latency. Summary of the Invention

[0005] The present disclosure will provide a decoding method, a system-on-chip, and a decoding apparatus including the system-on-chip that can store multiple decoded pictures with limited interruption or no interruption.

[0006] The present disclosure will provide a decoding method, a system-on-chip, and a decoding apparatus including the system-on-chip having reduced decoding latency.

[0007] A decoding method according to some example embodiments for solving technical challenges includes: reading first input data including information about a first coded bitstream buffer address from an input data buffer, reading first DPB data including information about a first DPB address from a DPB data buffer, generating a first decoded picture by decoding a first coded bitstream stored at the first coded bitstream buffer address, and storing the first decoded picture at the first DPB address.

[0008] A system-on-chip according to some example embodiments includes: a processor configured to write first input data including information about a first coded bitstream buffer address into an input data buffer and write first DPB data including information about a first DPB address into a DPB data buffer; and a codec configured to read the first input data from the input data buffer, read the first DPB data from the DPB data buffer, generate a first decoded picture by decoding a first coded bitstream stored at the first coded bitstream buffer address, and store the first decoded picture at the first DPB address.

[0009] A decoding apparatus according to some example embodiments includes: a working memory including: an encoded bitstream buffer configured to store a plurality of encoded bitstreams; an input data buffer configured to store a plurality of input data including information about addresses of the plurality of encoded bitstream buffers; a decoded picture buffer (DPB) configured to store a plurality of decoded pictures; and a DPB data buffer configured to store a plurality of DPB data including information about addresses of the plurality of DPBs; and a system-on-chip configured to: read first input data including information about a first encoded bitstream buffer address from the input data buffer, read first DPB data including information about a first DPB address from the DPB data buffer, read a first encoded bitstream stored at the first encoded bitstream buffer address, generate a first decoded picture by decoding the first encoded bitstream, and store the first decoded picture at the first DPB address of the decoded picture buffer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram of a video encoding apparatus including a system-on-chip according to some example embodiments.

[0011] Figure 2 is a block diagram showing a codec according to some example embodiments.

[0012] Figure 3 is a diagram showing a working memory according to a comparative example.

[0013] Figure 4 is a diagram showing an input data buffer of a working memory according to a comparative example.

[0014] Figure 5 is a flowchart showing a decoding method according to a comparative example.

[0015] Figure 6 is a diagram showing a working memory according to some example embodiments.

[0016] Figure 7 is a diagram showing a decoded picture buffer (DPB) data buffer of a working memory according to some example embodiments.

[0017] Figure 8 is a flowchart showing a decoding method according to some example embodiments.

[0018] Figure 9 is a flowchart showing a method of using DPB data in a DPB data buffer according to some example embodiments.

[0019] Figure 10 is a diagram showing a DPB and a DPB data buffer according to some example embodiments.

[0020] Figure 11 is a flowchart showing a method of updating DPB data in a DPB data buffer according to some example embodiments.

[0021] Figure 12 is a diagram showing a DPB and a DPB data buffer according to some example embodiments.

[0022] Figure 13 is a flowchart showing a decoding method according to some example embodiments. Detailed Description

[0023] In the following detailed description, some example embodiments of the present invention are shown and described only by way of example. As those skilled in the art will recognize, the described example embodiments can be modified in various different ways without departing from the spirit or scope of the present invention.

[0024] Therefore, the drawings and embodiments are considered to be exemplary rather than restrictive in nature. Throughout the specification, the same reference numerals denote the same elements. In the flowcharts described with reference to the drawings, the order of operations can be changed, and several operations can be combined, and operations can be divided, and some operations may not be performed.

[0025] In addition, unless an explicit expression such as "a", "an", or "single" is used, expressions written in the singular form can be understood as the singular form or the plural form. Terms including ordinal numbers (such as, first and second) are used to describe various constituent elements, but the constituent elements are not limited by the terms. The terms are only used to distinguish one constituent element from other constituent elements.

[0026] Figure 1 is a block diagram of a video encoding device including a system on a chip according to some example embodiments.

[0027] Referring to Figure 1 , the video encoding device 100 can be implemented as a TV, a digital TV (DTV), an Internet protocol TV (IPTV), a set-top box, a personal computer (PC), a laptop computer, a desktop computer, a computer workstation, a smart phone, a tablet PC, a digital camera, a video game platform (or a video game console), a server, etc. The video encoding device 100 can represent various devices capable of processing two-dimensional (2D) or 3D graphic data and displaying the processed data.

[0028] The video encoding device 100 may include a system on a chip (SoC) 110, a video source 120, a display 130, an input device 140, a working memory 150, and a storage device 160.

[0029] The video source 120 may be implemented as a camera equipped with a CCD or CMOS image sensor. The video source 120 may capture a subject, generate data regarding the subject, and provide the generated data to the SoC 110.

[0030] The SoC 110 may control the overall operation of the video encoding device 100. For example, the SoC 110 may include an integrated circuit (IC), a motherboard, an application processor (AP), or a mobile AP. The SoC 110 may process the data output from the video source 120 and display the processed data through the display 130, store the processed data in the storage device 160, or send the processed data to another data processing system. The data output from the video source 120 may be sent to the preprocessing circuit 111 via an interface (e.g., a Mobile Industry Processor Interface (MIPI) Camera Serial Interface (CSI)).

[0031] The SoC 110 may include a preprocessing circuit 111, a codec 112, a processor 113, a modem 114, a display controller 115, a user interface (I / F) 116, a memory controller 117, a memory interface 118, and a bus 119.

[0032] The codec 112, the processor 113, the modem 114, the display controller 115, the user interface 116, the memory controller 117, and the memory interface 118 may send data to and receive data from each other via the bus 119. For example, the bus 119 may be implemented using at least one selected from a Peripheral Component Interconnect bus (PCI bus), a PCI Express (PCle) bus, an Advanced Microcontroller Bus Architecture (AMBA), an Advanced High-Performance Bus (AHB), an Advanced Peripheral Bus (APB), an Advanced eXtensible Interface (AXI) bus, and combinations thereof, but is not limited thereto.

[0033] The preprocessing circuit 111 may receive the data output from the video source 120. The preprocessing circuit 111 may process the received data and output the processed data to the codec 112. The preprocessing circuit 111 may be implemented as, for example, an Image Signal Processor (ISP). In Figure 1 it is shown that the preprocessing circuit 111 is implemented inside the SoC 110; however, the preprocessing circuit 111 may be implemented outside the SoC 110.

[0034] The codec 112 may perform an encoding (or encrypting) operation on the data processed by the preprocessing circuit 111. The codec 112 may perform a decoding (or decrypting) operation on the data provided from the processor 113 or stored in the working memory 150. The encoding operation and the decoding operation may use encoding techniques and decoding techniques (such as, Joint Photographic Experts Group (JPEG), Moving Picture Experts Group (MPEG), MPEG-2, MPEG-4, VC-1, VP9, AV1, H.264, H.265, High Efficiency Video Coding, etc.), but are not limited thereto. The codec 112 may be implemented as a hardware codec or a software codec.

[0035] In some example embodiments, the codec 112 may read each of the input data from the working memory 150 to read the data stored in the working memory 150 (e.g., the encoded bitstream of video data) and the DPB data on the decoding picture buffer (DPB). The codec 112 may decode the encoded bitstream and store the decoded picture in the DPB in the working memory 150 indicated by the DPB data. The codec 112 may store the decoded picture in the DPB indicated by the DPB data by referring to the flag data corresponding to the DPB data. For example, when the flag data of the DPB data is a first value (e.g., “0”), the codec 112 may not store the decoded picture in the DPB indicated by the DPB data. The codec 112 may wait until the flag data of the DPB data is changed to a second value different from the first value (e.g., “1”). When the flag data of the DPB data is the second value, the codec 112 may store the decoded picture in the first DPB indicated by the DPB data. In other example embodiments, the value “1” may be referred to as the first value, and the value “0” may be referred to as the second value.

[0036] The processor 113 may control the operation of the SoC 110. The processor may execute software (application programs, operating systems, and / or device drivers). The processor 113 may execute the operating system (OS) 151 loaded in the working memory 150. The processor 113 may execute various application programs to be run on the operating system (OS). The processor 113 may be set as a homogeneous multi-core processor or a heterogeneous multi-core processor.

[0037] The modem 114 may output the data encoded by the codec 112 or the processor 113 to the outside using wireless communication technology. The modem 114 may be configured as a unidirectional communication interface or a bidirectional communication interface, and may be configured to, for example, send and receive messages for establishing a connection and check and exchange any other information related to data transmission (such as, transmission of a communication link and / or encoded data).

[0038] The display controller 115 may send the data output from the codec 112 or the processor 113 to the display 130. The display controller 115 may send the data to the display 130 via a Mobile Industry Processor Interface (MIPI) Display Serial Interface (DSI). The display 130 may be or include any type of display configured to present decoded pictures (such as, an integrated display or an external display or monitor). For example, the display may include a liquid crystal display (LCD), an organic light emitting diode (OLED) display, a plasma display, a projector, a micro LED display, liquid crystal on silicon (LCoS), a digital light processor (DLP), or any other type of display.

[0039] The input device 140 may receive user input entered by a user and send an input signal as a response to the user manipulation to the user interface 116. The input device 140 may be implemented as a touch panel, a touch screen, a voice recognizer, a stylus, a keyboard, a mouse, a track point, etc., but is not limited thereto. For example, when the input device 140 is a touch screen, the input device 140 may include a touch panel and a touch panel controller. In addition, when the input device 140 is a voice recognizer, the input device 140 may include a voice recognition sensor and a voice recognition controller. The input device 140 may be connected to the display 130 and may also be implemented separately from the display 130.

[0040] The user interface 116 may receive the input signal from the input device 140 and send the data generated by the input manipulation to the processor 113.

[0041] The memory controller 117 may read the data stored in the working memory 150 under the control of the codec 112 or the processor 113 and send the read data to the codec 112 or the processor 113. In addition, the memory controller 117 may write the data output from the codec 112 or the processor 113 into the working memory 150 under the control of the codec 112 or the processor 113.

[0042] The working memory 150 may receive and store the data encoded and / or decoded by the codec 112. In addition, the working memory 150 may send the data stored in the working memory 150 to the processor 113 or the modem 114. In some example embodiments, the input data and the DPB data may be stored in different memory regions in the working memory 150. In other words, at least one input data may be stored in a region including consecutive addresses in the working memory 150, and at least one DPB data may be stored in another region including consecutive addresses. One region and the other region may be arranged non - consecutively in the working memory 150.

[0043] The working memory 150 can be implemented as a volatile memory. The volatile memory can be implemented as a random access memory (RAM), a static RAM (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), a thyristor RAM (T-RAM), a zero-capacitor RAM (Z-RAM), or a two-transistor RAM (TTRAM).

[0044] The memory interface 118 accesses the storage device 160 in response to a request from the processor 113. In other words, the memory interface 118 provides an interface between the system-on-chip (SoC) and the storage device 160. For example, data processed by the processor 113 is stored in the storage device 160 via the memory interface 118. As another example, data stored in the storage device 160 can be provided to the processor 113 via the memory interface 118.

[0045] The storage device 160 can be set as the storage medium of the video encoding device 100. The storage device 160 can store user data, an OS image, application programs, etc. The storage device 160 can be implemented as a non-volatile memory.

[0046] The non-volatile memory can be implemented as an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic RAM (MRAM), a spin-transfer torque MRAM, a ferroelectric RAM (FeRAM), a phase-change RAM (PRAM), or a resistive RAM (RRAM). Optionally, the non-volatile memory can be implemented as a multimedia card (MMC), an embedded MMC (eMMC), a universal flash storage (UFS), a solid-state drive or a solid-state disk (SSD), a USB flash drive, or a hard disk drive (HDD).

[0047] Figure 2 is a block diagram showing a codec according to some example embodiments.

[0048] Referring to Figure 2 , the codec 200 can restore an encoded bitstream to a decoded picture by decoding, and encode the picture to generate an encoded bitstream. The codec 200 can include a codec memory 210 and a processing unit 220.

[0049] The codec memory 210 may be a write buffer or a read buffer connected to temporarily store data input to the codec 200. The codec memory 210 may be configured to store various information required for the operation of the codec 200. For example, the codec memory 210 may store software, firmware, and / or information related to encoding operations and decoding operations. In some example embodiments, the codec memory 210 may be SRAM; however, the scope of the present invention is not limited thereto, and the codec memory 210 may be implemented as various types of memory devices (such as, DRAM, MRAM, or PRAM). In Figure 2 the figures, for simplicity of illustration and ease of explanation, the codec memory 210 is shown as being included in the codec 200; however, the scope of the present invention is not limited thereto. The codec memory 210 may be located outside the codec 200, and the codec 200 may communicate with the buffer memory via a separate communication channel or interface.

[0050] The codec memory 210 may include a count register 211. The count register 211 may include a first count register that is referenced to read input data, a second count register that indicates an index of the processing of the input data that has been completed, and a third count register that is referenced to store output data. In some example embodiments, when writing input data to the working memory, the count value of the first count register may be incremented. For example, the processor 113 may store the input data in the working memory 150 and change the value of the first count register of the codec 200. The codec 200 may determine an address in the working memory 150 with reference to the count value of the first count register and read the input data stored at the determined address. In addition, in some example embodiments, the second count register may count the number of input data that have been decoded. In some example embodiments, the third count register may count the number of decoding times. When the codec 200 finishes decoding the encoded bitstream, the third count register may increment the number of decoding times. The codec 200 may refer to the count value of the third count register to determine an address in the working memory 150 and write the output data related to the decoded picture to the determined address.

[0051] Firmware (FW) 212 can be loaded into codec memory 210. Firmware 212 can send the preprocessed picture data and the encoded bitstream to codec processing unit 220. For example, when codec 200 receives an interrupt signal from processor 113, firmware 212 can read the input data stored in working memory 150 through processor 113. Firmware 212 can send the encoded bitstream read based on the input data to codec processing unit 220. In some example embodiments, firmware 212 can read DPB data with reference to the flag data of the DPB data, and can use or not use the DPB indicated by the DPB data. Firmware 212 can change the value of the flag data of the DPB data indicating the used DPB. For example, when the flag data of the DPB data is a second value, firmware 212 can store the decoded picture in the DPB indicated by the DPB data. If the DPB indicated by the DPB data is used, firmware 212 can change the flag data of the DPB data from the second value to the first value. When the flag data of the DPB data is the first value, firmware 212 can not use the DPB indicated by the DPB data. Firmware 212 can use a read pointer to read the DPB data. The read pointer can sequentially indicate a DPB area including multiple DPB data in working memory 150. The read pointer can cyclically indicate a DPB area including multiple DPB data in working memory 150.

[0052] Codec memory 210 can include special function registers (SFRs). The special function registers can be used to decode the encoded bitstream in an interlaced scanning manner.

[0053] Processing unit 220 can include a decoder (DEC) 221 that decodes the encoded bitstream received from firmware 212, and an encoder (ENC) 222 that encodes the preprocessed picture data.

[0054] Decoder 221 can receive the encoded bitstream and provide the decoded picture. Encoder 222 (also referred to as a video encoder) can receive the preprocessed picture data, process the preprocessed picture data, and provide the encoded bitstream.

[0055] Each of decoder 221 and encoder 222 can be implemented using various suitable circuits (e.g., one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, hardware, or any combination thereof). If the technology is implemented partially using software, the device can store the software instructions in a suitable non-transitory computer-readable storage medium and use hardware (such as one or more processors) to execute the instructions to perform the techniques of the present disclosure. Any of the above (including hardware, software, combinations of hardware and software, etc.) can be considered as one or more processors.

[0056] Figure 3 is a diagram showing a working memory according to a comparative example.

[0057] Refer to Figure 3 , the working memory 300 may include a plurality of buffer regions (e.g., a first region 310, a second region 320, a third region 330, and a fourth region 340). In the first region 310, an encoded bitstream may be stored. In the second region 320, input data may be stored. In the third region 330, output data may be stored. In the fourth region 340, decoded pictures may be stored. The first to fourth regions 310, 320, 330, and 340 may be arranged discontinuously in the working memory 300, and the sizes of the respective regions may be set differently. Hereinafter, the first to fourth regions 310, 320, 330, and 340 will be referred to as an encoded bitstream buffer, an input data buffer, an output data buffer, and a decoded picture buffer, respectively.

[0058] In some example embodiments, the operating system 151 may allocate an address range from ADDR10 to ADDR1n in the working memory 300 as the first region 310, an address range from ADDR20 to ADDR2m as the second region 320, an address range from ADDR30 to ADDR3p as the third region 330, and an address range from ADDR40 to ADDR4q as the fourth region 340. The first region 310 may include a plurality of encoded bitstream buffer regions in the address range from ADDR10 to ADDR1n. The second region 320 may include a plurality of input data buffer regions in the address range from ADDR20 to ADDR2m. The third region 330 may include a plurality of output data buffer regions in the address range from ADDR30 to ADDR3p. The fourth region 340 may include a plurality of DPB regions in the address range from ADDR40 to ADDR40. Here, n, m, p, and q may be any natural numbers greater than 0 (e.g., 5, 10, 15, etc. simultaneously or respectively).

[0059] Figure 4 is a diagram showing an input data buffer of a working memory according to a comparative example.

[0060] Refer to Figure 4, the input data buffer 400 may include multiple input data 410. One input data 410a may contain information about the coded bitstream buffer address 411, the frame data size 412, and the DPB address 413. The input data 410 may be generated by the processor 113. When the operating system 151 allocates the DPB for storing the coded bitstream data to the processor 113, the processor may generate the input data 410 including the information about the DPB address 413 indicating the allocated DPB.

[0061] Figure 5 is a flowchart showing a decoding method of a comparative example.

[0062] Referring to Figures 1 to 5 , the operating system 151 allocates multiple buffer areas 310, 320, 330, and 340 in the working memory 300 and notifies the processor 113 of the information about the multiple buffer areas 310, 320, 330, and 340 (S500). For example, the operating system 151 may notify the processor 113 of the information about the addresses of the multiple buffer areas and the size of each area. The processor 113 may send the information about the multiple buffer areas 310, 320, 330, and 340 to the codec 112.

[0063] The processor 113 stores the input data including the DPB address in the working memory 150 (S510 to S513). The processor 113 may generate the input data including the address where the coded bitstream has been stored in the coded bitstream buffer, the size of the coded bitstream, and the DPB address. For example, in response to multiple coded bitstreams, the processor 113 may generate the input data including the DPB address 0, the DPB address 1, the DPB address 2, and the DPB address 3, respectively. The processor 113 may store the input data generated in response to the multiple coded bitstreams in the input data buffer in the working memory 150.

[0064] If an input data item is stored, the processor 113 sends an interrupt signal INTERRUPT H0 to the codec 112 (S514). The processor 113 may send the interrupt signal INTERRUPT H0 whenever the storage of the input data is completed or when the storage of a predetermined (or optionally, desired or selected) number of input data is completed. The interrupt signal INTERRUPT H0 sent when the storage of a predetermined (or optionally, desired or selected) number of input data is completed may include the number of stored input data items.

[0065] The codec 112 reads the input data INPUT DATA0 from the input data buffer of the working memory 150 based on the interrupt signal INTERRUPT H0 (S515). The codec 112 may receive the address range of the input data buffer from the processor 113 before operation S515. When the interrupt signal INTERRUPT H0 is received for the first time, the codec 112 may read the input data INPUT DATA0 from the base address of the input data buffer.

[0066] The codec 112 decodes the encoded bitstream ENCODED BITSTREAM 0 stored at the encoded bitstream buffer address with reference to the input data INPUT DATA 0 (S516). The codec 112 may read the encoded bitstream ENCODEDBITSTREAM 0 from the working memory 150 based on the encoded bitstream buffer address included in the input data INPUT DATA 0, and decode the encoded bitstream ENCODED BITSTREAM 0 to generate the decoded picture DECODEDPICTURE 0.

[0067] The codec 112 writes the decoded picture DECODED PICTURE 0 into the DPB with reference to the input data INPUT DATA 0 (S517). The codec 112 may write the decoded picture DECODED PICTURE 0 into the working memory 150 based on the DPB address DPB ADDRESS 0 included in the input data INPUT DATA 0.

[0068] The codec 112 writes the output data OUTPUT DATA 0 related to the decoded picture DECODED PICTURE 0 into the output data buffer (S518). When the decoding is completed for the first time, the codec 112 may write the output data into the base address of the output data buffer.

[0069] When the writing of the output data is completed, the codec 112 sends the interrupt signal INTERRUPT C0 to the processor 113 (S519).

[0070] The processor 113 receives the interrupt signal INTERRUPT C0 and reads the output data OUTPUT DATA 0 from the output data buffer (S520). The processor 113 may determine the address where the output data OUTPUT DATA 0 has been stored in the output data buffer based on the number of times the interrupt signal INTERRUPT C0 has been received. The processor 113 may read the output data OUTPUT DATA 0 from the determined address.

[0071] The processor 113 sends a control signal for displaying the decoded picture DECODED PICTURE 0 to the display controller 115 (S521). The control signal may include the DPB address DPB ADDRESS0 determined based on the output data OUTPUT DATA 0.

[0072] The display controller 115 reads the decoded picture DECODED PICTURE 0 at the DPB address DPB ADDRESS 0 stored in the DPB (S522).

[0073] The display controller 115 may display the decoded picture DECODED PICTURE 0 on the display 130 (S523).

[0074] After sending the interrupt signal INTERRUPT C0, the codec 112 reads the input data INPUT DATA 1 from the input data buffer (S524). When decoding is completed, the codec 112 may read the input data INPUT DATA 1 from the next address of the base address of the input data buffer (for example, the address obtained by adding the product of the index of the input data that has completed decoding (such as the count value of the second count register) and the offset address size to the base address).

[0075] The codec 112 decodes the encoded bitstream ENCODED BITSTREAM 1 stored at the encoded bitstream buffer address with reference to the input data INPUT DATA 1 (S525). The codec 112 may read the encoded bitstream ENCODED BITSTREAM 1 from the working memory 150 based on the encoded bitstream buffer address included in the input data INPUT DATA 1, and decode the encoded bitstream ENCODED BITSTREAM 1 to generate the decoded picture DECODED PICTURE10.

[0076] The encoded bitstream ENCODED BITSTREAM 1 may be multi-frame data. In other words, the encoded bitstream ENCODED BITSTREAM 1 may be a bitstream into which pictures of several frames have been encoded. The encoded bitstream ENCODED BITSTREAM 1 may be encoded by an encoding technique (such as VP9, AV1, etc.).

[0077] The codec 112 writes the decoded picture DECODED PICTURE 10 into the DPB with reference to the input data INPUT DATA 1 (S526). When the encoded bitstream ENCODED BITSTREAM 1 includes pictures of three frames, the codec 112 can complete the decoding of a frame of picture and write the decoded frame of picture into the DPB. The codec 112 can write the decoded picture DECODE PICTURE 10 into the working memory 150 based on the DPB address DPB ADDRESS1 included in the input data INPUT DATA 1.

[0078] The codec 112 writes the output data OUTPUT DATA 1 related to the decoded picture DECODED PICTURE 10 into the output data buffer (S527). The codec 112 can write the output data OUTPUT DATA 1 at the next address of the base address of the output data buffer.

[0079] When the writing of the output data OUTPUT DATA 1 is completed, the codec 112 sends an interrupt signal INTERRUPT C1 to the processor 113 (S528).

[0080] When the encoded bitstream ENCODED BITSTREAM 1 includes undecoded data, the codec 112 requests the DPB address from the processor 113 (S529).

[0081] The encoded bitstream ENCODED BITSTREAM 1 can include information about the number of encoded pictures. The codec 112 can decode the encoded bitstream ENCODED BITSTREAM 1 and determine whether the decoding of the encoded pictures in the encoded bitstream ENCODED BITSTREAM 1 has been completed based on the information about the number of encoded pictures.

[0082] When the decoding of a frame of picture from the encoded bitstream ENCODED BITSTREAM 1 is completed, the codec 112 may determine whether the decoding of the encoded pictures in the encoded bitstream ENCODED BITSTREAM 1 has been completed based on whether the encoded bitstream ENCODED BITSTREAM 1 includes undecoded data. The encoded bitstream ENCODED BITSTREAM 1 may include information about the size of the encoded bitstream ENCODED BITSTREAM 1. The codec 112 may determine whether the encoded bitstream ENCODED BITSTREAM 1 includes undecoded data by comparing the size of the encoded bitstream ENCODED BITSTREAM 1 with the size of the decoded data of the encoded bitstream ENCODED BITSTREAM 1.

[0083] Since the encoded bitstream ENCODED BITSTREAM 1 is multi-frame data, even after the operation S525 is performed, the encoded bitstream ENCODED BITSTREAM 1 may include undecoded data. The codec 112 may decode the undecoded data (e.g., remaining data) included in the encoded bitstream ENCODED BITSTREAM 1. However, since each input data includes a DPB address, the input data INPUT DATA1 of the encoded bitstream ENCODED BITSTREAM 1 may also include only one DPB address DPB ADDRESS1. Therefore, if the decoded picture DECODED PICTURE 10 is stored at the DPB address DPB ADDRESS1, the codec 112 needs an additional DPB address for storing the picture obtained by decoding the data to be decoded (e.g., remaining data).

[0084] The processor 113 requests the operating system 151 to release the memory allocated to the input data (S530). The operating system 151 may release the input data stored in the working memory 300. Each input data may include a DPB address, and the codec 112 may sequentially read the input data from the base address of the input data buffer that has stored the input data. Therefore, when the input data INPUT DATA 1 including a new DPB address (e.g., DPB address DPB ADDRESS2) is additionally stored in the input data buffer, it is necessary to perform the decoding of the coded bitstream indicated by the input data INPUT DATA 1 after the decoding of the coded bitstreams indicated by the other input data INPUT DATA 2 and input data INPUT DATA 3 stored in the input data buffer is completed, and thus the throughput of the codec memory 210 may be reduced. In addition, when the display order of the decoded pictures is the order of the input data INPUT DATA 1, input data INPUT DATA 2, and input data INPUT DATA 3, the decoding of the coded bitstream indicated by the input data INPUT DATA 1 is performed after the decoding of the coded bitstream indicated by the input data INPUT DATA 3 is completed, and thus the display of the input data INPUT DATA 1 may not be performed normally. For this reason, the processor 113 may request the operating system 151 to release the input data from the working memory and sequentially store the input data from the base address of the input data buffer. In addition, the count register 211 for reading the input data of the codec 200 may be reset.

[0085] The processor 113 may request the operating system 151 to allocate a DPB address (S531).

[0086] The operating system 151 allocates the used DPB address to the processor 113 (S532). For example, the operating system 151 may allocate the DPB address that has been read by the display controller 115 (e.g., used) as a new DPB address to the processor 113.

[0087] The processor 113 stores the input data including the new DPB address in the working memory 150 (S533 to S535). The processor 113 may generate input data including DPB address 2, DPB address 3, and DPB address 4 in response to multiple coded bitstreams respectively. The processor 113 may store the input data generated in response to the multiple coded bitstreams in the input data buffer in the working memory 150.

[0088] After storing the input data item, the processor 113 sends an interrupt signal INTERRUPT H1 to the codec 112 (S536).

[0089] The codec 112 reads the input data INPUT DATA 1 from the input data buffer of the working memory 150 based on the interrupt signal INTERRUPT H1 (S537). Since the count register 211 of the codec 112 has been reset, when the codec 112 receives the interrupt signal INTERRUPT H1, it can read the input data INPUT DATA 1 from the base address of the input data buffer.

[0090] The codec 112 decodes the encoded bitstream ENCODED BITSTREAM 2 with reference to the input data INPUT DATA 1 (S538). When the encoded bitstream buffer address included in the input data INPUT DATA 1 is the same as the encoded bitstream buffer address included in the input data INPUT DATA 1 read in operation S524, the codec 112 can decode the remaining undecoded data in operation S525. The codec 112 can decode the remaining data of the encoded bitstream ENCODEDBITSTREAM 1 (e.g., ENCODED BITSTREAM 2) to generate the decoded picture DECODEDPICTURE 11.

[0091] The codec 112 writes the decoded picture DECODED PICTURE 11 into the DPB with reference to the input data INPUT DATA 1 (S539). The codec 112 can write the decoded picture DECODED PICTURE 11 into the working memory 150 based on the DPB address DPBADDRESS2 included in the input data INPUT DATA 1.

[0092] The codec 112 writes the output data OUTPUT DATA 2 related to the decoded picture DECODED PICTURE 11 into the output data buffer (S540). The codec 112 can write the output data OUTPUT DATA 2 into the next address of the address where the output data OUTPUT DATA 1 has been stored in the output data buffer.

[0093] When the writing of the output data OUTPUT DATA 2 is completed, the codec 112 sends the interrupt signal INTERRUPT C2 to the processor 113 (S541).

[0094] When the encoded bitstream ENCODED BITSTREAM 1 includes undecoded data, the codec 112 requests the DPB address from the processor 113 again (S542).

[0095] The processor 113 sends a control signal for displaying the decoded picture DECODED PICTURE 10 to the display controller 115 (S543). The control signal may include a DPB address DPB ADDRESS1 determined based on the output data OUTPUT DATA1.

[0096] The display controller 115 reads the decoded picture DECODED PICTURE 10 stored at the DPB address DPB ADDRESS1 in the DPB (S544).

[0097] The display controller 115 may display the decoded picture DECODED PICTURE 10 on the display 130 (S545).

[0098] The delay may be caused by operations S529 to S537 and / or operation S542, which decode the encoded bitstream ENCODED BITSTREAM 1 as multi-frame data and request a DPB address from the processor 113 and the operating system 151 to store the decoded picture. This delay is greater than the time taken by the codec 112 to decode a single-frame picture.

[0099] Figure 6 It is a diagram showing a working memory according to some example embodiments.

[0100] Referring to Figure 6 , the working memory 600 may include a plurality of buffer regions 610, 620, 630, 640, and 650. In the first region 610, the encoded bitstream may be stored. In the second region 620, the input data may be stored. In the third region 630, the output data may be stored. In the fourth region 640, the decoded picture may be stored. In the fifth region 650, the DPB data may be stored. In some example embodiments, the input data may not include information about the DPB address, and the DPB data may include information about the DPB address. The first to fifth regions 610, 620, 630, 640, and 650 may be arranged non-continuously in the working memory 600, and the sizes of the respective regions may be set in various ways. Hereinafter, the first to fifth regions 610, 620, 630, 640, and 650 will be referred to as the encoded bitstream buffer, the input data buffer, the output data buffer, the decoded picture buffer, and the DPB data buffer, respectively.

[0101] In some example embodiments, the operating system 151 may allocate an address range from ADDR10 to ADDR1n in the working memory 600 as a first region 610, an address range from ADDR20 to ADDR2m as a second region 620, an address range from ADDR30 to ADDR3p as a third region 630, an address range from ADDR40 to ADDR4q as a fourth region 640, and an address range from ADDR50 to ADDR5r as a fifth region 650. Here, n, m, p, q, and r may be any natural numbers greater than 0 (e.g., 2, 5, 15, etc. simultaneously or separately).

[0102] Figure 7 is a diagram of a DPB data buffer showing the working memory accuracy according to some example embodiments.

[0103] Referring Figure 7 , the DPB data buffer 700 may include a plurality of DPB data 710 (710a to 710d, e.g., DPB DATA0 to DPB DATA 3). One DPB data 710a may include flag data 711 and information about a DPB address 712. The flag data 711 may indicate whether the DPB data 710a is available. When the operating system 151 allocates a DPB for storing encoded bitstream data to the processor 113, the processor may generate DPB data 710 including information about the DPB address 712 indicating the allocated DPB.

[0104] In some example embodiments, the processor 113 may update the DPB data 710a based on the flag data 711 of the DPB data 710a. For example, when the flag data 711 of the DPB data 710a is a first value, the processor 113 may change the flag data 711 of the DPB data 710a to a second value and store the information about the allocated DPB address in the DPB data 710a. In other words, the processor may write DPB data 710a including flag data 711 having the second value and information about the allocated DPB address to the address where the DPB data 710a has already been stored. After storing the new DPB data 710a, the processor 113 may read the next DPB data 710b of the DPB data 710a. When the flag data 711 of the DPB data 710a is the second value, the processor 113 may wait until the flag data 711 of the DPB data 710a is changed to the first value.

[0105] When the flag data 711 of the DPB data 710a is the second value, the codec 112 may store the decoded picture at the DPB address 712 of the DPB data 710a. The codec 112 may store the decoded picture at the DPB address 712 and change the flag data 711 of the DPB data 710a to the first value. After using the DPB data 710a, the codec 112 may read the next DPB data 710b of the DPB data 710a. When the flag data 711 of the DPB data 710a is the first value, the codec 112 may wait until the flag data 711 of the DPB data 710a is changed to the second value.

[0106] Figure 8 is a flowchart showing a decoding method according to some example embodiments.

[0107] Referring to Figure 1 、 Figure 2 and Figures 6 to 8 and

[0108] The processor 113 stores the input data in the working memory 150 (S810). The processor 113 may generate input data including the address of the encoded bitstream buffer storing the encoded bitstream and the size of the encoded bitstream. For example, the processor 113 may store multiple input data INPUT DATA 1 to INPUT DATA 3 generated in response to multiple encoded bitstreams in the input data buffer in the working memory 600.

[0109] The processor 113 stores the DPB data in the working memory 150 (S811). For example, the processor 113 may generate multiple DPB data DPB DATA 1 to DPB DATA 3 corresponding to multiple encoded bitstreams. The multiple DPB data DPB DATA 1 to DPB DATA 3 may each include a DPB address. The processor 113 may sequentially store the multiple DPB data from the base address of the DPB data buffer.

[0110] If the input data and the DPB data items are stored, the processor 113 sends an interrupt signal INTERRUPT H10 to the codec 112 (S812). The processor 113 may send the interrupt signal INTERRUPT H10 whenever the storage of the input data and the DPB data is completed or when the storage of a predetermined (or optionally, desired or selected) number of the input data and the DPB data is completed. The interrupt signal INTERRUPT H10 sent when the storage of a predetermined (or optionally, desired or selected) number of the input data and the DPB data is completed may include the number of the stored input data and the stored DPB data items.

[0111] The codec 112 reads the input data INPUT DATA 1 from the input data buffer of the working memory 150 based on the interrupt signal INTERRUPT H10 (S813). The codec 112 may receive the address range of the input data buffer from the processor 113 before the operation S813. When the interrupt signal INTERRUPT H10 is received for the first time, the codec 112 may read the input data INPUT DATA 1 from the base address of the input data buffer.

[0112] The codec 112 reads the DPB data DPB DATA 1 from the DPB data buffer of the working memory 150 based on the interrupt signal INTERRUPT H10 (S814). The codec 112 may receive the address range of the DPB data buffer from the processor 113 before the operation S813. When the interrupt signal INTERRUPT H10 is received for the first time, the codec 112 may read the DPB data DPB DATA 1 from the base address of the DPB data buffer.

[0113] The codec 112 decodes the encoded bitstream ENCODED BITSTREAM 1 stored at the encoded bitstream buffer address with reference to the input data INPUT DATA 1 (S815). Here, the encoded bitstream ENCODED BITSTREAM 1 may be multi-frame data. The codec 112 may read the encoded bitstream ENCODED BITSTREAM 1 from the working memory 150 based on the encoded bitstream buffer address included in the input data INPUT DATA 1, and decode the encoded bitstream ENCODED BITSTREAM 1 to generate a decoded picture DECODED PICTURE 1A.

[0114] The codec 112 writes the decoded picture DECODED PICTURE 1A into the DPB with reference to the DPB data DPB DATA 1 (S816). The codec 112 can write the decoded picture DECODED PICTURE 1A into the working memory 150 based on the DPB address DPB ADDRESS1 included in the DPB data DPB DATA 1.

[0115] The codec 112 writes the output data OUTPUT DATA 1A related to the decoded picture DECODED PICTURE 1A into the output data buffer (S817). When the decoding is first completed, the codec 112 can write the output data into the base address of the output data buffer.

[0116] When the writing of the output data is completed, the codec 112 sends an interrupt signal INTERRUPT 1A to the processor 113 (S818).

[0117] The processor 113 receives the interrupt signal INTERRUPT 1A and reads the output data OUTPUT DATA 1A from the output data buffer (S819). The processor 113 can determine the address in the output data buffer where the output data OUTPUT DATA 1A has been stored based on the number of times the interrupt signal INTERRUPT 1A has been received. The processor 113 can read the output data OUTPUT DATA 1A from the determined address. The processor 113 can determine the display order of the decoded picture DECODARED PICTURE 1A from the output data OUTPUT DATA 1A. Hereinafter, it is assumed that the decoded picture DECODED PICTURE 1A is displayed after the decoded picture DECODED PICTURE 1B. Therefore, after reading the output data OUTPUT DATA 1A, the processor 113 may not send a control signal to the display controller 115 until the output data OUTPUT DATA 1B related to the decoded picture DECODED PICTURE 1B is read.

[0118] When the encoded bitstream ENCODED BITSTREAM 1 includes undecoded data, the codec 112 reads the DPB data DPB DATA 2 from the DPB data buffer of the working memory 150 (S820). How the codec 112 determines whether the encoded bitstream ENCODED BITSTREAM 1 includes undecoded data is related to Figure 5How the codec 112 in the description determines whether the encoded bitstream ENCODED BITSTREAM 1 includes undecoded data is the same or similar, and thus its description will not be given. When the decoding is completed, the codec 112 can read the DPB data DPB DATA2 from the next address of the base address of the DPB data buffer (for example, the address obtained by adding the product of the number of times the decoding has been completed and the offset address size to the base address).

[0119] The codec 112 decodes the remaining data of the encoded ENCODED BITSTREAM 1 (for example, ENCODED BITSTREAM2) (S821). The codec 112 can decode the undecoded data in the encoded bitstream ENCODED BITSTREAM 1 to generate the decoded picture DECODED PICTURE 1B.

[0120] The codec 112 writes the decoded picture DECODED PICTURE 1B into the DPB with reference to the DPB data DPB DATA 2 (S822). The codec 112 can write the decoded picture DECODED PICTURE 1B into the working memory 150 based on the DPB address DPB ADDRESS2 included in the DPB data DPB DATA 2.

[0121] The codec 112 writes the output data OUTPUT DATA 1B related to the decoded picture DECODED PICTURE 1B into the output data buffer (S823). The codec 112 can write the output data into the next address of the address where the output data OUTPUT DATA 1A has been stored in the output data buffer.

[0122] When the writing of the output data OUTPUT DATA 1B is completed, the codec 112 sends the interrupt signal INTERRUPT1B to the processor 113 (S824).

[0123] When the encoded bitstream ENCODED BITSTREAM 1 includes undecoded data, the codec 112 reads the DPB data DPB DATA 3 from the DPB data buffer of the working memory 150 (S825).

[0124] The codec 112 decodes the remaining data of the encoded bitstream ENCODED BITSTREAM 1 (e.g., ENCODED BITSTREAM 3) (S826). The codec 112 may decode the undecoded data of the encoded bitstream ENCODED BITSTREAM 1 to generate the decoded picture DECODED PICTURE 1C.

[0125] The codec 112 writes the decoded picture DECODED PICTURE 1C into the DPB with reference to the DPB data DPB DATA 3 (S827). The codec 112 may write the decoded picture DECODED PICTURE 1C into the working memory 150 based on the DPB address DPB ADDRESS 3 included in the DPB data DPB DATA 3.

[0126] The codec 112 writes the output data OUTPUT DATA 1C related to the decoded picture DECODED PICTURE 1C into the output data buffer (S828). The codec 112 may write the output data into the next address of the address where the output data OUTPUT DATA 1C has been stored in the output data buffer.

[0127] When the writing of the output data is completed, the codec 112 sends the interrupt signal INTERRUPT 1C to the processor 113 (S829).

[0128] The processor 113 receives the interrupt signal INTERRUPT 1B and reads the output data OUTPUT DATA 1B from the output data buffer (S830). The processor 113 may determine the address where the output data OUTPUT DATA 1B has been stored in the output data buffer based on the number of times the interrupt signal INTERRUPT 1B has been received. The processor 113 may read the output data OUTPUT DATA 1B from the determined address.

[0129] The processor 113 sends a control signal for displaying the decoded picture DECODED PICTURE 1B to the display controller 115 (S831). The control signal may include the DPB address DPB ADDRESS2 determined based on the output data OUTPUT DATA 1B.

[0130] The display controller 115 reads the decoded picture DECODED PICTURE 1B stored at the DPB address DPB ADDRESS2 in the DPB (S832).

[0131] The display controller 115 may display the decoded picture DECODED PICTURE 1B on the display 130 (S833).

[0132] The processor 113 sends a control signal for displaying the decoded picture DECODED PICTURE 1A to the display controller 115 (S834). The control signal may include the DPB address DPBADDRESS1 determined based on the output data OUTPUT DATA 1A.

[0133] The display controller 115 reads the decoded picture DECODEDPICTURE 1A stored at the DPB address DPB ADDRESS1 in the DPB (S835).

[0134] The display controller 115 may display the decoded picture DECODED PICTURE 1A on the display 130 (S836).

[0135] According to some example embodiments, when the codec 112 needs a DPB address, it reads the DPB address from the DPB data buffer without the need for an additional DPB address, and thus the latency associated with the DPB address allocation (see the "Latency" in Figure 5 ) may be reduced.

[0136] For example, according to some example embodiments, based on the above decoding method, the speed, accuracy, and / or power efficiency of the memory device may be increased. Thus, the improved apparatus and method overcome the deficiencies of conventional apparatuses and methods for decoding data related to decoding / encoding image data, while reducing resource consumption, data accuracy, and resource allocation (e.g., latency). In addition, communication and reliability in the apparatus are improved by providing capabilities such as those related to the DPB address and the memory storage architecture disclosed herein.

[0137] Hereinafter, how the codec 112 and the processor 113 use the DPB data buffer will be described with reference to Figures 9 to 12 .

[0138] Figure 9 is a flowchart showing a method of using the DPB data in the DPB data buffer according to some example embodiments, and Figure 10 is a diagram showing the DPB and the DPB data buffer according to some example embodiments.

[0139] Refer to Figure 9 and Figure 10, the codec 112 reads the flag data of the DPB data 1030b indicated by the read pointer READPOINTER 1 from the DPB data buffer 1020 (S900). The DPB data buffer 1020 may contain a plurality of DPB data 1030a to 1030e. The DPB 1000 may include a plurality of DPB regions 1010a to 1010e. Each of the plurality of DPB regions 1010a to 1010e may store a decoded picture. The DPB regions 1010c and 1010e containing the decoded pictures may be in the "used" state, and the DPB regions 1010a, 1010b, and 1010d not containing the decoded pictures may be in the "unused" state. The plurality of DPB data 1030a to 1030e may indicate the plurality of DPB regions 1010a to 1010e. When the DPB regions 1010a to 1010e indicated by the plurality of DPB data 1030a to 1030e are in the "used" state, the flag data of the plurality of DPB data 1030a to 1030e may have a first value ("0"), and when the DPB regions 1010a to 1010e indicated by the plurality of DPB data 1030a to 1030e are in the "unused" state, the flag data of the plurality of DPB data 1030a to 1030e may have a second value ("1").

[0140] The codec 112 determines whether the value of the flag data is the second value ("1") (S910). The codec 112 may determine whether the DPB region 1010b indicated by the DPB data 1030b is in the "used" state or the "unused" state based on the value of the flag data of the DPB data 1030b.

[0141] When the flag data of the DPB data 1030b is the second value ("1"), the codec 112 uses the DPB address 1010b of the DPB data 1030b (S920). For example, when the DPB region 1010b indicated by the DPB data 1030b is in the "unused" state, the codec 112 may store the decoded picture at the DPB address 1010b.

[0142] The codec 112 changes the flag data of the DPB data 1030b to the first value ("0") (S930). The codec 112 may change the flag data of the DPB data 1030b to the first value ("0") for indicating that the DPB region 1010b indicated by the DPB data 1030b is in the "used" state.

[0143] When the flag data of the DPB data 1030b is the first value ("0"), the codec 112 can read again the flag data of the DPB data 1030b indicated by the read pointer READ POINTER 1 from the DPB data buffer 1020. The codec 112 can read again the flag data of the DPB data 1030b at a predetermined (or optionally, desired or selected) interval. Thus, the codec 112 can wait until the flag data of the DPB data 1030b is changed to the second value ("1").

[0144] After using the DPB data 1030b, increment / move the read pointer (S940). Then, the codec 112 can read the DPB data 1030c indicated by the read pointer READ POINTER 2. The read pointer can indicate the DPB data to be read while cycling through the DPB data buffer 1020. For example, in operation S900, the read pointer can indicate the address of the DPB data buffer 1020 where the last DPB data 1030e has been stored, and the read pointer is incremented in operation S940 to indicate the base address.

[0145] Figure 11 is a flowchart showing a method of updating DPB data in a DPB data buffer according to some example embodiments, and Figure 12 is a diagram showing a DPB and a DPB data buffer according to some example embodiments, where the DPB 1200 may include a plurality of DPB regions 1210a to 1210f, and the DPB data buffer 1220 may include a plurality of DPB data 1230a to 1230e.

[0146] Referring to Figure 11 and Figure 12 , the processor 113 reads the flag data of the DPB data 1230e indicated by the write pointer WRITEPOINTER 1 from the DPB data buffer 1020 (S1100). However, the scope of the present invention is not limited thereto, and the processor 113 can read the flag data of the DPB data 1230a indicated by the write pointer WRITE POINTER 2 from the DPB data buffer 1020.

[0147] The processor 113 determines whether the value of the flag data is the first value ("0") (S1110). The processor 113 can determine whether the DPB region 1210b indicated by the DPB data 1230e is in the "used" state or the "unused" state based on the value of the flag data of the DPB data 1230e.

[0148] When the flag data of the DPB data 1230e is the first value (“0”), the processor 113 stores the DPB data 1230e indicating the new DPB address 1210f (S1120). For example, when the DPB area 1210e indicated by the DPB data 1230e is in the “used” state, the processor 113 may store the DPB data 1230e indicating the DPB address 1210f with the “unused” state in the area indicated by the write pointer WRITE POINTER 1.

[0149] The processor 113 changes the flag data of the DPB data 1230e to the second value (“1”) (S1130). The processor 113 may change the flag data of the DPB data 1230e to the second value (“1”) for indicating that the DPB area 1210e indicated by the DPB data 1230e is in the “unused” state.

[0150] When the flag data of the DPB data 1230e is the second value (“1”), the processor 113 may read again the flag data of the DPB data 1230e indicated by the write pointer WRITE POINTER 1 from the DPB data buffer 1220. The processor 113 may re-read the flag data of the DPB data 1230e at a predetermined (or optionally, desired or selected) interval. Thus, until the flag data of the DPB data 1230e is changed to the first value (“0”), the processor 113 may wait.

[0151] After storing the new DPB data 1230e, the write pointer is incremented or moved (S1140). Then, the processor 113 may read the next DPB data 1230a of the DPB data 1230e. The write pointer may indicate the DPB data to be read while cycling through the DPB data buffer 1220.

[0152] Figure 13 is a flowchart showing a decoding method according to some example embodiments.

[0153] Refer to Figure 1 、 Figure 2 、 Figure 6 、 Figure 7 and Figure 13, the operating system 151 allocates multiple buffer regions 610, 620, 630, 640, and 650 in the working memory 600 and notifies the processor 113 of information regarding the multiple buffer regions 610, 620, 630, 640, and 650 (S1300). For example, the operating system 151 may notify the processor 113 of information regarding the addresses of the multiple buffer regions and the size of each region. The processor 113 may send the information regarding the multiple buffer regions 610, 620, 630, 640, and 650 to the codec 112.

[0154] The processor 113 stores the input data in the working memory 150 (S1310). The processor 113 may generate input data including the address of the stored coded bitstream in the coded bitstream buffer and the size of the coded bitstream. For example, the processor 113 may store multiple input data INPUT DATA 4 to INPUT DATA 7 generated in response to multiple coded bitstreams in the input data buffer in the working memory 600.

[0155] The processor 113 stores the DPB data in the working memory 150 (S1311). For example, the processor 113 may generate multiple DPB data DPB DATA 4 to DPB DATA 7 corresponding to the multiple coded bitstreams. The multiple DPB data DPB DATA 4 to DPB DATA 7 may each include a DPB address. The processor 113 may sequentially store the multiple DPB data from the base address of the DPB data buffer.

[0156] If the input data and DPB data items are stored, the processor 113 sends an interrupt signal INTERRUPT H20 to the codec 112 (S1312). The processor 113 may send the interrupt signal INTERRUPT H20 whenever the storage of the input data and DPB data is completed or when the storage of a predetermined (or optionally, desired or selected) number of input data and DPB data is completed. The interrupt signal INTERRUPT H20 sent when the storage of a predetermined (or optionally, desired or selected) number of input data and DPB data is completed may include the number of stored input data INPUT DATA 4 to INPUT DATA7 and the number of stored DPB data DPB DATA 4 to DPB DATA 7.

[0157] The codec 112 reads the input data INPUT DATA 4 (S1313) from the input data buffer of the working memory 150 based on the interrupt signal INTERRUPT H20. The codec 112 may receive the address range of the input data buffer from the processor 113 before operation S1313. When the interrupt signal INTERRUPT H20 is received for the first time, the codec 112 may read the input data INPUT DATA 4 from the base address of the input data buffer.

[0158] The codec 112 reads the DPB data DPB DATA 4 (S1314) from the DPB data buffer of the working memory 150 based on the interrupt signal INTERRUPT H20. The codec 112 may receive the address range of the DPB data buffer from the processor 113 before operation S1313. When the interrupt signal INTERRUPT H20 is received for the first time, the codec 112 may read the DPB data DPB DATA 4 from the base address of the DPB data buffer.

[0159] The codec 112 decodes the encoded bitstream ENCODED BITSTREAM 4 stored at the encoded bitstream buffer address with reference to the input data INPUT DATA 42 (S1315). Here, the encoded bitstream ENCODED BITSTREAM 4 may be an interlaced picture. For example, the encoded bitstream ENCODED BITSTREAM 4 may be a top field picture or a bottom field picture. The encoded bitstream ENCODED BITSTREAM 4 may include information on whether the decoded picture has been arranged according to the interlaced scan type and information on whether the decoded picture is a top field picture or a bottom field picture, as information on the picture arrangement method. The codec 112 may read the encoded bitstream ENCODED BITSTREAM 4 from the working memory 150 based on the encoded bitstream buffer address included in the input data INPUT DATA 4, and decode the encoded bitstream ENCODED BITSTREAM 4 to generate the top field data of an interlaced picture of one frame.

[0160] The codec 112 writes the decoded picture DECODED PICTURE 4 into the DPB with reference to the DPB data DPB DATA 4 (S1316). The codec 112 may write the decoded picture DECODED PICTURE 4 into the working memory 150 based on the DPB address DPB ADDRESS 4 included in the DPB data DPB DATA 4.

[0161] The codec 112 writes the output data OUTPUT DATA 4 related to the decoded picture DECODED PICTURE 4 into the output data buffer (S1317). When the decoding is completed for the first time, the codec 112 may write the output data into the base address of the output data buffer. The output data OUTPUT DATA 4 may include information indicating that the decoding of the top field of an interlaced picture has been completed.

[0162] When the writing of the output data is completed, the codec 112 sends an interrupt signal INTERRUPT C4 to the processor 113 (S1318).

[0163] The processor 113 receives the interrupt signal INTERRUPT C4 and reads the output data OUTPUT DATA 4 from the output data buffer (S1319). The processor 113 may determine the address in the output data buffer where the output data OUTPUT DATA 4 has been stored based on the number of times the interrupt signal INTERRUPT C4 has been received. The processor 113 may read the output data OUTPUT DATA 4 from the determined address. The processor 113 may determine from the output data OUTPUT DATA 4 that the decoded picture DECODED PICTURE 4 is the top field data of an interlaced picture of one frame. Therefore, after reading the output data OUTPUT DATA 4, the processor 113 may not send a control signal for displaying an interlaced picture of one frame to the display controller 115 until the output data (e.g., output data OUTPUT DATA5) indicating that the decoding of an interlaced picture of one frame has been completed is read.

[0164] If the decoding of the interlaced picture has not been completed, the codec 112 reads the input data INPUT DATA 5 from the input data buffer of the working memory 150 (S1320).

[0165] The codec 112 decodes the encoded bitstream ENCODED BITSTREAM 5 stored at the encoded bitstream buffer address with reference to the input data INPUT DATA 5 (S1321). The codec 112 may generate the bottom field data of an interlaced picture of one frame.

[0166] The codec 112 writes the decoded picture DECODED PICTURE 5 into the DPB according to the DPB address DPB ADDRESS 4 where the top field data has been stored (S1322).

[0167] The codec 112 writes the output data OUTPUT DATA 5 related to the decoded picture DECODED PICTURE 5 into the output data buffer (S1323). The codec 112 may generate the output data OUTPUT DATA 5 including information indicating that the decoding of an interlaced picture of a frame has been completed. The codec 112 may write the output data into the next address of the address in the output data buffer where the output data OUTPUT DATA 4 has been stored.

[0168] When the writing of the output data OUTPUT DATA 5 is completed, the codec 112 sends an interrupt signal INTERRUPT C5 to the processor 113 (S1324).

[0169] The processor 113 receives the interrupt signal INTERRUPT C5 and reads the output data OUTPUT DATA 5 from the output data buffer (S1325). The processor 113 may determine the address in the output data buffer where the output data OUTPUT DATA 5 has been stored based on the number of times the interrupt signal INTERRUPT C5 has been received. The processor 113 may read the output data OUTPUT DATA 5 from the determined address.

[0170] The processor 113 sends control signals for displaying the decoded picture DECODED PICTURE 4 and the decoded picture DECODED PICTURE 5 to the display controller 115 based on the output data OUTPUT DATA 5 (S1326). The processor 113 may detect the information indicating that the decoding of an interlaced picture of a frame of the output data OUTPUT DATA 5 has been completed and generate control signals for displaying the decoded picture DECODED PICTURE 4 and the decoded picture DECODED PICTURE 5. The control signals may include a DPB address DPB ADDRESS 4 determined based on the output data OUTPUT DATA 5.

[0171] The display controller 115 reads the decoded picture DECODED PICTURE 4 and the decoded picture DECODED PICTURE 5 stored at the DPB address DPB ADDRESS 4 in the DPB (S1327).

[0172] The display controller 115 may display the decoded picture DECODED PICTURE 4 and the decoded picture DECODED PICTURE 5 on the display 130 (S1340).

[0173] After sending the interrupt signal INTERRUPT C5, the codec 112 reads the input data INPUT DATA 6 from the input data buffer (S1328).

[0174] Based on the interrupt signal INTERRUPT H20, the codec 112 reads the DPB data DPB DATA 6 from the DPB data buffer of the working memory 150 (S1329).

[0175] The codec 112 decodes the encoded bitstream ENCODED BITSTREAM 6 stored at the encoded bitstream buffer address with reference to the input data INPUT DATA 6 (S1330).

[0176] The codec 112 writes the decoded picture DECODED PICTURE 6 into the DPB with reference to the DPB data DPB DATA 5. The codec 112 can write the decoded picture DECODED PICTURE 6 into the working memory 150 based on the DPB address DPB ADDRESS 5 included in the DPB data DPB DATA 5.

[0177] The codec 112 writes the output data OUTPUT DATA 6 related to the decoded picture DECODED PICTURE 6 into the output data buffer (S1332).

[0178] When the writing of the output data is completed, the codec 112 sends the interrupt signal INTERRUPT C6 to the processor 113 (S1333).

[0179] The processor 113 receives the interrupt signal INTERRUPT C6 and reads the output data OUTPUT DATA 6 from the output data buffer (S1334).

[0180] The processor 113 sends a control signal for displaying the decoded picture DECODED PICTURE 6 to the display controller 115 (S1335). The control signal may include the DPB address DPB ADDRESS5 determined based on the output data OUTPUT DATA 6.

[0181] The display controller 115 reads the decoded picture DECODED PICTURE 6 stored at the DPB address DPB ADDRESS 5 of the DPB (S1336).

[0182] The display controller 115 can display the decoded picture DECODED PICTURE 6 on the display 130 (S1337).

[0183] According to the method of using the working memory 150 described with reference to Figure 5 the top field data and the bottom field data of a bitstream encoded in an interlaced manner can be stored in different DPB regions respectively. Therefore, the bitstream encoded in an interlaced manner can be decoded using the SFR in the codec memory 210. In the case of using the SFR, when the codec 112 is decoding the encoded bitstream stored in the SFR, since the SFR is in use, the processor 113 cannot use a new encoded bitstream in the SFR. In addition, when the processor 113 is processing the decoded picture, the codec 112 cannot perform the decoding operation until the processor 113 stores a new encoded bitstream in the SFR. Therefore, in the decoding method using the SFR, a delay occurs.

[0184] According to some example embodiments, in the case of decoding a bitstream encoded in an interlaced manner, the codec 112 can store the top field data and the bottom field data in one DPB region. Therefore, according to some example embodiments, compared with the case of using the SFR, the delay can be reduced.

[0185] For example, according to some example embodiments, based on the above decoding method, the speed, accuracy, and / or power efficiency of the memory device can be increased. Therefore, the improved device and the improved method overcome the deficiencies of the conventional devices and methods for decoding data related to decoding / encoding image data, while reducing resource consumption, data accuracy, and resource allocation (e.g., delay). In addition, the communication and reliability in the device are improved by providing the capabilities related to, for example, DPB addresses and memory storage architectures disclosed herein.

[0186] In some example embodiments, with reference to Figures 1 to 13 each component described or a combination of two or more components can be implemented as a digital circuit, a programmable or non-programmable logic device or array, an application specific integrated circuit (ASIC), etc.

[0187] As described herein, any electronic device and / or portions thereof according to any example embodiment may include one or more instances of processing circuitry (such as hardware including logic circuitry, a hardware / software combination such as a processor executing software, or any combination thereof), may be included in one or more instances of processing circuitry (such as hardware including logic circuitry, a hardware / software combination such as a processor executing software, or any combination thereof), and / or may be implemented by one or more instances of processing circuitry (such as hardware including logic circuitry, a hardware / software combination such as a processor executing software, or any combination thereof). For example, the processing circuitry may more specifically include, but is not limited to: a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA) and programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), a neural network processor (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. In some example embodiments, the processing circuitry may include a non-transitory computer-readable storage device (e.g., a memory) (e.g., a DRAM device) storing an instruction program and a processor (e.g., a CPU), the processor being configured to execute the instruction program to implement functions and / or methods performed by some or all of any device, system, module, unit, controller, circuit, architecture, and / or portions thereof according to any example embodiment and / or any portion thereof.

[0188] Although the present invention has been described in connection with example embodiments that are presently considered to be practical, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, the intention is to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A decoding method, comprising: reading first input data including information about an address of a first encoded bitstream buffer from an input data buffer; reading first decoded picture buffer data including information about a first decoded picture buffer address from a decoded picture buffer data buffer; generating a first decoded picture by decoding a first coded bitstream stored at a first coded bitstream buffer address; as well as The first decoded picture is stored at a first decoded picture buffer address.

2. The decoding method according to claim 1, further comprising: determining whether a value of the flag data of the first decoded picture buffer data is a first value; The step of storing the first decoded picture at the first decoded picture buffer address includes: based on the value of the flag data of the first decoded picture buffer data being a first value, storing the first decoded picture at the first decoded picture buffer address.

3. The decoding method according to claim 2, further comprising: Based on storing the first decoded picture at the first decoded picture buffer address, the value of the flag data of the first decoded picture buffer data is changed to a second value.

4. The decoding method according to claim 2, further comprising: Based on the value of the flag data of the first decoded picture buffer data being a second value, the second decoded picture buffer data is read from an address of the decoded picture buffer data buffer next to the address where the first decoded picture buffer data has been stored.

5. The decoding method according to claim 1, further comprising: reading second decoded picture buffer data including information about a second decoded picture buffer address from the decoded picture buffer data buffer; generating a second decoded picture by decoding the first encoded bit stream; as well as The second decoded picture is stored at the second decoded picture buffer address.

6. The decoding method according to claim 5, wherein The step of reading the second decoded picture buffer data comprises: The second decoded picture buffer data is read from an address of the decoded picture buffer data buffer next to the address where the first decoded picture buffer data has been stored.

7. The decoding method according to claim 5, further comprising: reading second input data including information about an address of a second encoded bitstream buffer from the input data buffer; reading third decoded picture buffer data including information about a third decoded picture buffer address from the decoded picture buffer data buffer; generating a third decoded picture by decoding a second encoded bitstream stored at the second encoded bitstream buffer address; as well as The third decoded picture is stored at a third decoded picture buffer address.

8. The decoding method according to claim 1, further comprising: reading second input data including information about an address of a second encoded bitstream buffer from the input data buffer; generating a second decoded picture by decoding a second coded bitstream stored at the second coded bitstream buffer address; as well as The second decoded picture is stored at the first decoded picture buffer address.

9. The decoding method according to claim 8, wherein The first decoded picture and the second decoded picture are respectively the top field data and the bottom field data of an interlaced picture of one frame, and The decoding method further comprises: Output data including information indicating that decoding of the interlaced picture of the one frame has been completed is written into the output data buffer.

10. The decoding method according to claim 1, further comprising: The second decoded picture buffer data including information about the second decoded picture buffer address is written into the decoded picture buffer data buffer.

11. The decoding method according to claim 10, wherein The step of writing the second decoded picture buffer data comprises the following steps: determining whether the value of the flag data of the first decoded picture buffer data is a second value; as well as Based on the value of the flag data of the first decoded picture buffer data being a second value, the second decoded picture buffer data is written into the address where the first decoded picture buffer data has been stored.

12. A system on chip, comprising: The processor is configured as: writing the first input data including information about the address of the first encoded bit stream buffer into the input data buffer, and writing first decoded picture buffer data including information about the first decoded picture buffer address into a decoded picture buffer data buffer; as well as Codecs are configured as: reading first input data from the input data buffer, reading first decoded picture buffer data from a decoded picture buffer data buffer, generating a first decoded picture by decoding a first coded bitstream stored at a first coded bitstream buffer address, and The first decoded picture is stored at a first decoded picture buffer address.

13. The system on chip according to claim 12, wherein The codec is also configured to: determine whether the value of the flag data of the first decoded picture buffer data is a first value; based on the value of the flag data of the first decoded picture buffer data being the first value, store the first decoded picture at the first decoded picture buffer address; and based on storing the first decoded picture at the first decoded picture buffer address, change the value of the flag data of the first decoded picture buffer data to a second value.

14. The system on chip according to claim 13, wherein The codec is further configured to read second decoded picture buffer data from an address of the decoded picture buffer data buffer next to an address where the first decoded picture buffer data has been stored, based on the value of the flag data of the first decoded picture buffer data being a second value.

15. The system on chip according to claim 12, wherein The processor is also configured to: determine whether the value of the flag data of the first decoded picture buffer data is a second value; and based on the value of the flag data of the first decoded picture buffer data being the second value, write the second decoded picture buffer data including information about the address of the second decoded picture buffer into the address where the first decoded picture buffer data has been stored.

16. The system on chip according to claim 12, wherein The codec is also configured to: read second decoded picture buffer data including information about a second decoded picture buffer address from the decoded picture buffer data buffer, generate a second decoded picture by decoding the first encoded bit stream, and store the second encoded picture at the second decoded picture buffer address.

17. The system on chip according to claim 16, wherein The codec is also configured to: read second input data including information about a second encoded bitstream buffer address from the input data buffer, read third decoded picture buffer data including information about a third decoded picture buffer address from the decoded picture buffer data buffer, generate a third decoded picture by decoding the second encoded bitstream stored at the second encoded bitstream buffer address, and store the third decoded picture at the third decoded picture buffer address.

18. The system on chip according to claim 12, wherein The codec is also configured to: read second input data including information about a second encoded bitstream buffer address from the input data buffer, generate a second decoded picture by decoding a second encoded bitstream stored at the second encoded bitstream buffer address, and store the second decoded picture at the first decoded picture buffer address.

19. A decoding device, comprising: Working memory, including: A coded bitstream buffer configured to store a plurality of coded bitstreams, an input data buffer configured to store a plurality of input data including information on addresses of a plurality of encoded bit stream buffers, a decoded picture buffer configured to store a plurality of decoded pictures, and a decoded picture buffer data buffer configured to store a plurality of decoded picture buffer data including information on a plurality of decoded picture buffer addresses; and The system on chip is configured as: reading first input data including information about an address of a first encoded bitstream buffer from an input data buffer, reading first decoded picture buffer data including information about a first decoded picture buffer address from a decoded picture buffer data buffer, reading a first encoded bit stream stored at a first encoded bit stream buffer address, generating a first decoded picture by decoding the first encoded bitstream, and The first decoded picture is stored at a first decoded picture buffer address of the decoded picture buffer.

20. The decoding device according to claim 19, wherein The plurality of decoded picture buffer data further comprises a plurality of flag data, and The system on chip is further configured to use or update the plurality of decoded picture buffer data based on the plurality of flag data.

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