Substrate

Abstract

The invention provides a substrate, the substrate comprises a first surface layer, the first surface layer is provided with a primary power supply converter assembly and at least two primary power supply loads, the substrate comprises a first end and a second end which are opposite to each other along a first direction, the primary power supply converter assembly is arranged close to the first end, and the at least two primary power supply loads are arranged close to the second end; the first surface layer is provided with a first power supply copper foil, one end of the first power supply copper foil is electrically connected with the primary power supply converter, and the other end of the first power supply copper foil is electrically connected with at least two primary power supply loads so as to supply power to the at least two primary power supply loads. According to the invention, the primary power supply converter assembly and the plurality of primary power supply loads are respectively arranged at the two opposite ends of the substrate, and the primary power supply converter assembly supplies power to the plurality of primary power supply loads through the first power supply copper foil, so that the substrate area occupied by the first power supply copper foil is reduced; and the interference of the first power supply copper foil on other components on the substrate is reduced.

Description

Technical Field

[0001] This application relates to communication technologies, and in particular, to a substrate. Background Art

[0002] A substrate is a main component in an electronic device, and its main function is to provide connection and support for various electronic components to realize the functions of a circuit. For example, an external cable can be arranged on the substrate to realize connection with external devices, and a BUCK power module can be arranged to realize conversion and distribution of electric energy.

[0003] In the solutions of related technologies, a plurality of electronic components are also arranged on the substrate, and the BUCK power module is connected with a plurality of power copper foils, and the plurality of power copper foils are respectively connected with the plurality of electronic components for power supply. However, with the above solutions, the area of the substrate occupied by the power copper foils is relatively large, and it is easy to interfere with other components on the substrate. Summary of the Invention

[0004] In order to overcome the above defects in related technologies, the purpose of this application is to provide a substrate, which reduces the area of the substrate occupied by the power copper foils, thereby reducing the interference of the power copper foils on other components on the substrate.

[0005] On the one hand, this application provides a substrate, including a first surface layer, on which a primary power converter component and at least two primary power loads are arranged. The substrate includes a first end and a second end opposite to each other in a first direction. The primary power converter component is arranged close to the first end, and at least two of the primary power loads are both arranged close to the second end; a first power copper foil is arranged on the first surface layer, one end of the first power copper foil is electrically connected to the primary power converter, and the other end of the first power copper foil is electrically connected to at least two of the primary power loads to supply power to at least two of the primary power loads.

[0006] This application arranges the primary power converter component and a plurality of primary power loads at opposite ends of the substrate respectively, and the primary power converter component supplies power to the plurality of primary power loads through the first power copper foil, thereby reducing the area of the substrate occupied by the first power copper foil and reducing the interference of the first power copper foil on other components on the substrate.

[0007] In a possible implementation manner, the first power copper foil includes a first main power trace and at least two first power trace branches. The at least two first power trace branches are respectively connected to the first main power trace, and the at least two first power trace branches are respectively used for connecting at least two of the primary power loads; the first main power trace is electrically connected to the primary power converter component;

[0008] And / or, the first power supply copper foil includes a first main power supply trace and at least one first power supply trace branch; at least one of the first power supply trace branches is connected to the first main power supply trace, the first main power supply trace is connected to at least one of the primary power load; at least one of the first power supply trace branches is respectively used to connect at least one of the primary power load; the first main power supply trace is electrically connected to the primary power converter assembly.

[0009] In a possible implementation, the substrate includes a first inner layer, and the primary power converter assembly and at least two of the primary power loads are provided with a first ground line at the projection position of the first inner layer adjacent to the first surface layer;

[0010] The first power supply copper foil is provided with a first inner layer at an adjacent layer of the first surface layer; in a direction perpendicular to the substrate, the projection of the primary power converter assembly, the first power supply copper foil, and at least two of the primary power loads on the first inner layer overlaps with the projection of the first ground line by an area greater than or equal to 40%.

[0011] In a possible implementation, the substrate includes a substrate ground line, the primary power converter assembly includes a negative output terminal and a positive output terminal, and the negative output terminal is electrically connected to the substrate ground line; at least two of the primary power loads include ground pins, and at least two of the primary power loads are electrically connected to the substrate ground line through the ground pins.

[0012] In a possible implementation, the primary power load includes a primary electronic load, an isolation device assembly, and a second secondary electronic load; or, the primary power load includes a secondary power converter assembly and a second secondary electronic load.

[0013] In a possible implementation, a signal line and a power line are provided on a second inner layer adjacent to the first inner layer; in a direction perpendicular to the substrate, the projections of the signal line and the power line on the first surface layer overlap with the primary power converter assembly, the first power supply copper foil, and at least two of the primary power loads.

[0014] In a possible implementation, a second ground line is provided on the first surface layer, and the second ground line surrounds the primary power converter assembly, the first main power supply trace, and the at least two power supply trace branches.

[0015] In a possible implementation, the primary power converter assembly includes an output capacitor, one end of the first power supply copper foil is electrically connected to the positive electrode of the output capacitor and the positive output terminal, the substrate includes a substrate ground line, and the substrate ground line is electrically connected to the negative electrode of the output capacitor.

[0016] On the other hand, the present application provides a substrate, including a first surface layer and a second surface layer. An primary power converter assembly is provided on the first surface layer, and at least two primary power loads are provided on the second surface layer. The substrate includes a first end and a second end opposite to each other in a first direction. The primary power converter assembly is disposed near the first end, and at least two of the primary power loads are all disposed near the second end. A second power copper foil is provided on the first surface layer, and the second power copper foil is electrically connected to the power converter. A third power copper foil is provided on the second surface layer, and the third power copper foil is electrically connected to at least two primary power loads. The second power copper foil is electrically connected to the third power copper foil to supply power to at least two of the primary power loads.

[0017] In the present application, the primary power converter assembly and multiple primary power loads are respectively disposed at opposite ends of the substrate. The primary power converter assembly supplies power to multiple primary power loads through the second power copper foil and the third power copper foil, thereby reducing the area of the substrate occupied by the second power copper foil and the third power copper foil, and reducing the interference of the second power copper foil and the third power copper foil on other components on the substrate.

[0018] In a possible implementation, the third power copper foil includes a second main power trace and at least two second power trace branches. At least two of the second power trace branches are all connected to the second main power trace, and at least two of the second power trace branches are respectively used to connect at least two of the primary power loads. The second main power trace is electrically connected to the primary power converter assembly.

[0019] In a possible implementation, in a direction perpendicular to the substrate, a third inner layer is provided adjacent to the first surface layer where the second power copper foil is located. A second ground copper foil is provided at the projection position of the primary power converter assembly and the second power copper foil on the third inner layer. The projections of the primary power converter assembly and at least two primary power loads on the third inner layer all fall within the range of the second ground copper foil. The substrate includes a substrate ground line, and the second ground copper foil is electrically connected to the substrate ground line.

[0020] In a direction perpendicular to the substrate, a fourth inner layer is provided adjacent to the first surface layer or the second surface layer where the third power copper foil is located. A third ground copper foil is provided at the projection position of the third power copper foil on the fourth inner layer. The projection of the third power copper foil on the fourth inner layer all falls within the range of the third ground copper foil. The substrate includes a substrate ground line, and the third ground copper foil is electrically connected to the substrate ground line.

[0021] In a possible implementation, the primary power converter assembly includes a negative output terminal, and the negative output terminal of the primary power converter assembly is electrically connected to the substrate grounding line; the primary power load includes a grounding pin, and the grounding pin of the primary power load is electrically connected to the substrate grounding line.

[0022] In a possible implementation, the second power copper foil is connected to the positive pad of the output capacitor of the primary power converter assembly.

[0023] In a possible implementation, the primary power load includes a primary electronic load, an isolation device assembly, and a first secondary electronic load; alternatively, the primary power load includes a secondary power converter assembly and a second secondary electronic load. Description of the Drawings

[0024] To more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings required for use in the description of the embodiments or the related art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0025] Figure 1 It is a schematic diagram of the structure of the substrate in the related art;

[0026] Figure 2 For Figure 1 A cross-sectional view of the substrate at the position of the external connector;

[0027] Figure 3 It is a schematic diagram of the structure of the substrate provided by an embodiment of the present application;

[0028] Figure 4 It is a cross-sectional view of the pulsed magnetic field at a position on the substrate of the external connector and the BUCK power module provided by an embodiment of the present application;

[0029] Figure 5 It is a cross-sectional view of the pulsed magnetic field at another position on the substrate of the external connector and the BUCK power module provided by an embodiment of the present application;

[0030] Figure 6 It is a cross-sectional view of the pulsed electric field at a position on the substrate of the external connector and the BUCK power module provided by an embodiment of the present application;

[0031] Figure 7 It is a cross-sectional view of the pulsed electric field at another position on the substrate of the external connector and the BUCK power module provided by an embodiment of the present application;

[0032] Figure 8Magnetic field cross-sectional view of the MOSFET power switch provided by an embodiment of the present application at a position on the substrate;

[0033] Figure 9 Pulse electric field cross-sectional view of the MOSFET power switch provided by an embodiment of the present application at a position on the substrate;

[0034] Figure 10 Magnetic field cross-sectional view of the MOSFET power switch provided by an embodiment of the present application at another position on the substrate;

[0035] Figure 11 Pulse electric field cross-sectional view of the MOSFET power switch provided by an embodiment of the present application at another position on the substrate;

[0036] Figure 12 Cross-sectional view along one direction of the layer-changing position of the top-layer power copper foil and the first inner-layer power copper foil provided by an embodiment of the present application;

[0037] Figure 13 Cross-sectional view along another direction of the layer-changing position of the top-layer power copper foil and the first inner-layer power copper foil provided by an embodiment of the present application;

[0038] Figure 14 Structural schematic diagram of the substrate provided by another embodiment of the present application;

[0039] Figure 15 Top view of the power supply and load power supply system provided by another embodiment of the present application on the substrate;

[0040] Figure 16 For Figure 14 Cross-sectional view of the substrate in the vertical direction in;

[0041] Figure 17 Top view of the ground wire provided by an embodiment of the present application;

[0042] Figure 18 Top view of the ground copper foil provided by an embodiment of the present application;

[0043] Figure 19 Top view of the ground copper foil provided by another embodiment of the present application;

[0044] Figure 20 Top view of the ground wire provided by another embodiment of the present application;

[0045] Figure 21 Top view of the ground copper foil provided by still another embodiment of the present application;

[0046] Figure 22 Top view of the ground copper foil provided by yet another embodiment of the present application;

[0047] Figure 23Top view of the power supply and load power supply system provided by another embodiment of the present application on a substrate;

[0048] Figure 24 Top view of the power supply and load power supply system provided by yet another embodiment of the present application on a substrate. Detailed implementation manners

[0049] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application.

[0050] All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application. Without conflict, the following embodiments and the features in the embodiments may be combined with each other.

[0051] As Figure 1 and Figure 2 shown, in the solution of the related art, an external cable 74 is provided on the first surface layer at position A of the substrate. The cable is connected to an external connector on the first surface layer. The pad definition order of the external connector is divided from left to right into: pad 1: connected to the GND of the external cable 74; pad 2: connected to the input power supply VIN of the external cable 74; pad 3: connected to the SENSE pin of the external cable 74; pad 4: connected to the CAM-L of the external cable 74; pad 5: connected to the CAM-H of the external cable 74; pad 6: connected to the V_OUT1 of the external cable 74; pad 7: connected to the V_OUT2 of the external cable 74; pad 8: connected to the V_OUT3 of the external cable 74; pad 9: connected to the V_OUT4 of the external cable 74.

[0052] An external cable 74 and an external connector 69 are provided on the first surface layer of the substrate, and a BUCK power module, an LDO1 module, an LDO2 module, an LDO3 module, a bead 1, and a bead 2 are provided on the second surface layer at the position of the external cable 74.

[0053] The output capacitor of the BUCK power module (set on the second surface layer) leads out to the Vcc copper foil on the second surface layer, and is connected to the input terminals of the LDO1 module, the LDO2 module, the LDO3 module, the pad at one end of the bead 1, and the pad at one end of the bead 2 through the Vcc copper foil; vias 5, 3, and 4 are respectively led out from the output terminals of the LDO1 module, the LDO2 module, and the LDO3 module; if a power trace Vo2 is set on the second layer of via 5, a power trace Vo6 is set on the second layer of via 3, and a power trace Vo4 is set on the second layer of via 4. Vias 1 and 2 are respectively led out from the pads at the other ends of the bead 1 and the bead 2.

[0054] A Vo1 power trace is set on the second layer of via 1, a Vo2 power trace is set on the second layer of via 5, a Vo3 power trace is set on the second layer of via 6, a Vo4 power trace is set on the second layer of via 4, a Vo6 power trace is set on the second layer of via 6, and a Vo5 power trace is set on the second layer of via 2. If all power traces are set on the second layer, then all the power traces on the second layer will be adjacent to all the pads of the external connector on the first surface layer. The input voltage of the pad of pin 2 of the external connector is as high as 8 - 100V, and it is also necessary to perform a 200V - 500V surge test (the 200V surge test corresponds to the 24V engine surge test including the engine, and the 500V surge test corresponds to the 48V - 72V electric bicycle and electric motorcycle surge test). The power of 8 - 100V in the pad of pin 2 of the external connector is respectively output as 4 paths of 8 - 100V power after being controlled by 4 - way switches at the pads of pins 6, 7, 8, and 9 of the external connector.

[0055] The Vo1 power trace on the second layer is adjacent to the pad of pin 2 of the external connector, and the pad of pin 2 of the external connector contains a power supply of 8 - 100V, a 200V - 500V surge, power supply noise, and 8KV static electricity. That is, the adjacent layer (the second layer) of the Vo1 power trace on the second layer is not the GND plane. The power supply of 8 - 100V, the 200V - 500V surge, noise, and 8KV static electricity in the pad of pin 2 on the first surface layer will be coupled to the Vo1 power trace on the second layer. And the Vo1 power trace on the second layer supplies power to the Bluetooth module, so the Bluetooth module will be interfered by the power supply of 8 - 100V, the 200V - 500V surge, noise, and 8KV static electricity; if the Bluetooth module generates noise, it will also be coupled to the pad of pin 2 of the external connector on the first surface layer, and then be taken out through the external connector and the external cable 74, resulting in excessive conduction and radiation in the EMC.

[0056] The Vo2 power trace on the second layer is adjacent to the pad of pin 3 of the external connector, and the pad of pin 3 of the external connector contains noise and 8KV static electricity. That is, the adjacent layer (the second layer) of the Vo2 power trace on the second layer is not the GND plane. The noise and 8KV static electricity in the pad of pin 2 on the first surface layer will be coupled to the Vo2 power trace on the second layer. And the Vo2 power trace on the second layer supplies power to the MCU module. When the MCU module is powered, it will be interfered by noise and 8KV static electricity. If the noise generated by the MCU module is also coupled to the pad of pin 3 of the external connector on the first surface layer, and then brought out through the external connector and the external cable 74, it will cause the conduction and radiation in the EMC to exceed the standard.

[0057] The Vo3 power trace on the second layer is adjacent to the pad of pin 4 of the external connector, and the pad of pin 4 of the external connector contains noise and 8KV static electricity. That is, the adjacent layer (the second layer) of the Vo3 power trace on the second layer is not the GND plane. The noise and 8KV static electricity in the pad of pin 3 on the first surface layer will be coupled to the Vo3 power trace on the second layer. And the Vo3 power trace on the second layer supplies power to the LTE module. When the MCU module is powered, it will be interfered by noise and 8KV static electricity. If the noise generated by the LTE module through the Vo3 power trace is also coupled to the pad of pin 4 of the external connector on the first surface layer, and then brought out through the external connector and the external cable 74, it will cause the conduction and radiation in the EMC to exceed the standard.

[0058] The Vo4 power trace on the second layer is adjacent to the pad of pin 6 of the external connector, and the pad of pin 6 of the external connector contains 8 - 100V power supply, power supply noise and 8KV static electricity. That is, the adjacent layer (the second layer) of the Vo4 power trace on the second layer is not the GND plane. The 8 - 100V power supply, noise and 8KV static electricity in the pad of pin 6 on the first surface layer will be coupled to the Vo4 power trace on the second layer. And the Vo4 power trace on the second layer supplies power to the LTE module. When the LTE module is powered, it will be interfered by noise and 8KV static electricity. If the noise generated by the LTE module through the Vo4 power trace is also coupled to the pad of pin 6 of the external connector on the first surface layer, and then brought out through the external connector and the external cable 74, it will cause the conduction and radiation in the EMC to exceed the standard.

[0059] The Vo6 power trace on the second layer is adjacent to the pad of pin 7 of the external connector, and the pad of pin 7 of the external connector contains a power supply of 8 - 100V, power noise, and 8KV static electricity. That is, the adjacent layer (the second layer) of the Vo6 power trace on the second layer is not the GND plane. The 8 - 100V power supply, power noise, and 8KV static electricity in the pad of pin 7 on the first surface layer will be coupled to the Vo6 power trace on the second layer. The Vo6 power trace on the second layer supplies power to the GPS module, and the power supply to the GPS module will be interfered by the 8 - 100V power supply, power noise, and 8KV static electricity. If the noise generated by the GPS module through the Vo6 power trace is also coupled to the pad of pin 6 of the external connector on the first surface layer, and then taken out through the external connector and the external cable 74, it will cause the conduction and radiation in the EMC to exceed the standard.

[0060] The Vo5 power trace on the second layer is adjacent to the pad of pin 8 of the external connector, and the pad of pin 8 of the external connector contains a power supply of 8 - 100V, power noise, and 8KV static electricity. That is, the adjacent layer (the second layer) of the Vo5 power trace on the second layer is not the GND plane. The 8 - 100V power supply, power noise, and 8KV static electricity in the pad of pin 8 on the first surface layer will be coupled to the Vo5 power trace on the second layer. The Vo5 power trace on the second layer supplies power to the GPS module, and the power supply to the WIFI module will be interfered by the 8 - 100V power supply, power noise, and 8KV static electricity. If the noise generated by the WIFI module through the Vo5 power trace is also coupled to the pad of pin 8 of the external connector on the first surface layer, and then taken out through the external connector and the external cable 74, it will cause the conduction and radiation in the EMC to exceed the standard.

[0061] Since the Vo1 power trace, Vo2 power trace, Vo3 power trace, Vo4 power trace, Vo6 power trace, and Vo5 power trace on the second layer are routed along the Y direction of the substrate, and it is necessary to set up a CAM chip module, a charge pump module, a 485 module, and a power conversion switch on the second surface layer ( Figure 1Since there are no related components such as (not marked), etc., only some signal traces can be set in the X direction of the third layer. In this way, the signal traces on the third layer can be staggered from the Vo1 power trace, Vo2 power trace, Vo3 power trace, Vo4 power trace, Vo6 power trace, and Vo5 power trace on the second layer. Otherwise, the traces on the substrate 73 will not work. This also brings a problem, that is, the signal traces on the third layer are adjacent to the Vo1 power trace, Vo2 power trace, Vo3 power trace, Vo4 power trace, Vo6 power trace, and Vo5 power trace on the second layer, resulting in mutual interference problems. At the same time, there is no complete GND plane for the Vo1 power trace, Vo2 power trace, Vo3 power trace, Vo4 power trace, Vo6 power trace, and Vo5 power trace on the second layer in the third layer, resulting in a large return area for the Vo1 power trace, Vo2 power trace, Vo3 power trace, Vo4 power trace, Vo6 power trace, and Vo5 power trace on the second layer during transmission, generating relatively large noise and affecting their respective loads (such as LTE modules, MCU modules, WIFI modules, Bluetooth modules, GPS modules, 485 modules). Moreover, the signal traces on the third layer also need to be adjacent to the components on the second surface layer (such as charge pumps, CAM chips, 485 chips), resulting in mutual interference problems. And a GPS antenna needs to be set on the first surface layer, and a GND plane needs to be set on the first surface layer of the GPS antenna, and signal traces and power traces cannot be set.

[0062] In addition, the Vo1 power trace, Vo2 power trace, Vo3 power trace, Vo4 power trace, Vo6 power trace, and Vo5 power trace arranged on the first inner layer are basically led out from the position of the output capacitor of the BUCK power module near the second surface layer of the substrate to each load near the B end of the substrate: Bluetooth module 70, MCU module 102, LTE module 32, GPS module 31, 485 module 30, and wifi module 101. The Vo1 power trace, Vo2 power trace, Vo3 power trace, Vo4 power trace, Vo6 power trace, and Vo5 power trace arranged on the first inner layer almost span the entire substrate. The longer the trace, the greater the voltage drop. The line width of the Vo1 power trace is W1, and it is recommended that W1≥0.6mm; the line width of the Vo2 power trace is W2, and it is recommended that W2≥0.8mm; the spacing between the Vo1 power trace and the Vo2 power trace is W8, and it is recommended that W1≥0.2mm; the line width of the Vo3 power trace is W3, and it is recommended that W3≥2.5mm; the line width of the Vo4 power trace is W4, and it is recommended that W4≥0.6mm; the spacing between the Vo3 power trace and the Vo4 power trace is W10, and it is recommended that W1≥0.2mm; the line width of the Vo6 power trace is W5, and it is recommended that W5≥0.6mm; the line width of the Vo5 power trace is W6, and it is recommended that W6≥0.8mm; the spacing between the Vo6 power trace and the Vo5 power trace is W7, and it is recommended that W7≥0.2mm. The Vo1 power trace, Vo2 power trace, Vo3 power trace, Vo4 power trace, Vo6 power trace, and Vo5 power trace almost fill up the routing space of the first inner layer. If the substrate density is very high and a 4-layer board cannot be used, the number of substrate layers needs to be increased (for example, a 6-layer board), which greatly increases the cost of the substrate 73.

[0063] If all power traces are arranged on the third layer, all the power traces on the third layer will be adjacent to all the components on the second surface layer (such as 485 chip module, CAM chip module, charge pump), resulting in mutual interference. The return paths of all the power traces (Vo1 power trace, Vo2 power trace, Vo3 power trace, Vo4 power trace, Vo6 power trace, Vo5 power trace) on the third layer on the second surface layer have the problem of cross-segmentation (the return area becomes larger) due to the lack of a complete GND plane, and all the power traces on the third layer generate relatively large noise. First, it affects their corresponding loads. In addition, all the components on the second surface layer (such as 485 chip module, CAM chip module, charge pump) will also be affected by the signal quality in all the components on the second surface layer because there is no complete GND plane on the adjacent third layer. The original signal traces designed on the third layer must be arranged on the second layer, and a GND plane needs to be set below the GPS antenna body (B end), and signal traces and power traces cannot be set. The second-layer signal traces are adjacent to all the power traces on the third layer, and there is mutual interference between them.

[0064] Therefore, there are some risks in the stacking of the above substrate 73 and the layout of the power devices, which will cause mutual interference and affect signal quality, power quality, radio frequency spurious index, EMC radiation index and other issues.

[0065] In view of this, the embodiments of the present application aim to provide a substrate and an electronic device. By respectively arranging the BUCK power module and multiple electronic components at opposite ends of the substrate, and connecting the multiple electronic components to the same component power copper foil, therefore, a power copper foil is led out from the BUCK power module and electrically connected to the component power copper foil, so as to realize the power supply to the multiple electronic components, thereby reducing the area of the substrate occupied by the power copper foil and reducing the interference of the power copper foil to other components on the substrate.

[0066] The content of the embodiments of the present application will be described in detail below with reference to the drawings, so that those skilled in the art can understand the content of the present application in more detail. It should be noted that in this embodiment, the first direction is the -Z-Z direction, the second direction is the -X-X direction, and the third direction is the -Y-Y direction.

[0067] This embodiment provides a substrate 73, including a second surface layer, on which a BUCK power module 51 and multiple electronic components are provided. The substrate 73 includes a first end and a second end opposite to each other in the first direction. The BUCK power module 51 is disposed near the first end, and the multiple electronic components are all disposed near the second end. The multiple electronic components are all connected to the component power copper foil 37.

[0068] A first inner layer, on which a power copper foil 86 is provided. The power copper foil 86 is electrically connected to the BUCK power module 51 and is also electrically connected to the component power copper foil 37 to supply power to the multiple electronic components.

[0069] In this embodiment, by respectively arranging the BUCK power module 51 and multiple electronic components at opposite ends of the substrate 73, and connecting the multiple electronic components to the same component power copper foil 37, therefore, a power copper foil 86 is led out from the BUCK power module 51 and electrically connected to the component power copper foil 37, so as to realize the power supply to the multiple electronic components, thereby reducing the area of the substrate 73 occupied by the power copper foil 86 and reducing the interference of the power copper foil 86 to other components on the substrate 73.

[0070] In a possible embodiment, the power copper foil 86 and the component power copper foil 37 of this embodiment can be located on the same layer or different layers.

[0071] Preferably, the component power copper foil 37 of this embodiment is located on the second surface layer, and the power copper foil 86 is electrically connected to the component power copper foil 37 through multiple power vias.

[0072] In a possible embodiment, the component power copper foil 37 of this embodiment includes a main power trace and a plurality of power trace branches. The plurality of power trace branches are all connected to the main power trace, and the plurality of power trace branches are respectively used to connect a plurality of electronic components.

[0073] In a possible embodiment, the electronic component includes any one of a GPS module 31, an MCU module 102, an LTE module 32, an audio power amplifier module 30, a wifi module 101, and a Bluetooth module 70.

[0074] In a possible embodiment, a second surface layer power copper foil 72 is provided on the second surface layer of this embodiment. The second surface layer power copper foil 72 is connected to the positive electrode pad of the output capacitor of the BUCK power module 51, and the second surface layer power copper foil 72 is connected to the power copper foil 86 through a power via.

[0075] In a possible embodiment, the substrate 73 of this embodiment further includes a first surface layer, and the first surface layer and the second surface layer are disposed opposite to each other in a direction perpendicular to the substrate 73.

[0076] An external cable 74 and a GPS antenna 82 are provided on the first surface layer. The substrate 73 further includes a third end and a fourth end opposite to each other in a second direction. In a first direction, the external cable 74 is disposed close to the first end of the first surface layer. The external cable 74 includes a plurality of cable lines. The plurality of cable lines all extend in the first direction and are spaced apart in the second direction. One of the plurality of cable lines is a ground cable line, and the ground cable line is disposed close to the third end; a first ground copper foil G1 connected to the ground cable line is further provided on the first surface layer; the GPS antenna 82 is separated from the power copper foil 86 by the first ground copper foil G1.

[0077] In this embodiment, the GPS antenna 82 and the power copper foil 86 are separated by the first ground copper foil G1 to avoid mutual interference between the power copper foil 86 and the GPS antenna 82.

[0078] In a possible embodiment, the substrate 73 of this embodiment further includes a second inner layer. The second inner layer is adjacent to the second surface layer, and a second ground copper foil G3 is provided on the second inner layer; other components are further provided on the second surface layer. In a direction perpendicular to the substrate 73, the projection of the other components is within the projection range of the power copper foil 86, and the projections of the other components and the power copper foil 86 are both within the projection range of the second ground copper foil G3.

[0079] In this embodiment, the power copper foil 86 is separated from other components on the second surface layer by the second ground copper foil G3 to avoid mutual interference between the power copper foil 86 and other components.

[0080] Optionally, the other components of this embodiment include a power trace, a signal trace, or an R232 module 87.

[0081] This embodiment also provides an electronic device, including the substrate 73 of the above embodiment.

[0082] Specifically, as Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 shown, among which, Figure 4 , Figure 6 is Figure 3 the cross-sectional view cut along the position of the substrate edge B3 - B4 in Figure 5 , Figure 7 is Figure 3 the cross-sectional view cut along the position of the substrate edge B1 - B2 in . An external cable 74 and an external connector 69 are arranged at the A end (the first end, the same below) of the first surface layer of the substrate 73. A BUCK power module 51 is arranged at the A end of the second surface layer of the external cable 74, that is, the BUCK power module 51 is arranged at the projection of the first surface layer on the second surface layer of the external connector 69. The "-" pole pad of the output capacitor 47 in the BUCK power module 51 is connected to the ground cable line GND of the external cable 74, and the "+" pole pad of the output capacitor 47 in the BUCK power module 51 leads out the second surface layer power copper foil 72 (arranged on the second surface layer). Power vias 79 (referring to multiple power vias) are arranged on the second surface layer power copper foil 72 near the "-" pole pad of the output capacitor 47. The more the number of the power vias 79, the smaller the parasitic inductance ESL and the DC resistance ESR of the power vias 79, the smaller the voltage drop generated in the power vias 79, and at the same time, the faster the response speed of the power dynamics and the smaller the ripple on the second surface layer power copper foil 72.

[0083] The second surface layer power copper foil 72 of the second surface layer is electrically connected to the power copper foil 86 of the first inner layer after changing layers through the power vias 79. The power copper foil 86 of the first inner layer crosses the projection of the ground cable line of the external connector 69 on the first surface layer through the power vias 79. The GPS antenna 82 on the first surface layer and the R232 module 87 on the second surface layer, other modules 89 on the second surface layer are projected on the first inner layer. As Figure 4 , Figure 6As shown, since the trajectory of the power copper foil 86 in the first inner layer on the first surface layer falls on the first ground copper foil G1 and the ground cable pad of the external connector, but does not fall on the pad of pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, pin 8, pin 9 of the external connector 69. And the ground cable pad of the external connector 69 is electrically connected to the first ground copper foil G1 and belongs to the same network. They form an integral metal ground (that is, the ground cable of the external connector 69 is included by the first ground copper foil G1). A low-frequency pulse electric field e1 is formed between the power copper foil 86 in the first inner layer and the first ground copper foil G1 on the first surface layer and the ground cable pad of the external connector 69; and a pulse electric field e5 is formed between the pad of pin 2 of the external connector 69 and the third ground copper foil G2 in the first inner layer; a pulse electric field e6 is formed between the pad of pin 3 of the external connector 69 and the third ground copper foil G2 in the first inner layer; a pulse electric field e7 is formed between the pad of pin 4 of the external connector 69 and the third ground copper foil G2 in the first inner layer; a pulse electric field e8 is formed between the pad of pin 5 of the external connector 69 and the third ground copper foil G2 in the first inner layer; a pulse electric field e9 is formed between the pad of pin 6 of the external connector 69 and the third ground copper foil G2 in the first inner layer; a low-frequency pulse electric field e10 is formed between the pad of pin 7 of the external connector 69 and the third ground copper foil G2 in the first inner layer; a low-frequency pulse electric field e11 is formed between the pad of pin 8 of the external connector 69 and the third ground copper foil G2 in the first inner layer; a low-frequency pulse electric field e12 is formed between the pad of pin 9 of the external connector 69 and the third ground copper foil G2 in the first inner layer. That is, the noise, surges, and static electricity generated in the pad of pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, pin 7, pin 8, pin 9 of the external connector 69 will not be coupled to the power copper foil 86 in the first inner layer in the form of a pulse electric field. The noise generated in the power copper foil 86 in the first inner layer (including the noise generated by the BUCK power module and various loads electrically connected to the power copper foil 86 in the first inner layer) will not be coupled to the pad of pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, pin 7, pin 8, pin 9 of the external connector 69 in the form of a pulse electric field.

[0084] A low-frequency pulsed electric field e4 is generated between the power copper foil 86 of the first inner layer and the second ground copper foil G3 of the second inner layer, which is confined between the first inner layer and the second inner layer. At the projection position of the power copper foil 86 of the first inner layer on the second surface layer, an R232 module 87 and the like are provided. Although the R232 module 87 overlaps with the power copper foil 86, a pulsed electric field e14 is generated between the R232 module 87 and the second ground copper foil G3 of the second inner layer, which is confined between the second inner layer and the second surface layer. That is, the pulsed electric field e14 generated between the R232 module 87 on the second surface layer and the second ground copper foil G3 of the second inner layer and the low-frequency pulsed electric field e4 generated between the power copper foil 86 of the first inner layer and the second ground copper foil G3 of the second inner layer do not overlap in space and there is no interference between them. In addition, power traces, signal traces, etc. can also be set at the projection position of the power copper foil 86 of the first inner layer on the second surface layer. It is not necessary to set the R232 module 87. The analysis principle is the same as that of setting the R232 module 87 on the second surface layer, and it will not be described repeatedly.

[0085] As Figure 4 shown, a current i1 is generated in the power copper foil 86 of the first inner layer, and its return path on the first surface layer falls on the first ground copper foil G1 of the first surface layer and the pads of the external connector ground cable. A pulsed magnetic field B61 is generated between the power copper foil 86 of the first inner layer and the first ground copper foil G1 of the first surface layer and the pads of the external connector ground cable. And a current i10 is generated in the pad of pin 2 of the external connector 69, and its return path falls on the third ground copper foil G2 of the first inner layer. A pulsed magnetic field B13 is generated between the pad of pin 2 of the external connector 69 and the third ground copper foil G2 of the first inner layer. By analogy, the pulsed magnetic fields generated between the pads of pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, pin 8, pin 9 of the external connector 69 and the third ground copper foil G2 of the first inner layer are B13, B14, B15, B16, B17, B18, B19, B20 respectively. The return paths of the pads of pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, pin 8, pin 9 all fall on the third ground copper foil G2 of the first inner layer. Since the return ground of the power copper foil 86 of the first inner layer falls on the first ground copper foil G1 of the first surface layer and the pads of the ground cable of the external connector 69, while the pads of pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, pin 8, pin 9 of the external connector 69 fall on the third ground copper foil G2 of the first inner layer, and the pulsed magnetic fields generated between them are staggered in space. That is, there is no coupling interference between the pulsed magnetic field B61 generated by the power copper foil 86 of the first inner layer and the pulsed magnetic fields generated by the pads of pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, pin 8, pin 9 of the external connector 69.

[0086] A low-frequency pulsed magnetic field B62 is generated between the power copper foil 86 of the first inner layer and the second ground copper foil G3 of the second inner layer, which is restricted between the first inner layer and the second inner layer. At the projection position of the power copper foil 86 of the first inner layer on the second surface layer, an R232 module 87 etc. are provided (to increase the layout and wiring density of the substrate 73, reduce the size and number of layers of the substrate 73, so as to reduce the cost of the substrate). Although the R232 module 87 overlaps with the power copper foil 86, a pulsed magnetic field B21 is generated between the R232 module 87 and the second ground copper foil G3 of the second inner layer, which is restricted between the second inner layer and the second surface layer. That is, the pulsed magnetic field B21 generated by the R232 module 87 on the second surface layer and the second ground copper foil G3 of the second inner layer and the pulsed magnetic field B62 generated by the power copper foil 86 of the first inner layer and the second ground copper foil G3 of the second inner layer do not overlap in space and there is no interference between them. In addition, power traces, signal traces, etc. can also be set at the projection position of the power copper foil 86 of the first inner layer on the second surface layer. It is not necessary to set the R232 module 87. The analysis principle is the same as that of setting the R232 module 87 on the second surface layer and will not be repeated.

[0087] Such as Figure 3 , Figure 6As shown, a ground wire 84 is provided at a position of the power supply copper foil 86 of the first inner layer close to the left board edge B3. Spaced ground vias 90 are provided on the ground wire 84 along the left board edge. The ground vias 90 achieve low-impedance electrical connection between the ground wire 84 and the first ground copper foil G1 of the first surface layer, the second ground copper foil G3 of the second inner layer, and the ground copper foil G4 of the second surface layer. A third ground copper foil G2 is provided on the right side of the power supply copper foil 86 of the first inner layer. The projection trajectory of the power supply copper foil 86 of the first inner layer on the second inner layer is the second ground copper foil G3 of the second inner layer; that is, the upper, lower, left, and right of the power supply copper foil 86 of the first inner layer are all ground copper foils, belonging to three-dimensional ground wrapping. Since the ground cable of the external connector 69 overlaps with the power supply copper foil 86 of the first inner layer in the vertical direction (Y direction) of the substrate 73, and the power supply copper foil 86 of the first inner layer does not overlap with other functional pins of the external connector 69 in the vertical direction (Y direction) of the substrate 73, it will not cause mutual interference between it and the functional pins of the external connector 69, and there will be no adjacent problems caused by cross-segmentation. Nor will the noise generated in the power supply copper foil 86 of the first inner layer (including the noise generated by the BUCK power module and the noise generated by various loads electrically connected to the power supply copper foil 86 of the first inner layer) be coupled to the pad of each pin of the external connector 69 and the external cable 74 in the form of pulsed electric field and pulsed magnetic field, resulting in excessive EMC radiation or conduction. The noise, surge, and static electricity generated by the pad of each pin of the external connector 69 and the external cable 74 will not be coupled to the power supply copper foil 86 of the first inner layer. At the same time, the power supply copper foil 86 of the first inner layer and the signal traces, power traces, or components (including sensitive components and strongly interfering components) provided at the position where the power supply copper foil 86 is projected on the second surface layer are separated by the second ground copper foil G3 of the second inner layer, and there will be no mutual influence between the power supply copper foil 86 of the first inner layer and the signal traces, power traces, or components provided at the position where the power supply copper foil 86 is projected on the second surface layer. Therefore, the position of the power supply copper foil 86 of the first inner layer is scientific and reasonable.

[0088] On the ground pin of the external connector 69 on the first surface layer ( Figures 3 to 7The projection of the middle ground pin, which can be a ground cable or not, sets the power copper foil 86 at the first inner layer position. The projection of the ground pin of the external connector 69 sets the second ground copper foil G3 at the second inner layer position, and the projection of the ground pin of the external connector 69 sets signal traces, power traces, or components at the second surface layer position. This not only saves the layout space on both sides of the substrate 73 but also eliminates the mutual interference between the functional pins of the first surface layer external connector 69 and the power copper foil 86 at the first inner layer. At the same time, there is no mutual interference between the power copper foil 86 at the first inner layer and the signal traces, power traces, or components set at the second surface layer position. Therefore, this setting position is scientific and reasonable. In addition, components are set on both the front and back sides of the position of the substrate external connector 69, which greatly improves the density of the entire substrate 73, saves the substrate layout space, saves the substrate area, that is, saves the cost of the substrate 73.

[0089] Continue to refer to Figure 3 、 Figure 5 and Figure 7 As shown, since the first ground copper foil G1 is set at the projection of the GPS antenna 82 on the first surface layer, a high-frequency pulsed electric field e22 (1.575 GHz) is formed between the GPS antenna 82 and the first ground copper foil G1, providing good conditions for the GPS antenna 82 to receive signals emitted by near-earth orbit satellites. A low-frequency pulsed electric field e1 is formed between the power copper foil 86 at the first inner layer and the first ground copper foil G1 at the first surface layer. Although the power copper foil 86 at the first inner layer and the GPS antenna 82 at the first surface layer overlap in the vertical direction, the low-frequency pulsed electric field e1 generated by the power copper foil 86 and the high-frequency pulsed electric field e22 generated by the GPS antenna 82 are spatially separated by the third ground copper foil G2 at the first inner layer, that is, there is no coupling interference between the power copper foil 86 at the first inner layer and the GPS antenna 82 in the spatial pulsed electric field.

[0090] At the overlapping position of the GPS antenna 82 on the first surface layer, the power copper foil 86 at the first inner layer, and a certain functional module 89 on the second surface layer (which can be a GPS module, an RR232 module, a 485 module, etc., without restricting the type of components), a low-frequency pulsed electric field e2 is formed between the power copper foil 86 at the first inner layer and the second ground copper foil G3 of L02, and a pulsed electric field e13 is formed between the certain functional module 89 on the second surface layer and the second ground copper foil G3 of L03. Although the power copper foil 86 at the first inner layer and the certain functional module 89 on the second surface layer overlap in the vertical direction, the low-frequency pulsed electric field e1 generated by the power copper foil 86 and the pulsed electric field e13 generated by the certain functional module 89 on the second surface layer are spatially separated by the third ground copper foil G2 at the first inner layer, that is, there is no coupling interference between the power copper foil 86 at the first inner layer and the certain functional module 89 on the second surface layer in the spatial pulsed electric field.

[0091] A current i1 is generated in the power supply copper foil 86 of the first inner layer. A pulsed magnetic field B61 is generated between the power supply copper foil 86 of the first inner layer and the first ground copper foil G1 of the first surface layer. A pulsed magnetic field B62 is generated between the power supply copper foil 86 of the first inner layer and the second ground copper foil G3 of the second inner layer. A current i19 is generated in a certain functional module 89 of the second surface layer. A pulsed magnetic field B22 is generated between the certain functional module 89 of the second surface layer and the second ground copper foil G3 of the second inner layer. Although the power supply copper foil 86 of the first inner layer and the certain functional module 89 of the second surface layer overlap in the vertical direction, the low-frequency pulsed magnetic field B62 generated by the power supply copper foil 86 and the pulsed magnetic field B22 generated by the certain functional module 89 of the second surface layer are spatially separated by the second ground copper foil G3 of the second inner layer. That is, there is no coupling interference in the spatial pulsed magnetic field between the power supply copper foil 86 of the first inner layer and the certain functional module 89 of the second surface layer. Although the power supply copper foil 86 of the first inner layer and the GPS antenna 82 of the first surface layer overlap in the vertical direction, the low-frequency pulsed magnetic field B62 generated by the power supply copper foil 86 and the pulsed magnetic field B70 generated by the GPS antenna 82 are spatially separated by the first ground copper foil G1 of the first surface layer. That is, there is no coupling interference in the pulsed magnetic field in space between the power supply copper foil 86 of the first inner layer and the GPS antenna of the first surface layer.

[0092] The power supply copper foil 86 is arranged at the position of the projection of the GPS antenna 82 of the first surface layer in the first inner layer. The second ground copper foil G3 is arranged at the position of the projection of the power supply copper foil 86 of the first inner layer in the second inner layer. Signal traces, power traces or components are arranged at the position of the projection of the power supply copper foil 86 of the first inner layer in the second surface layer. This not only saves the layout space on the front and back sides of the substrate, but also there is no mutual interference between the GPS antenna 82 of the first surface layer and the power supply copper foil 86 of the first inner layer. At the same time, there is no mutual interference between the power supply copper foil 86 of the first inner layer and the signal traces, power traces or components arranged at the position of the second surface layer. Therefore, this arrangement position is scientific and reasonable. In addition, components are arranged on both the front and back sides of the GPS position of the substrate, so that the density of the entire substrate 73 is greatly increased, saving the substrate layout space and the substrate area, that is, saving the cost of the substrate 73.

[0093] The ground cable pad in the external connector 69 is connected to the ground cable pin in the external connector 69. The ground cable pin in the external connector 69 is connected to the external cable 1 (connected to GND), providing a ground loop for each functional pin such as the input power supply VIN of the external cable. The pad of pin 2 in the external connector 69 is connected to the pin of pin 2 in the external connector 69. The pin of pin 2 in the external connector 69 is connected to the external cable 2 (input power supply VIN).

[0094] A BUCK power module 51 is provided at the position where the external cable 74 and the external connector 69 are projected on the second surface layer. The BUCK power module 51 includes an input clamping and filtering circuit (not shown in the figure) and a BUCK power supply (not shown in the figure). One end of the input clamping and filtering circuit is connected to the pad of pin 2 in the external connector 69, and the other end of the input clamping and filtering circuit is connected to the input end of the BUCK power supply. The input clamping and filtering circuit and the BUCK power supply are both connected to the ground cable pad in the external connector 69. The "-" pole pad (i.e., the negative pole pad) of the output capacitor 47 of the BUCK power supply is connected to all the ground copper foils of the substrate 73, and the external power cable 74, the external power connector 69, and the BUCK power module 51 form a loop. The "+" pole pad (i.e., the positive pole pad) of the output capacitor 47 of the BUCK power supply leads out the second surface layer power copper foil 72 to supply VCC to the entire substrate 73.

[0095] The external cable 74 and the external connector 69 inject a surge voltage of 200V to 500V into the BUCK power module 51, contact an 8KV electrostatic discharge, and there are various noises on the vehicle or on the motorcycle.

[0096] Technical features: The substrate is long and strip-shaped. The external cable 74 and the external connector 69 are provided on the right side (the first surface layer of the substrate 73) above the substrate 73 (end A). The Bluetooth antenna and its clearance area are provided on the left side above the substrate 73 (end A) (the Bluetooth antenna radiator is provided on the first surface layer of the substrate 73). The LTE antenna and its clearance area are provided below the substrate 73 (end B) (the LTE antenna radiator is provided on the second surface layer of the substrate 73). The GPS antenna is provided between the external connector 69 and the LTE antenna and its clearance area. The metal component bodies around the GPS antenna body satisfy a 45-degree angle.

[0097] A. If the GPS antenna is placed on the second surface layer of the substrate, the GPS antenna will be on the same layer as the radiator of the LTE antenna, and the GPS antenna will be interfered by the LTE antenna. Therefore, the GPS antenna is preferably placed between the external connector 69 and the LTE antenna and its clearance area, and on the front of the substrate. The GPS antenna and the LTE antenna are distributed on different layers of the substrate to reduce the coupling of the LTE antenna transmitting signal to the GPS antenna and affect the sensitivity of the GPS antenna receiving satellite signals, etc.

[0098] B. Surge voltages of 200V to 500V are injected into the BUCK power module through the external cable 74 and the external connector 69, and it is exposed to 8KV electrostatic discharge, as well as various noises in cars or motorcycles. The external cable 74 and the external connector 69 need to be close to the upper part of the substrate 73, which is convenient for leading out the external cable 74 from the plastic housing (not shown in the figure). In addition, the external cable 74 and the external connector 69 (which are large metal parts) should be as close as possible to the upper edge (A end) of the substrate 73, and a certain distance can be maintained from the GPS antenna to meet the requirement that the metal component bodies around the GPS antenna body have a 45-degree reception angle, and at the same time, avoid the interference of the 200V to 500V surge voltage, 8KV electrostatic discharge, various noises in cars or motorcycles in the external connector 69 to the GPS antenna.

[0099] C. Since the external cable 74 and the external connector 69 are arranged on the first surface layer close to the upper edge (A end) of the long strip-shaped substrate 73, while the LTE antenna and its clearance area are arranged close to the lower edge (B end) of the long strip-shaped substrate 73. The external cable 74 and the external connector 69 are far from the TE antenna and its clearance area, and the LTE antenna will not be interfered by the 200V to 500V surge voltage, 8KV electrostatic discharge, various noises in cars or motorcycles in the external connector 69.

[0100] D. The input terminal of the BUCK power module is subject to a surge voltage of 200V to 500V, contact with 8KV electrostatic discharge, various noises in automobiles or motorcycles, and the switching noise generated by the BUCK power supply in the BUCK power module, which has strong interference on the GPS antenna, GPS module, LTE module, LTE antenna, Bluetooth module, and Bluetooth antenna. Therefore, the BUCK power module is preferably placed in the projection area of the external cable 74 (first surface layer) and the external connector 69 (first surface layer) on the second surface layer of the substrate. The switching circuits of the input capacitor, switching transistor, freewheeling diode, inductor, and output capacitor in the BUCK power supply generate noises including: pulsed pulse electric field radiation, pulsed magnetic field radiation generated by the inductor, etc. The GPS antenna on the first surface layer is an extremely sensitive component. Placing the BUCK power module at the projection position of the GPS antenna on the second surface layer, the input terminal of the BUCK power module has a surge voltage of 200V to 500V, contact with 8KV electrostatic discharge, various noises in automobiles or motorcycles, and the pulsed pulse electric field radiation and pulsed magnetic field radiation generated by the inductor in the BUCK power supply may be coupled into the GPS antenna, and the common ground noise of the freewheeling diode will also be coupled into the G1 ground copper foil adjacent to the GPS antenna and the GPS module. Therefore, the BUCK power module cannot be placed on the second surface layer corresponding to the GPS antenna (first surface layer) to avoid interference to the GPS antenna. The external cable 74 and external connector 69 on the first surface layer are not sensitive components. Placing the BUCK power module in the projection area of the external cable 74 and external connector 69 on the first surface layer on the second surface layer will not affect the normal functions of the external cable 74 and external connector 69. At the same time, the VIN power supply of the external cable 74 and external connector 69 is closer to the BUCK power module, the loop of the VIN power supply trace is shorter, the voltage drop on the VIN power supply trace is smaller, and the interference to other parts is smaller.

[0101] E. Figure 8 A partial cross-section of the external cable + Bluetooth antenna + BUCK power supply on the substrate 73 is given Figure 1 , Figure 4 A partial cross-section of the external cable + Bluetooth antenna + BUCK power supply on the substrate 73 is given Figure 2 . As Figure 8 , Figure 4 shown, the BUCK power module 43 presents an input capacitor 104, a BUCK chip 105, an inductor 106, and an output capacitor 107, and in the input clamping and filtering circuit Figure 8 , Figure 4Unlabeled, with a very compact layout. A shielding cover is added to the BUCK power module 43 mainly to avoid radiation interference to the left Bluetooth antenna and at the same time reduce the EMI radiation and spurious indexes of the BUCK power module 43 to the whole machine. At least one layer of ground copper foil (such as at least one of the first ground copper foil G1 on the first surface layer, the third ground copper foil G2 on the first inner layer, the second ground copper foil G3 on the second inner layer, and the ground copper foil G4 on the L4 layer) needs to be set on the substrate between the BUCK power module 43 (second surface layer) and the external cables 74 and external connectors 69 on the first surface layer to separate the BUCK power module 43 (second surface layer) from the external cables 74 and external connectors 69 on the first surface layer (the most important technical feature). That is, the BUCK power module 43 on the second surface layer is covered by at least one of the first ground copper foil G1 on the first surface layer, the third ground copper foil G2 on the first inner layer, the second ground copper foil G3 on the second inner layer, and the ground copper foil G4 on the L4 layer, and the external cables 74 and external connectors 69 on the first surface layer are covered by at least one of the first ground copper foil G1 on the first surface layer, the third ground copper foil G2 on the first inner layer, the second ground copper foil G3 on the second inner layer, and the ground copper foil G4 on the L4 layer. There are two purposes: at least one layer of ground copper foil provides a complete return path for the BUCK power module 43 on the second surface layer, which can minimize the switching noise generated by the BUCK power module 43, reduce the conduction and space radiation interference to the board components, and reduce external radiation (improve spurious and EMI radiation indexes). At the same time, the 200V - 500V surge voltage, 8KV contact discharge, various noises in the car or various noises on the motorcycle in the external cables 74 and external connectors 69 on the first surface layer will not be coupled to the BUCK power module 43, but will be coupled to at least one of the first ground copper foil G1 on the first surface layer, the third ground copper foil G2 on the first inner layer, the second ground copper foil G3 on the second inner layer, and the ground copper foil G4 on the L4 layer, and will not cause interference to the BUCK power module 43. The switching noise radiation generated in the BUCK power module 43 will not be coupled to the external cables 74 and external connectors 69 on the first surface layer, resulting in excessive radiation and conduction.

[0102] F. If the BUCK power module 43 on the second surface layer overlaps with the Bluetooth module, GPS module, LTE module, audio codce module, etc. on the first surface layer vertically, the switching noise in the BUCK power module 43 will be coupled to the Bluetooth module, GPS module, and LTE module on the first surface layer, resulting in deterioration of the performance indexes of the Bluetooth module, GPS module, LTE module, and audio codce module. Therefore, the best solution is to place the BUCK power module 43 on the second surface layer in the projection area of the external cables 74 and external connectors 10 on the second surface layer.

[0103] G. Such as Figure 8 、 Figure 4As shown, the BUCK chip 105 internally integrates an upper MOSFET (not shown in the figure) and a lower MOSFET (or a freewheeling diode, not shown in the figure). The upper MOSFET integrated in the BUCK chip 105 is connected to the input capacitor 104, while the lower MOSFET integrated in the BUCK chip 105 is connected to at least one of the ground copper foils of the first ground copper foil G1 on the first surface layer, the third ground copper foil G2 on the first inner layer, the second ground copper foil G3 on the second inner layer, and the ground copper foil G4 on the L4 layer through the ground pin 42 of the BUCK chip 105 and the ground via 45. The connection position of the upper MOSFET and the lower MOSFET integrated in the BUCK chip 105 leads out a pin and is connected to one end of the inductor 106, and the other end of the inductor 106 is connected to the output capacitor 107. When the upper MOSFET integrated in the BUCK chip 105 is turned on, a loop is formed from the input capacitor 104 to the upper MOSFET integrated in the BUCK chip 105, the inductor 106, and the output capacitor 107, generating a low-frequency pulsed magnetic field B1; when the upper MOSFET integrated in the BUCK chip 105 is turned off and the lower MOSFET is turned on, the energy stored in the inductor 106 passes through the lower MOSFET, the ground pin 42 of the BUCK chip 105, the ground via 45 to at least one of the ground copper foils of the first ground copper foil G1 on the first surface layer, the third ground copper foil G2 on the first inner layer, the second ground copper foil G3 on the second inner layer, and the ground copper foil G4 on the L4 layer, the load, and the output capacitor 107 to the inductor 106 to form a loop, generating a low-frequency pulsed magnetic field B2; the low-frequency pulsed magnetic field B1 and the low-frequency pulsed magnetic field B2 are restricted between the second surface layer and at least one of the ground copper foils of the first ground copper foil G1 on the first surface layer, the third ground copper foil G2 on the first inner layer, the second ground copper foil G3 on the second inner layer, and the ground copper foil G4 on the L4 layer. With the external shielding cover 14 of the BUCK power module 43, the low-frequency pulsed magnetic field B1 and the low-frequency pulsed magnetic field B2 hardly leak outwards; low-frequency pulsed electric fields e1, e2, e3, and e4 are respectively formed between the input capacitor 104, the BUCK chip 105, the inductor 106, the output capacitor 107 and at least one of the ground copper foils of the first ground copper foil G1 on the first surface layer, the third ground copper foil G2 on the first inner layer, the second ground copper foil G3 on the second inner layer, and the ground copper foil G4 on the L4 layer. Due to the existence of at least one of the ground copper foils of the first ground copper foil G1 on the first surface layer, the third ground copper foil G2 on the first inner layer, the second ground copper foil G3 on the second inner layer, and the ground copper foil G4 on the L4 layer, the low-frequency pulsed electric fields e1, e2, e3, and e4 are not coupled to the external cable 74 and the external connector 69, and the generated noise radiation will not be coupled to the external cable 74 and the external connector 69 to cause excessive EMI radiation, conduction, and spurious emissions.Due to the addition of the shielding cover 14 to the BUCK power module 43, the low-frequency pulsed magnetic field and low-frequency pulsed electric field generated inside the BUCK power module 43 are suppressed inside the shielding cover 14 and will not interfere with other components on the board (such as the Bluetooth antenna, Bluetooth module, GPS module, etc. set beside the BUCK power module 43).

[0104] H. The output capacitor 107 of the BUCK power module 43 generates a stepped-down and stabilized power supply, which is output to supply power to the entire board.

[0105] As previously introduced, the external cable 74 and the external connector 69 are set at the A end of the first surface layer above the substrate 73, and the BUCK power module 51 is preferably set in the projection area of the external cable 74 and the external connector 69 on the second surface layer.

[0106] As Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 As shown, the second surface layer power copper foil 72 is led out from the positive pad of the output capacitor 107 of the BUCK power supply 51 on the second surface layer, and a power via 79 is set at the position of the second surface layer power copper foil 72 close to the positive pad of the output capacitor 107. The power copper foil 86 is led out at the first inner layer of the power via 79. The power copper foil 86 passes through the projection of the first surface layer GPS antenna 82 and the R232 module 87 / a certain functional module 89 on the second surface layer on the first inner layer, that is, although the power copper foil 86 overlaps with the first surface layer GPS antenna 82 and the R232 module 87 / a certain functional module 89 on the second surface layer in the vertical substrate direction (Y direction), since the first surface layer first ground copper foil G1 is set between the power copper foil 86 on the first inner layer and the first surface layer GPS antenna 82, they are separated by the first ground copper foil G1 of the L1 layer, and they are not directly adjacent to each other and there is no mutual interference; the second inner layer second ground copper foil G3 is set between the power copper foil 86 on the first inner layer and the R232 module 87 / a certain functional module 89 on the second surface layer, and they are separated by the second ground copper foil G3 of the second inner layer, and they are not directly adjacent to each other and there is no mutual interference.

[0107] The power copper foil 86 on the first inner layer is led to the area outside the projection of the GPS antenna 82 to set power vias 78 (referring to multiple power vias), and the layer is changed to the component power copper foil 37 on the second surface layer through the power vias 78. The component power copper foil 37 on the second surface layer is connected to the power trace branches 6, power trace branches 5, power trace branches 71, bead 81, and power trace branches 22 on the second surface layer.

[0108] The power trace branch 6 is connected to the capacitor 10 on the second surface layer and the input terminal of the low dropout linear regulator 19. The output terminal of the low dropout linear regulator 19 on the second surface layer and the positive pad of the capacitor 16 are connected to the GPS module on the second surface layer through the power trace 18 on the second surface layer. The power trace branch 5 is connected to the capacitor 68 on the second surface layer and the input terminal of the low dropout linear regulator 13 on the second surface layer. The output terminal of the low dropout linear regulator 13 on the second surface layer and the capacitor 69 are connected to the MCU module 102 on the second surface layer through the power trace 15. One end of the component power copper foil 37 on the second surface layer is connected to one end of the bead 76. The other end of the bead 76, the positive pad of the large capacitor 97 on the second surface layer, and the positive pad of the small capacitor 98 are connected to the audio power amplifier module 30 on the second surface layer through the power trace 75 on the second surface layer. One end of the component power copper foil 37 is connected to one end of the bead 81. The other end of the bead 81, the positive pad of the large capacitor 95, and the positive pad of the small capacitor 96 are connected to the wifi module 101 through the power trace 77 on the second surface layer. The power trace branch 22 is connected to the capacitor 21 on the second surface layer and the input terminal of the low dropout linear regulator 24 on the second surface layer. The output terminal of the low dropout linear regulator 24 on the second surface layer and the capacitor 27 are connected to the Bluetooth module 70 on the second surface layer through the power trace 26.

[0109] The setting idea is that when the BUCK power module 51 cannot be close to each load terminal for various reasons, various loads (such as GPS module 31, MCU module 102, LTE module 32, audio power amplifier module 30, wifi module 101, Bluetooth module 70), power conversion switches (such as MOSEFT power switch 20), power converters (such as low-dropout linear regulators 19, 13, 24, etc.), and beads / inductors / resistors (such as beads 76, 81, etc.) are concentrated and close. In this way, the power supply copper foil 86 led out from the BUCK power module 51 can be led to the second surface layer (or the first surface layer). On the second surface layer (or the first surface layer), a power supply copper foil 78 is used to connect the input ends of the power converters (on the second surface layer or the first surface layer), the input ends of the power conversion switches (on the second surface layer or the first surface layer), and one end of the beads / inductors / resistors (on the second surface layer or the first surface layer). There is no need to punch power vias to change layers to connect the power supply traces of each load. In this way, it is ensured that the entire power supply system from the power supply copper foil 78 to the load (such as the LTE module) does not need to punch power vias to change layers (eliminating the voltage drop problem caused by power vias and the problem of power vias occupying the precious space of the high-density substrate). Nor is it like in the prior art where multiple independent power supply traces are led out from the output end of the BUCK power module 51 to the load end (not only do multiple power supply traces occupy the PCB trace space, but multiple independent power supply traces punching through and changing layers occupy a large amount of space). This greatly saves the substrate trace space and at the same time reduces the problems caused by excessive via distributed inductance of multiple independent power supply traces punching through and changing layers, such as excessive voltage drop, increased power ripple, interference problems, cross-cutting return problems, and EMI radiation problems when multiple independent power supply traces are adjacent to signal traces; interference problems, cross-cutting return problems, EMI radiation problems, electrostatic coupling problems, and surge coupling problems when multiple independent power supply traces are adjacent to the pad of multiple pins of the connector.

[0110] At the same time, on the second surface layer (or the first surface layer), a ground copper foil (such as the second ground copper foil G3 is set on the second inner layer) is set for the power supply copper foil 78, power converters, power conversion switches, beads / inductors / resistors, or loads (such as the LTE module) projected on the adjacent layer. In this way, it is ensured that there is a complete second ground copper foil G3 on the adjacent layer of the entire power supply system from the power supply copper foil 78 to the load (such as the LTE module) to provide the shortest return path for the power supply copper foil 78 to the load (such as the LTE module).

[0111] Taking the LTE module 32 + MOSFET power switch 20 and the component power supply copper foil 37 set on the first surface layer (it can also be set on the second surface layer) as an example for illustration.

[0112] Among them, Figure 8 、 Figure 9 is the partial cross-sectional view along the Figure 3 position of the MOSFET power switch A9 - A10 inFigure 10 , Figure 11 is the partial cross-sectional view along the position of MOSFET power switch A7 - A8 in Figure 3 . Figure 16 The cross-sectional view in the X - X direction (position A1 - A2) of the layer-changing position of the top-layer power copper foil and the first inner-layer power copper foil is given; Figure 17 The cross-sectional view in the Z - Z direction of the layer-changing position of the top-layer power copper foil and the first inner-layer power copper foil is given. Figure 16 , Figure 17 is Figure 3 the cross-sectional views at different angles along the positions of power via 76 and ground via 110 in

[0113] Such as Figure 8 , Figure 9As shown, the source pin 68 of the MOSFET power switch 20, the component power copper foil 37, the drain pin 67 of the MOSFET power switch 20, and the power copper foil 63 are oriented in the Z direction. The MOSFET power switch 20 projects a third ground copper foil G2 on the first inner layer; the source pin 68 of the MOSFET power switch 20 on the first surface layer, the component power copper foil 37, the drain pin 67 of the MOSFET power switch 20, and the power copper foil 63 form a pulsed electric field e31 with the third ground copper foil G2 on the first inner layer, which is confined to a very narrow space between the first surface layer and the first inner layer; a current i6 is generated in the source pin 68 of the MOSFET power switch 20 on the first surface layer, the component power copper foil 37, the drain pin 67 of the MOSFET power switch 20, and the power copper foil 63, and a magnetic field B6 is formed between the source pin 68 of the MOSFET power switch 20 on the first surface layer, the component power copper foil 37, the drain pin 67 of the MOSFET power switch 20, and the power copper foil 63 and the third ground copper foil G2 on the first inner layer. The MOSFET power switch 20 projects signal traces 671, 541, 531 along the X direction of the substrate on the second inner layer; the signal traces 671, 541, 531 on the second inner layer form pulsed electric fields e30, e32, e33 with the third ground copper foil G2 on the first inner layer respectively, which are confined to a very narrow space between the first inner layer and the second inner layer. The pulsed electric fields e30, e32, e33 and the pulsed electric field e31 are separated by the third ground copper foil G2 on the first inner layer and are not in the same space, so there is no coupling interference between the pulsed electric fields of the signal traces 671, 541, 531 on the second inner layer and the MOSFET power switch 20, the component power copper foil 37, and the power copper foil 63 on the first surface layer. The source pin 68 of the MOSFET power switch 20 on the first surface layer, the component power copper foil 37, the drain pin 67 of the MOSFET power switch 20, and the power copper foil 63 form a planar capacitor with the third ground copper foil G2 on the first inner layer. The ESL of the PCB planar capacitor is very small and can filter out noise up to several GHz, so as to reduce the noise radiation interference to the external space of the source pin 68 of the MOSFET power switch 20 on the first surface layer, the component power copper foil 37, the drain pin 67 of the MOSFET power switch 20, the power copper foil 63, etc., and at the same time reduce the external EMI radiation, conduction, and radio frequency spurs. Such as Figure 9As shown, taking the example of forming a PCB parallel-plate capacitor C with the source pin 68 of the MOSFET power switch 20 on the first surface layer, the component power copper foil 37, the drain pin 67 of the MOSFET power switch 20, the power copper foil 63 and the third ground copper foil G2 on the first inner layer. L is the series equivalent inductance of the PCB parallel-plate capacitor C, and R is the series equivalent resistance of the PCB parallel-plate capacitor C. As shown in Table 2, between the source pin 68 of the MOSFET power switch 20 on the first surface layer of the substrate 73, the component power copper foil 37, the drain pin 67 of the MOSFET power switch 20, the power copper foil 63 and the third ground copper foil G2 on the first inner layer is PP (semi-cured sheet, a sheet-shaped bonding material synthesized from resin and carrier, that is, fiberglass epoxy resin material, abbreviated as FR-4 medium), and the dielectric constant of the FR-4 medium is 3.5 - 4.5. For the parallel-plate capacitor C formed between the source pin 68 of the MOSFET power switch 20 on the first surface layer of the substrate 73, the component power copper foil 37, the drain pin 67 of the MOSFET power switch 20, the power copper foil 63 and the third ground copper foil G2 on the first inner layer, the following is the calculation formula for the PCB parallel-plate capacitor C:

[0114] C = ε × ε0 × S / d

[0115] In the formula:

[0116] The parallel-plate capacitor C, unit F.

[0117] ε is the dielectric constant of the PP (semi-cured sheet, a sheet-shaped bonding material synthesized from resin and carrier, that is, fiberglass epoxy resin material, abbreviated as FR-4 medium) between the source pin 68 of the MOSFET power switch 20 on the first surface layer of the substrate 73, the component power copper foil 37, the drain pin 67 of the MOSFET power switch 20, the power copper foil 63 and the third ground copper foil G2 on the first inner layer. Usually, the dielectric constant of the FR-4 medium is 3.5 - 4.5.

[0118] ε0 is the dielectric constant of vacuum: 8.86×10-12 F / m.

[0119] S is the area, that is, the overlapping area between the source pin 68 of the MOSFET power switch 20 on the first surface layer of the substrate 73, the component power copper foil 37, the drain pin 67 of the MOSFET power switch 20, the power copper foil 63 and the third ground copper foil G2 on the first inner layer. Since it is required that the projections of the source pin 68 of the MOSFET power switch 20 on the first surface layer, the component power copper foil 37, the drain pin 67 of the MOSFET power switch 20, and the power copper foil 63 on the third ground copper foil G2 on the first inner layer all fall within the range of the third ground copper foil G2 on the first inner layer, only the areas of the source pin 68 of the MOSFET power switch 20 on the first surface layer, the component power copper foil 37, the drain pin 67 of the MOSFET power switch 20, and the power copper foil 63 need to be calculated.

[0120] d is the distance between the plates, that is, the distance between the source pin 68 of the MOSFET power switch 20 on the first surface layer, the component power copper foil 37, the drain pin 67 of the MOSFET power switch 20, the power copper foil 63 and the third ground copper foil G2 on the first inner layer (that is, the PP thickness, generally 3 mil to 8 mil). The unit of the distance between the plates is m.

[0121] The distance between the source pin 68 of the MOSFET power switch 20 on the first surface layer, the component power copper foil 37, the drain pin 67 of the MOSFET power switch 20, the power copper foil 63 and the third ground copper foil G2 on the first inner layer is 3 mil to 8 mil (recommended to be 4 mil). The reflux area is very small, and the noise generated in the component power copper foil 37 and the power copper foil 63 radiated externally is very small. At the same time, the component power copper foil 37 and the power copper foil 63 will not generate mutual pulse electric field and magnetic field interference with the signal traces 671, 541, 531 because they are not in the same space and are separated by the third ground copper foil G2 on the first inner layer.

[0122] The projections of the MOSFET power switch 20 on the second surface layer are provided with signal traces 67, 54, 53 along the Z direction. The signal traces 67, 54, 53 on the second surface layer and the third ground copper foil G2 on the first inner layer form pulsed electric fields e34, e35, e36. The signal traces 67, 54, 53 on the second surface layer and the third ground copper foil G2 on the first inner layer form pulsed magnetic fields B1, B2, B3. The signal traces 67, 54, 53 on the second surface layer and the signal traces 671, 541, 531 on the second inner layer are staggered by 90 degrees from each other. Therefore, the pulsed electric field and pulsed magnetic field coupling between them is relatively small, and it will not affect their normal operation. The pulsed magnetic field and pulsed electric field generated by the signal traces 67, 54, 53 on the second surface layer and the source pin 68 of the MOSFET power switch 20 on the first surface layer, the component power copper foil 37, the drain pin 67 of the MOSFET power switch 20, and the power copper foil 63 are not in the same space. Therefore, there is no interference problem between them. Therefore, this stack structure can accommodate two layers of signal traces (such as the signal traces 67, 54, 53 on the second surface layer and 671, 541, 531 on the second inner layer) and one layer of power trace (such as the component power copper foil 37 and the power copper foil 63), and power devices (such as the MOSFET power switch 20, the large capacitors 12 / 52, and the small capacitors 63 / 64) at the same position. Without increasing the number of substrate layers or the area, the layout and wiring density of the substrate 73 space is greatly increased, thus taking into account both the performance of the product and the cost of the substrate.

[0123] Such as Figure 10 , Figure 11As shown, the VCC power supply is generated from the "+" pole pad of the output capacitor 107 in the BUCK power module 51 and the second surface layer power supply copper foil 72, and is changed to the first inner layer power supply copper foil 86 through the power via 79 to the power via 78, and then changed to the first surface layer (or the second surface layer) component power supply copper foil 37 and sent to the MOSFET power switch 20. The cross-sectional view along the positions of the power pins 33 / 39 of the LTE module 32, the large capacitor 52, the small capacitor 64, the power supply copper foil 63, and the MOSFET power switch 20, that is, the cross-sectional view at the A7 - A8 position. The MOSFET power switch 20, the small capacitor 64, the large capacitor 52, and the power pins 33 / 39 of the LTE module 32 are electrically connected through the power supply copper foil 63, and the third ground copper foil G2 is arranged on their adjacent layers. The ground via 110 is arranged near the power via 78. The ground via 110 is used to provide a return path for the ground copper foil of different layers when the first surface layer component power supply copper foil 37 is changed to the first inner layer power supply copper foil 86 through the power via 78. The distance between the ground via 110 and the power via 78 shall not exceed 20 mm. The closer the distance between the ground via 110 and the power via 78, the shorter the return path generated by the ground copper foils of the two different layers when the first surface layer component power supply copper foil 37 is changed to the first inner layer power supply copper foil 86 through the power via 78. As Figure 10 , Figure 11 , Figure 16 , Figure 17As shown, when the LTE module 32 receives and transmits wireless signals, a VCC power supply is generated from the "+" pole of the output capacitor 107 in the BUCK power module 51 and the second surface power copper foil 72, and is changed to the first inner layer power copper foil 86 through the power via 79 to the power via 78, and then changed to the first surface (or second surface) component power copper foil 37 to supply power to the power pins 33 / 39 of the MOSFET power switch 20, the small capacitor 64, the large capacitor 52, and the LTE module 32, generating a current i6 and a low-frequency pulsed magnetic field B6, and then flowing back to the first ground copper foil G1 (not shown in the figure) on the first surface, the third ground copper foil G2 on the first inner layer, the second ground copper foil G3 on the second inner layer (not shown in the figure), and the ground copper foil G4 on the second surface (not shown in the figure) through the ground pins 35 / 36 of the LTE module 32 and the ground via 2.Since the third ground copper foil G2 of the first inner layer is the main return path of the entire LTE power supply, the current i6 passing through the power pins 33 / 39 of the MOSFET power switch 20, the small capacitor 64, the large capacitor 52, the power copper foil 63, and the LTE module 32 will flow along the ground pins 35 / 36 of the LTE module 32, the ground vias 2, the third ground copper foil G2 of the first inner layer, the negative pad of the small capacitor 64, the negative pad of the large capacitor 52, and the third ground copper foil G2 of the first inner layer back to the ground via 110. After passing through the ground via 110, it is switched to the third ground copper foil G2 of the first inner layer and the second ground copper foil G3 of the second inner layer, and then from the "+" pad of the output capacitor 107 in the BUCK power module 51, the second surface layer power copper foil 72, the power via 79, the first inner layer power copper foil 86, the power via 78, the first surface layer component power copper foil 37, the MOSFET power switch 20, the power pins 33 / 39 of the LTE module 32, the large capacitor 52, the small capacitor 64, the power copper foil 63, the power pins 33 / 39 of the LTE module 32, and the ground pins 35 / 36 of the LTE module 32. The entire LTE power supply line (including the "+" pad of the output capacitor 107 in the BUCK power module 51, the second surface layer power copper foil 72, the power via 79, the first inner layer power copper foil 86, the power via 78, the first surface layer component power copper foil 37, the MOSFET power switch 20, the power pins 33 / 39 of the LTE module 32, the large capacitor 52, the small capacitor 64, the power copper foil 63, the power pins 33 / 39 of the LTE module 32, and the ground pins 35 / 36 of the LTE module 32) is surrounded by a complete ground plane and ground wires, without being adjacent to other signal traces or power traces, and there are no problems of adjacent interference or cross-ground segmentation. At the same time, the distance between the LTE power supply line and the ground copper foil of the adjacent layer is very close (for example, the PP thickness from the first surface layer to the first inner layer is only 3mil - 8mil), the generated return path is very small, the noise generated by the power line itself is very small (the larger the return path, the greater the noise generated by the power line itself), the generated pulse magnetic field is very small, the generated pulse electric field is very small, and the external EMI radiation can be ignored, and there is no interference to other signal traces and power traces on the board. Therefore, this kind of layer stack, layout of power devices, power copper foil, and structure setting of loads (such as wifi, LTE module, etc.) is scientific and reasonable. The power line and the ground copper foils of each layer form a planar capacitor, and the planar capacitor can filter out the noise above GHz, without worrying about the excessive EMI radiation and spurious of the product.

[0124] An LTE antenna radiator and a clearance area 99 are provided on the second surface layer at the B end of the board edge below the substrate 73. The LTE module 32 + MOSFET power switch 20 is arranged at a position close to the LTE antenna radiator and the clearance area 99 (close to the right side of the board edge), facilitating the extraction of RF traces (marked in the figure) from the LTE module 32 for electrical connection to the LTE antenna radiator. The MOSFET power switch 20 uses a PMOSFET. The source pin 68 of the MOSFET power switch 20 is connected to the positive pad of the large-capacity capacitor 34 through the component power copper foil 37, and the large-capacity capacitor 34 is used for energy storage and discharge. The drain pin 68 of the MOSFET power switch 20 is connected to the positive pads of the large-capacity capacitor 12 / the positive pad of the large-capacity capacitor 52 / the positive pad of the small capacitor 63 / the positive pad of the small capacitor 64 through the power copper foil 63. The positive pads of the large-capacity capacitor 12 / the positive pad of the large-capacity capacitor 52 / the positive pad of the small capacitor 63 / the positive pad of the small capacitor 64 are respectively connected to the ground copper foil of any layer of the substrate 73 through the ground vias 2. The positive pads of the large-capacity capacitor 12 (not marked in the figure) and the positive pad of the small capacitor 63 (not marked in the figure) are vertically placed towards the B end of the substrate and connected to the power copper foil 63. The positive pads of the large-capacity capacitor 12 (not marked in the figure) and the positive pad of the small capacitor 63 (not marked in the figure) are vertically placed towards the A end of the substrate, and the positive pads of the large-capacity capacitor 12 and the small capacitor 63 are respectively connected to the ground copper foil of each layer of the substrate 73 through the ground vias 2. The positive pads of the large-capacity capacitor 52 (not marked in the figure) and the positive pad of the small capacitor 64 (not marked in the figure) are vertically placed towards the A end of the substrate and connected to the power copper foil 63. The positive pads of the large-capacity capacitor 52 (not marked in the figure) and the positive pad of the small capacitor 64 (not marked in the figure) are placed towards the B end of the substrate, and the positive pads of the large-capacity capacitor 52 and the small capacitor 64 are respectively connected to the ground copper foil of each layer of the substrate 73 through the ground vias 2. The large-capacity capacitor 52 and the large-capacity capacitor 12 are used to provide low-frequency dynamic current response for the LTE module 32 when receiving / transmitting signals in the operating frequency range of 700 MHz to 2.7 G, while the small capacitor 64 and the small capacitor 63 provide high-frequency bypass for the LTE module 32 in the operating frequency range of 700 MHz to 2.7 G to filter out high-frequency noise generated by the LTE module 32. The ground pins 35 and 36 of the LTE module 32 are connected to the ground copper foil of each layer of the substrate 73 through the ground vias 2, forming a loop with the positive pads of the large-capacity capacitor 12 / the large-capacity capacitor 52 / the small capacitor 63 / the small capacitor 64 (connected to the ground copper foil of each layer of the substrate 73), providing a low-impedance return path for the low-frequency energy storage and discharge and high-frequency filtering of the large-capacity capacitor 12 / the large-capacity capacitor 52 / the small capacitor 63 / the small capacitor 64. The MOSFET power switch 20 is a power switch used to control the power-on sequence of the power pins 33 and 39 of the LTE module 32.

[0125] The MOSFET power switch 20, large-value capacitors 12 and 52, and small capacitors 63 and 64 are close to the power pins 33 and 36 of the LTE module 32. The length of the power trace 63 between the large-value capacitors 12 and 52, and small capacitors 63 and 64 and the power pins 33 and 36 of the LTE module 32 is less than 30 mm. Otherwise, it will affect the low-frequency dynamic discharge of the large-value capacitors 12 and 52 and the power supply noise suppression of the small capacitors 63 and 64 for the LTE module. The length of the MOSFET power switch 20 is less than 80 mm.

[0126] The GPS module 31 (load) and the differential pressure linear regulator 19 are arranged near the B7 - B8 position and within the second surface projection area of the GPS antenna, near the right side of the board edge. While the conventional Figure 1 scheme is to set the LDO low-dropout linear regulator 3 at the output capacitor position of the BUCK power module. This is the difference point. A capacitor 10 is set at the input pin of the differential pressure linear regulator 19, and a capacitor 16 is set at the output pin. The capacitor 10, differential pressure linear regulator 3, and capacitor 16 are close to the GPS module 31 (load). The distances between the capacitor 16 and capacitor 10 and the differential pressure linear regulator 19 should not exceed 30 mm. The length of the power trace 18 between the capacitor 16, differential pressure linear regulator 19, and capacitor 16 and the GPS module 31 (load) is less than 20 mm to avoid affecting the suppression of ripple and noise. Since the input voltage of the differential pressure linear regulator 19 is about 3.3V - 4.5V, and the output voltage is about 3.0V - 3.3V, the voltage drop of the power trace 18 between the output of the differential pressure linear regulator 19 and the GPS module 31 (load) will affect the normal operation of the GPS module 31. Therefore, the closer the differential pressure linear regulator 19 is to the GPS module 31, the smaller the voltage drop of the backend power supply voltage obtained by the GPS module 31 (load), and the smaller the ripple and noise. The front-end voltage drop generated by the length of the power trace 6 of the input of the differential pressure linear regulator 19 and the capacitor 10 has a very small impact on the GPS module 31 (load). Therefore, the capacitor 10, differential pressure linear regulator 19, and capacitor 16 can be far away from the BUCK power module 51, but not far away from the GPS module 31 (load).

[0127] The positive electrode pads of the input capacitor 10 and the positive electrode pads of the output capacitor 16 are connected to the ground copper foil of any layer of the substrate 73 through ground vias 2; the positive electrode pads of the input capacitor 10 are connected to the input pin of the low-dropout linear regulator 19 through the power trace branch 6, and the positive electrode pads of the output capacitor 16 are connected to the output pin of the low-dropout linear regulator 19 and the GPS module 31 through the power trace 18. Since the low-dropout linear regulator 19 is connected in series between the power trace branch 6 and the GPS module 31, the currents of the input pin and the output pin of the low-dropout linear regulator 19 are basically equal, and a current i3 is generated in the power trace branch 6 and the power trace 18. The power trace branch 6 is electrically connected to the component power copper foil 37.

[0128] The MCU module 102 (load) + the low-dropout linear regulator 13 are arranged between the GPS module 31 and the LTE module 32. The low-dropout linear regulator 13 + the input capacitor 68 + the output capacitor 69 are close to the MCU module 102 (load): the input capacitor 68 and the output capacitor 69 are respectively close to the low-dropout linear regulator 13, and the distance shall not exceed 30 mm to avoid affecting the suppression of ripples and noise. Since the input voltage of the low-dropout linear regulator 13 is about 3.3V - 4.5V, and the output voltage of the low-dropout linear regulator 13 is about 3.0V - 3.3V, the voltage drop of the power trace 15 between the output end of the low-dropout linear regulator 13 and the MCU module 102 (load) will affect the normal operation of the MCU module 102. Therefore, the closer the low-dropout linear regulator 13 is to the MCU module 102, the smaller the voltage drop of the backend power supply voltage obtained by the MCU module 102 (load), and the smaller the ripples and noise; while the influence of the front-end voltage drop generated by the length of the power trace 6 of the input end of the low-dropout linear regulator 13 + the capacitor 10 on the MCU module 102 (load) is very small. Therefore, the capacitor 68 + the low-dropout linear regulator 13 + the capacitor 69 can be far away from the BUCK power module 51, but cannot be far away from the MCU module 102 (load). The positive electrode pads of the input capacitor 68 and the positive electrode pads of the output capacitor 69 are connected to the ground copper foil of any layer of the substrate 73 through ground vias 2; the positive electrode pads of the input capacitor 68 are connected to the input pin of the low-dropout linear regulator 13 through the power trace branch 5, and the positive electrode pads of the output capacitor 69 are connected to the output pin of the low-dropout linear regulator 13 and the MCU module 102 through the power trace 15. Since the low-dropout linear regulator 13 is connected in series between the power trace branch 5 and the MCU module 102, the currents of the input pin and the output pin of the low-dropout linear regulator 13 are basically equal, and a current i4 is generated in the power trace branch 5 and the power trace 15. The power trace branch 5 is electrically connected to the component power copper foil 37;

[0129] A Bluetooth module 70, an input capacitor 21 + a low dropout linear regulator 24 + an output capacitor 27 are arranged on the left side (in the X direction of the substrate) of the low dropout linear regulator 19. The Bluetooth module 70 is close to the right edge of the board, which is convenient for arranging a Bluetooth antenna (not shown in the figure) on the right edge of the board. The input capacitor 21 + the low dropout linear regulator 24 + the output capacitor 27 are arranged on the left side of the Bluetooth module 70. The positive pads of the input capacitor 21 and the positive pad of the output capacitor 27 are respectively close to the input pin and the output pin of the low dropout linear regulator 24, and the distance shall not exceed 30 mm to reduce the suppression of ripple and noise and improve the performance of power dynamic discharge. Since the input voltage of the low dropout linear regulator 24 is about 3.3V - 4.5V, and the output voltage of the low dropout linear regulator 24 is about 3.0V - 3.3V, the voltage drop of the power supply trace 26 between the output of the low dropout linear regulator 24 and the Bluetooth module 70 (load) will affect the normal operation of the Bluetooth module 70. Therefore, the closer the low dropout linear regulator 24 is to the Bluetooth module 70, the smaller the voltage drop of the backend power supply voltage obtained by the Bluetooth module 70 (load), and the smaller the ripple and noise; while the influence of the length of the power supply trace 22 of the input terminal of the low dropout linear regulator 24 + the capacitor 21 on the Bluetooth module 70 (load) is very small. Therefore, the capacitor 21 + the low dropout linear regulator 24 + the capacitor 69 can be far away from the BUCK power module 51, but cannot be far away from the Bluetooth module 70 (load). The positive pads of the input capacitor 21 and the positive pad of the output capacitor 27 are connected to the ground copper foil of any layer of the substrate 73 through ground vias 2; the positive pad of the input capacitor 21 is connected to the input pin of the low dropout linear regulator 24 through the power supply trace branch 22, and the positive pad of the output capacitor 27 is connected to the output pin of the low dropout linear regulator 24 and the Bluetooth module 70 through the power supply trace 26. Since the low dropout linear regulator 24 is connected in series between the power supply trace branch 22 and the Bluetooth module 70, the currents of the input pin and the output pin of the low dropout linear regulator 24 are basically equal, and a current i6 is generated in the power supply trace branch 22 and the power supply trace 26. The power supply trace branch 22 is electrically connected to the component power copper foil 37;

[0130] A Wi-Fi module 101, a bead 81 + a large capacitor 95 + a small capacitor 96 are arranged on the left side (in the X direction of the substrate) of the low dropout linear regulator 13. The Wi-Fi module 101 is close to the right board edge, which is convenient for setting a Wi-Fi antenna (not shown in the figure) on the right board edge. The bead 81 + the large capacitor 95 + the small capacitor 96 are arranged on the left side of the Wi-Fi module 101. One pin of the bead 81 is connected to the component power copper foil 37, and the other pin of the bead 81 is connected to the positive pads of the large capacitor 95 and the small capacitor 96 through a power trace 77. The positive pads of the large capacitor 95 and the small capacitor 96 are connected to the ground copper foil of any layer of the substrate 73 through a ground via 2; and the positive pads of the large capacitor 95 and the small capacitor 96 are respectively close to the Wi-Fi module 101, and the distance cannot exceed 30 mm to reduce the suppression of ripple and noise and improve the performance of power dynamic discharge. The bead 81 + the large capacitor 95 + the small capacitor 96 can be far away from the BUCK power module 51, but cannot be far away from the Wi-Fi module 101 (load). The current injected into the Wi-Fi module 101 from the component power copper foil 37, the bead 81, and the power trace 77 is i5. The Wi-Fi module 101 belongs to a high-frequency and high-current dynamic flip load: Wi-Fi 2.4G works at 2.4 GHz to 2.5 GHz, and Wi-Fi 5G works at 5.15 GHz to 5.825 GHz. The component power copper foil 37 and the bead 81 need to have sufficient current-carrying capacity, and at the same time, the large capacitor 95 meets the dynamic response of the Wi-Fi module 101 during high-frequency and high-current dynamic flipping. The Wi-Fi module 101 is internally connected to the ground copper foil of any layer of the substrate 73 through a ground via 2. At the same time, a reverse return current i51 is generated on the ground copper foil of any layer of the substrate 73. The return current i51 will also pass through the positive pads of the small capacitor 96 and the large capacitor 95 and the nearby ground via 2, and finally reach the ground copper foil of any layer of the substrate 73 (including the third ground copper foil G2 of the first inner layer adjacent to the first surface layer Wi-Fi module 101 and the power trace 77).

[0131] An audio power amplifier module 30, a magnetic bead 76 + a large capacitor 97 + a small capacitor 98 are arranged on the left side (in the X direction of the substrate) of the MOFET transistor (power switch) 20. The audio power amplifier module 30 is close to the right board edge, which is convenient for arranging a speaker socket (not shown in the figure) on the right board edge and connecting it to a speaker cable (not shown in the figure). The magnetic bead 76 + the large capacitor 97 + the small capacitor 98 are arranged on the left side of the audio power amplifier module 30. One end pin of the magnetic bead 76 is connected to the power copper foil 75 through the power trace branch 71, and the other end pin of the magnetic bead 76 is connected to the positive electrode pads of the large capacitor 97 and the small capacitor 98 through the power trace 77. The positive electrode pads of the large capacitor 97 and the small capacitor 98 are connected to the ground copper foil of any layer of the substrate 73 through the ground vias 2; and the positive electrode pads of the large capacitor 97 and the small capacitor 98 are respectively close to the audio power amplifier module 30, and the distance shall not exceed 30 mm to reduce the suppression of ripple and noise and improve the performance of power dynamic discharge. The magnetic bead 76 + the large capacitor 97 + the small capacitor 98 can be far away from the BUCK power supply module 51, but cannot be far away from the audio power amplifier module 30 (load). The current injected into the audio power amplifier module 30 from the power copper foil 75, the magnetic bead 76, and the power trace 77 is i4. The audio power amplifier module 30 is a load with low frequency and large current dynamic inversion, and the operating frequency is 20 Hz to 20 kHz. The power trace branch 71, the power copper foil 75, and the magnetic bead 76 are required to have sufficient current-carrying capacity, and at the same time, the large capacitor 97 meets the dynamic response of the audio power amplifier module 30 during low-frequency and large-current dynamic inversion.

[0132] Figure 14 The structural top view of the substrate provided by another embodiment of the present application. Compared with Figure 3 comparison, Figure 14The BUCK power module 51 in it and multiple power loads (such as the battery holder 70, the low-dropout linear regulators 19 of the charging module 24 and the GPS module 31, the MCU module and the low-dropout linear regulator 13, the Wifi module 101, the audio power amplifier 30, the LTE module 32 and the MOSEFT power switch 20, the bead / inductor / resistor, etc.) are all arranged on the top layer (the first surface layer) of the substrate 73. The positive electrode of the output capacitor 72 of the BUCK power module 51 (the positive electrode of the output terminal of the BUCK power module 51) leads out the main load power trace 37 and is directly connected to multiple power loads. The negative electrode of the output capacitor 72 of the BUCK power module 51 (the negative electrode of the output terminal of the BUCK power module 51) is electrically connected to the ground copper foil in the substrate through a ground via. The positive electrode of the output capacitor 72 of the BUCK power module 51 (the positive electrode of the output terminal of the BUCK power module 51) and the multiple power loads do not need to punch power vias to change layers for electrical connection. Because the power trace changes layers through multiple power vias to be electrically connected to each power load respectively, two problems will arise: A. Each power load needs to be provided with multiple power vias, and multiple power vias need to occupy the precious space of the substrate 73. In the case of limited substrate space, it is impossible to implement multiple power vias for each power load in the space of the substrate 73; B. Currently, when the substrate manufacturer processes vias, the hole copper complies with the IPC secondary standard. Generally, the thickness of the first copper (full-board electroplating) is 5μm - 7μm, and the thickness of the second copper (pattern electroplating) is 13μm - 15μm. Therefore, the hole copper thickness is between 18μm - 22μm. Adding the losses caused by etching and other reasons, the final hole copper is about 20μm. Limited by the hole copper thickness, the impedance of the power via is relatively high, mainly affected by the DC resistance and distributed inductance. The impedance of the power via will affect the dynamic response requirements of high-speed loads or high-frequency loads (such as ARM architecture CPUs, X86 architecture CPUs, GPUs, APUs, 2.4G WIFI chips, 5G WIFI chips, LTE modules, cellular 5G modules, etc.).

[0133] The positive electrode of the output capacitor 72 of the BUCK power module 51 (the positive electrode of the output terminal of the BUCK power module 51) is directly electrically connected to the multiple power loads through the main load power trace 37, saving multiple power vias for each power load. It not only saves the precious space of the substrate 73, enabling the device layout and routing of the high-density substrate 73 to be realized, but also saves the drilling process for multiple power vias of each power load, reducing the processing cost and processing cycle; multiple power vias for each power load greatly improve the dynamic response of the power supply, reducing a series of problems such as ripple, noise, and interference caused by the high impedance of the power trace during transmission.

[0134] Table 1 shows the stack-up structure of a 4-layer via board with a substrate thickness of 1.2 mm. In Table 1, layer L1 is the top layer (the first surface layer or the second surface layer) of the substrate, and layer L4 is the bottom layer (the second surface layer or the first surface layer) of the substrate. That is, when layer L1 (the top layer of the substrate) is the first surface layer of the substrate, layer L4 (the bottom layer of the substrate) is the second surface layer of the substrate; when layer L1 (the top layer of the substrate) is the second surface layer of the substrate, layer L4 (the bottom layer of the substrate) is the first surface layer of the substrate. Figure 14 In the top view of the substrate structure provided by the illustrated embodiment, the copper thickness of layer L1 (the first surface layer) is 1.59 mil, and this thickness includes the base copper thickness + the electroplated copper thickness; layer L2 belongs to the inner layer, and the copper thickness of layer L2 (the inner layer) is 1.2 mil, and this thickness is only the base copper thickness. The layer between layer L1 (the first surface layer) and layer L2 (the inner layer) is a prepreg (abbreviation: PP), which is a sheet-shaped bonding material synthesized from resin and a carrier, that is, a glass fiber epoxy resin material, and is a type of FR-4 medium. The PP thickness H1 = 4 mil. Layer L3 belongs to the inner layer, and the copper thickness of layer L3 (the inner layer) is 1.2 mil, and this thickness is only the base copper thickness; the layer between layer L2 (the inner layer) and layer L2 (the inner layer) is a core board (abbreviation: Core), which is a glass fiber epoxy resin material and is a type of FR-4 medium. The Core thickness H1 = 33.6 mil. The copper thickness of layer L4 (the second surface layer) is 1.59 mil, and this thickness includes the base copper thickness + the electroplated copper thickness; the layer between layer L4 (the second surface layer) and layer L3 (the inner layer) is a prepreg (abbreviation: PP), which is a sheet-shaped bonding material synthesized from resin and a carrier, that is, a glass fiber epoxy resin material, and is a type of FR-4 medium. The PP thickness H1 = 4 mil.

[0135] Continuing to refer to Table 1, in combination with Figure 14 the top view of the substrate structure shown, the primary power converter assembly 51 ( Figure 14 taking only the BUCK power converter assembly as an example for illustration), the first main power trace 37, the battery holder 70 (belonging to the first secondary electronic load), and the charging module 24 (belonging to the isolation device assembly), the low dropout linear regulator 19 of the GPS module 31 (belonging to the secondary power converter assembly), the MCU module and the low dropout linear regulator 13 (belonging to the secondary power converter assembly), the MCU module 102 (belonging to the second secondary electronic load), the magnetic bead 81 (belonging to the isolation device assembly), the Wifi module 101 (belonging to the first secondary electronic load), the audio power amplifier 30 (belonging to the primary electronic load), the LTE module 32 (belonging to the first secondary electronic load), and the MOSEFT power switch 20 (belonging to the isolation device assembly), etc. are all arranged on the top layer (the first surface layer) of the substrate 103. In combination with Figure 8 、 Figure 9 、 Figure 10 、 Figure 11, in the direction perpendicular to the substrate 73, a first ground copper foil G2 is provided at the projection of the primary power converter assembly 51, the first main power trace 37, the battery holder 70 (belonging to the first secondary electronic load), the charging module 24 (belonging to the isolation device assembly), the low-dropout linear regulator 19 of the GPS module 31 (belonging to the secondary power converter assembly), the MCU module and the low-dropout linear regulator 13 (belonging to the secondary power converter assembly), the MCU module 102 (belonging to the second secondary electronic load), the magnetic bead 81 (belonging to the isolation device assembly), the Wifi module 101 (belonging to the first secondary electronic load), the audio power amplifier 30 (belonging to the primary electronic load), the LTE module 32 (belonging to the first secondary electronic load), and the MOSEFT power switch 20 (belonging to the isolation device assembly) on the L02 layer. That is, the projections of the primary power converter assembly 51, the first main power trace 37, the battery holder 70 (belonging to the first secondary electronic load), the charging module 24 (belonging to the isolation device assembly), the low-dropout linear regulator 19 of the GPS module 31 (belonging to the secondary power converter assembly), the MCU module and the low-dropout linear regulator 13 (belonging to the secondary power converter assembly), the MCU module 102 (belonging to the second secondary electronic load), the magnetic bead 81 (belonging to the isolation device assembly), the Wifi module 101 (belonging to the first secondary electronic load), the audio power amplifier 30 (belonging to the primary electronic load), the LTE module 32 (belonging to the first secondary electronic load), and the MOSEFT power switch 20 (belonging to the isolation device assembly) on the L1 layer (the first surface layer) all fall within the range of the first ground copper foil G2 on the L02 layer, so that the first ground copper foil G2 on the L02 layer provides a low-impedance return path for the primary power converter assembly 51, the first main power trace 37, the battery holder 70 (belonging to the first secondary electronic load), the charging module 24 (belonging to the secondary power converter assembly), the low-dropout linear regulator 19 of the GPS module 31 (belonging to the secondary power converter assembly), the low-dropout linear regulator 13 (belonging to the secondary power converter assembly), the MCU module 102 (belonging to the second secondary electronic load), the magnetic bead 81 (belonging to the isolation device assembly), the Wifi module 101 (belonging to the first secondary electronic load), the audio power amplifier 30 (belonging to the primary electronic load), the LTE module 32 (belonging to the first secondary electronic load), and the MOSEFT power switch 20 (belonging to the isolation device assembly) on the L01 layer (the first surface layer).Taking the substrate stack structure shown in Table 1 as an example, the thickness of the PP between the L01 layer (the first surface layer) and the L02 layer (the inner layer) is only 4 mil (about 0.1 mm). That is, the return area between the first ground copper foil G2 of the L02 layer and the primary power converter component 51, the first main power trace 37, the battery holder 70 (belonging to the first secondary electronic load), the charging module 24 (belonging to the isolation device component), the low dropout linear regulator 19 of the GPS module 31 (belonging to the secondary power converter component), the MCU module and the low dropout linear regulator 13 (belonging to the secondary power converter component), the MCU module 102 (belonging to the second secondary electronic load), the magnetic bead 81 (belonging to the isolation device component), the Wifi module 101 (belonging to the first secondary electronic load), the audio power amplifier 30 (belonging to the primary electronic load), the LTE module 32 (belonging to the first secondary electronic load), and the MOSEFT power switch 20 (belonging to the isolation device component) in the L01 layer (the first surface layer) is very small and can almost be ignored; a planar capacitor can be formed between the first ground copper foil G2 of the L02 layer and the primary power converter component 51, the first main power trace 37, the battery holder 70 (belonging to the first secondary electronic load), the charging module 24 (belonging to the isolation device component), the low dropout linear regulator 19 of the GPS module 31 (belonging to the secondary power converter component), the low dropout linear regulator 13 (belonging to the secondary power converter component), the MCU module 102 (belonging to the second secondary electronic load), the magnetic bead 81 (belonging to the isolation device component), the Wifi module 101 (belonging to the first secondary electronic load), the audio power amplifier 30 (belonging to the primary electronic load), the LTE module 32 (belonging to the first secondary electronic load), and the MOSEFT power switch 20 (belonging to the isolation device component) in the L01 layer (the first surface layer), which can filter out the noise in the upper GHz (such as a large number of high-frequency component noises generated when the LTE module flips at high speed and low-frequency noises generated by dropping). Coupled with the capacitors of various frequency bands set on the first main power trace 37 (such as the output capacitor 72 of the primary power converter component 51 and the large-capacity capacitor 34), large capacitors 52, small capacitors 64, and large-capacitance capacitors 12 are set on the power pins 39, / 33 and the power branch copper foil 63 of the LTE module 32; the first power trace branch 22 (the first power trace branch 22 is connected to the first main power trace 37) is connected to the input pin 23 of the charging module 24, an input capacitor 21 is set on the first power trace branch 22, the output pin 25 of the charging module 24 is connected to the battery holder 70 (belonging to the first secondary electronic load) through the power trace 26, and an output capacitor 27 is set on the power trace 26. That is, the noises on the first main power trace 37, the first power trace branch 22, the power trace 26, the power branch copper foil 63, etc. are all within a certain low threshold range and will not exceed the level of EMI radiation exceeding the standard or spurious exceeding the standard at all.

[0136] Table 1 Stacking Structure of 4-Layer Through-Hole Board with Substrate Thickness of 1.2 mm

[0137]

[0138] Continue to refer to Figure 3 、 Figure 14 and refer to Figures 8 to 10 and Table 1 at the same time. More specifically, taking the power supply path from the primary power converter component 51 to the LTE module (belonging to the first and second electronic loads) as an example, between the primary power converter component 51 on the L01 layer (the first surface layer), the first main power trace 37, the LTE module 32 (belonging to the first and second electronic loads), the MOSEFT power switch 20 (belonging to the isolation device component), and the power branch copper foil 63 and the first ground copper foil G2 on the L02 layer, a current i6 will be generated, generating a return magnetic field B6. The length of the first main power trace 37 between the output capacitor 47 of the primary power converter component 51 and the MOSFET power switch 20 is L11, and the length between the MOSFET power switch 20 and the power pins 39 / 33 of the LTE module 32 (belonging to the first and second electronic loads) is L12. The distance between the L01 layer (the first surface layer) and the L02 layer (the inner layer) is H1, and the return area of the power supply path from the primary power converter component 51 to the LTE module (belonging to the first and second electronic loads) to the first ground copper foil G2 is S = H1 × (L11 + L12). According to the magnetic field strength calculation formula: B = Φ / S, the external power supply clamping and filtering component 81 to the first ground copper foil G generates a low-frequency magnetic field B6:

[0139] B6 = Φ / S = Φ / H1 × (L11 + L12)

[0140] where Φ is the magnetic flux of the power supply path from the primary power converter component 51 to the LTE module (belonging to the first and second electronic loads) to the first ground copper foil G1

[0141] For example, taking the stacking structure of the 4-layer through-hole board with the substrate 73 thickness of 1.2 mm shown in Table 1 as an example, when the first ground copper foil G1 is set on the L02 layer, the distance H1 between the power supply path from the primary power converter component 51 to the LTE module (belonging to the first and second electronic loads) and the first ground copper foil G1 is 3 mil (about 0.1 mm), that is, the low-frequency magnetic field B6 generated by the power supply path from the primary power converter component 51 to the LTE module (belonging to the first and second electronic loads) is almost concentrated between the power supply path from the primary power converter component 51 on the L01 layer to the LTE module (belonging to the first and second electronic loads) and the first ground copper foil G1 on the L02 layer, and the externally leaked low-frequency magnetic field is very small, and the external radiation energy of the low-frequency magnetic field B6 is very low, and it will not cause the EMI radiation to exceed the standard (the EMI radiation in the EU CE certification and the Chinese 3C certification refers to the frequency band of 30 MHz to 1 GHz).

[0142] Continue to refer to Figure 14 and also refer to Figures 8 to 10 Table 1. A low-frequency electric field e31 will be generated on the power supply path from the primary power converter assembly 51 to the LTE module (belonging to the first and second electronic loads) to the first ground copper foil G1 on the L02 layer ( Figures 11 to 14 the first ground copper foil in is arranged in the L3 layer). More specifically, according to the electric field strength calculation formula: e = U / d, where d is the distance (H1) between the power supply path from the primary power converter assembly 51 to the LTE module (belonging to the first and second electronic loads) and the first ground copper foil G1 on the L02 layer. The low-frequency electric field e31 generated between the power supply path from the primary power converter assembly 51 to the LTE module (belonging to the first and second electronic loads) and the first ground copper foil G1 on the L02 layer is:

[0143] e8 = U / d = U / H1

[0144] where U is the voltage difference between the power supply path from the primary power converter assembly 51 to the LTE module (belonging to the first and second electronic loads) and the first ground copper foil G1 on the L02 layer

[0145] For example, taking the 4-layer via board stack structure with a substrate 73 thickness of 1.2 mm shown in Table 1 as an example, when the first ground copper foil G1 is arranged in the L2 layer, the distance H1 between the power supply path from the primary power converter assembly 51 to the LTE module (belonging to the first and second electronic loads) and the first ground copper foil G1 on the L02 layer is 4 mil (about 0.1 mm), that is, the electric field e31 generated by the power supply path from the primary power converter assembly 51 to the LTE module (belonging to the first and second electronic loads) to the first ground copper foil G1 on the L02 layer is almost concentrated between the power supply path from the primary power converter assembly 51 to the LTE module (belonging to the first and second electronic loads) and the first ground copper foil G1 on the L02 layer, and the leaked low-frequency magnetic field is very small and will not cause the EMI radiation to exceed the standard (the EMI radiation in the EU CE certification and the Chinese 3C certification refers to the frequency band of 30 MHz to 1 GHz).

[0146] Figure 15 Figure shows a top view of the power supply and load power supply system provided by an embodiment of the present application on a substrate Figure 15 is Figure 14Vertical cross-sectional view of the substrate 73 therein. The primary power converter assembly 51, the charging module 24 (secondary power converter assembly), the battery holder 70 (second secondary electronic load), the low dropout linear regulator 19 (secondary power converter assembly), the GPS module 31 (second secondary electronic load), the magnetic bead 81 (isolation device assembly), the wifi module 101 (first secondary electronic load), the low dropout linear regulator 13 (secondary power converter assembly), the MCU module 102 (second secondary electronic load), the MOSFET power switch 20 (isolation device assembly), the LTE module 32 (second secondary electronic load), the audio power amplifier module 30 (primary electronic load), etc. are all arranged on the L01 layer (first surface layer) of the substrate 73. At the same time, the first power copper foil 103, the second power trace branch 26, the second power trace branch 18, the second power trace branch 77, the second power trace branch 15, the first power trace branch 63, etc. are all arranged on the L01 layer (first surface layer) of the substrate 73.

[0147] The first power supply copper foil 103 is composed of a main power supply trace 37, a first power supply trace branch 22, a first power supply trace branch 6, a first power supply trace branch 5, and a first power supply trace branch 75. The primary power converter assembly 51 is electrically connected to the main power supply trace 37 through the positive electrode of the internal output capacitor 47. The primary power converter assembly 51 is electrically connected to the first power supply copper foil G1 of the L02 layer (the first inner layer) of the substrate 73 through the negative electrode of the internal output capacitor 47, and the first power supply copper foil G1 is electrically connected to the ground of the substrate 73. The negative electrode 42 of the battery socket 70 (the second secondary electronic load) is electrically connected to the first power supply copper foil G1 of the L02 layer (the first inner layer) of the substrate 73 through a ground via 41; the ground pin 44 of the GPS module 31 (the second secondary electronic load) is electrically connected to the first power supply copper foil G1 of the L02 layer (the first inner layer) of the substrate 73 through a ground via 43; the ground pin 46 of the wifi module 101 (the first secondary electronic load) is electrically connected to the first power supply copper foil G1 of the L02 layer (the first inner layer) of the substrate 73 through a ground via 45; the ground pin 48 of the MCU module 102 (the second secondary electronic load) is electrically connected to the first power supply copper foil G1 of the L02 layer (the first inner layer) of the substrate 73 through a ground via 47; the ground pin 101 of the audio power amplifier module 30 (the primary electronic load) is electrically connected to the first power supply copper foil G1 of the L02 layer (the first inner layer) of the substrate 73 through a ground via 49; the ground pin 35 of the LTE module 32 (the second secondary electronic load) is electrically connected to the first power supply copper foil G1 of the L02 layer (the first inner layer) of the substrate 73 through a ground via 2; that is, a return path is formed between the primary power converter assembly 51, the main power supply trace 37, the first power supply trace branch 22, the charging module 24 (the secondary power converter assembly), the second power supply trace branch 26, the battery socket 70 (the second secondary electronic load), the first power supply trace branch 6, the low dropout linear regulator 19 (the secondary power converter assembly), the second power supply trace branch 18, the GPS module 31 (the second secondary electronic load), the magnetic bead 81 (the isolation device assembly), the second power supply trace branch 15, the wifi module 101 (the first secondary electronic load), the first power supply trace branch 5, the low dropout linear regulator 13 (the secondary power converter assembly), the trace branch 15, the MCU module 102 (the second secondary electronic load), the first power supply trace branch 75, the audio power amplifier module 30 (the primary electronic load), the MOSFET power switch 20 (the isolation device assembly), the first power supply trace branch 63, the LTE module 32 (the second secondary electronic load) on the L01 layer (the first surface layer) of the substrate 73 and the first ground copper foil G1 of the L02 layer (the first inner layer).The PP thickness from the L01 layer (the first surface layer) to the L02 layer is only 2 mil to 8 mil (the example in Table 1 is 4 mil). The primary power converter assembly 51, the main power trace 37, the first power trace branch 22, the charging module 24 (secondary power converter assembly), the second power trace branch 26, the battery holder 70 (the second secondary electronic load), the first power trace branch 6, the low-dropout linear regulator 19 (secondary power converter assembly), the second power trace branch 18, the GPS module 31 (the second secondary electronic load), the bead 81 (isolation device assembly), the second power trace branch 15, the wifi module 101 (the first secondary electronic load), the first power trace branch 5, the low-dropout linear regulator 13 (secondary power converter assembly), the trace branch 15, the MCU module 102 (the second secondary electronic load), the first power trace branch 75, the audio power amplifier module 30 (primary electronic load), the MOSFET power switch 20 (isolation device assembly), the first power trace branch 63, the LTE module 32 (the second secondary electronic load) on the L01 layer (the first surface layer) of the substrate 73 and the first ground copper foil G1 on the L02 layer (the first inner layer) form a very small return area. A parallel-plate capacitor is formed between them. The noise between the primary power converter assembly 51 and multiple primary power loads is very small (the parallel-plate capacitor can filter out noise above GHz), and the influence on the power supply of multiple primary power loads is relatively small.

[0148] Continue to refer to Figure 15 , the primary power converter assembly 51 is arranged at the first end A of the substrate 73, while the charging module 24 (secondary power converter assembly), the battery holder 70 (the second secondary electronic load), the low-dropout linear regulator 19 (secondary power converter assembly), the GPS module 31 (the second secondary electronic load), the bead 81 (isolation device assembly), the wifi module 101 (the first secondary electronic load), the low-dropout linear regulator 13 (secondary power converter assembly), the MCU module 102 (the second secondary electronic load), the MOSFET power switch 20 (isolation device assembly), the LTE module 32 (the second secondary electronic load), the audio power amplifier module 30 (primary electronic load), etc. are all arranged on the L01 layer (the first surface layer) of the substrate 73, that is, the primary power converter assembly is arranged close to the first end, and at least two of the primary power loads are all arranged close to the second end.

[0149] The main power trace 37, the first power trace branch 22, the first power trace branch 6, the first power trace branch 5, the first power trace branch 75, the first power trace branch 63, the second power trace branch 15, the second power trace branch 15, the second power trace branch 18, the second power trace branch 26.

[0150] AndFigure 15 Comparison Figure 16 That is, Figure 15 the charging module 24 (secondary power converter assembly), battery holder 70 (second secondary electronic load), low dropout linear regulator 19 (secondary power converter assembly), GPS module 31 (second secondary electronic load), magnetic bead 81 (isolation device assembly), wifi module 101 (first secondary electronic load), low dropout linear regulator 13 (secondary power converter assembly), MCU module 102 (second secondary electronic load), MOSFET power switch 20 (isolation device assembly), LTE module 32 (second secondary electronic load), audio power amplifier module 30 (primary electronic load), etc. in

[0151] Figure 15 That is Figure 14 the A end of the substrate 73 in Figure 3 the BUCK power module 51 in

[0152] is set on the bottom layer (second surface layer) of the substrate 103, while multiple power loads (such as the battery holder 70 and the charging module 24, the low dropout linear regulator 19 of the GPS module 31, the MCU module and the low dropout linear regulator 13, the Wifi module 101, the audio power amplifier 30, etc.) are set on the top layer (first surface layer) of the substrate 103. The other parts are basically the same and will not be described repeatedly.

[0152] The power converter module includes: Buck power module, BOOST power module, Buck - Boost power module, Boost power module, push - pull power module, flyback power module, forward power module, isolated power module, non - isolated power module, active clamp power module, etc. The type of the power converter component is not limited. The application only takes the BUCK power module 51 as an example for illustration.

[0153] The output terminal of the power converter refers to the positive pole of the output capacitor of the power converter, the output terminal of the BUCK power module 51. The first grounding line includes ground copper foil and ground wire. The specific form of grounding is not limited. Here, the ground copper foil or ground wire 234 is taken as an example of the first grounding line for illustration. Figure 17 A specific implementation manner of the ground wire is given. Figure 18 A specific implementation manner of the ground copper foil is given. Figure 19 Another specific implementation manner of the ground copper foil is given.

[0154] Figure 17The top view of the ground wire provided by an embodiment of the present application; Figure 18 The top view of the ground copper foil provided by an embodiment of the present application; Figure 19 The top view of the ground copper foil provided by another embodiment of the present application. Please refer to Figures 17 to 19 wherein Figure 18 shows the top view of the ground copper foil with a regular shape; Figure 19 shows the top view of the ground copper foil with an irregular shape. It should be noted that the ground copper foil 234 (which is a type of the first grounding line) and the ground wire 234 (which is a type of the first grounding line) have the same function, except that the width of the ground copper foil 234 (which is a type of the first grounding line) is larger than that of the ground wire 234 (which is a type of the first grounding line): the ground wire 234 (which is a type of the first grounding line) < 1 mm, and the width W21 of the ground copper foil 234 (which is a type of the first grounding line) ≥ 1 mm. In addition, the line width of the ground wire 234 (which is a type of the first grounding line) is fixed. For example, the line width W21 of a ground wire is all 0.8 mm or 0.9 mm, etc. Figure 17 The ground wire 234 (which is a type of the first grounding line) in Figure 18 is bent around the signal via 9011 to avoid short circuit caused by the connection between the signal via 9011 and the ground wire 234 (which is a type of the first grounding line). Two ground vias 800 are respectively arranged at both ends of the ground wire 234 (which is a type of the first grounding line), that is, both two ground vias 800 are electrically connected to the ground wire 234 (which is a type of the first grounding line), so that impedance grounding connection can be realized by electrically connecting with other layer ground wires or ground copper foils 802 through the two ground vias 800. The shape of the ground wire 234 (which is a type of the first grounding line) is not limited. The shape of the ground copper foil 234 (which is a type of the first grounding line) can be a regular shape, such as Figure 19The shape of the middle ground copper foil 234 (which belongs to one of the first ground lines) is an irregular figure. There is also a slot 9055 below the middle ground copper foil 234 (which belongs to one of the first ground lines). At the same time, the middle ground copper foil 234 (which belongs to one of the first ground lines) can also have ground vias 9000, power vias 9033, and signal vias 9011. To avoid short circuits of the power vias 9033 and signal vias 9011 in the middle ground copper foil 234 (which belongs to one of the first ground lines), a clearance area 9044 (copper-free area) is set between the middle ground copper foil 234 (which belongs to one of the first ground lines) and the power via 9033, and a clearance area 9066 (copper-free area) is set between the middle ground copper foil 234 (which belongs to one of the first ground lines) and the signal via 9011. That is Figure 19 The middle ground copper foil 234 (which belongs to one of the first ground lines) has a slot 9055, clearance areas 9066, 9044, etc. The middle ground copper foil 234 (which belongs to one of the first ground lines) is an irregular figure in shape.

[0155] The second ground line includes a ground copper foil and a ground wire, and does not limit the specific form of grounding. Here, the ground copper foil or ground wire 233 is taken as an example of the second ground line for illustration. Figure 20 A specific implementation manner of the ground wire is given. Figure 21 A specific implementation manner of the ground copper foil is given. Figure 23 Another specific implementation manner of the ground copper foil is given.

[0156] Figure 20 This is the top view of the ground wire provided by an embodiment of the present application; Figure 21 This is the top view of the ground copper foil provided by another embodiment of the present application; Figure 22 This is the top view of the ground copper foil provided by yet another embodiment of the present application. Please refer to Figures 20 to 22 , where Figure 21 The top view of the regular-shaped ground copper foil is given; Figure 22 The top view of the irregular-shaped ground copper foil is given. It should be noted that the functions of the ground copper foil 233 (which belongs to one of the second ground lines) and the ground wire 233 (which belongs to one of the second ground lines) are the same, but the width of the ground copper foil 233 (which belongs to one of the second ground lines) is larger than that of the ground wire 233 (which belongs to one of the second ground lines): the ground wire 233 (which belongs to one of the second ground lines) < 1 mm, and the width W31 of the ground copper foil 233 (which belongs to one of the second ground lines) ≧ 1 mm. In addition, the line width of the ground wire 233 (which belongs to one of the second ground lines) is fixed. For example, the line width W31 of a ground wire is all 0.8 mm or 0.9 mm, etc. Figure 20The ground wire 233 (which belongs to one of the second grounding lines) bypasses the signal via 901. The ground wire 233 (which belongs to one of the second grounding lines) also has a bend 902 to prevent the signal via 9011 from being connected to the ground wire 234 (which belongs to one of the first grounding lines) and causing a short circuit. Two ground vias 801 are respectively arranged at both ends of the ground wire 234 (which belongs to one of the first grounding lines), that is, both of the two ground vias 801 are electrically connected to the ground wire 234 (which belongs to one of the first grounding lines). In this way, impedance grounding connection can be achieved by connecting the two ground vias 800 to the ground wires or ground copper foils 803 on other layers. The shape of the ground wire 233 (which belongs to one of the second grounding lines) is not limited. The shape of the ground copper foil 233 (which belongs to one of the second grounding lines) can be a regular figure, for example Figure 21 in the ground copper foil 233 (which belongs to one of the second grounding lines) has a regular rectangular shape, the width W32 of the ground copper foil 233 (which belongs to one of the second grounding lines) is ≥ 1 mm, and a plurality of ground holes 900 are also distributed in the ground copper foil 233 (which belongs to one of the second grounding lines). The shape of the ground copper foil 233 (which belongs to one of the second grounding lines) can also be an irregular figure, for example Figure 22 in the ground copper foil 233 (which belongs to one of the second grounding lines) has an irregular shape, and there is also a slot 905 below the ground copper foil 233 (which belongs to one of the second grounding lines). At the same time, the ground copper foil 233 (which belongs to one of the second grounding lines) can also have ground holes 900, power vias 903, and signal vias 901. To prevent the power via 903 and the signal via 901 from short-circuiting in the ground copper foil 233 (which belongs to one of the second grounding lines), a clearance area 904 (copper-free area) is set between the ground copper foil 233 (which belongs to one of the second grounding lines) and the power via 903, and a clearance area 906 (copper-free area) is set between the ground copper foil 233 (which belongs to one of the second grounding lines) and the signal via 901. That is Figure 22 in the ground copper foil 233 (which belongs to one of the second grounding lines) has a slot 905, a clearance area 906, a clearance area 904, etc., and the ground copper foil 233 (which belongs to one of the second grounding lines) is an irregularly shaped figure.

[0157] Figure 23 is a top view of the power supply and load power supply system provided by another embodiment of the present application on a substrate; Figure 24 is a top view of the power supply and load power supply system provided by another embodiment of the present application on a substrate.

[0158] Continue to refer to Figure 23, the primary power converter assembly 51 is disposed at the first end A of the substrate 73, while the charging module 24 (secondary power converter assembly), the battery holder 70 (second secondary electronic load), the magnetic bead 81 (isolation device assembly), the wifi module 101 (first secondary electronic load), etc. are all disposed on the L01 layer (first surface layer) of the substrate 73. That is, the primary power converter assembly is disposed close to the first end, and at least two of the primary power loads are both disposed close to the second end. Around the primary power converter assembly 51, the first main power trace 37, the first power trace branch 22, the charging module 24 (secondary power converter assembly), the power trace 26, the battery holder 70, the magnetic bead 81 (isolation device assembly), the power trace 77, the wifi module 101 (first secondary electronic load), etc. on the L01 layer (first surface layer), a ground wire 233 (a type of the second grounding line) is provided. A plurality of ground vias 311 are also provided on the ground wire 233. The ground wire 233 is electrically connected to the first ground copper foil G1 (a type of the first grounding line) through the ground vias 311 to achieve a lower grounding impedance and improve the grounding performance. The positive electrode 57 of the output capacitor 47 is electrically connected to the first main power trace 37, and the negative electrode 56 of the output capacitor 47 is electrically connected to the first ground copper foil G1 (a type of the first grounding line) through the ground via 58. At the same time, the negative electrode 56 of the output capacitor 47, the ground via 58 and the ground wire 233 are electrically connected.

[0159] The grounding pin 46 of the wifi module 101 (first secondary electronic load) is electrically connected to the first ground copper foil G1 (a type of the first grounding line) through the ground via 45. At the same time, the grounding pin 46 of the wifi module 101 (first secondary electronic load), the ground via 45 and the ground wire 233 are electrically connected.

[0160] The grounding pin 40 of the battery holder 70 (first secondary electronic load) is electrically connected to the first ground copper foil G1 (a type of the first grounding line) through the ground via 41. At the same time, the grounding pin 41 of the battery holder 70 (first secondary electronic load), the ground via 41 and the ground wire 233 are electrically connected.

[0161] On the L01 layer (the first surface layer), sensitive signal traces (such as microphone signal traces) and sensitive signal vias (such as microphone signal vias) are provided. The sensitive signal traces (such as microphone signal traces) and sensitive signal vias (such as microphone signal vias) are near the primary power converter component 51 and the first main power trace 37. The sensitive signal traces (such as microphone signal traces) and sensitive signal vias (such as microphone signal vias) are vulnerable to interference when close to the primary power converter component 51 and the first main power trace 37. Ground wires 233 and a plurality of ground vias 311 are provided between the sensitive signal traces (such as microphone signal traces), sensitive signal vias (such as microphone signal vias) and the primary power converter component 51, the first main power trace 37, which can increase the isolation between the two and prevent the primary power converter component 51 and the first main power trace 37 from interfering with the sensitive signal traces (such as microphone signal traces), sensitive signal vias (such as microphone signal vias). That is, ground wires 233 (which belong to a type of the second grounding line) are provided for the primary power converter component 51, the charging module 24 (secondary power converter component), the battery holder 70 (second secondary electronic load), the magnetic bead 81 (isolation device component), and the wifi module 101 (first secondary electronic load), which can provide a return path for the power supply system on the same layer, reduce the noise of the power supply system, reduce the external radiation of the power supply system, and reduce the interference to the sensitive signal traces and sensitive signal vias in the substrate 73.

[0162] The charging module 24 (secondary power converter component), the battery holder 70 (second secondary electronic load), the magnetic bead 81 (isolation device component), and the wifi module 101 (first secondary electronic load) all belong to the primary power loads.

[0163] Compared with Figure 23 the Figure 24 ground wire 233 (which belongs to a type of the second grounding line) in the Figure 23 solution is replaced with a ground copper foil 233 (which belongs to a type of the second grounding line). Figure 23 The ground wire 233 in the Figure 24 solution and the ground copper foil 233 in the

[0164] Increase the substrate density and utilization rate. Set a power copper foil path on the first surface layer. The projection of the power copper foil path on the first surface layer on the L02 layer (the first inner layer) sets the first ground copper foil G1. The power copper foil path on the first surface layer sets signal lines and power lines on the L03 layer (the second inner layer). The return area from the power copper foil path on the first surface layer to the first ground copper foil G1 on the L02 layer is very small, the power noise is small, and their radiation is very small. The signal lines and power lines on the L03 layer (the second inner layer) use the first ground copper foil G1 on the L02 layer as the return path. The power copper foil path on the first surface layer is separated from the signal lines and power lines on the L03 layer (the second inner layer) by the first ground copper foil G1 on the L02 layer. The power copper foil path on the first surface layer is not adjacent to the signal lines and power lines on the L03 layer (the second inner layer) between them, that is, there will be no mutual electric field and magnetic field coupling interference between the power copper foil path on the first surface layer and the signal lines and power lines on the L03 layer (the second inner layer) between them).

[0165] The primary converter component refers to obtaining a stable power supply after stepping down or stepping up the external power supply of the substrate through the primary converter component, and can directly supply power to the primary electronic load, isolation device component + second primary electronic load, secondary power converter component + second secondary electronic load in the substrate. The primary converter component can be an AC-DC converter component, a DC-DC converter component (such as a linear voltage regulator component, a buck DC-DC converter component, a boost DC-DC converter component), etc. The type of the primary converter component is not restricted;

[0166] For example, a wireless vehicle-mounted device: A wireless device that can be connected to a fuel vehicle, an electric vehicle, an electric bicycle, an electric motorcycle, a scooter, etc. belongs to a wireless vehicle-mounted device. The range of the external power supply of the substrate is 8V to 100V. The primary converter component used is a buck converter component. The buck converter component (the primary converter component) outputs a 4.4V power supply to supply power to the entire substrate. The 4.4V power supply voltage output by the buck converter component (the primary converter component) meets the power supply voltage of the audio power amplifier module. The 4.4V power supply voltage output by the buck converter component (the primary converter component) does not require the secondary converter component to perform further boosting or reducing processing. The 4.4V power supply voltage output by the buck converter component (the primary converter component) can directly supply power to the audio power amplifier module.

[0167] The primary power load includes a primary electronic load, an isolation device component, and a first secondary electronic load, a secondary power converter component, and a second secondary electronic load.

[0168] The primary power load refers to obtaining a power supply after the external power supply cable of the substrate is processed by the primary converter component, and this power supply uses three schemes to supply power to the primary electronic load, the first secondary electronic load, and the second secondary electronic load.

[0169] Solution 1: The power supply output by the buck converter component (primary converter component) can directly supply power to the primary electronic load (such as an audio power amplifier module, a motor, etc.), without the need for further boosting or bucking. There is also no need for an isolation device component to isolate between the stable power supply VCC and the primary electronic load (for example, there is no need to add a diode or a MOSFET power switch between the stable power supply VCC and the primary electronic load).

[0170] For example, a wireless vehicle-mounted device: A wireless device that can be connected to a fuel vehicle, an electric vehicle, an electric bicycle, an electric motorcycle, a scooter, etc. belongs to a wireless vehicle-mounted device. The range of the external power supply of the substrate is 8V to 100V. The primary converter component is a buck converter component. The buck converter component (primary converter component) outputs a 4.4V power supply to supply power to the entire substrate. The 4.4V power supply voltage (stable power supply VCC) output by the buck converter component (primary converter component) meets the power supply voltage of the audio power amplifier module. The 4.4V power supply voltage (stable power supply VCC) output by the buck converter component (primary converter component) does not require a secondary converter component to perform further boosting or bucking. There is also no need for an isolation device component to isolate between the stable power supply VCC and the primary electronic load (for example, there is no need to add a diode or a MOSFET power switch between the stable power supply VCC and the primary electronic load). The 4.4V power supply voltage output by the buck converter component (primary converter component) can directly supply power to the audio power amplifier module. The audio power amplifier module belongs to the primary electronic load.

[0171] Solution 2: An isolation device component needs to be connected in series to supply power between the power supply output by the buck converter component (primary converter component) and the first secondary electronic load.

[0172] Taking the wireless vehicle-mounted device as an example, the range of the external power supply of the substrate is 8V to 100V. The primary converter component is a buck converter component. The buck converter component (primary converter component) outputs a 4.4V power supply voltage (stable power supply VCC) to supply power to the entire substrate. A MOSFET power switch needs to be added between the LTE module (the first secondary electronic load) and the output 4.4V power supply voltage (stable power supply VCC) for timing control, so as to control when the LTE module starts to work or stops working; the LTE module belongs to the first secondary electronic load.

[0173] The output 4.4V power supply voltage of the buck converter component (primary converter component) meets the power supply voltage requirements of the audio module. However, since the 4.4V power supply output by the buck converter component (primary converter component) supplies power to various high-speed load flip loads, there are various noises or noises in the 4.4V power supply output by the buck converter component (primary converter component). The audio module (the first and second electronic loads) is an extremely sensitive load. A bead, inductor, or resistor with a small resistance value needs to be added between the 4.4V power supply output by the buck converter component (primary converter component) and the audio module (the first and second electronic loads) to block the interference of the noise in the 4.4V power supply output by the buck converter component (primary converter component) to the audio module (the first and second electronic loads); the audio module belongs to the first and second electronic loads.

[0174] Isolation device components (such as isolation diodes, MOSFETs, IGBTs, inductors, beads, resistors, etc.) all belong to passive devices.

[0175] Solution three: A secondary power converter component needs to be connected in series between the output power supply of the buck converter component (primary converter component) and the second and second electronic loads.

[0176] Taking a wireless vehicle-mounted device as an example, the range of the external power supply of the substrate is 8V to 100V. The primary converter component is a buck converter component. The buck converter component (primary converter component) outputs a 4.4V power supply voltage (stable power supply VCC) to supply power to the entire substrate. The power supply voltage of the GPS module (the second and second electronic loads) is only 1.8V. The 4.4V power supply voltage output by the buck converter component (primary converter component) far exceeds the power supply voltage of 1.8V of the GPS module (the second and second electronic loads). Therefore, a secondary power converter component needs to be added between the GPS module (the second and second electronic loads) and the 4.4V power supply output by the buck converter component (primary converter component). The secondary power converter component can use a linear voltage regulator, a buck DC-DC converter, etc. to meet the power supply requirements of the GPS module (the second and second electronic loads); the GPS module belongs to the second and second electronic loads. The secondary power converter component belongs to an active device.

[0177] In addition, if the buck converter component (primary converter component) supplies power to the charging module (secondary power converter component), the charging module (including the charging module composed of a linear circuit and the charging module composed of a switching circuit, and the type of the charging module is not limited) is also a secondary power converter component. The charging module charges the battery (such as a lithium battery, a nickel-metal hydride battery, etc., and the type of the battery is not limited), and the battery is the second and second electronic load.

[0178] If a charging module (including a charging module composed of a linear circuit and a charging module composed of a switching circuit, without restricting the type of the charging module) directly supplies power with an external power cable, the output end of the charging module (primary converter assembly) charges a battery (such as a lithium battery, nickel-metal hydride battery, etc., without restricting the type of the battery). The charging module belongs to the primary converter assembly, and the battery is the primary electronic load.

[0179] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application.

[0180] In the present application, unless otherwise clearly defined and limited, the terms "mounted", "connected", "connected to", "fixed", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0181] It should be noted that in the description of the present application, the terms "first" and "second" are only used for conveniently describing different components, and cannot be understood as indicating or implying a sequential relationship, relative importance, or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features.

[0182] In the present application, the embodiments or implementation manners are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0183] In the description of the present application, the descriptions referring to terms such as "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present application, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0184] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A substrate, characterized in that: It includes a first surface layer, on which a primary power converter component and at least two primary power loads are arranged, the substrate includes a first end and a second end opposite to each other along a first direction, the primary power converter component is arranged close to the first end, and at least two primary power loads are arranged close to the second end; a first power copper foil is arranged on the first surface layer, one end of the first power copper foil is electrically connected to the primary power converter, and the other end of the first power copper foil is electrically connected to at least two primary power loads to supply power to the at least two primary power loads.

2. The substrate according to claim 1, characterized in that The first power copper foil includes a first main power line and at least two first power line branches, at least two of the first power line branches are respectively connected to the first main power line, and at least two of the first power line branches are respectively used to connect at least two of the primary power loads; the first main power line is electrically connected to the primary power converter component; And / or, the first power copper foil includes a first main power line and at least one first power line branch; at least one first power line branch is connected to the first main power line, and the first main power line is connected to at least one primary power load; at least one first power line branch is respectively used to connect at least one primary power load; the first main power line is electrically connected to the primary power converter component.

3. The substrate according to claim 2, characterized in that The substrate comprises a first inner layer, the primary power converter assembly and at least two of the primary power loads are provided with a first grounding circuit at a projection position of the first inner layer adjacent to the first surface layer; The first power copper foil is provided with a first inner layer in an adjacent layer to the first surface layer; in a direction perpendicular to the substrate, an overlapping area of ​​the projections of the primary power converter assembly, the first power copper foil, and at least two primary power loads on the first inner layer and the projection of the first ground line is greater than or equal to 40%.

4. The substrate according to claim 1, characterized in that The substrate includes a substrate grounding circuit, the primary power converter component includes a negative output terminal and a positive output terminal, and the negative output terminal is electrically connected to the substrate grounding circuit; at least two of the primary power loads include a grounding pin, and at least two of the primary power loads are electrically connected to the substrate grounding circuit through the grounding pin.

5. The substrate according to any one of claims 1 to 4, characterized in that: The primary power load includes a primary electronic load, an isolation device component and a second secondary electronic load; or, the primary power load includes a secondary power converter component and a second secondary electronic load.

6. The substrate according to claim 3, characterized in that A signal line and a power line are arranged in a second inner layer adjacent to the first inner layer; in a direction perpendicular to the substrate, projections of the signal line and the power line on the first surface layer overlap with the primary power converter component, the first power copper foil and at least two of the primary power loads.

7. The substrate according to claim 3, characterized in that The first surface layer is provided with a second grounding circuit, and the second grounding circuit surrounds the primary power converter component, the first main power wiring and the at least two power wiring branches.

8. The substrate according to claim 1 or 4, characterized in that: The primary power converter component includes an output capacitor, one end of the first power copper foil is electrically connected to the positive electrode of the output capacitor and the positive electrode of the output end, and the substrate includes a substrate grounding circuit, and the substrate grounding circuit is electrically connected to the negative electrode of the output capacitor.

9. A substrate, characterized in that: It includes a first surface layer and a second surface layer, a primary power converter component is arranged on the first surface layer, and at least two primary power loads are arranged on the second surface layer, the substrate includes a first end and a second end opposite to each other along a first direction, the primary power converter component is arranged close to the first end, and at least two primary power loads are arranged close to the second end; a second power copper foil is arranged on the first surface layer, and the second power copper foil is electrically connected to the power converter; a third power copper foil is arranged on the second surface layer, and the third power copper foil is electrically connected to at least two primary power loads, and the second power copper foil is electrically connected to the third power copper foil, so as to supply power to at least two primary power loads.

10. The substrate according to claim 9, characterized in that The third power copper foil includes a second main power line and at least two second power line branches, at least two of the second power line branches are connected to the second main power line, and at least two of the second power line branches are respectively used to connect at least two of the primary power loads; the second main power line is electrically connected to the primary power converter component.

11. The substrate according to claim 9, characterized in that In a direction perpendicular to the substrate, the second power copper foil is provided with a third inner layer in an adjacent layer of the first surface layer, the primary power converter component and the second power copper foil are provided with a second ground copper foil at a projection position of the third inner layer, and the projections of the primary power converter component and at least two primary power loads on the third inner layer all fall within the range of the second ground copper foil; the substrate includes a substrate grounding circuit, and the second ground copper foil is electrically connected to the substrate grounding circuit; In a direction perpendicular to the substrate, the third power copper foil is provided with a fourth inner layer in an adjacent layer of the first surface layer or the second surface layer, the third power copper foil and a third ground copper foil are provided at a projection position of the fourth inner layer, and the projection of the third power copper foil on the fourth inner layer all falls within the range of the third ground copper foil; the substrate includes a substrate grounding circuit, and the third ground copper foil is electrically connected to the substrate grounding circuit.

12. The substrate according to claim 9, characterized in that The primary power converter component includes a negative output terminal, and the negative output terminal of the primary power converter component is electrically connected to the substrate grounding circuit; the primary power load includes a grounding pin, and the primary power load grounding pin is electrically connected to the substrate grounding circuit.

13. The substrate according to claim 9, characterized in that The second power copper foil is connected to the positive electrode pad of the output capacitor of the primary power converter assembly.

14. The substrate according to any one of claims 9 to 11, characterized in that: The primary power load includes a primary electronic load, an isolation device component and a first secondary electronic load; or, the primary power load includes a secondary power converter component and a second secondary electronic load.

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