Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises a substrate, a patterned stack structure on the substrate, the patterned stack structure comprising first dielectric layers and first conductive layers stacked alternately, the first conductive layers comprising a wire connection portion and first conductive wires connected to the wire connection portion in a first direction, and a step structure on the substrate, the step structure comprising a plurality of step layer groups stacked, the plurality of step layer groups forming a plurality of steps distributed along a second direction, and each step layer group comprising a second dielectric layer, a second conductive layer connected to the wire connection portion in the first direction, and a third dielectric layer, in the same step layer group, the third dielectric layer and the second conductive layer are arranged along the second direction, and the orthographic projection of the third dielectric layer and the second conductive layer on the substrate overlaps the orthographic projection of the second dielectric layer on the substrate, and the orthographic projection areas of the plurality of second conductive layers of the plurality of step layer groups on the substrate are the same. The embodiments of the present disclosure improve the RC delay between the conductive wires of each layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] With the development of semiconductor technology, three-dimensional memory devices have emerged. In three-dimensional memory devices, the conductive lines (such as bit lines and word lines) of each layer of memory devices are usually led out through a step structure.

[0003] However, when using the conventional step structure to lead out signals, as the number of stacked layers increases, there is a large RC delay problem between the conductive lines (such as bit lines and word lines) of each layer of memory devices. SUMMARY

[0004] Based on this, the present disclosure provides a semiconductor structure and a preparation method thereof to effectively improve the RC delay problem between the conductive lines (such as bit lines and word lines) of each layer.

[0005] A semiconductor structure, comprising:

[0006] a substrate;

[0007] a patterned stack structure on the substrate, comprising first dielectric layers and first conductive layers alternately stacked and overlapping in orthographic projection on the substrate, the first conductive layers comprising a wire connection portion and first conductive lines connected to the wire connection portion in a first direction;

[0008] a step structure on the substrate and on a side of the wire connection portion away from the first conductive lines in the first direction, comprising a plurality of step layer groups stacked, the plurality of step layer groups forming a plurality of steps distributed in a second direction, and the step layer group comprising a second dielectric layer, a second conductive layer, and a third dielectric layer, the second conductive layer connecting the wire connection portion in the first direction, and in the same step layer group, the third dielectric layer and the second conductive layer are arranged in the second direction and their orthographic projections on the substrate overlap the orthographic projection of the second dielectric layer on the substrate, the orthographic projection areas of the plurality of second conductive layers of the plurality of step layer groups on the substrate are the same, and the second direction intersects the first direction.

[0009] In one of the embodiments, in the same step layer group, the second dielectric layer is away from the substrate relative to the second conductive layer and the third dielectric layer.

[0010] In one of the embodiments, the step structure has a first step region, a non-step region, and a second step region, the first step region and the second step region are located at two sides of the non-step region in the second direction, the plurality of step groups forms the multi-step in the first step region and the second step region, and the second conductive layer is disposed in the first step region and / or the second step region in the same step group.

[0011] In one of the embodiments, the second conductive layer is disposed at two sides of the third dielectric layer in the second direction in the same step group.

[0012] In one of the embodiments, the second conductive layer is disposed at one side of the third dielectric layer in the second direction in the same step group, and the second conductive layer in the adjacent step group is disposed at opposite sides of the second direction.

[0013] In one of the embodiments, the semiconductor structure further comprises a plurality of conductive plugs, the plurality of conductive plugs respectively penetrates the multi-step to connect the corresponding second conductive layer, and the conductive plug penetrating the odd-step is located in the first step region, and the conductive plug penetrating the even-step is located in the second step region.

[0014] In one of the embodiments, the plurality of second conductive layers of the plurality of step groups are sequentially and completely staggered in the second direction.

[0015] In one of the embodiments, the plurality of second conductive layers of the plurality of step groups are sequentially and partially staggered in the second direction.

[0016] In one of the embodiments, the first conductive line is provided with the wire connecting part at two sides in the first direction, and the patterned stack structure is provided with the step structure at two sides in the first direction.

[0017] A method for manufacturing a semiconductor structure, comprising:

[0018] providing a substrate;

[0019] forming a patterned stack structure on the substrate, the patterned stack structure comprises first dielectric layers and first conductive layers which are alternately stacked and have overlapping projections on the substrate in the second direction, the first conductive layers comprise wire connecting parts and first conductive lines, and the first conductive lines are connected to the wire connecting parts in the first direction;

[0020] A step structure is formed on the substrate on the side of the wire connection portion away from the first conductive line in the first direction, the step structure comprises a plurality of step layer groups arranged in a stack, the plurality of step layer groups constitute a plurality of steps distributed in a second direction, and the step layer group comprises a second dielectric layer, a second conductive layer, and a third dielectric layer, the second conductive layer connects the wire connection portion in the first direction, and in the same step layer group, the third dielectric layer and the second conductive layer are arranged in the second direction, and the orthographic projection of the third dielectric layer and the second conductive layer on the substrate overlaps the orthographic projection of the second dielectric layer on the substrate, the orthographic projection areas of the plurality of second conductive layers of the plurality of step layer groups on the substrate are the same, and the second direction intersects the first direction.

[0021] In one of the embodiments, the step of forming a patterned stack structure on the substrate comprises:

[0022] The first dielectric material layer and the sacrificial material layer are alternately stacked on the substrate;

[0023] The first dielectric material layer and the sacrificial material layer are patterned, the remaining first dielectric material layer forms the first dielectric layer, and the remaining sacrificial material layer forms a sacrificial layer;

[0024] The sacrificial layer is removed, and the first conductive layer is formed in the removed area of the sacrificial layer.

[0025] In one of the embodiments, the material of the first dielectric material layer comprises silicon oxide, and the material of the sacrificial material layer comprises silicon nitride.

[0026] In one of the embodiments, the step of forming a step structure on the substrate on the side of the wire connection portion away from the first conductive line in the first direction comprises:

[0027] A step initial structure is formed on the substrate on the side of the wire connection portion away from the first conductive line in the first direction, the step initial structure comprises a plurality of step initial layer groups arranged in a stack, the plurality of step initial layer groups constitute a plurality of steps distributed in the second direction, and the width of the step initial layer group in the second direction decreases with the stacking height to form a plurality of steps distributed in the second direction, and the step initial layer group comprises a third dielectric initial layer and a second dielectric layer formed in sequence, and in the same step initial layer group, the orthographic projection of the third dielectric initial layer on the substrate overlaps the orthographic projection of the second dielectric layer on the substrate;

[0028] The third dielectric initial layer is laterally etched to form a hollow region, and the remaining third dielectric initial layer forms the third dielectric layer;

[0029] The second conductive layer is formed in the hollow region.

[0030] In one embodiment, the step of forming a step initial structure on the substrate on the side of the wire connection part away from the first conductive line in the first direction comprises:

[0031] alternately stacking a second dielectric material layer and a third dielectric material layer on the substrate;

[0032] performing etching on the second dielectric material layer and the third dielectric material layer to form the step initial structure, the third dielectric material layer remaining after etching forms the third dielectric initial layer, and the second dielectric material layer remaining after etching forms the second dielectric layer.

[0033] In one embodiment, the material of the second dielectric material layer comprises silicon oxide, and the material of the third dielectric material layer comprises silicon nitride.

[0034] In one embodiment, after the step of forming a step structure on the substrate on the side of the wire connection part away from the first conductive line in the first direction, the method further comprises:

[0035] forming a plurality of contact holes penetrating through the plurality of steps respectively;

[0036] forming a conductive plug in each of the contact holes, the conductive plug on each of the steps being connected to the second conductive layer corresponding to the step.

[0037] The semiconductor structure and the preparation method thereof, the first conductive line of each layer of memory device is connected to the same area of the second conductive layer through the corresponding wire connection part, so that the signal is led out through the same area of the second conductive layer, thereby effectively reducing the RC delay between the first conductive lines of each layer. Moreover, the plurality of steps are distributed in the second direction, thereby effectively saving the area of the step structure, and further facilitating the improvement of the storage density. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0039] Figure 1 a three-dimensional structure diagram of the semiconductor structure provided in one embodiment;

[0040] FIG. 2(a) is a related top structure diagram of the first conductive layer and the second conductive layer provided in one embodiment;

[0041] Figure 2(b) is a top view of the first dielectric layer in one embodiment;

[0042] Figure 3 Figure 3 is a perspective view of a semiconductor structure in one embodiment;

[0043] Figure 4 Figure 4 is a flow chart of a method of fabricating a semiconductor structure in one embodiment;

[0044] Figure 5 Figure 5 is a perspective view of a structure resulting from the formation of alternating stacks of first dielectric material layers and sacrificial material layers in a method of fabricating a semiconductor structure in one embodiment;

[0045] Figure 6(a) is a top view of the first dielectric layer after patterning the first dielectric material layers and the sacrificial material layers in a method of fabricating a semiconductor structure in one embodiment;

[0046] Figure 6(b) is a top view of the sacrificial layers after patterning the first dielectric material layers and the sacrificial material layers in a method of fabricating a semiconductor structure in one embodiment;

[0047] Figure 7 Figure 7 is a perspective view of region B in Figures 6(a) and 6(b);

[0048] Figure 8 Figure 8 is a perspective view of the structure after removing the sacrificial layers in Figure 7; Figure 7

[0049] Figure 9 Figure 9 is a perspective view of the structure after forming a first conductive layer in Figure 8; Figure 8

[0050] Figure 10 Figure 10 is a perspective view of the structure after forming a step initial structure in a method of fabricating a semiconductor structure in one embodiment;

[0051] Figure 11 Figure 11 is a perspective view of the structure after forming a hollowed region in a method of fabricating a semiconductor structure in one embodiment;

[0052] Figure 12 Figure 12 is a perspective view of the structure after forming a second conductive layer in a method of fabricating a semiconductor structure in one embodiment;

[0053] Figure 13 Figure 13 is a top view of the first conductive layer and the second conductive layer after forming a contact hole in a method of fabricating a semiconductor structure in one embodiment;

[0054] ​​Figure 14 A partial perspective view of a semiconductor structure after forming the conductive plug in the method of fabricating a semiconductor structure according to one embodiment is shown in FIG. 1C.

[0055] Figure 15 A perspective view of a semiconductor structure according to another embodiment is shown in FIG. 2.

[0056] BRIEF DESCRIPTION OF DRAWINGS

[0057] 100 - substrate; 200 - patterned stack structure; 210 - first dielectric layer; 2101 - first dielectric material layer; 220 - first conductive layer; 221 - wire connection portion; 222 - first conductive line; 230 - sacrificial layer; 2301 - sacrificial material layer; 300 - step structure; 3001 - step initial structure; 310 - step layer group; 3101 - step initial layer group; 311 - second dielectric layer; 312 - second conductive layer; 313 - third dielectric layer; 3131 - third dielectric initial layer; 400 - conductive plug; 500 - memory array; 10 - contact hole; 20 - conductive line hole. DETAILED DESCRIPTION

[0058] For the purposes of this disclosure, reference will be made to the accompanying drawings in which it is shown a preferred embodiment of the present disclosure. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the present disclosure to those skilled in the art.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the present disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure.

[0060] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, for example, a first doped type can be P-type and a second doped type can be N-type, or a first doped type can be N-type and a second doped type can be P-type.

[0061] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (for example, rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. The terms "first", "second", "third", etc. can be used herein to describe various elements, components, regions, layers and / or sections but are not intended to be limiting. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, for example, a first doped type can be P-type and a second doped type can be N-type, or a first doped type can be N-type and a second doped type can be P-type.

[0062] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It should also be understood that, when the term "comprising" is used in the specification, claims and / or the like, it can be considered that the elements or components so described are required, but not necessarily exclusive. Also, use of the "and / or" language includes any and all combinations of one or more of the associated listed items. It should also be understood that, although the terms "first", "second", "third", etc. can be used herein to describe various elements, components, regions, layers and / or sections, these terms are not intended to be limiting. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, for example, a first doped type can be P-type and a second doped type can be N-type, or a first doped type can be N-type and a second doped type can be P-type.

[0063] As described in the background, when a conventional stepped structure is used to lead out a signal, as the number of stacked layers increases, there is a large RC delay problem between the conductive lines (such as bit lines and word lines) of the memory devices of each layer.

[0064] Based on this, the embodiments of the present disclosure provide a semiconductor structure and a preparation method of the semiconductor structure. The semiconductor structure can be prepared by the preparation method of the semiconductor structure in the embodiments, but is not limited thereto. Meanwhile, the semiconductor structure and the preparation method of the semiconductor structure provided by the embodiments of the present disclosure can be applied to the preparation of a three-dimensional dynamic random access memory (DRAM) device, but are not limited thereto.

[0065] In one embodiment, referring to Figure 1 , a semiconductor structure is provided. The semiconductor structure includes a substrate 100, a patterned stack structure 200, and a stepped structure 300. The patterned stack structure 200 and the stepped structure 300 are located on different regions of the substrate 100.

[0066] It should be noted that, Figure 1 In the above embodiment, in order to make the drawings clear, the substrate 100 below the stepped structure 300 is not shown, but in fact the stepped structure 300 is also formed on the substrate 100.

[0067] The substrate 100 can include a substrate. The substrate can include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate can also include a Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator substrate, etc. Therefore, the type of the substrate should not limit the protection scope of the present disclosure.

[0068] As an example, the substrate 100 can also include a peripheral circuit structure (not shown), which can be formed based on the semiconductor substrate. Of course, the peripheral circuit structure is located away from the substrate 100 on the side of the stepped structure 300, which is not limited herein.

[0069] The patterned stack structure 200 includes first dielectric layers 210 and first conductive layers 220 arranged in an alternating stack. The bottom layer of the patterned stack structure can be the first dielectric layer 210 or the first conductive layer 220. And the top layer of the patterned stack structure can be the first dielectric layer 210 or the first conductive layer 220.

[0070] Referring to FIG. 2(a), the first conductive layer 220 includes a wire connection portion 221 and a first conductive line 222 connected to the wire connection portion 221 in a first direction.

[0071] The material of the first conductive layer 220 can include, but is not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al), etc.

[0072] As an example, the first conductive line 222 can be a bit line or a word line of a memory cell. The first conductive layer 220 can include a plurality of first conductive lines 222. The plurality of first conductive lines 222 can be arranged along a second direction. The second direction intersects the first direction. For example, the second direction can be perpendicular to the first direction. Meanwhile, on the same side in the first direction, the plurality of first conductive lines 222 can be connected to the same wire connection portion 221.

[0073] Referring to FIG. 2(b), the first dielectric layer 210 and the first conductive layer 220 are alternately stacked, have the same shape, and have overlapping orthographic projections on the substrate 100.

[0074] It can be understood that the "overlapping orthographic projections" referred to herein means that the orthographic projections are consistent and overlap each other. Meanwhile, the "overlapping orthographic projections" is a broad sense of overlapping, which allows a certain process error in actual processes.

[0075] The material of the first dielectric layer 210 includes, but is not limited to, a silicon oxide layer (SiO2), a silicon nitride layer (Si3N4), an aluminum oxide (Al2O3), or a silicon oxynitride layer (SiON).

[0076] In addition, the opening region of the patterned stack structure 200 can be filled with a fourth dielectric layer (not shown), and the opening region can further be provided with a memory cell (e.g., including a transistor, a capacitor, etc.) located in the fourth dielectric layer. The memory cell can be connected to the first conductive line 222. And a plurality of memory cells can be arranged in an array, thereby forming a memory array 500, referring to FIG. 2(a). In order to make the drawing clear, the memory array 500 is shown in a block diagram form in FIG. 2(a).

[0077] Referring to Figure 1 and FIG. 2(a), the step structure 300 is located on the side of the wire connection portion 221 away from the first conductive line 222 in the first direction. That is, the opposite sides of the wire connection portion 221 in the first direction are respectively provided with the step structure 300 and the first conductive line 222.

[0078] Referring to Figure 1The step structure 300 comprises a plurality of step layer groups 310 stacked in the second direction. Meanwhile, the plurality of step layer groups 310 stacked in the second direction constitute a plurality of steps in the second direction.

[0079] Each step layer group 310 comprises a second dielectric layer 311, a second conductive layer 312, and a third dielectric layer 313.

[0080] In the same step layer group 310, the third dielectric layer 313 and the second conductive layer 312 are arranged in the second direction, and thus are located at the same film layer position.

[0081] For example, in the same step layer group 310, the second dielectric layer 311 can be away from the substrate 100 relative to the second conductive layer 312 and the third dielectric layer 313. At this time, the third dielectric layer 313 and the second conductive layer 312 can be located at the lower layer of the step layer group 310, and the second dielectric layer 311 can be located at the upper layer of the step layer group 310.

[0082] Alternatively, in the same step layer group 310, the second dielectric layer 311 can be close to the substrate 100 relative to the second conductive layer 312 and the third dielectric layer 313. At this time, the third dielectric layer 313 and the second conductive layer 312 can be located at the upper layer of the step layer group 310, and the second dielectric layer 311 can be located at the lower layer of the step layer group 310.

[0083] Meanwhile, in the same step layer group 310, the orthographic projection of the third dielectric layer 313 and the second conductive layer 312 on the substrate 100 overlaps the orthographic projection of the second dielectric layer 311 on the substrate 100.

[0084] Referring to Figure 1 and FIG. 2(a), the second conductive layer 312 is connected to the wire connection part 221 in the first direction, and is electrically connected to the first conductive wire 222 through the wire connection part 221. The projections of the plurality of second conductive layers 312 of the plurality of step layer groups 310 on the substrate 100 can be arranged at least partially staggered in the second direction, so as to facilitate the signal of the first conductive wire 222 to be led out through the second conductive layers 312, and can effectively reduce the parasitic capacitance between the second conductive layers 312.

[0085] For example, the projections of the plurality of second conductive layers 312 of the plurality of step layer groups 310 on the substrate 100 can be arranged completely staggered in the second direction. Alternatively, the projections of the plurality of second conductive layers 312 of the plurality of step layer groups 310 on the substrate 100 can be arranged partially staggered in the second direction.

[0086] The material of the second conductive layer 312 can include, but is not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al), etc. The material of the second conductive layer 312 can be the same as or different from the material of the first conductive layer 220, which is not limited herein.

[0087] Meanwhile, in the first direction, the third dielectric layer 313 can connect the wire connection part 221, and the second dielectric layer 311 can connect the first dielectric layer 210. The thickness of the third dielectric layer 313 and the second conductive layer 312 can be the same as the thickness of the first conductive layer 220, and the thickness of the second dielectric layer 311 can be the same as the thickness of the first dielectric layer 210.

[0088] The material of the third dielectric layer 313 and / or the second dielectric layer 311 can include, but is not limited to, a silicon oxide layer (SiO2), a silicon nitride layer (Si3N4), an aluminum oxide (Al2O3), or a silicon oxynitride layer (SiON). As an example, the material of the second dielectric layer 311 can be the same as the material of the first dielectric layer 210, and different from the material of the third dielectric layer 313. For example, the material of the second dielectric layer 311 and the material of the first dielectric layer 210 can be silicon oxide, and the material of the third dielectric layer 313 can be silicon nitride.

[0089] Meanwhile, the second conductive layers 312 of the plurality of step layer groups 310 have the same area in the orthogonal projection on the substrate 100. That is, the area of each second conductive layer 312 is the same.

[0090] In the embodiment, the plurality of step layer groups 310 are configured to form a plurality of steps distributed along the second direction. The distribution direction of the steps is set to be another direction intersecting the first direction, rather than the first direction (the connection direction of the second conductive layer 312 and the first conductive layer 220). Therefore, the length of the second conductive layer 312 in the first direction can not increase with the increase of the number of stacked layers. Meanwhile, in each step layer group 310, the third dielectric layer 313 is arranged at the same film layer position as the second conductive layer 312, and the third dielectric layer 313 and the second conductive layer 312 are arranged along the second direction. Therefore, the length of the second conductive layer 312 in the second direction can also not increase with the increase of the number of stacked layers, so that the area of each second conductive layer 312 can be set to be the same. Meanwhile, the second conductive layer 312 is connected to the wire connection part 221 in the first direction. At this time, the first conductive wire 222 and the second conductive layer 312 can be effectively electrically connected through the wire connection part 221.

[0091] At this time, the first conductive lines 222 of each layer of memory device are connected to the same area of the second conductive layer 312 through the corresponding wire connection part 221, so that the signals are led out through the same area of the second conductive layer 312, and thus the RC delay between the first conductive lines 222 of each layer can be effectively reduced.

[0092] In this embodiment, the multi-step steps are distributed along the second direction, so that the area of the step structure 300 can be effectively saved, and thus the storage density can be improved.

[0093] In one embodiment, referring to Figure 1 , the step structure 300 has a first step area A1, a non-step area A2, and a second step area A3. The first step area A1, the non-step area A2, and the second step area A3 can be arranged in sequence along the second direction. That is, the first step area A1 and the second step area A3 are located on both sides of the non-step area A2 in the second direction.

[0094] The plurality of step layer groups 310 form multi-step steps in the first step area A1 and the second step area A3. In the same step layer group 310, the second conductive layer 312 can be arranged in the first step area A1 and / or the second step area A3.

[0095] At this time, the different layers of first conductive lines 222 (bit lines or word lines) can be led out through the second conductive layer 312 in the first step area A1 and the second step area A3, respectively, so as to reduce the signal interference between the different layers of first conductive lines 222.

[0096] In one embodiment, referring to Figure 1 , when the plurality of step layer groups 310 form multi-step steps in the first step area A1 and the second step area A3, the second conductive layer 312 is arranged on both sides of the third dielectric layer 313 in the second direction in the same step layer group 310.

[0097] For each step layer group 310, the second conductive layer 312 can be symmetrically arranged on both sides of the third dielectric layer 313 in the second direction. In each step layer group 310, the second conductive layer 312 on both sides of the third dielectric layer 313 in the second direction can be located at the step position of the first step area A1 and the second step area A3, respectively. At this time, the processing and preparation of the step layer group 310 are facilitated.

[0098] Of course, in other embodiments, the arrangement of the second conductive layer 312 and the third dielectric layer 313 in the step layer group 310 is not limited to this. For example, referring to Figure 15In the same step layer group 310, the second conductive layer 312 is only located on one side of the third dielectric layer 313 in the second direction. In the direction perpendicular to the substrate 100, the second conductive layer 312 in the adjacent step layer group 310 is located on the opposite sides in the second direction. At this time, in the adjacent step layer group 310 in the direction perpendicular to the substrate 100, the second conductive layer 312 can be arranged in the first step region A1 and the second step region A3, respectively.

[0099] In one embodiment, referring to Figure 3 The semiconductor structure further comprises a plurality of conductive plugs 400, which respectively pass through the multi-step and connect the corresponding second conductive layer 312. At the same time, the conductive plug 400 can extend to the peripheral circuit structure in the substrate 100, so that the conductive plug 400 is electrically connected with the peripheral circuit structure. It should be noted that Figure 3 In order to make the figure clear, the substrate 100 under the step structure 300 is moved down. However, in the actual structure, the substrate 100 under the step structure 300 and the substrate 100 under the patterned stack structure 200 are the same substrate.

[0100] Of course, the peripheral circuit structure can also be arranged on the top of the conductive plug 400, so that the conductive plug 400 is electrically connected with the peripheral circuit structure.

[0101] When the plurality of conductive plugs 400 respectively pass through the multi-step and connect the corresponding second conductive layer 312, at each step, the conductive plug 400 can pass through the second conductive layer 312 and be connected therewith. Of course, the connection between the conductive plug 400 and the second conductive layer 312 is not limited to this. For example, in some embodiments, the second conductive layer 312 can also be provided with a third dielectric layer 313 (not shown) on both sides in the second direction, at this time, the conductive plug 400 can also pass through the third dielectric layer 313 and connect the second conductive layer 312 in the second direction. Or, the conductive plug 400 can also pass through the third dielectric layer 313 and the second conductive layer 312 at the same time.

[0102] At the same time, the plurality of step layer groups 310 are arranged in the first step region A1 and the second step region A3 to form multi-step. And the conductive plug 400 passing through the odd step is located in the first step region A1, and the conductive plug 400 passing through the even step is located in the second step region A3.

[0103] At this time, the conductive plug 400 for leading out the signal of the different layer first conductive line 222 (bit line or word line) can be arranged in the first step region A1 and the second step region A3, respectively, so as to reduce the arrangement density of the conductive plug 400, and thus the risk of short circuit between the conductive plugs 400 can be effectively prevented.

[0104] In one embodiment, referring toFigure 1 As shown in FIG. 2(a), the first conductive lines 222 are provided with wire connection portions 221 on both sides in the first direction, and the patterned stack structure 200 is provided with step structures 300 on both sides in the first direction.

[0105] At this time, as an example, referring to FIG. 2(a), the semiconductor structure can include two wire connection portions 221 extending in the second direction. The two wire connection portions 221 are oppositely arranged in the first direction.

[0106] A plurality of first conductive lines 222 (such as bit lines or word lines) are arranged in the second direction between the two wire connection portions 221. Each first conductive line 222 is arranged to be connected to the two wire connection portions 221 on both sides in the first direction.

[0107] At this time, the first conductive lines 222 (bit lines or word lines) in different layers can be connected to the second conductive layers 312 in different step structures 300 through different wire connection portions 221 to lead out signals, so as to reduce the signal interference between the first conductive lines 222 in different layers. At the same time, the conductive plugs 400 arranged on the second conductive layers 312 can be distributed on the step structures 300 on both sides of the patterned stack structure 200 in the first direction, so as to reduce the arrangement density of the conductive plugs 400, and further effectively prevent the short circuit risk between the conductive plugs 400.

[0108] In one embodiment, referring to Figure 4 A preparation method of a semiconductor structure is also provided, including the following steps:

[0109] Step S10, providing a substrate 100;

[0110] Step S20, forming a patterned stack structure 200 on the substrate 100, the patterned stack structure 200 including first dielectric layers 210 and first conductive layers 220 alternately stacked and overlapping in orthographic projection on the substrate 100, the first conductive layers 220 including wire connection portions 221 and first conductive lines 222, the first conductive lines 222 being connected to the wire connection portions 221 in the first direction;

[0111] At step S30, a step structure 300 is formed on the substrate 100 at a side of the wire connecting part 221 away from the first conductive wire 222 in the first direction, the step structure 300 includes a plurality of step layer groups 310 stacked, the plurality of step layer groups 310 form a plurality of steps distributed in a second direction, and the step layer group 310 includes a second dielectric layer 311, a second conductive layer 312, and a third dielectric layer 313, the second conductive layer 312 is connected to the wire connecting part 221 in the first direction, and in the same step layer group 310, the third dielectric layer 313 and the second conductive layer 312 are arranged in the second direction, and the orthographic projection of the third dielectric layer 313 and the second conductive layer 312 on the substrate 100 overlaps the orthographic projection of the second dielectric layer 311 on the substrate 100, and the orthographic projection areas of the plurality of second conductive layers 312 of the plurality of step layer groups 310 on the substrate 100 are the same, and the second direction intersects the first direction.

[0112] In step S10, the substrate 100 can include a substrate. The substrate can include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate can also include a Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator, etc. substrate. Therefore, the type of substrate should not limit the protection scope of the present disclosure.

[0113] As an example, the substrate 100 can also include a peripheral circuit structure, which can be formed based on the semiconductor substrate. Of course, the peripheral circuit structure can also be formed after the step structure 300 is formed, which is not limited here.

[0114] In step S20, referring to Figure 5 and Figure 9 , the patterned stack structure 200 can be formed on the first region A4 of the substrate 100, which can be formed through a patterning process. The patterned stack structure 200 includes the first dielectric layer 210 and the first conductive layer 220. The bottom layer of the patterned stack result can be the first dielectric layer 210, or the first conductive layer 220. And the top layer of the patterned stack result can be the first dielectric layer 210, or the first conductive layer 220.

[0115] The first dielectric layer 210 and the first conductive layer 220 are alternately stacked, both have the same shape, and the orthographic projections of both on the substrate 100 overlap.

[0116] It can be understood that the "orthographic projection overlap" referred to herein means that the outlines of the orthographic projections are consistent and overlap each other. At the same time, the "orthographic projection overlap" is a broad overlap, which allows for a certain process error in actual processes.

[0117] The material of the first conductive layer 220 can include, but is not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al), etc.

[0118] The first conductive layer 220 includes a wire connection portion 221 and a first conductive wire 222 connected to the wire connection portion 221 in a first direction.

[0119] As an example, the first conductive wire 222 can be a bit line or a word line of a memory cell. The first conductive layer 220 can include a plurality of first conductive wires 222. The plurality of first conductive wires 222 can be arranged along a second direction. The second direction intersects the first direction. For example, the second direction can be perpendicular to the first direction. Meanwhile, on the same side in the first direction, the plurality of first conductive wires 222 can be connected to the same wire connection portion 221.

[0120] The material of the first dielectric layer 210 includes, but is not limited to, a silicon oxide layer (SiO2), a silicon nitride layer (Si3N4), an aluminum oxide layer (Al2O3), or a silicon oxynitride layer (SiON). l2 O3) or a silicon oxynitride layer (SiON).

[0121] In step S30, referring to Figure 5 and Figure 12 , a step structure 300 can be formed on the substrate 100 in a second region A5. The second region A5 is connected to the first region A4 in the first direction. As an example, the second region A5 is located at an edge of the substrate 100 in the first direction.

[0122] Before forming the step structure 300, the fourth dielectric layer can be first filled in the opening region of the patterned stack structure 200 in the first region A4, so as to fill the first region A4 flat. The material of the fourth dielectric layer can include, but is not limited to, a silicon oxide layer (SiO2), a silicon nitride layer (Si3N4), an aluminum oxide layer (Al2O3), or a silicon oxynitride layer (SiON).

[0123] The fourth dielectric layer can be a single-layer structure or a multi-layer structure.

[0124] As an example, before forming the step structure 300, in addition to filling the fourth dielectric layer in the opening region of the patterned stack structure 200, a memory cell (for example, including a transistor, a capacitor, etc.) located in the fourth dielectric layer can also be formed in the opening region. The memory cell can be arranged in an array, forming a memory array.

[0125] After filling the fourth dielectric layer, the step structure 300 is formed, so that the formation of the step structure 300 will not affect the structure in the first region A4.

[0126] After the step structure 300 is formed, a plurality of step layer groups 310 are formed in a stacked manner. Meanwhile, the plurality of step layer groups 310 constitute a plurality of steps distributed along the second direction.

[0127] Each step layer group 310 includes a second dielectric layer 311, a second conductive layer 312, and a third dielectric layer 313.

[0128] In the same step layer group 310, the third dielectric layer 313 and the second conductive layer 312 are arranged along the second direction, and thus are located at the same film layer position.

[0129] For example, in the same step layer group 310, the second dielectric layer 311 can be away from the substrate 100 relative to the second conductive layer 312 and the third dielectric layer 313. At this time, the third dielectric layer 313 and the second conductive layer 312 can be located at the lower layer of the step layer group 310, and the second dielectric layer 311 can be located at the upper layer of the step layer group 310.

[0130] Alternatively, in the same step layer group 310, the second dielectric layer 311 can be close to the substrate 100 relative to the second conductive layer 312 and the third dielectric layer 313. At this time, the third dielectric layer 313 and the second conductive layer 312 can be located at the upper layer of the step layer group 310, and the second dielectric layer 311 can be located at the lower layer of the step layer group 310.

[0131] Meanwhile, in the same step layer group 310, the orthographic projection of the third dielectric layer 313 and the second conductive layer 312 on the substrate 100 overlaps the orthographic projection of the second dielectric layer 311 on the substrate 100.

[0132] The second conductive layer 312 is connected to the wire connection part 221 in the first direction, and is electrically connected to the first conductive wire 222 through the wire connection part 221. The projections of the plurality of second conductive layers 312 of the plurality of step layer groups 310 on the substrate 100 can be arranged at least partially staggered along the second direction, so as to facilitate the signal output of the first conductive wire 222 through the second conductive layers 312, and can effectively reduce the parasitic capacitance between the second conductive layers 312.

[0133] For example, the projections of the plurality of second conductive layers 312 of the plurality of step layer groups 310 on the substrate 100 can be arranged completely staggered along the second direction. Alternatively, the projections of the plurality of second conductive layers 312 of the plurality of step layer groups 310 on the substrate 100 can be arranged partially staggered along the second direction.

[0134] The material of the second conductive layer 312 can include, but is not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), tantalum titanium (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al), etc. The material of the second conductive layer 312 can be the same as or different from the material of the first conductive layer 220, which is not limited herein.

[0135] Meanwhile, in the first direction, the third dielectric layer 313 can be connected to the wire connection part 221, and the second dielectric layer 311 can be connected to the first dielectric layer 210. The thickness of the third dielectric layer 313 and the second conductive layer 312 can be the same as the thickness of the first conductive layer 220, and the thickness of the second dielectric layer 311 can be the same as the thickness of the first dielectric layer 210.

[0136] The material of the third dielectric layer 313 and / or the second dielectric layer 311 can include, but is not limited to, a silicon oxide layer (SiO2), a silicon nitride layer (Si3N4), an aluminum oxide (Al2O3), or a silicon oxynitride layer (SiON). As an example, the material of the second dielectric layer 311 can be the same as the material of the first dielectric layer 210 and different from the material of the third dielectric layer 313. For example, the material of the second dielectric layer 311 and the material of the first dielectric layer 210 can be silicon oxide, and the material of the third dielectric layer 313 can be silicon nitride.

[0137] Meanwhile, the second conductive layers 312 of the plurality of step layer groups 310 have the same area in the orthographic projection on the substrate 100. That is, each of the second conductive layers 312 has the same area.

[0138] In the embodiment, the first conductive wires 222 of each layer of memory devices are connected to the second conductive layers 312 with the same area through the corresponding wire connection parts 221, so that the signals are led out through the second conductive layers 312 with the same area, and thus the RC delay between the first conductive wires 222 of each layer can be effectively reduced. In addition, the multiple steps are distributed along the second direction, so that the area of the step structure 300 can be effectively saved, and thus the storage density can be improved.

[0139] In one embodiment, the step S20 includes:

[0140] In step S21, the first dielectric material layers 2101 and the sacrificial material layers 2301 are alternately stacked on the substrate 100, please refer to FIG. 5(a). Figure 5

[0141] In step S22, the first dielectric material layers 2101 and the sacrificial material layers 2301 are patterned, and the remaining first dielectric material layers 2101 form the first dielectric layer 210, please refer to FIG. 6(a), and the remaining sacrificial material layers 2301 form the sacrificial layer 230, please refer to FIG. 6(b).​

[0142] Step S23, removing the sacrificial layer 230, and forming the first conductive layer 220 in the region where the sacrificial layer 230 is removed, please refer to Figure 7 to Figure 9 .

[0143] In step S21, please refer to Figure 5 , the first dielectric material layer 2101 and the sacrificial material layer 2301 can be formed on the substrate 100 by deposition process. As an example, the material of the first dielectric material layer 2101 can include silicon oxide, and the material of the sacrificial material layer 2301 can include silicon nitride.

[0144] The deposition process can include, but not limited to, one or more of the following processes: chemical vapor deposition (CVD), atomic layer deposition (ALD), high-density plasma (HDP) deposition, plasma-enhanced deposition, and spin-on dielectric (SOD) process.

[0145] As an example, the first dielectric material layer 2101 can be formed on the surface of the substrate 100 first, and then the sacrificial material layer 2301 can be formed, and then the first dielectric material layer 2101 and the sacrificial material layer 2301 can be alternately formed. At this time, after the first conductive layer 220 is formed in the subsequent step S23, the first conductive layer 220 can be effectively isolated from the substrate 100 by the first dielectric layer 210. Of course, in other examples, the sacrificial material layer 2301 can be formed on the surface of the substrate 100 first. Herein, no limitation is made.

[0146] As an example, after the first dielectric material layer 2101 and the sacrificial material layer 2301 are alternately stacked on the substrate 100, the top layer of the stacked layer can be the first dielectric material layer 2101. At this time, after the sacrificial layer 230 is removed in the subsequent step S23, the top first dielectric layer 210 can be effectively retained. Of course, in other examples, after the first dielectric material layer 2101 and the sacrificial material layer 2301 are alternately stacked on the substrate 100, the top layer of the stacked layer can also be the sacrificial material layer 2301. Herein, no limitation is made.

[0147] In step S22, the first dielectric material layer 2101 and the sacrificial material layer 2301 can be formed on the first dielectric material layer 2101 and the sacrificial material layer 2301. Then, based on the patterned photoresist, the first dielectric material layer 2101 and the sacrificial material layer 2301 are dry etched to form the first dielectric layer 210 and the sacrificial layer 230, please refer to FIG. 6(a) and FIG. 6(b). Then, the patterned photoresist can be removed.

[0148] In step S23, dry etching can be performed on the sacrificial layer 230 from the region where the first dielectric material layer 2101 and the sacrificial material layer 2301 are etched away, so as to remove the sacrificial layer 230. Please refer to Figure 7 and Figure 8 .

[0149] Then, the first conductive layer 220 can be formed in the region where the sacrificial layer 230 is removed by electroplating or chemical vapor deposition, etc. Please refer to Figure 9 .

[0150] In this embodiment, the first dielectric material layer 2101 and the sacrificial material layer 2301 are first alternately stacked, so as to facilitate good etching and good patterning in the process of forming the patterned stack structure 200. Of course, in other embodiments, the first dielectric material layer 2101 and the first conductive material layer can be directly alternately stacked in the process of forming the patterned stack structure 200, and then the two are patterned to form the first dielectric layer 210 and the first conductive layer 220.

[0151] In one embodiment, step S30 includes:

[0152] In step S31, please refer to Figure 10 , a step initial structure 3001 is formed on the substrate 100 away from the first conductive wire 222 along the first direction on the side of the wire connection part 221, the step initial structure 3001 includes a plurality of step initial layer groups 3101 stacked, the width of the plurality of step initial layer groups 3101 in the second direction decreases with the stacking height to form a plurality of steps distributed along the second direction, and the step initial layer group 3101 includes a third dielectric initial layer 3131 and a second dielectric layer 311 formed in sequence, and in the same step initial layer group 3101, the orthographic projection of the third dielectric initial layer 3131 on the substrate 100 overlaps the orthographic projection of the second dielectric layer 311 on the substrate 100;

[0153] In step S32, please refer to Figure 11 , the third dielectric initial layer 3131 is laterally etched to form a hollow region, and the remaining third dielectric initial layer 3131 forms a third dielectric layer 313;

[0154] In step S33, please refer to Figure 12 , a second conductive layer 312 is formed in the hollow region.

[0155] In step S31, please refer to Figure 10The third dielectric initial layer 3131 can be disposed opposite to the first conductive layer 220, and the two can have the same thickness. The second dielectric layer 311 can be disposed opposite to the first dielectric layer 210, and the two can have the same thickness.

[0156] As an example, step S31 may include:

[0157] Step S311: A second dielectric material layer and a third dielectric material layer are alternately stacked on the substrate 100;

[0158] Step S312: Etch the second dielectric material layer and the third dielectric material layer to form a step initial structure 3001. The remaining third dielectric material layer after etching forms the third dielectric initial layer 3131, and the remaining second dielectric material layer after etching forms the second dielectric layer 311.

[0159] In step S311, a second dielectric material layer and a third dielectric material layer can be formed by alternating stacking on the substrate 100 through a deposition process.

[0160] As an example, the material of the second dielectric material layer includes silicon oxide, and the material of the third dielectric material layer includes silicon nitride.

[0161] In step S312, the second dielectric material layer and the third dielectric material layer can be etched by means of cyclic shrinkage photoresist to form the initial step structure 3001.

[0162] As an example, the initial step structure 3001 may include two sets of multi-step steps symmetrically arranged in the second direction.

[0163] In step S32, please refer to Figure 10 as well as Figure 11 The initial layer 3131 of the third medium can be etched laterally by wet etching to form a hollow area.

[0164] When the initial structure 3001 of the steps can include two sets of multi-step steps symmetrically arranged in the second direction, the initial layer 3131 of the third medium can be laterally etched on both sides in the second direction to form a symmetrical hollow area.

[0165] In step S33, please refer to Figure 12 A second conductive layer 312 can be formed in the hollowed-out area through processes such as electroplating or chemical vapor deposition.

[0166] When a symmetrical hollow area is formed, a symmetrical second conductive layer 312 can be formed on both sides of the third dielectric layer 313 along the second direction.

[0167] In the embodiment, the hollowed region is formed by lateral etching, and then the second conductive layer 312 is formed in the hollowed region. The lateral etching technology is mature and controllable, and can effectively control the same area of the orthogonal projection of the different second conductive layers 312 on the substrate 100, thereby effectively reducing the RC delay. At the same time, the steps of the semiconductor structure can be prepared in a single piece, thereby reducing the wafer process cost.

[0168] In one embodiment, after step S30, further comprising:

[0169] In step S40, a plurality of contact holes 10 are formed to respectively penetrate the plurality of steps, please refer to Figure 13 ;

[0170] In step S50, a conductive plug 400 is formed in the contact hole 10, and the conductive plug 400 on each step is connected to the second conductive layer 312 corresponding to the step, please refer to Figure 14 .

[0171] In step S40, the plurality of contact holes 10 can penetrate the second conductive layer 312 corresponding to each step. The second conductive layer 312 can be completely staggered, thereby facilitating the formation of mutually spaced contact holes 10. Of course, the second conductive layer 312 can also be partially staggered.

[0172] In step S50, a plug material layer can be first deposited, and then subjected to chemical mechanical polishing (CMP) treatment, thereby forming the conductive plug 400.

[0173] The conductive plug 400 can extend to the peripheral circuit structure located in the substrate 100, thereby making the conductive plug 400 electrically connected with the peripheral circuit structure. Alternatively, the peripheral circuit structure can be formed on the top of the conductive plug 400 after the formation of the conductive plug 400, thereby making the conductive plug 400 electrically connected with the peripheral circuit structure.

[0174] The material of the conductive plug 400 can include, but is not limited to, cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), titanium tantalum (TaTi), tungsten nitride (WN), copper (Cu), and aluminum (Al), etc. The material of the conductive plug 400 can be the same as or different from the material of the second conductive layer 312.

[0175] As an example, when the two sides of the third medium layer 313 along the second direction form symmetrical second conductive layers 312, the step structure 300 can include two groups of multi-step structures symmetrically arranged in the second direction. One group of multi-step structures is located in the first step area A1, and the other group of multi-step structures is located in the second step area A3, and the area between them is the non-step area A2.

[0176] At this time, the contact holes 10 penetrating the odd-order steps can be arranged in the first step region A1, and the contact holes 10 penetrating the even-order steps can be arranged in the second step region A3. At this time, the density of the contact holes 10 can be effectively reduced, and then the density of the conductive plugs 400 formed subsequently can be reduced, thereby preventing short circuit between the conductive plugs 400.

[0177] As an example, the second region A5 in which the step structure 300 is formed can be located on both sides of the first region A4 in which the patterned stack structure 200 is formed, so that the step structure 300 is located on both sides of the patterned stack structure 200 along the first direction.

[0178] At this time, the first conductive lines 222 formed in the first region A4 can be led out from the second conductive layers 312 located on both sides thereof along the first direction, and then the arrangement flexibility of the contact holes 10 and the conductive plugs 400 on the second conductive layers 312 can be improved, and then the arrangement density thereof can be reduced.

[0179] Meanwhile, as an example, the step S40 of forming the plurality of contact holes 10 penetrating the plurality of steps respectively can also form the conductive line holes 20 penetrating the patterned stack structure 200. The step S50 of forming the conductive plugs 400 in the contact holes 10 can also form second conductive lines (not shown) in the conductive line holes 20. One of the second conductive lines and the first conductive lines 222 is a bit line, and the other is a word line.

[0180] It should be understood that, although Figure 4 The steps in the flowchart of the above-mentioned embodiments are shown in sequence according to the arrows, but these steps are not necessarily executed in sequence according to the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, Figure 4 At least part of the steps in the above-mentioned embodiments can include a plurality of steps or a plurality of stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or steps or stages in other steps.

[0181] The technical features of the above-mentioned embodiments can be combined in any way. In order to make the description concise, all possible combinations of the technical features of the above-mentioned embodiments are not described, but as long as the combination of the technical features does not exist, it should be considered as the scope of the description.

[0182] The above-described embodiments are merely illustrative of several embodiments of the present disclosure, which are described in a relatively specific and detailed manner, but should not be construed as limiting the scope of the patent application. It should be noted that for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure should be subject to the appended claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; a patterned stack structure on the substrate, comprising first dielectric layers and first conductive layers arranged in an alternating stack and overlapping in orthographic projection on the substrate, the first conductive layers comprising wire connection portions and first conductive wires connected to the wire connection portions in a first direction; a step structure on the substrate and on a side of the wire connection portions away from the first conductive wires in the first direction, comprising a plurality of step layer groups arranged in a stack, the plurality of step layer groups constituting a plurality of steps distributed in a second direction, and the step layer groups comprising second dielectric layers, second conductive layers, and third dielectric layers, the second conductive layers connecting the wire connection portions in the first direction, and in the same step layer group, the third dielectric layers and the second conductive layers are arranged in the second direction and their orthographic projections on the substrate overlap with the orthographic projection of the second dielectric layers on the substrate, the orthographic projection areas of the second conductive layers of the plurality of step layer groups on the substrate are the same, and the second direction intersects the first direction.

2. The semiconductor structure of claim 1, wherein, In the same step layer group, the second dielectric layers are away from the substrate relative to the second conductive layers and the third dielectric layers.

3. The semiconductor structure of claim 1, wherein, The step structure has a first step region, a non-step region, and a second step region, the first step region and the second step region are located on both sides of the non-step region in the second direction, the plurality of step layer groups constitute the plurality of steps in the first step region and the second step region, and in the same step layer group, the second conductive layers are arranged in the first step region and / or the second step region.

4. The semiconductor structure of claim 3, wherein, In the same step layer group, the second conductive layers are located on both sides of the third dielectric layers in the second direction.

5. The semiconductor structure of claim 3, wherein, In the same step layer group, the second conductive layers are located on only one side of the third dielectric layers in the second direction, and the second conductive layers in adjacent step layer groups are located on opposite sides in the second direction in a direction perpendicular to the substrate.

6. The semiconductor structure of claim 3, wherein, The semiconductor structure further comprises a plurality of conductive plugs, the plurality of conductive plugs respectively penetrate the plurality of steps to connect corresponding second conductive layers, and the conductive plugs penetrating odd-numbered steps are located in the first step region, and the conductive plugs penetrating even-numbered steps are located in the second step region.

7. The semiconductor structure of claim 1, wherein, The plurality of second conductive layers of the plurality of step layer groups are arranged in the second direction in sequence and completely staggered.

8. The semiconductor structure of claim 1, wherein, The plurality of second conductive layers of the plurality of step layer groups are arranged in the second direction in sequence and partially staggered.

9. The semiconductor structure of claim 1, wherein, The first conductive wires are provided with the wire connection portions on both sides in the first direction, and the patterned stack structure is provided with the step structure on both sides in the first direction.

10. A method of fabricating a semiconductor structure, characterized by, The semiconductor structure comprises: providing a substrate; forming a patterned stack structure on the substrate, the patterned stack structure comprising first dielectric layers and first conductive layers arranged in an alternating stack and overlapping in orthographic projection on the substrate, the first conductive layers comprising wire connection portions and first conductive wires connected to the wire connection portions in a first direction; A step structure is formed on the substrate on the side of the wire connection portion away from the first conductive line in the first direction, the step structure comprises a plurality of step layer groups stacked, the plurality of step layer groups constitute a plurality of steps distributed in a second direction, and the step layer group comprises a second dielectric layer, a second conductive layer and a third dielectric layer, the second conductive layer connects the wire connection portion in the first direction, and in the same step layer group, the third dielectric layer and the second conductive layer are arranged in the second direction, and the orthographic projection of the third dielectric layer and the second conductive layer on the substrate overlaps the orthographic projection of the second dielectric layer on the substrate, the orthographic projection areas of the plurality of second conductive layers of the plurality of step layer groups on the substrate are the same, and the second direction intersects the first direction.

11. The method of claim 10, wherein the semiconductor structure is prepared by a method comprising: The forming a patterned stack structure on the substrate comprises: alternately stacking a first dielectric material layer and a sacrificial material layer on the substrate; performing a patterning process on the first dielectric material layer and the sacrificial material layer, the remaining first dielectric material layer forms the first dielectric layer, and the remaining sacrificial material layer forms a sacrificial layer; removing the sacrificial layer, and forming the first conductive layer in the removed area of the sacrificial layer.

12. The method of claim 11, wherein the semiconductor structure is prepared by a method comprising: The material of the first dielectric material layer comprises silicon oxide, and the material of the sacrificial material layer comprises silicon nitride.

13. The method of claim 10, wherein the semiconductor structure is prepared by a method comprising: The forming a step structure on the substrate on the side of the wire connection portion away from the first conductive line in the first direction comprises: forming a step initial structure on the substrate on the side of the wire connection portion away from the first conductive line in the first direction, the step initial structure comprises a plurality of step initial layer groups stacked, the plurality of step initial layer groups in the second direction have widths that decrease in turn with the stacking height to constitute a plurality of steps distributed in the second direction, and the step initial layer group comprises a third dielectric initial layer and a second dielectric layer formed in turn, and in the same step initial layer group, the orthographic projection of the third dielectric initial layer on the substrate overlaps the orthographic projection of the second dielectric layer on the substrate; laterally etching the third dielectric initial layer to form a hollow region, and the remaining third dielectric initial layer forms the third dielectric layer; forming the second conductive layer in the hollow region.

14. The method of claim 13, wherein the semiconductor structure is prepared by a method comprising: The forming a step initial structure on the substrate on the side of the wire connection portion away from the first conductive line in the first direction comprises: alternately stacking a second dielectric material layer and a third dielectric material layer on the substrate; performing etching on the second dielectric material layer and the third dielectric material layer to form the step initial structure, the third dielectric material layer remaining after etching forms the third dielectric initial layer, and the second dielectric material layer remaining after etching forms the second dielectric layer.

15. The method of claim 10, wherein the semiconductor structure is prepared by a method comprising: After the forming a step structure on the substrate on the side of the wire connection portion away from the first conductive line in the first direction, the method further comprises: forming a plurality of contact holes penetrating the plurality of steps respectively; forming a conductive plug in each of the contact holes, and the conductive plug on each step connects the corresponding second conductive layer of the step.

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