Semiconductor element and manufacturing method thereof

Abstract

A semiconductor device includes a landing pad, a first nitride layer, a first oxide layer, a second nitride layer, a second oxide layer, a third nitride layer, and an electrode layer. The first nitride layer is disposed over the landing pad. The first oxide layer is disposed on the first nitride layer. The second nitride layer is disposed on the first oxide layer. The second oxide layer is disposed on the second nitride layer. The third nitride layer is disposed on the second oxide layer. The trench penetrates the third nitride layer, the second oxide layer, the second nitride layer, the first oxide layer, and the first nitride layer. The trench further has an extension through the first nitride layer. The width of the top of the extended portion of the trench is greater than or equal to the width of the top of the trench. The electrode layer is disposed on the inner sidewall of the trench and on the top surface of the third nitride layer. As a whole, the manufacturing method of the semiconductor element improves the electrical performance of the whole semiconductor element.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] As semiconductor processes continue to evolve, the process of forming trenches will face challenges. For example, in a semiconductor structure of a dynamic random access memory (DRAM), the trenches are preferably manufactured to have a high aspect ratio. However, due to the large etching resistance of the nitride layer, the portion of the trench passing through the nitride layer may experience a shrinkage problem, resulting in a high resistance between the electrode layer and the landing pad formed in subsequent processes. Summary of the Invention

[0003] In view of this, an object of the present disclosure is to provide a semiconductor device and a method for manufacturing the same that can solve the above problems.

[0004] According to an embodiment of the present disclosure, a semiconductor device includes a landing pad, a first nitride layer, a first oxide layer, a second nitride layer, a second oxide layer, a third nitride layer, and an electrode layer. The first nitride layer is disposed above the landing pad. The first oxide layer is disposed on the first nitride layer. The second nitride layer is disposed on the first oxide layer. The second oxide layer is disposed on the second nitride layer. The third nitride layer is disposed on the second oxide layer. A trench penetrates through the third nitride layer, the second oxide layer, the second nitride layer, the first oxide layer, and the first nitride layer. The trench further has an extended portion passing through the first nitride layer. The width of the top of the extended portion of the trench is greater than or equal to the width of the top of the trench. The electrode layer is disposed on the inner sidewall of the trench and on the top surface of the third nitride layer.

[0005] In one or more embodiments of the present disclosure, the electrode layer contacts the landing pad.

[0006] In one or more embodiments of the present disclosure, the extended portion of the trench is located above the landing pad.

[0007] In one or more embodiments of the present disclosure, the width of the extended portion of the trench tapers downward from the top surface of the first nitride layer to the top surface of the landing pad.

[0008] In one or more embodiments of the present disclosure, the width of the top of the extended portion of the trench is greater than the width of the bottom of the extended portion of the trench.

[0009] In one or more embodiments of the present disclosure, the width of the top of the extended portion of the trench is greater than the width of the top of the trench.

[0010] In one or more embodiments of the present disclosure, the height from the top surface of the first nitride layer to the top surface of the landing pad is in the range of 20 nanometers to 25 nanometers.

[0011] In one or more embodiments of the present disclosure, the first oxide layer comprises borophosphosilicate glass.

[0012] In one or more embodiments of the present disclosure, the second oxide layer comprises tetraethylorthosilicate.

[0013] To achieve the above object, according to an embodiment of the present disclosure, a method for manufacturing a semiconductor device includes: sequentially forming a landing pad, a first nitride layer, a first oxide layer, a second nitride layer, a second oxide layer, and a third nitride layer; forming a trench penetrating through the third nitride layer, the second oxide layer, the second nitride layer, and the first oxide layer; depositing a protective liner layer on the inner sidewalls of the trench and on the top surface of the third nitride layer; punching through the first nitride layer to expose the landing pad; isotropically etching the first nitride layer to form an extension portion and increase the overall width of the extension portion; removing the protective liner layer; and depositing an electrode layer on the inner sidewalls of the trench and on the top surface of the third nitride layer.

[0014] In one or more embodiments of the present disclosure, performing the step of forming the trench exposes the first nitride layer.

[0015] In one or more embodiments of the present disclosure, performing the deposition of the protective liner layer causes the protective liner layer to contact the top surface of the first nitride layer.

[0016] In one or more embodiments of the present disclosure, performing the step of punching through the first nitride layer to expose the landing pad removes the portion of the protective liner layer located on the top surface of the first nitride layer.

[0017] In one or more embodiments of the present disclosure, the step of isotropically etching the first nitride layer is performed after the step of punching through the first nitride layer to expose the landing pad.

[0018] In one or more embodiments of the present disclosure, performing the step of isotropically etching the first nitride layer causes an extension portion of the trench to be formed, and the extension portion of the trench penetrates through the first nitride layer.

[0019] In one or more embodiments of the present disclosure, performing the step of isotropically etching the first nitride layer causes the extension portion of the trench to be connected between the landing pad and the top surface of the first nitride layer.

[0020] In one or more embodiments of the present disclosure, performing the step of isotropically etching the first nitride layer causes the width of the top of the extension portion of the trench to be greater than the width of the bottom of the extension portion of the trench.

[0021] In one or more embodiments of the present disclosure, performing the step of performing isotropic etching on the first nitride layer causes the width of the top of the extended portion of the trench to be greater than or equal to the width of the top of the trench.

[0022] In one or more embodiments of the present disclosure, performing the step of depositing the electrode layer causes the electrode layer to contact the landing pad.

[0023] In one or more embodiments of the present disclosure, the thickness of the protective liner layer is greater than or equal to 2 nanometers.

[0024] In summary, in the semiconductor device and its manufacturing method of the present disclosure, since the protective liner layer lines the inner sidewalls of the trenches, the critical dimensions of the trenches are not enlarged after performing the step of punching through the first nitride layer. In the semiconductor device and its manufacturing method of the present disclosure, since only the portion of the protective liner layer located on the top surface of the first nitride layer is removed, only the width of the bottom of the trench increases when performing the step of isotropic etching on the first nitride layer. In the semiconductor device and its manufacturing method of the present disclosure, since the trench has an extended portion when performing the step of isotropic etching on the first nitride layer, the contact area between the electrode layer and the landing pad can be increased, thereby reducing the resistance between the electrode layer and the landing pad. Overall, the manufacturing method of the semiconductor device of the present disclosure improves the electrical performance of the entire semiconductor device.

[0025] The above is only used to elaborate on the problems to be solved by the present disclosure, the technical means for solving the problems, and the effects produced thereby. The specific details of the present disclosure will be introduced in detail in the following embodiments and related drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] To make the above and other objects, features, advantages, and embodiments of the present disclosure more obvious and understandable, the descriptions of the accompanying drawings are as follows:

[0027] Figure 1 FIG. is a flowchart showing a manufacturing method of a semiconductor device according to an embodiment of the present disclosure.

[0028] Figure 2 FIG. is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0029] Figure 3 FIG. is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0030] Figure 4 FIG. is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0031] Figure 5 FIG. is a cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0032] Figure 6 A cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0033] Figure 7 A cross-sectional view showing an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure. Detailed Embodiments

[0034] The following disclosure provides many different embodiments or examples for implementing different features of the provided patent subject matter. Specific examples of components and configurations are illustrated below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various embodiments. Such repetition is for simplicity and clarity purposes and does not itself prescribe a relationship between the various embodiments and / or configurations discussed.

[0035] In addition, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship between one element or feature shown in the drawings and another. Except for the orientation depicted in the figures, spatially relative terms are intended to encompass different orientations of the device during use or operation. The device may be positioned otherwise (rotated 90 degrees or in other orientations) and the spatially relative terms used herein may be interpreted accordingly.

[0036] As used herein, "about", "approximately", "substantially" or "essentially" generally means within 20%, or within 10%, or within 5% of a given value or range. The numerical values given herein are approximate, meaning that the terms "about", "approximately", "substantially" or "essentially" can be inferred if not explicitly stated.

[0037] Please refer to Figure 1 . Figure 1 A flowchart of a method M for manufacturing a semiconductor device 100 as shown in Figure 7 according to an embodiment of the present disclosure. Figure 1 The method M shown includes steps S101, S102, S103, S104, S105, S106, and S107. For a better understanding of steps S101 and S102, please refer to Figure 1 andFigure 2 For a better understanding of step S103, please refer to Figure 1 and Figure 3 For a better understanding of step S104, please refer to Figure 1 and Figure 4 For a better understanding of step S105, please refer to Figure 1 and Figure 5 For a better understanding of step S106, please refer to Figure 1 and Figure 6 For a better understanding of step S107, please refer to Figure 1 and Figure 7 .

[0038] Steps S101, S102, S103, S104, S105, S106 and S107 are described in detail below.

[0039] In step S101, a landing pad 110, a first nitride layer 120, a first oxide layer 130, a second nitride layer 140, a second oxide layer 150, and a third nitride layer 160 are sequentially formed.

[0040] Please refer to Figure 1 and Figure 2 . Figure 2 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. In this embodiment, a landing pad 110, a first nitride layer 120, a first oxide layer 130, a second nitride layer 140, a second oxide layer 150, and a third nitride layer 160 are sequentially formed. More specifically, the first nitride layer 120 is disposed above the landing pad 110. In some embodiments, the first nitride layer 120 covers the landing pad 110. In some embodiments, the first nitride layer 120 covers at least the top surface and several side surfaces of the landing pad 110. The first oxide layer 130 is disposed on the first nitride layer 120. The second nitride layer 140 is disposed on the first oxide layer 130. The second oxide layer 150 is disposed on the second nitride layer 140. The third nitride layer 160 is disposed on the second oxide layer 150. As Figure 2 shown, the third nitride layer 160 has a top surface 160a.

[0041] In some embodiments, the landing pad 110 may be a conductive material. In some embodiments, the landing pad 110 may be a metal material. In some embodiments, the landing pad 110 may include a material such as tungsten (W) or other similar materials. However, any suitable material may be used.

[0042] In some embodiments, the landing pad 110 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma-enhanced atomic layer deposition), ECP (electrochemical plating), electroless plating, or other similar methods. The present disclosure is not intended to be limited to the method of forming the landing pad 110.

[0043] In some embodiments, the first nitride layer 120 can be a nitride material. In some embodiments, the first nitride layer 120 can comprise, for example, silicon nitride (Si x N y ) or other similar materials. However, any suitable material can be used.

[0044] In some embodiments, the first nitride layer 120 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma-enhanced atomic layer deposition), ECP (electrochemical plating), electroless plating, or other similar methods. The present disclosure is not intended to be limited to the method of forming the first nitride layer 120.

[0045] In some embodiments, the first oxide layer 130 can be an oxide material. In some embodiments, the first oxide layer 130 can comprise, for example, borophosphosilicate glass (BPSG) or other similar materials. However, any suitable material can be used.

[0046] In some embodiments, the first oxide layer 130 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma-enhanced atomic layer deposition), ECP (electrochemical plating), electroless plating, or other similar methods. The present disclosure is not intended to be limited to the method of forming the first oxide layer 130.

[0047] In some embodiments, the second nitride layer 140 can be a nitride material. In some embodiments, the second nitride layer 140 can comprise, for example, silicon nitride (Si x N y ) or other similar materials. However, any suitable material can be used.

[0048] In some embodiments, the second nitride layer 140 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), electroless plating, or other similar methods. The present disclosure is not intended to be limited to the method of forming the second nitride layer 140.

[0049] In some embodiments, the second oxide layer 150 can be an oxide material. In some embodiments, the second oxide layer 150 can include tetraethyl orthosilicate (TEOS) or other similar materials. However, any suitable materials can be used.

[0050] In some embodiments, the second oxide layer 150 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), electroless plating, or other similar methods. The present disclosure is not intended to be limited to the method of forming the second oxide layer 150.

[0051] In some embodiments, the third nitride layer 160 can be a nitride material. In some embodiments, the third nitride layer 160 can include, like silicon nitride (Si x N y ) or other similar materials. However, any suitable materials can be used.

[0052] In some embodiments, the third nitride layer 160 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), electroless plating, or other similar methods. The present disclosure is not intended to be limited to the method of forming the third nitride layer 160.

[0053] In step S102, a trench T is formed.

[0054] Please continue to refer to Figure 1 and Figure 2 . As Figure 2As shown, in the present embodiment, the trench T is formed from the top surface 160a of the third nitride layer 160. In some embodiments, forming the trench T exposes the first nitride layer 120. In some embodiments, the trench T penetrates through the third nitride layer 160, the second oxide layer 150, the second nitride layer 140, and the first oxide layer 130. In some embodiments, performing step S102 positions the trench T above the landing pad 110. As Figure 2 shown, the first nitride layer 120 has a top surface 120a. In some embodiments, forming the trench T exposes the top surface 120a of the first nitride layer 120. In some embodiments, performing step S102 positions the bottom of the trench T flush with the top surface 120a of the first nitride layer 120.

[0055] In some embodiments, the trench T can be formed by any suitable method, for example, dry etching or other similar methods. The present disclosure is not intended to be limited to the method of forming the trench T.

[0056] In step S103, a protective liner layer 170 is formed.

[0057] Please refer to Figure 1 and Figure 3 . Figure 3 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor element 100 according to an embodiment of the present disclosure. As Figure 3 shown, in the present embodiment, the trench T has an inner sidewall Ta. The protective liner layer 170 is disposed on the third nitride layer 160. In some embodiments, the protective liner layer 170 lines the trench T. In some embodiments, the protective liner layer 170 is deposited on the inner sidewall Ta of the trench T and the top surface 160a of the third nitride layer 160. In some embodiments, forming the protective liner layer 170 causes the protective liner layer 170 to contact the top surface 120a of the first nitride layer 120. In some embodiments, the protective liner layer 170 is deposited on the top surface 120a of the first nitride layer 120.

[0058] In some embodiments, the protective liner layer 170 has a thickness T 170 . In some embodiments, the thickness T of the protective liner layer 170 170 is equal to or greater than about 2 nanometers (nm), but the present disclosure is not limited thereto. In some embodiments where the thickness T of the protective liner layer 170 170 is less than about 2 nanometers, the trench T may not be able to resist the etching process in subsequent steps, resulting in deterioration of the quality of the trench T.

[0059] In some embodiments, the protective liner layer 170 comprises an oxide. In some embodiments, the protective liner layer 170 can comprise, for example, silicon oxide (SiO2 ) or other similar materials. However, any suitable materials can be used.

[0060] In some embodiments, the protective liner layer 170 can be formed by any suitable method, such as CVD (Chemical Vapor Deposition), PECVD (Plasma-Enhanced Chemical Vapor Deposition), PVD (Physical Vapor Deposition), ALD (Atomic Layer Deposition), PEALD (Plasma-Enhanced Atomic Layer Deposition), ECP (Electrochemical Plating), electroless plating or other similar methods. The present disclosure is not intended to limit the method for forming the protective liner layer 170. In some embodiments, the protective liner layer 170 is preferably formed by an ALD process.

[0061] In some embodiments, the protective liner layer 170 is formed by a blanket deposition process. The present disclosure is not intended to limit the method for forming the protective liner layer 170.

[0062] In step S104, the first nitride layer 120 is punched through to expose the landing pad 110.

[0063] Please refer to Figure 1 and Figure 4 . Figure 4 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. As Figure 4 shown, in this embodiment, punching through the first nitride layer 120 causes the landing pad 110 to be exposed. As Figure 4 shown, the landing pad 110 has a top surface 110a. In some embodiments, the first nitride layer 120 is etched through the trench T to expose the top surface 110a of the landing pad 110. In some embodiments, performing step S104 causes the portion of the protective liner layer 170 located on the top surface 120a of the first nitride layer 120 to be removed. In some embodiments, punching through the first nitride layer 120 causes the trench T to communicate with the landing pad 110.

[0064] Please refer to Figure 4 , in some embodiments, performing step S104 causes the width of the first nitride layer 120 to taper downward from the top surface 120a of the first nitride layer 120 to the top surface 110a of the landing pad 110.

[0065] In some embodiments, the first nitride layer 120 can be punched through by any suitable method, such as, dry etching or other similar methods. The present disclosure is not intended to limit the method for punching through the first nitride layer 120.

[0066] In some embodiments, the first nitride layer 120 can be punctured by any suitable method, for example, isotropic etching or other similar methods. The present disclosure is not intended to limit the method of puncturing the first nitride layer 120.

[0067] In some embodiments, the first nitride layer 120 can be punctured by using any suitable etchant, for example, ammonia (NH 3 )), hydrogen fluoride (HF) or other similar etchants. The present disclosure is not intended to limit the method of puncturing the first nitride layer 120.

[0068] In step S105, the first nitride layer 120 is isotropically etched to increase the overall width of the extension portion T120.

[0069] Please refer to Figure 1 and Figure 5 . Figure 5 is a cross-sectional view of an intermediate stage of manufacturing the semiconductor element 100 according to an embodiment of the present disclosure. In this embodiment, after the first nitride layer 120 is punctured and the landing pad 110 is exposed, the first nitride layer 120 is isotropically etched. More specifically, after performing step S104, the first nitride layer 120 is further consumed. As Figure 5 shown, in some embodiments, isotropically etching the first nitride layer 120 causes the formation of the extension portion T120 of the trench T. More specifically, the extension portion T120 extends from the trench T and penetrates through the first nitride layer 120. In some embodiments, the extension portion T120 of the trench T is connected between the landing pad 110 and the top surface 120a of the first nitride layer 120. As Figure 5 shown, in step S105, the overall width of the extension portion T120 is increased relative to Figure 4 increase.

[0070] In some embodiments, the first nitride layer 120 can be isotropically etched by using any suitable etching gas, for example, ammonia (NH 3 )), hydrogen fluoride (HF) or other similar etching gases. The present disclosure is not intended to limit the method of etching the first nitride layer 120.

[0071] In some embodiments, the width of the top of the extension portion T120 of the trench T is greater than the width of the bottom of the extension portion T120 of the trench T. In some embodiments, the width of the extension portion T120 of the trench T tapers downward from the top surface 120a of the first nitride layer 120 to the top surface 110a of the landing pad 110.

[0072] In some embodiments, the extension portion T120 has a height H 120。In some embodiments, the height H 120 is defined as the distance from the top surface 120a of the first nitride layer 120 to the top surface 110a of the landing pad 110. In some embodiments, the height H 120 is in the range between about 20 nanometers (nm) and about 25 nanometers (nm). In some embodiments where the distance from the top surface 120a to the top surface 110a is greater than about 25 nanometers, the top surface 110a may not be exposed. In some embodiments where the distance from the top surface 120a to the top surface 110a is less than about 20 nanometers, the first nitride layer 120 may be over-etched, resulting in a leakage problem in the capacitor formed in a subsequent process due to the presence of a seam in the portion of the first nitride layer 120 surrounding the landing pad 110.

[0073] In step S106, the protective liner layer 170 is removed.

[0074] Please refer to Figure 1 and Figure 6 。 Figure 6 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor element 100 according to an embodiment of the present disclosure. As Figure 6 shown, in this embodiment, the protective liner layer 170 is removed from the inner sidewall Ta of the trench T and the top surface 160a of the third nitride layer 160. In some embodiments, the protective liner layer 170 is sacrificial, and the protective liner layer 170 is completely removed.

[0075] In some embodiments, the protective liner layer 170 can be removed by any suitable method, for example, wet etching or other similar methods. In some embodiments, the protective liner layer 170 can be removed by using, for example, hydrofluoric acid (HF) or other similar materials. The present disclosure is not intended to limit the method for removing the protective liner layer 170.

[0076] In some embodiments, the protective liner layer 170 can be removed by any suitable method, for example, isotropic etching or other similar methods. The present disclosure is not intended to limit the method for removing the protective liner layer 170.

[0077] As Figure 6 shown, in some embodiments, the extension portion T120 of the trench T has a width W at the top of the extension portion T120 of the trench T T120U and a width W at the bottom of the extension portion T120 of the trench T T120L 。More specifically, the width W T120U is defined as the width by which the extension portion T120 extends on the top surface 120a, and the width W T120LIs defined as the width by which the extension part T120 extends on the top surface 110a. The trench T has a width W at the top of the trench T T . More specifically, the width W T Is defined as the width by which the trench T extends on the top surface 160a. In some embodiments, the width W at the top of the extension part T120 of the trench T T120U Is greater than the width W at the bottom of the extension part T120 of the trench T T120L . In some embodiments, the width W at the top of the extension part T120 of the trench T T120U Is greater than the width W at the top of the trench T T .

[0078] In step S107, the electrode layer 180 is formed.

[0079] Please refer to Figure 1 And Figure 7 . Figure 7 Is a cross-sectional view of an intermediate stage of manufacturing the semiconductor element 100 according to an embodiment of the present disclosure. As Figure 7 Shown, in this embodiment, the electrode layer 180 is disposed on the third nitride layer 160. In some embodiments, the electrode layer 180 wraps the trench T and the extension part T120 of the trench T. In some embodiments, the electrode layer 180 is deposited on the inner sidewall Ta of the trench T, the top surface 160a of the third nitride layer 160, and the extension part T120. In some embodiments, forming the electrode layer 180 causes the electrode layer 180 to contact the top surface 110a of the landing pad 110. In some embodiments, the electrode layer 180 is deposited on the top surface 110a of the landing pad 110.

[0080] In some embodiments, the electrode layer 180 is configured as the lower electrode of a capacitor.

[0081] In some embodiments, the electrode layer 180 includes a conductive material. In some embodiments, the electrode layer 180 includes a nitride. In some embodiments, the electrode layer 180 may include materials such as titanium nitride (TiN) or other similar materials. However, any suitable material can be used.

[0082] In some embodiments, the electrode layer 180 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), electroless plating, or other similar methods. The present disclosure is not intended to limit the method for forming the electrode layer 180. In some embodiments, the electrode layer 180 is preferably formed by a CVD process.

[0083] In some embodiments, the electrode layer 180 is formed by a blanket deposition process. The present disclosure is not intended to be limited to the method of forming the electrode layer 180.

[0084] In some embodiments, method M also includes a step of modifying trench T that is performed after step S106 and before step S107. More specifically, trench T can be pulled back, causing the profile of trench T to become straighter. Thus, in some embodiments, the width W at the top of the extension portion T120 of trench T T120U is equal to the width W at the top of trench T T .

[0085] By performing method M shown in the present disclosure Figure 1 a semiconductor element 100 with better electrical performance can be formed.

[0086] From the above detailed description of the specific embodiments of the present disclosure, it can be clearly seen that in the semiconductor element and its manufacturing method of the present disclosure, since the protective liner layer lines the inner sidewalls of the trenches, the critical dimensions of the trenches will not be enlarged after performing the step of punching through the first nitride layer. In the semiconductor element and its manufacturing method of the present disclosure, since only the portion of the protective liner layer located on the top surface of the first nitride layer is removed, only the width at the bottom of the trench increases when performing the step of anisotropically etching the first nitride layer. In the semiconductor element and its manufacturing method of the present disclosure, since the trench has an extension portion when performing the step of anisotropically etching the first nitride layer, the contact area between the electrode layer and the landing pad can be increased, thereby reducing the resistance between the electrode layer and the landing pad. Overall, the manufacturing method of the semiconductor element of the present disclosure improves the electrical performance of the entire semiconductor element.

[0087] Although the present disclosure has been described in considerable detail with reference to certain of its embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0088] The above content outlines the features of several embodiments, enabling those skilled in the art to better understand the aspects of this case. Those skilled in the art should understand that, without departing from the spirit and scope of this case, the above content can be easily used as a basis for designing or modifying into other variations in order to implement the same purpose and / or achieve the same advantages of the embodiments introduced herein. The above content should be understood as an example of the present disclosure, and its scope of protection should be subject to the claims.

[0089]

Symbol Description

[0090] 100: Semiconductor element

[0091] 110: Landing pad

[0092] 110a, 120a, 160a: Top surface

[0093] 120: First nitride layer

[0094] 130: First oxide layer

[0095] 140: Second nitride layer

[0096] 150: Second oxide layer

[0097] 160: Third nitride layer

[0098] 170: Protective liner layer

[0099] 180: Electrode layer

[0100] H 120 : Height

[0101] M: Method

[0102] S101, S102, S103, S104, S105, S106, S107: Steps

[0103] T: Trench

[0104] T120: Extension

[0105] T 170 : Thickness

[0106] Ta: Inner sidewall

[0107] W T , W T120L , W T120U : Width

Claims

1. A semiconductor element, characterized in that: Include: Landing pad; a first nitride layer disposed above the landing pad; A first oxide layer, disposed on the first nitride layer; A second nitride layer is disposed on the first oxide layer; A second oxide layer is disposed on the second nitride layer; a third nitride layer, disposed on the second oxide layer, and a trench penetrating the third nitride layer, the second oxide layer, the second nitride layer, the first oxide layer, and the first nitride layer, wherein the trench further has an extension portion penetrating the first nitride layer, and a width of a top of the extension portion of the trench is greater than or equal to a width of a top of the trench; as well as The electrode layer is disposed on the inner sidewall of the groove and on the top surface of the third nitride layer.

2. The semiconductor device according to claim 1, characterized in that The electrode layer contacts the landing pad.

3. The semiconductor device according to claim 1, wherein: The extended portion of the groove is located above the landing pad.

4. The semiconductor device according to claim 1, wherein: The width of the extended portion of the trench tapers downward from a top surface of the first nitride layer to a top surface of the landing pad.

5. The semiconductor device according to claim 1, wherein: The width of the top of the extended portion of the groove is greater than the width of the bottom of the extended portion of the groove.

6. The semiconductor device according to claim 1, characterized in that The width of the top of the extended portion of the groove is greater than the width of the top of the groove.

7. The semiconductor device according to claim 1, wherein: A height from a top surface of the first nitride layer to a top surface of the landing pad is in a range from 20 nanometers to 25 nanometers.

8. The semiconductor device according to claim 1, wherein: The first oxide layer includes borophosphosilicate glass.

9. The semiconductor device according to claim 1, wherein: The second oxide layer includes tetraethyl orthosilicate.

10. A method for manufacturing a semiconductor element, characterized in that: Include: sequentially forming a landing pad, a first nitride layer, a first oxide layer, a second nitride layer, a second oxide layer, and a third nitride layer; forming a groove penetrating the third nitride layer, the second oxide layer, the second nitride layer, and the first oxide layer; Depositing a protective liner layer on the inner sidewalls of the trench and on the top surface of the third nitride layer; punching through the first nitride layer and exposing the landing pad; isotropically etching the first nitride layer to form an extension and increase an overall width of the extension; removing the protective liner; as well as An electrode layer is deposited on the inner sidewall of the trench and on the top surface of the third nitride layer.

11. The method according to claim 10, characterized in that The step of forming the trench is performed such that the first nitride layer is exposed.

12. The method according to claim 10, characterized in that The depositing the protective liner layer is performed such that the protective liner layer contacts a top surface of the first nitride layer.

13. The method according to claim 12, characterized in that Performing the step of punching through the first nitride layer and exposing the landing pad results in the removal of a portion of the protective liner layer located on the top surface of the first nitride layer.

14. The method according to claim 10, characterized in that The step of isotropically etching the first nitride layer is performed after the step of punching through the first nitride layer and exposing the landing pad.

15. The method according to claim 10, characterized in that Performing the step of isotropically etching the first nitride layer results in forming an extension portion of the trench, and wherein the extension portion of the trench penetrates the first nitride layer.

16. The method according to claim 15, characterized in that Performing the step of isotropically etching the first nitride layer causes the extension portion of the trench to connect between the landing pad and a top surface of the first nitride layer.

17. The method according to claim 15, characterized in that Performing the step of isotropically etching the first nitride layer causes a width of a top portion of the extension portion of the trench to be greater than a width of a bottom portion of the extension portion of the trench.

18. The method according to claim 17, characterized in that Performing the step of isotropically etching the first nitride layer causes the width of the top of the extension portion of the trench to be greater than or equal to the width of the top of the trench.

19. The method according to claim 10, characterized in that The step of depositing the electrode layer is performed such that the electrode layer contacts the landing pad.

20. The method according to claim 10, characterized in that The thickness of the protective lining layer is greater than or equal to 2 nanometers.

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