Method of manufacturing semiconductor memory device

Abstract

A method of manufacturing a semiconductor memory device includes forming a channel structure including a channel pattern on a substrate; forming a silicide material layer including an alloy of a semiconductor material and a metal on the channel structure, the metal including a eutectic component; forming a sacrificial semiconductor layer between the channel structure and the silicide material layer, and forming a mold layer surrounding the sacrificial semiconductor layer; forming a capacitor hole by removing the sacrificial semiconductor layer; forming a lower electrode filling the capacitor hole; removing the mold layer; forming a capacitor dielectric layer covering the surface of the lower electrode; and forming an upper electrode covering the capacitor dielectric layer.

Description

Technical Field

[0001] One or more example embodiments of the present disclosure relate to a method of manufacturing a semiconductor memory device. More specifically, one or more example embodiments of the present disclosure relate to a method of manufacturing a semiconductor memory device including a capacitor structure. Background Art

[0002] According to the rapid development of the electronics industry and the needs of users, electronic devices are becoming more compact and lightweight. Therefore, semiconductor memory devices need to have a high degree of integration for use in electronic devices. Thus, the design rules of the components of semiconductor memory devices are being reduced. As a result, it is difficult to ensure the reliability of semiconductor memory devices. Summary of the Invention

[0003] One or more example embodiments of the present disclosure provide a method of manufacturing a semiconductor memory device, which can improve the reliability of the semiconductor memory device by ensuring the capacitance of the capacitor structure.

[0004] According to an aspect of an example embodiment of the present disclosure, there is provided a method of manufacturing a semiconductor memory device, the method including: forming a channel structure including a channel pattern on a substrate; forming a silicide material layer including an alloy of a semiconductor material and a metal including a eutectic composition on the channel structure; forming a sacrificial semiconductor layer between the channel structure and the silicide material layer, and forming a mold layer surrounding the sacrificial semiconductor layer; forming a capacitor hole by removing the sacrificial semiconductor layer; forming a lower electrode filling the capacitor hole; removing the mold layer; forming a capacitor dielectric layer covering a surface of the lower electrode; and forming an upper electrode covering the capacitor dielectric layer.

[0005] According to an aspect of an exemplary embodiment of the present disclosure, a method of manufacturing a semiconductor memory device is provided. The method includes: forming a plurality of word lines, a plurality of channel structures, and a plurality of bit lines on a substrate, wherein the plurality of word lines extend in a first horizontal direction, wherein the plurality of channel structures are adjacent to the plurality of word lines and arranged in rows in the first horizontal direction, each of the plurality of channel structures including a channel pattern extending in a vertical direction, and wherein the plurality of bit lines extend in a second horizontal direction different from the first horizontal direction and are electrically connected to a first end of the plurality of channel patterns; forming a plurality of silicide material layers respectively on the plurality of channel structures, each of the plurality of silicide material layers including an alloy of a semiconductor material and a metal, the metal including a eutectic composition; performing metal-induced crystallization to transform the plurality of silicide material layers into a plurality of induced silicide material layers having a circular planar shape; forming a plurality of sacrificial semiconductor layers between an upper surface of the plurality of induced silicide material layers and the plurality of channel structures, and forming a mold layer surrounding the plurality of sacrificial semiconductor layers; forming a plurality of capacitor holes by removing the plurality of sacrificial semiconductor layers; forming a plurality of lower electrodes respectively filling the plurality of capacitor holes and respectively electrically connected to a second end of the plurality of channel patterns; removing the mold layer; forming a capacitor dielectric layer covering a surface of the plurality of lower electrodes; and forming an upper electrode covering the capacitor dielectric layer.

[0006] According to another aspect of the inventive concept, a method of manufacturing a semiconductor memory device is provided, the method including: forming a plurality of word lines, a plurality of back gate lines, a plurality of channel patterns, and a plurality of bit lines on a substrate, wherein the plurality of word lines extend in a first horizontal direction, wherein the plurality of back gate lines extend in the first horizontal direction and are spaced apart from the plurality of word lines in a second horizontal direction different from the first horizontal direction, wherein the plurality of channel patterns are disposed between one of the plurality of word lines and one of the plurality of back gate lines adjacent to the one word line, the plurality of channel patterns extending in a vertical direction, and wherein the plurality of bit lines extend under the plurality of channel patterns in a second horizontal direction different from the first horizontal direction and are electrically connected to a first end of the plurality of channel patterns; forming a plurality of connection structures by injecting impurities into an upper portion of the plurality of channel patterns; forming a plurality of silicide material layers on the plurality of connection structures, each of the plurality of silicide material layers including an alloy of a semiconductor material and a metal including a eutectic composition; forming a plurality of sacrificial semiconductor layers, a mold layer, and a plurality of support patterns on the plurality of connection structures; forming a plurality of capacitor holes by removing the plurality of sacrificial semiconductor layers; forming a plurality of lower electrodes respectively filling the plurality of capacitor holes and respectively electrically connected to a second end of the plurality of channel patterns; removing the mold layer; forming a capacitor dielectric layer covering surfaces of the plurality of lower electrodes and surfaces of the plurality of support patterns; and forming an upper electrode covering the capacitor dielectric layer, wherein each of the plurality of sacrificial semiconductor layers includes a plurality of sub-sacrificial semiconductor layers having a cylindrical shape, the mold layer includes a plurality of sub-mold layers, and wherein forming the plurality of sacrificial semiconductor layers, the mold layer, and the plurality of support patterns includes: heating the plurality of silicide material layers and transforming the plurality of silicide material layers into a plurality of induced silicide material layers having a circular planar shape; a first operation of forming one of the plurality of sub-sacrificial semiconductor layers between an upper surface of the plurality of induced silicide material layers and an upper surface of the plurality of connection structures by injecting a semiconductor material precursor and performing metal-induced crystallization; a second operation of forming one of the plurality of sub-mold layers surrounding a part of a side surface of the one sub-sacrificial semiconductor layer; a third operation of forming one of the plurality of support patterns covering a side surface of an upper portion of the one sub-sacrificial semiconductor layer; and repeating the first operation, the second operation, and the third operation at least three times. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a plan layout showing a semiconductor memory device according to one or more example embodiments;

[0009] Figures 2A to 2D is a cross-sectional view showing a semiconductor memory device according to one or more example embodiments;

[0010] Figures 3A to 18 is a perspective view and a cross-sectional view showing a method of manufacturing a semiconductor memory device according to one or more example embodiments, Figure 19 is a cross-sectional view showing a semiconductor memory device according to one or more example embodiments;

[0011] Figures 20 to 25 is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to one or more example embodiments;

[0012] Figures 26A to 26E is a conceptual diagram showing a method of forming a sacrificial structure used in a method of manufacturing a semiconductor memory device according to one or more example embodiments;

[0013] Figures 27 to 30 is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to one or more example embodiments, Figure 31 is a cross-sectional view showing a semiconductor memory device according to one or more example embodiments;

[0014] Figures 32A to 35B is a perspective view and a cross-sectional view showing a method of manufacturing a semiconductor memory device according to one or more example embodiments, Figure 36 is a cross-sectional view showing a semiconductor memory device according to one or more example embodiments;

[0015] Figures 37 to 44 is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to one or more example embodiments, Figure 45 is a cross-sectional view showing a semiconductor memory device according to one or more example embodiments; and

[0016] Figure 46 is a planar layout of a semiconductor memory device according to one or more example embodiments. Detailed Description

[0017] Figure 1 is a planar layout of a semiconductor memory device 1 according to one or more example embodiments. Figure 1 may be a plan view when viewed from a vertical direction (e.g., the Z direction).

[0018] Reference Figure 1, the semiconductor memory device 1 may include a plurality of word lines WL extending in a first horizontal direction (e.g., the X direction), a plurality of bit lines BL extending in a second horizontal direction (e.g., the Y direction) different from the first horizontal direction (X direction), a plurality of back gate lines BG extending in the first horizontal direction (X direction), and a plurality of channel patterns CH extending in a vertical direction (Z direction). The first horizontal direction (X direction) and the second horizontal direction (Y direction) may be perpendicular to each other. In some embodiments, the semiconductor memory device 1 may include a dynamic random access memory (DRAM).

[0019] The plurality of word lines WL and the plurality of back gate lines BG may be spaced apart from each other in the second horizontal direction (Y direction) and extend parallel to each other in the first horizontal direction (X direction). Each of the plurality of back gate lines BG may be located between a pair of adjacent word lines WL among the plurality of word lines WL. The number of word lines WL may be approximately twice the number of back gate lines BG. For example, the plurality of word lines WL and the plurality of back gate lines BG may be arranged such that two word lines WL among the plurality of word lines WL and one back gate line BG among the plurality of back gate lines BG are alternately arranged in the second horizontal direction (Y direction).

[0020] The plurality of channel patterns CH may be arranged in rows in the first horizontal direction (X direction) between an adjacent word line WL and a back gate line BG among the plurality of word lines WL and the plurality of back gate lines BG. The plurality of channel patterns CH may be arranged in rows in the second horizontal direction (Y direction). For example, each of the plurality of channel patterns CH arranged in rows in the second horizontal direction (Y direction) may be located between an adjacent word line WL and a back gate line BG in the second horizontal direction (Y). For example, a pair of channel patterns CH spaced apart from each other in the second horizontal direction (Y direction) with one back gate line BG therebetween may have shapes symmetric with respect to the one back gate line BG.

[0021] Each of the plurality of channel patterns CH may include a first sidewall facing the back gate line BG and a second sidewall facing the word line WL and connected to an edge of the first sidewall. The first sidewall may be flat, and the second sidewall may be curved. That is, in a plan view, the first sidewall may have a straight shape, and the second sidewall may have a curved shape. For example, in a plan view, each of the plurality of channel patterns CH may have a quasi-rectangular shape in which two corners facing the word line WL are rounded, or may have a shape in which the second sidewall has an arc or elliptical arc shape.

[0022] The gate insulating layer Gox may be located between the channel pattern CH and the word line WL, and the back gate insulating layer BGox may be located between the channel pattern CH and the back gate line BG. In some embodiments, in a plan view, the gate insulating layer Gox may surround at least a portion of the channel pattern CH. In some embodiments, the back gate insulating layer BGox may extend in the first horizontal direction (X direction) on both sides in the second horizontal direction (Y direction) along the back gate line BG. The first sidewall of the channel pattern CH may be covered by the back gate insulating layer BGox, and the second sidewall of the channel pattern CH may be covered by the gate insulating layer Gox. Figure 1 It is shown that the gate insulating layer Gox only covers the second sidewall of the channel pattern CH, but the embodiments are not limited thereto. For example, the gate insulating layer Gox may be located between the first sidewall of the channel pattern CH and the back gate insulating layer BGox, and thus completely surround the channel pattern CH in a plan view.

[0023] The plurality of bit lines BL may be spaced apart from each other in the first horizontal direction (X direction) and extend parallel to each other in the second horizontal direction (Y direction). The plurality of bit lines BL may extend in the second horizontal direction (Y direction) and be electrically connected to the plurality of channel patterns CH. For example, the plurality of bit lines BL may be electrically connected to the first ends of the two ends in the vertical direction (Z direction) of each of the plurality of channel patterns CH. One bit line BL may be electrically connected to the channel patterns CH arranged in a row in the second horizontal direction (Y direction). The covering insulating layer BLO may cover the plurality of bit lines BL. The covering insulating layer BLO may conformally cover the plurality of bit lines BL, but does not completely fill the space of the plurality of bit lines BL. The shielding conductive layer SL may cover the plurality of bit lines BL and have the covering insulating layer BLO therebetween. The space between the plurality of bit lines BL that is not completely filled by the covering insulating layer BLO may be filled with the shielding conductive layer SL.

[0024] Figure 1 It is shown that a plurality of covering insulating layers BLO are arranged on both sides of each of the plurality of bit lines BL, and a plurality of shielding conductive layers SL are arranged between two covering insulating layers BLO that respectively cover the facing sidewalls of two adjacent bit lines BL. However, Figure 1 it is only a conceptual diagram of the plan view of the semiconductor memory device 1, and the embodiments are not limited thereto. For example, in Figure 1 each of the shielding conductive layer SL and the covering insulating layer BLO shown as a plurality of sections may be connected to each other under the plurality of bit lines BL to form an integral body.

[0025] The portion of the shielding conductive layer SL located between two adjacent bit lines BL may have the shape of a line extending in the second horizontal direction (Y direction). Between two adjacent bit lines BL, the portion of the covering insulating layer BLO located between the bit line BL and the shielding conductive layer SL may have the shape of a line extending in the second horizontal direction (Y direction). For example, a pair of portions of the covering insulating layer BLO that are spaced apart from each other in the first horizontal direction (X direction) and have the shape of a line extending in the second horizontal direction (Y direction) may be arranged between the two adjacent bit lines BL.

[0026] The bit line BL, the word line WL, the channel pattern CH (which is adjacent to the portion of the word line WL intersecting the bit line BL in a plan view), and the gate insulating layer Gox between the word line WL and the channel pattern CH may constitute a vertical channel transistor. A capacitor structure 300 (see Figure 2A and Figure 2D ) may be provided on the vertical channel transistor, and the vertical channel transistor and the capacitor structure 300 may form a memory cell. The lower electrode 310 of the capacitor structure 300 (see Figure 2A and Figure 2D ) may be electrically connected to the channel pattern CH.

[0027] Figures 2A to 2D is a cross-sectional view showing a semiconductor memory device 1 according to one or more example embodiments. Specifically, Figure 2A is a cross-sectional view of the semiconductor memory device 1 taken along line A-A' of Figure 1 , Figure 2B is a cross-sectional view of the semiconductor memory device 1 taken along line B-B' of Figure 1 , Figure 2C is a cross-sectional view of the semiconductor memory device 1 taken along line C-C' of Figure 1 , Figure 2D is a cross-sectional view of the semiconductor memory device 1 taken along line D-D' of Figure 1 .

[0028] Refer together to Figures 2A to 2D, the semiconductor memory device 1 includes a plurality of bit line structures 140 on a peripheral circuit structure PS, a plurality of back gate structures BGS on the plurality of bit line structures 140, a transistor structure including a plurality of word line structures 130 and a plurality of channel patterns 106P, a plurality of capacitor structures 300 on the transistor structure, and a plurality of connection structures 180 that electrically connect the plurality of channel patterns 106P to the plurality of capacitor structures 300. The plurality of capacitor structures 300 may be formed by sequentially stacking a plurality of lower electrodes 310, a capacitor dielectric layer 320, and an upper electrode 330. The plurality of channel patterns 106P may be electrically connected to the plurality of lower electrodes 310 via the plurality of connection structures 180. The plurality of word line structures 130 and the plurality of channel patterns 106P of the transistor structure constitute a plurality of transistors. Each of the plurality of transistors may include a vertical channel transistor (VCT).

[0029] Each of the plurality of back gate structures BGS may include a back gate insulating layer 114, a back gate line 116, and a back gate covering layer 118. The back gate insulating layer 114 may be located between the back gate line 116 and the channel pattern 106P. The back gate covering layer 118 may cover the bottom surface of the back gate line 116. In some embodiments, in a plane (Y-Z plane) formed by a second horizontal direction (Y direction) and a vertical direction (Z direction), the back gate insulating layer 114 may have an inverted U shape and cover the side surface of the back gate covering layer 118, the side surface of the back gate line 116, and the upper surface of the back gate line 16. Each of the plurality of word line structures 130 may include a gate insulating layer 132, a word line 134, and a gate covering layer 138. The gate insulating layer 132 may be located between the word line 134 and the channel pattern 106P. The gate covering layer 138 may cover the bottom surface of the word line 134. The back gate insulating layer 114, the back gate line 116, the gate insulating layer 132, and the word line 134 may respectively include Figure 1 the back gate insulating layer BGox, the back gate line BG, the gate insulating layer Gox, and the word line WL as shown. The plurality of back gate structures BGS and the plurality of word line structures 130 may be spaced apart from each other in a second horizontal direction (Y direction) and extend parallel to each other in a first horizontal direction (X direction).

[0030] The back gate insulating layer 114 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, oxide / nitride / oxide (ONO), and a high-k dielectric having a higher dielectric constant than silicon oxide. For example, the back gate insulating layer 114 may have a dielectric constant of about 10 to about 25. The back gate line 116 may include a semiconductor material, a metal material, a conductive metal nitride, or a combination thereof. In some embodiments, the back gate line 116 may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x or a combination thereof. The back gate capping layer 118 may include silicon oxide.

[0031] The gate insulating layer 132 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, ONO, and a high-k dielectric having a higher dielectric constant than silicon oxide. For example, the gate insulating layer 132 may have a dielectric constant of about 10 to about 25. The word line 134 may include a semiconductor material, a metal material, a conductive metal nitride, or a combination thereof. In some embodiments, the word line 134 may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x or a combination thereof. The gate capping layer 138 may include silicon nitride.

[0032] The isolation insulating layer 136 may be located between a pair of word lines 134, where the pair of word lines 134 are between a pair of channel patterns 106P adjacent to each other in the second horizontal direction (Y direction). The isolation insulating layer 136 may include silicon oxide. The buried capping layer 172 may cover a pair of word lines 134 provided between a pair of channel patterns 106P adjacent to each other in the second horizontal direction (Y direction), and cover the isolation insulating layer 136 provided between the pair of word lines 134. For example, the buried capping layer 172 may include silicon nitride. The gate capping layer 138 may cover the bottom surfaces of the word line 134 and the isolation insulating layer 136.

[0033] A plurality of base insulating structures 113 may be disposed on the plurality of back gate structures BGS. The back gate structures BGS and the base insulating structures 113 disposed on the back gate structures BGS may be arranged between a pair of channel patterns 106P adjacent to each other in a second horizontal direction (Y direction). The plurality of base insulating structures 113 may extend parallel to each other in a first horizontal direction (X direction). Each of the plurality of base insulating structures 113 may include a pair of lower insulating layers 111 covering a pair of channel patterns 106P adjacent to each other in the second horizontal direction (Y direction) and an upper insulating layer 112 provided between the pair of lower insulating layers 111. For example, each lower insulating layer 111 may include an oxide, and the upper insulating layer 112 may include a nitride.

[0034] The plurality of back gate lines 116 and the plurality of word lines 134 may be spaced apart from each other in the second horizontal direction (Y direction) and extend parallel to each other in the first horizontal direction (X direction). Each of the plurality of back gate lines 116 may be located between a pair of adjacent word lines 134 among the plurality of word lines 134. For example, two word lines 134 among the plurality of word lines 134 and one back gate line 116 among the plurality of back gate lines 116 may be alternately arranged in the second horizontal direction (Y direction).

[0035] The plurality of channel patterns 106P may be arranged in rows in the first horizontal direction (X direction) between one word line 134 and one back gate line 116 adjacent to each other among the plurality of word lines 134 and the plurality of back gate lines 116. The plurality of channel patterns 106P may be arranged in rows in the second horizontal direction (Y direction). For example, each of the channel patterns 106P arranged in rows in the second horizontal direction (Y direction) may be located between one word line 134 and one back gate line 116 adjacent to each other in the second horizontal direction (Y direction). The channel pattern 106P may include Figure 1 the channel pattern CH shown.

[0036] The channel pattern 106P may include a semiconductor material. For example, the channel pattern 106P may include single-crystalline silicon or polycrystalline silicon. In some embodiments, the channel pattern 106P may include an oxide semiconductor material. The channel pattern 106P may include at least one of a binary oxide semiconductor material containing a first metal element or a ternary oxide semiconductor material, a ternary oxide semiconductor material containing different first and second metal elements from each other, and a quaternary oxide semiconductor material containing different first, second, and third metal elements from each other.

[0037] The binary oxide semiconductor material or the ternary oxide semiconductor material may include, but are not limited to, for example, zinc oxide (ZnO or Zn xO), gallium oxide (GaO or Ga x O), titanium oxide (TiO or Ti x O), tin oxide (SnO or Sn x O), zinc oxynitride (ZnON or Zn x O y N), indium zinc oxide (IZO or In x Zn y O), gallium zinc oxide (GZO or Ga x Zn y O), tin zinc oxide (TZO or Sn x Zn y O) and tin gallium oxide (TGO or Sn x Ga y O). The quaternary oxide semiconductor material may include, but is not limited to, for example, indium gallium zinc oxide (IGZO or In x Ga y Zn z O), indium gallium silicon oxide (IGSO or In x Ga y Si z O), indium tin zinc oxide (ITZO or In x Sn y Zn z O), indium gallium tin oxide (IGTO or In x Ga y Sn z O), zirconium zinc tin oxide (ZZTO or Zr x Zn y Sn z O), hafnium indium zinc oxide (HIZO or Hf x In y Zn z O), gallium zinc tin oxide (GZTO or Ga x Zn y Sn z O), aluminum zinc tin oxide (AZTO or Al x Zn y Sn z O), ytterbium gallium zinc oxide (YGZO or Yb x Ga y Zn z O) and indium aluminum zinc oxide (IAZO).

[0038] In some embodiments, the channel pattern 106P may include a crystalline oxide semiconductor material or an amorphous oxide semiconductor material. When the channel pattern 106P includes a crystalline oxide semiconductor material, the channel pattern 106P may include at least one of single crystal, polycrystal, spinel, and c-axis aligned crystal (CAAC). In some embodiments, the channel pattern 106P may be formed by stacking at least two layers, the at least two layers including a first layer and a second layer, the first layer including a crystalline oxide semiconductor material, and the second layer including an amorphous oxide semiconductor material. For example, the channel pattern 106P may be formed by sequentially stacking a first layer including a crystalline oxide semiconductor material, a second layer including an amorphous oxide semiconductor material, and a third layer including a crystalline oxide semiconductor material.

[0039] Each of the plurality of bit line structures 140 may include a bit line 147 and an insulating cover line 148 for covering the bit line 147 (e.g., the bottom surface of the bit line 147). The plurality of bit line structures 140 may be spaced apart from each other in a first horizontal direction (X direction) and extend parallel to each other in a second horizontal direction (Y direction). A first end of each of the two ends in the vertical direction (Z direction) of each of the plurality of channel patterns 106P may be electrically connected to a corresponding one of the plurality of bit lines 147. The plurality of bit lines 147 and the plurality of insulating cover lines 148 may be spaced apart from each other in the first horizontal direction (X direction) and extend parallel to each other in the second horizontal direction (Y direction). The plurality of bit lines 147 may be electrically connected to the plurality of channel patterns 106P respectively. Each of the plurality of bit lines 147 may include polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the bit line 147 may include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, WSi, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x or a combination thereof. In addition, the bit line 147 may include a two-dimensional semiconductor material. The two-dimensional semiconductor material may include, for example, graphene, carbon nanotubes, or a combination thereof. The bit line 147 may include a single layer or multiple layers containing the above conductive materials.

[0040] The bit line 147 may have a stacked structure of a first line pattern 142, a second line pattern 144, and a third line pattern 146 that are sequentially stacked under the channel pattern 106P. For example, the first line pattern 142 may include a semiconductor material, and each of the second line pattern 144 and the third line pattern 146 may include a metal-based material. The second line pattern 144 and the third line pattern 146 may include different types of metal-based materials. For example, the first line pattern 142 may include doped polysilicon. For example, the second line pattern 144 may include titanium nitride (TiN) or TSN (Ti - Si - N), and the third line pattern 146 may include tungsten (W) or tungsten silicide (WSi x ). In some embodiments, the second line pattern 144 may be used as a diffusion barrier. The first line pattern 142 may be in contact with the lower surface of the channel pattern 106P. The insulating cover line 148 may cover the bottom surface of the bit line 147. The insulating cover line 148 may cover the lower surface of the third line pattern 146. For example, the insulating cover line 148 may include silicon nitride.

[0041] The covering insulating layer 156 may fill a part of each space between the plurality of bit line structures 140. The covering insulating layer 156 may conformally cover the bottom surfaces of the plurality of bit line structures 140, but does not completely fill the space between the plurality of bit line structures 140. The covering insulating layer 156 may cover the bottom surfaces of the plurality of word line structures 130, the bottom surfaces of the plurality of back gate structures BGS, and the bottom surfaces of the plurality of bit line structures 140. The covering insulating layer 156 may include silicon oxide.

[0042] The shielding conductive layer 162 may be disposed opposite to the plurality of channel patterns 106P on the plurality of bit lines 147, that is, under the plurality of bit lines 147. The shielding conductive layer 162 may cover the bottom surface of the covering insulating layer 156 and fill the space between the plurality of bit line structures 140. The covering insulating layer 156 may be located between the plurality of bit lines 147 and the shielding conductive layer 162. The shielding conductive layer 162 may prevent interference between the plurality of bit lines 147. The protective insulating layer 164 may cover the bottom surface of the shielding conductive layer 162. For example, the shielding conductive layer 162 may include a metal material. For example, the protective insulating layer 164 may include silicon nitride. The bit line 147, the covering insulating layer 156, and the shielding conductive layer 162 may respectively include Figure 1 the bit line BL, the covering insulating layer BLO, and the shielding conductive layer SL shown.

[0043] The first bonding insulating layer 170 may cover the bottom surface of the protective insulating layer 164. For example, the first bonding insulating layer 170 may include silicon oxide or silicon carbonitride (SiCN).

[0044] The plurality of connection structures 180 may be disposed on the plurality of channel patterns 106P. The plurality of connection structures 180 may be surrounded by a first surrounding insulating layer 192 and a second surrounding insulating layer 194. Each of the plurality of connection structures 180 may include a conductive material, such as a doped semiconductor material, a metal, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a conductive metal oxynitride, a conductive metal oxide, and a two-dimensional (2D) material, but embodiments are not limited thereto. In some embodiments, the plurality of connection structures 180 may be formed by implanting n-type impurities into the upper portions of the plurality of channel patterns 106P.

[0045] Each of the plurality of connection structures 180 may include a lower connection structure BC and an upper connection structure LP on the lower connection structure BC. In some embodiments, the corresponding lower connection structure BC and upper connection structure LP may be aligned with each other in the vertical direction (Z direction). In some embodiments, the corresponding lower connection structure BC and upper connection structure LP are not aligned with each other in the vertical direction (Z direction), but the upper connection structure LP may be offset from its corresponding lower connection structure BC in the horizontal direction. The lower connection structure BC may have a stacked structure of a first semiconductor layer 182 and a second semiconductor layer 184. The first semiconductor layer 182 may be in contact with the upper surface of the channel pattern 106P. In some embodiments, the first semiconductor layer 182 may include a single-crystal semiconductor material, and the second semiconductor layer 184 may include a polycrystalline semiconductor material. For example, the first semiconductor layer 182 may be epitaxially grown using the channel pattern 106P as a seed crystal. For example, the first semiconductor layer 182 may include single-crystalline silicon, and the second semiconductor layer 184 may include polycrystalline silicon. In some embodiments, the upper connection structure LP may have a stacked structure of a silicide layer 186 and a metal plug 188. For example, the silicide layer 186 may include WSi x , NiSi x , CoSi x or NiPtSi x , and the metal plug 188 may include W, Mo, Au, Cu, Al, Ni, or Co. For example, the first surrounding insulating layer 192 may include silicon oxide, and the second surrounding insulating layer 194 may include silicon nitride. In some embodiments, each of the plurality of connection structures 180 may include the lower connection structure BC, but may not include the upper connection structure LP.

[0046] The plurality of lower electrodes 310 may be electrically connected to the plurality of connection structures 180, respectively. Each of the plurality of channel patterns 106P may be electrically connected to a corresponding one of the plurality of lower electrodes 310 at a second end of two ends in the vertical direction (Z direction). For example, each of the plurality of channel patterns 106P may be electrically connected to a corresponding one of the plurality of lower electrodes 310 at a second end of two ends in the vertical direction (Z direction) via a corresponding one of the plurality of connection structures 180. Each of the plurality of connection structures 180 may include a lower connection structure BC and an upper connection structure LP on the lower connection structure BC. The lower connection structure BC may be oriented toward the channel pattern 106P and electrically connected to the channel pattern 106, and the upper connection structure LP may be oriented toward the lower electrode 310 and electrically connected to the lower electrode 310.

[0047] Each of the plurality of lower electrodes 310 may have a columnar shape, that is, a columnar shape with its interior filled so as to have a circular horizontal cross-section, but the embodiments are not limited thereto. In some embodiments, each of the plurality of lower electrodes 310 may have a cylindrical shape with a closed bottom. In some embodiments, the plurality of lower electrodes 310 may be arranged in a zigzag pattern in the first horizontal direction (X direction) and / or the second horizontal direction (Y direction) to form a honeycomb shape. In some embodiments, the plurality of lower electrodes 310 may be arranged in rows in each of the first horizontal direction (X direction) and the second horizontal direction (Y direction) to form a matrix shape. The plurality of lower electrodes 310 may include, for example, impurity-doped silicon, a metal (such as tungsten or copper), or a conductive metal compound (such as titanium nitride).

[0048] A plurality of support patterns 350 may be in contact with sidewalls of the plurality of lower electrodes 310. The plurality of support patterns 350 may include a first support pattern 350a, a second support pattern 350b, a third support pattern 350c, and a fourth support pattern 350d, which are at different vertical levels and thus spaced apart from each other in the vertical direction (Z direction), but the embodiments are not limited thereto. For example, the plurality of support patterns 350 may include two, three, or five or more support patterns, which are at different vertical levels and spaced apart from each other in the vertical direction (Z direction). The second support pattern 350b may be at a higher vertical level than the first support pattern 350a, the third support pattern 350c may be at a higher vertical level than the second support pattern 350b, and the fourth support pattern 350d may be at a higher vertical level than the third support pattern 350c. In some embodiments, an upper surface of the uppermost support pattern among the plurality of support patterns 350 (e.g., an upper surface of the fourth support pattern 350d) may be at the same vertical level as an uppermost end of the plurality of lower electrodes 310, but the embodiments are not limited thereto. In some embodiments, the uppermost end of the plurality of lower electrodes 310 may protrude upward from the upper surface of the fourth support pattern 350d. For example, the upper surface of the fourth support pattern 350d may be at a lower vertical level than the uppermost end of the plurality of lower electrodes 310. Each of the plurality of support patterns 350 may include any one of a silicon nitride (SiN) film, a silicon carbonitride (SiCN) film, an N-rich silicon nitride (N-rich SiN) film, and a Si-rich silicon nitride (Si-rich SiN) film, but the embodiments are not limited thereto.

[0049] In some embodiments, the lower electrode 310 may extend from the lower surface to the upper surface of the lower electrode 310 with a constant horizontal width. For example, the lower electrode 310 may extend between the lower surface of the lower electrode 310 and the lower surface of the lowermost support pattern 350 (e.g., the first support pattern 350a) among the plurality of support patterns 350 with a first constant horizontal width, and may extend between the upper surface of a support pattern 350 at a lower level and the lower surface of a support pattern 350 at a higher level with a second constant horizontal width, where the support pattern 350 at a lower level and the support pattern 350 at a higher level are two support patterns 350 adjacent to each other in the vertical direction (Z direction) among the plurality of support patterns 350. In some embodiments, the first constant horizontal width may be the same as the second constant horizontal width. In some other embodiments, the first constant horizontal width may be different from the second constant horizontal width. For example, the upper portion of the lower electrode 310 may have a larger horizontal width than the lower portion of the lower electrode 310. In addition, the lower electrode 310 may extend between the lower surface of the lower electrode 310 and the upper surface of the lowermost support pattern 350 (e.g., the first support pattern 350a) among the plurality of support patterns 350 with a third constant horizontal width, and may extend between the upper surfaces of two support patterns 350 adjacent to each other in the vertical direction (Z direction) among the plurality of support patterns 350 with a fourth constant horizontal width. In some embodiments, the third constant horizontal width may be the same as the fourth constant horizontal width. In some other embodiments, the third constant horizontal width may be different from the fourth constant horizontal width. For example, the upper portion of the lower electrode 310 may have a larger horizontal width than the lower portion of the lower electrode 310.

[0050] The capacitor dielectric layer 320 may conformally cover the surfaces of the plurality of lower electrodes 310 and the surfaces of the plurality of support patterns 350. In some embodiments, the capacitor dielectric layer 320 may be integrally formed to cover the plurality of lower electrodes 310 and the plurality of support patterns 350 within a specific region. The capacitor dielectric layer 320 may be, for example, TaO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST ((Ba,Sr)TiO), STO (SrTiO), BTO (BaTiO), PZT ((Pb,Zr,Ti)O), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)O, Sr(Zr,Ti)O, or a combination thereof.

[0051] The upper electrode 330 may fill the space between the plurality of lower electrodes 310 and the plurality of support patterns 350 and cover the capacitor dielectric layer 320. The upper electrode 330 may include, for example, W, Ru, RuO, Pt, PtO, Ir, IrO, SRO (SrRuO), BSRO ((Ba,Sr)RuO), CRO (CaRuO), BaRuO, La(Sr,Co)O, etc. In some embodiments, the upper electrode 330 may include a metallic material. For example, the upper electrode 330 may include W. In some embodiments, in addition to the metallic material, the upper electrode 330 may further include at least one of a doped semiconductor material layer and an interface layer and may have a stacked structure thereof. The doped semiconductor material layer may include, for example, at least one of doped polysilicon and doped polycrystalline silicon germanium (poly SiGe). The interface layer may include, for example, at least one of a metal oxide, a metal nitride, a metal carbide, and a metal silicide.

[0052] The peripheral circuit structure PS may include: a circuit board 202 having an active region AC defined by a circuit device isolation film 204; a circuit gate structure 210 located on the active region AC of the circuit board 202; an inter-wiring insulating layer 220 covering the circuit gate structure 210 on the circuit board 202; and a wiring structure 230 surrounded by the inter-wiring insulating layer 220 and electrically connected to the active region AC and / or the circuit gate structure 210.

[0053] The circuit board 202 may include, for example, a semiconductor material, such as a Group-IV semiconductor material, a Group-III-V semiconductor material, a Group-II-VI semiconductor material, and a Group-II-VI oxide semiconductor material. The Group-IV semiconductor material may include, for example, silicon (Si), germanium (Ge), or silicon germanium (Si-Ge). The Group-III-V semiconductor material may include, for example, gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimonide (InSb), or indium gallium arsenide (InGaAs). The Group-II-VI semiconductor material may include, for example, zinc telluride (ZnTe) or cadmium sulfide (CdS). The circuit board 202 may include a bulk wafer or an epitaxial layer. The circuit board 202 may be provided as a bulk wafer or an epitaxial layer. In some embodiments, the circuit board 202 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0054] The circuit gate structure 210 may include a circuit gate electrode 214 on the active region AC, a circuit gate insulating layer 212 between the active region AC and the circuit gate electrode 214, a circuit gate covering layer 216 covering the circuit gate electrode 214 (e.g., the upper surface of the circuit gate electrode 214), and a circuit gate spacer 218 covering the side surfaces of the circuit gate insulating layer 212, the side surfaces of the circuit gate electrode 214, and the side surfaces of the circuit gate covering layer 216. The active region AC and the circuit gate structure 210 may form a plurality of peripheral circuits.

[0055] The wiring structure 230 may include circuit wiring lines and circuit wiring contacts. The wiring structure 230 may include a conductive material such as copper (Cu), aluminum (Al), tungsten (W), silver (Ag), gold (Au), and / or a combination thereof. The inter-wiring insulating layer 220 may include an insulating material including silicon oxide, silicon nitride, a low-k material, or a combination thereof. The low-k material may have a lower dielectric constant than silicon oxide and includes, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), organosilicate glass (OSG), spin-on glass (SOG), spin-on polymer, or a combination thereof. In some embodiments, the inter-wiring insulating layer 220 may include an ultra-low-k (ULK) film having an ultra-low dielectric constant K of about 2.2 to about 2.4. The ULK film may include SiOC or SiCOH.

[0056] The second bonding insulating layer 270 may cover the inter-wiring insulating layer 220 and the wiring structure 230. The second bonding insulating layer 270 may include silicon oxide or silicon carbonitride (SiCN). The second bonding insulating layer 270 and the first bonding insulating layer 170 may bond to each other when forming a covalent bond.

[0057] Figures 3A to 18 are a perspective view and a cross-sectional view showing a method of manufacturing a semiconductor memory device according to one or more example embodiments, Figure 19 is a cross-sectional view showing a semiconductor memory device according to one or more example embodiments. Specifically, Figure 3A 、 Figure 4A 、 Figure 5A and Figure 6A are perspective views showing a method of manufacturing a semiconductor memory device according to one or more example embodiments, Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 6B and Figures 7 to 18 are cross-sectional views showing a method of manufacturing a semiconductor memory device according to one or more example embodiments.

[0058] Referring to Figure 3A and Figure 3B, a base substrate BSUB, an intermediate layer MLY on the base substrate BSUB, and a channel structure CHS, a word line WL, and a back gate line BG on the intermediate layer MLY can be formed. Each of the word line WL and the back gate line BG can extend in a first horizontal direction (X direction). The channel structure CHS can extend in a vertical direction (Z direction) between the word line WL and the back gate line BG adjacent in a second horizontal direction (Y direction). A gate insulating layer Gox can be located between the channel structure CHS and the word line WL, and a back gate insulating layer BGox can be located between the channel structure CHS and the back gate line BG. In some embodiments, a first upper insulating layer UFGI and a first lower insulating layer LFGI can be disposed above and below the word line WL, respectively. In some embodiments, a second upper insulating layer UBGI and a second lower insulating layer LBGI can be disposed above and below the back gate line BG, respectively.

[0059] The base substrate BSUB can include Figures 2A to 2D the circuit board 202 shown. In addition, the intermediate layer MLY can include Figures 2A to 2D the components disposed between the plurality of channel patterns 106P and the circuit board 202 shown. The channel structure CHS can include Figures 2A to 2D the channel pattern 106P and the connection structure 180 shown. The word line WL can include Figures 2A to 2D the word line 134 shown, and the gate insulating layer Gox can include Figures 2A to 2D the gate insulating layer 132 shown. The first upper insulating layer UFGI can include Figures 2A to 2D the buried covering layer 172 shown, and the first lower insulating layer LFGI can include Figures 2A to 2D the gate covering layer 138 shown. The back gate line BG can include Figures 2A to 2D the back gate line 116 shown, and the back gate insulating layer BGox can include Figures 2A to 2D the back gate insulating layer 114 shown. The second upper insulating layer UBGI can include Figures 2A to 2D the base insulating structure 113 shown, and the second lower insulating layer LBGI can include Figures 2A to 2D the back gate covering layer 118 shown. In some embodiments, each of the first upper insulating layer UFGI and the second upper insulating layer UBGI can further include Figures 2A to 2D the first surrounding insulating layer 192 and the second surrounding insulating layer 194 shown.

[0060] Figure 3A and Figure 3B The components of are shown by simplifying Figures 2A to 2D the components of. Their shapes are not limited to Figure 3A and Figure 3B the shapes shown, and their detailed descriptions are omitted.

[0061] Reference Figure 4A and Figure 4B , a connection structure CTS can be formed on the channel structure CHS. In some embodiments, the connection structure CTS can be formed by implanting impurities into the upper portion of the channel structure CHS. For example, the connection structure CTS can be formed by implanting n-type impurities into the upper portion of the channel structure CHS. In some embodiments, the connection structure CTS can be formed separately on the upper surface of the channel structure CHS. The connection structure CTS can include Figures 2A to 2D the connection structure 180 shown. In some embodiments, the connection structure CTS can include Figures 2A to 2D the lower connection structure BC shown.

[0062] Referring together to Figure 5A and Figure 5B , a silicide material layer SIL can be formed on the connection structure CTS. In some embodiments, the silicide material layer SIL can be formed by forming a metal material layer on the connection structure CTS and then performing a silicidation process on the metal material layer. The metal material layer can include Au, Al, Ag, Ni, Zn, Ti, Pd, W, or a transition metal, and the silicide material layer SIL can include an alloy of a metal material (such as Au, Al, Ag, Ni, Zn, Ti, Pd, W, and transition metals) and a semiconductor material (such as Si, Ge, and SiGe). The silicide material layer SIL can include an alloy of a semiconductor material and a metal, and the alloy can include a eutectic composition. For example, if the silicide material layer SIL includes a silicide of Au and Si (AuSi x ), the silicide material layer SIL can have a composition of 19 atomic % ± 5% of Au and 81 atomic % ± 10% of Si. For example, if the silicide material layer SIL includes a silicide of Al and Si (AlSi x ), the silicide material layer SIL can have a composition of 12 atomic % ± 5% of Al and 88 atomic % ± 10% of Si. For example, if the silicide material layer SIL includes a silicide of Ag and Si (AgSi x ), the silicide material layer SIL can have a composition of 11 atomic % ± 5% of Ag and 89 atomic % ± 10% of Si. After forming the silicide material layer SIL, the remaining metal material layer can be removed.

[0063] Referring together to Figure 6A and Figure 6B , metal-induced crystallization (MIC) can be performed by heating the channel structure CHS and the silicide material layer SIL and injecting a semiconductor material precursor into them. Thus, a first sub-sacrificial semiconductor layer SAC1 can be formed. Figure 5A and Figure 5BThe silicide material layer SIL shown can be transformed into an induced silicide material layer SILE having a circular planar shape and a hemispherical shape due to surface tension. The semiconductor material precursor can include a gas containing Ge or a gas containing Si and Ge. The first sub-sacrificial semiconductor layer SAC1 can be cylindrical with a constant horizontal width based on MIC. The first sub-sacrificial semiconductor layer SAC1 can include Ge or SiGe. For example, in the first sub-sacrificial semiconductor layer SAC1, the atomic % of Ge can be from about 1% to about 100%, and the atomic % of Si can be from about 0% to about 99%.

[0064] Referring Figure 7 , a first sub-mode layer MOL1 can be formed to cover the first sub-sacrificial semiconductor layer SAC1 and the induced silicide material layer SILE. The first sub-mode layer MOL1 can cover the side surfaces of each of the first sub-sacrificial semiconductor layer SAC1 and the induced silicide material layer SILE and cover the upper surface of the induced silicide material layer SILE. The first sub-mode layer MOL1 can include a material having an etching selectivity with respect to the first sub-sacrificial semiconductor layer SAC1 and the induced silicide material layer SILE. For example, the first sub-mode layer MOL1 can include a spin-on hard mask (SOH) material or a semiconductor oxide layer. For example, the semiconductor oxide layer can include an oxide such as tetraethyl orthosilicate (TEOS) oxide or high-density plasma (HDP) oxide.

[0065] Referring together Figure 7 and Figure 8 , the upper portion of the first sub-mode layer MOL1 can be removed to expose the induced silicide material layer SILE. For example, the upper portion of the first sub-mode layer MOL1 can be removed by performing a chemical mechanical polishing (CMP) process in which the induced silicide material layer SILE serves as an etch stop film.

[0066] Referring together Figure 8 and Figure 9 , the upper portion of the first sub-mode layer MOL1 can be removed such that the upper portion of the first sub-sacrificial semiconductor layer SAC1 is exposed. The upper portion of the first sub-mode layer MOL1 can be removed by performing an etching process using the etching selectivity with respect to the first sub-sacrificial semiconductor layer SAC1 and the induced silicide material layer SILE.

[0067] Referring Figure 10 , a first support pattern SPT1 covering the side surfaces of the upper portion of the first sub-sacrificial semiconductor layer SAC1 and the side surfaces of the induced silicide material layer SILE can be formed on the first sub-mode layer MOL1. The first support pattern SPT1 can include Figures 2A to 2DThe first support pattern 350a shown. The first initial support material layer covering the first sub-sacrificial semiconductor layer SAC1 and the induced silicide material layer SILE can be formed on the first sub-mode layer MOL1. Subsequently, the upper portion of the first initial support material layer can be removed by performing a CMP process using the induced silicide material layer SILE as an etch stop film. Thus, the first support pattern SPT1 can be formed.

[0068] Referring together Figure 10 and Figure 11 , MIC can be performed by heating the induced silicide material layer SILE and injecting a semiconductor material precursor into the induced silicide material layer SILE, so that the second sub-sacrificial semiconductor layer SAC2 can be formed on the first sub-sacrificial semiconductor layer SAC1. The second sub-sacrificial semiconductor layer SAC2 can have a cylindrical shape with a constant horizontal width by MIC. The second sub-sacrificial semiconductor layer SAC2 can include Ge or SiGe. The second sub-sacrificial semiconductor layer SAC2 can have the same horizontal width as the first sub-sacrificial semiconductor layer SAC1 and can be aligned with the first sub-sacrificial semiconductor layer SAC1 in the vertical direction (Z direction). The second sub-sacrificial semiconductor layer SAC2 can be formed integrally (or formed as one body) with the first sub-sacrificial semiconductor layer SAC1.

[0069] Referring to Figure 12 , the second sub-mode layer MOL2 can be formed, which covers the second sub-sacrificial semiconductor layer SAC2 and the induced silicide material layer SILE. For example, the second sub-mode layer MOL2 can include the same material as the first sub-mode layer MOL1.

[0070] Referring together Figure 12 and Figure 13 , the upper portion of the second sub-mode layer MOL2 can be removed to expose the induced silicide material layer SILE.

[0071] Referring together Figure 13 and Figure 14 , the upper portion of the second sub-mode layer MOL2 can be removed such that the upper portion of the second sub-sacrificial semiconductor layer SAC2 is exposed. Subsequently, the second support pattern SPT2 covering the side surfaces of the upper portion of the second sub-sacrificial semiconductor layer SAC2 and the side surface of the induced silicide material layer SILE can be formed on the second sub-mode layer MOL2. The second support pattern SPT2 can include Figures 2A to 2D the second support pattern 350b shown.

[0072] Referring to Figure 15 , based on the above reference Figures 6A to 14According to the description, a third sub-sacrificial semiconductor layer SAC3 can be formed on the second sub-sacrificial semiconductor layer SAC2, a third sub-mold layer MOL3 can be formed around the third sub-sacrificial semiconductor layer SAC3, a third support pattern SPT3 can be formed to cover the upper side surfaces of the third sub-sacrificial semiconductor layer SAC3, a fourth sub-sacrificial semiconductor layer SAC4 can be formed on the third sub-sacrificial semiconductor layer SAC3, a fourth sub-mold layer MOL4 can be formed around the fourth sub-sacrificial semiconductor layer SAC4, and a fourth support pattern SPT4 can be formed to cover the upper side surfaces of each of the fourth sub-sacrificial semiconductor layer SAC4 and the induced silicide material layer SILE. The third support pattern SPT3 can include Figures 2A to 2D the third support pattern 350c shown in, and the fourth support pattern SPT4 can include Figures 2A to 2D the fourth support pattern 350d shown in.

[0073] The sacrificial semiconductor layer SAC can include a first sub-sacrificial semiconductor layer SAC1, a second sub-sacrificial semiconductor layer SAC2, a third sub-sacrificial semiconductor layer SAC3, and a fourth sub-sacrificial semiconductor layer SAC4. The first sub-sacrificial semiconductor layer SAC1, the second sub-sacrificial semiconductor layer SAC2, the third sub-sacrificial semiconductor layer SAC3, and the fourth sub-sacrificial semiconductor layer SAC4 can be portions of the sacrificial semiconductor layer SAC arranged in sequence from the bottom to the top of the sacrificial semiconductor layer SAC. The plurality of support patterns SPT are shown to include a first support pattern SPT1, a second support pattern SPT2, a third support pattern SPT3, and a fourth support pattern SPT4, and the plurality of mold layers MOL are shown to include a first sub-mold layer MOL1, a second sub-mold layer MOL2, a third sub-mold layer MOL3, and a fourth sub-mold layer MOL4. However, the embodiments are not limited thereto. For example, the plurality of support patterns SPT can include two, three, five, or more support patterns, and the plurality of mold layers MOL can include two, three, five, or more mold layers. For example, each of the plurality of mold layers MOL can include the same material.

[0074] Referring together to Figure 15 and Figure 16, the induced silicide material layer SILE and the sacrificial semiconductor layer SAC can be removed to form capacitor holes CPH passing through the plurality of mold layers MOL and the plurality of support patterns SPT. In the capacitor holes CPH, the regions passing through the first support pattern SPT1, the second support pattern SPT2, the third support pattern SPT3, and the fourth support pattern SPT4 can be respectively referred to as the first support hole, the second support hole, the third support hole, and the fourth support hole. The connection structure CTS can be exposed through the bottom surface of the capacitor hole CPH. The first support hole, the second support hole, the third support hole, and the fourth support hole can have a first horizontal width W1, a second horizontal width W2, a third horizontal width W3, and a fourth horizontal width W4, respectively. In some embodiments, the first horizontal width W1, the second horizontal width W2, the third horizontal width W3, and the fourth horizontal width W4 can have the same value. In some embodiments, the first horizontal width W1, the second horizontal width W2, the third horizontal width W3, and the fourth horizontal width W4 can have the same value as the horizontal width of the channel structure CHS and the horizontal width of the connection structure CTS. In some embodiments, the capacitor hole CPH can have a constant horizontal width from the lowermost end to the uppermost end of the capacitor hole CPH.

[0075] Referring to Figure 17 , a lower electrode CBE can be formed to fill the capacitor hole CPH. The lower electrode CBE can pass through the plurality of mold layers MOL and the plurality of support patterns SPT. The plurality of support patterns SPT can be in contact with the sidewalls of the lower electrode CBE. The lower electrode CBE can fill all of the first support hole of the first support pattern SPT1, the second support hole of the second support pattern SPT2, the third support hole of the third support pattern SPT3, and the fourth support hole of the fourth support pattern SPT4.

[0076] Referring together to Figure 17 and Figure 18 , the plurality of mold layers MOL can be removed.

[0077] Referring to Figure 19 , a capacitor dielectric layer CDI and an upper electrode CTE can be formed. The capacitor dielectric layer CDI can cover the surfaces of the plurality of lower electrodes CBE and the surfaces of the plurality of support patterns SPT, and the upper electrode CTE can fill the space between the plurality of lower electrodes CBE and the plurality of support patterns SPT and cover the capacitor dielectric layer CDI. Accordingly, a plurality of capacitor structures CAP including the plurality of lower electrodes CBE, the capacitor dielectric layer CDI, and the upper electrode CTE can be formed. Accordingly, the semiconductor memory device 10 can be formed. The semiconductor memory device 10, the capacitor structure CAP, the lower electrode CBE, the capacitor dielectric layer CDI, and the upper electrode CTE can respectively include Figures 2A to 2DThe semiconductor memory device 1, capacitor structure 300, lower electrode 310, capacitor dielectric layer 320, and upper electrode 330 shown.

[0078] The lower electrode CBE may have a first horizontal width W1 in a region between the lower surface of the lower electrode CBE and the upper surface of the first support pattern SPT1 in the vertical direction (Z direction), a second horizontal width W2 in a region between the upper surface of the first support pattern SPT1 and the upper surface of the second support pattern SPT2 in the vertical direction (Z direction), a third horizontal width W3 in a region between the upper surface of the second support pattern SPT2 and the upper surface of the third support pattern SPT3 in the vertical direction (Z direction), and a fourth horizontal width W4 in a region between the upper surface of the third support pattern SPT3 and the upper surface of the fourth support pattern SPT4 in the vertical direction (Z direction). The first horizontal width W1, the second horizontal width W2, the third horizontal width W3, and the fourth horizontal width W4 may have the same value. The lower electrode CBE may have a constant horizontal width from the lowermost end to the uppermost end of the lower electrode CBE.

[0079] Refer together Figures 3A to 19 , a method of manufacturing a semiconductor memory device 10 according to one or more example embodiments of the present inventive concept includes removing a sacrificial semiconductor layer SAC to form a capacitor hole CPH filled with a lower electrode CBE. The sacrificial semiconductor layer SAC may be formed by performing MIC on a connection structure CTS. In addition, even if the height of the lower electrode CBE filling the capacitor hole CPH increases, since the capacitor hole CPH is formed by removing the sacrificial semiconductor layer SAC, the connection structure CTS may also be exposed through the bottom surface of the capacitor hole CPH. Accordingly, a non-opening defect in which the connection structure CTS is not exposed through the bottom surface of the capacitor hole CPH may not occur, thereby ensuring the reliability of the semiconductor memory device.

[0080] In addition, the sacrificial semiconductor layer SAC may be formed by performing MIC, and thus has a constant horizontal width from the lower surface to the upper surface of the sacrificial semiconductor layer SAC. Accordingly, even if the horizontal width of the sacrificial semiconductor layer SAC decreases, the height of the sacrificial semiconductor layer SAC may be increased, and the height of the lower electrode CBE may also be increased. Accordingly, the capacitance of the capacitor structure CAP of the semiconductor memory device 10 may be ensured, and thus the reliability of the semiconductor memory device 10 may be ensured.

[0081] Figures 20 to 25 is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to one or more example embodiments. Specifically, Figures 20 to 25 is a cross-sectional view showing an operation after Figure 8

[0082] Refer together​Figure 8 and Figure 20 the upper portion of the first sub-mold layer MOL1 and the induced silicide material layer SILE can be removed. The upper portion of the first sub-mold layer MOL1 and the induced silicide material layer SILE can be removed by performing a CMP process in which the first sub-sacrificial semiconductor layer SAC1 serves as an etch stop film.

[0083] Referring together to Figure 20 and Figure 21 the upper portion of the first sub-mold layer MOL1 can be further removed such that the upper portion of the first sub-sacrificial semiconductor layer SAC1 is exposed. The upper portion of the first sub-mold layer MOL1 can be removed by performing an etching process with an etching selectivity with respect to the first sub-sacrificial semiconductor layer SAC1. Subsequently, the first support pattern SPT1 can be formed on the first sub-mold layer MOL1 to cover the side surface of the upper portion of the first sub-sacrificial semiconductor layer SAC1.

[0084] The first sub-induced silicide material layer SILE1 can be formed on the upper surface of the first sub-sacrificial semiconductor layer SAC1. The first sub-induced silicide material layer SILE1 can be substantially similar to Figure 8 the induced silicide material layer SILE shown, and thus its detailed description is omitted. When MIC is performed after the silicide material layer is formed on the upper surface of the first sub-sacrificial semiconductor layer SAC1, the silicide material layer can be transformed into the first sub-induced silicide material layer SILE1.

[0085] Referring together to Figure 21 and Figure 22 MIC can be performed by heating the first sub-induced silicide material layer SILE1 and injecting a semiconductor material precursor into the first sub-induced silicide material layer SILE1, and thus, the second sub-sacrificial semiconductor layer SAC2 can be formed on the first sub-sacrificial semiconductor layer SAC1.

[0086] Referring together to Figure 22 and Figure 23 the second sub-mold layer MOL2 can be formed to cover the second sub-sacrificial semiconductor layer SAC2 and the first sub-induced silicide material layer SILE1. Subsequently, the upper portion of the second sub-mold layer MOL2 and the first sub-induced silicide material layer SILE1 can be removed to expose the upper portion of the second sub-sacrificial semiconductor layer SAC2. Subsequently, the second support pattern SPT2 can be formed on the second sub-mold layer MOL2 to cover the side surface of the upper portion of the second sub-sacrificial semiconductor layer SAC2.

[0087] Referring to Figure 24 the second sub-induced silicide material layer SILE2 can be formed on the upper surface of the second sub-sacrificial semiconductor layer SAC2. The second sub-induced silicide material layer SILE2 can be substantially similar toFigure 22 The first sub-induced silicide material layer SILE1 shown is thus omitted from detailed description.

[0088] Referring together to Figure 24 and Figure 25 , based on the above reference Figures 22 to 23 , a third sub-sacrificial semiconductor layer SAC3 can be formed on the second sub-sacrificial semiconductor layer SAC2, a third sub-mode layer MOL3 surrounding the third sub-sacrificial semiconductor layer SAC3, a third support pattern SPT3 covering the upper side surfaces of the third sub-sacrificial semiconductor layer SAC3, a fourth sub-sacrificial semiconductor layer SAC4 on the third sub-sacrificial semiconductor layer SAC3, a fourth sub-mode layer MOL4 surrounding the fourth sub-sacrificial semiconductor layer SAC4, and a fourth support pattern SPT4 covering the upper side surfaces of the fourth sub-sacrificial semiconductor layer SAC4. To form the fourth sub-sacrificial semiconductor layer SAC4, a third sub-induced silicide material layer similar to Figure 22 the first sub-induced silicide material layer SILE1 shown and Figure 24 the second sub-induced silicide material layer SILE2 shown can be formed. After forming the fourth sub-sacrificial semiconductor layer SAC4, the third sub-induced silicide material layer can be removed.

[0089] The induced silicide material layer SILE, the first sub-induced silicide material layer SILE1, the second sub-induced silicide material layer SILE2, and the third sub-induced silicide material layer can be referred to as the first induced silicide material layer, the second induced silicide material layer, the third induced silicide material layer, and the fourth induced silicide material layer, respectively. Figures 3A to 19 Shows a method of forming each of the first sub-sacrificial semiconductor layer SAC1, the second sub-sacrificial semiconductor layer SAC2, the third sub-sacrificial semiconductor layer SAC3, and the fourth sub-sacrificial semiconductor layer SAC4 using the induced silicide material layer SILE. Figures 20 to 25 Shows a method of forming the first sub-sacrificial semiconductor layer SAC1, the second sub-sacrificial semiconductor layer SAC2, the third sub-sacrificial semiconductor layer SAC3, and the fourth sub-sacrificial semiconductor layer SAC4 using the first induced silicide material layer, the second induced silicide material layer, the third induced silicide material layer, and the fourth induced silicide material layer, respectively.

[0090] Subsequently, the sacrificial semiconductor layer SAC can be removed to form Figure 16 the capacitor hole CPH shown. Thus, the semiconductor memory device 10 shown in Figures 17 to 19 can be formed.

[0091] Figures 26A to 26E is a conceptual diagram showing a method of forming a sacrificial structure used in a method of manufacturing a semiconductor memory device according to one or more example embodiments.

[0092] Referring to Figure 26A , a substrate SUB having a base layer BASE can be fabricated. The base layer BASE can correspond to Figure 4A and Figure 4B the connection structure CTS on the channel structure CHS shown.

[0093] Referring to Figure 26B , a silicide material layer SIL can be formed on the base layer BASE. In some embodiments, the silicide material layer SIL can have a horizontal shape that is substantially the same as the horizontal shape of the base layer BASE.

[0094] Referring together to Figure 26B and Figure 26C , when heat is applied to the silicide material layer SIL, an induced silicide material layer SILE having a circular planar shape and a hemispherical shape due to surface tension can be formed.

[0095] Referring to Figure 26D , when a semiconductor material precursor PRCS is injected into the base layer BASE and the induced silicide material layer SILE, MIC occurs. Accordingly, a nanowire NNW can be formed between the base layer BASE and the induced silicide material layer SILE. The nanowire NNW can have a planar shape that is substantially the same as the planar shape of the induced silicide material layer SILE. For example, the nanowire NNW can have a cylindrical shape with a constant horizontal width. For example, the horizontal width of the nanowire NNW can be substantially the same as the horizontal width of the induced silicide material layer SILE.

[0096] Referring together to Figure 26D and Figure 26E , MIC can continue to form a nanowire NNW having a desired height. The nanowire NNW can have a constant horizontal width from the lower surface to the upper surface of the nanowire NNW. The nanowire NNW can correspond to Figure 15 and Figure 25 the sacrificial semiconductor layer SAC shown.

[0097] Figures 27 to 30 is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to one or more example embodiments, Figure 31 is a cross-sectional view showing a semiconductor memory device according to one or more example embodiments.

[0098] Referring to Figure 27 , instead of Figure 16The plurality of mold layers MOL including a first sub-mold layer MOL1, a second sub-mold layer MOL2, a third sub-mold layer MOL3, and a fourth sub-mold layer MOL4 as shown can form a plurality of mold layers MOLa including a first sub-mold layer MOL1a, a second sub-mold layer MOL2a, a third sub-mold layer MOL3a, and a fourth sub-mold layer MOL4a, and then a capacitor via hole CPH passing through the plurality of mold layers MOLa and a plurality of support patterns SPT can be formed.

[0099] The first sub-mold layer MOL1a, the second sub-mold layer MOL2a, the third sub-mold layer MOL3a, and the fourth sub-mold layer MOL4a can include similar materials, but their etching rates can be different from each other. In some embodiments, the fourth sub-mold layer MOL4a can have a slightly higher etching rate than the third sub-mold layer MOL3a, the third sub-mold layer MOL3a can have a slightly higher etching rate than the second sub-mold layer MOL2a, and the second sub-mold layer MOL2a can have a slightly higher etching rate than the first sub-mold layer MOL1a. For example, the first sub-mold layer MOL1a, the second sub-mold layer MOL2a, the third sub-mold layer MOL3a, and the fourth sub-mold layer MOL4a can include a spin-on hard mask material or a semiconductor oxide layer, but can have different etching rates due to different composition ratios for forming the spin-on hard mask material or different composition ratios for forming the semiconductor oxide layer.

[0100] Referring together Figure 27 and Figure 28 , a part of each of the first sub-mold layer MOL1a, the second sub-mold layer MOL2a, the third sub-mold layer MOL3a, and the fourth sub-mold layer MOL4a can be removed via the capacitor via hole CPH. Thus, an enlarged capacitor via hole CPHE can be formed. The enlarged capacitor via hole CPHE can also be referred to as a capacitor via hole. In some embodiments, the horizontal width of the removed portion of the fourth sub-mold layer MOL4a can be greater than the horizontal width of the removed portion of the third sub-mold layer MOL3a, the horizontal width of the removed portion of the third sub-mold layer MOL3a can be greater than the horizontal width of the removed portion of the second sub-mold layer MOL2a, and the horizontal width of the removed portion of the second sub-mold layer MOL2a can be greater than the horizontal width of the removed portion of the first sub-mold layer MOL1a.

[0101] In the enlarged capacitor hole CPHE, the first support hole, the second support hole, the third support hole, and the fourth support hole passing through the first support pattern SPT1, the second support pattern SPT2, the third support pattern SPT3, and the fourth support pattern SPT4 may have a first horizontal width W1, a second horizontal width W2, a third horizontal width W3, and a fourth horizontal width W4, respectively. The first mold hole, the second mold hole, the third mold hole, and the fourth mold hole passing through the first sub-mold layer MOL1a, the second sub-mold layer MOL2a, the third sub-mold layer MOL3a, and the fourth sub-mold layer MOL4a may have a fifth horizontal width W5, a sixth horizontal width W6, a seventh horizontal width W7, and an eighth horizontal width W8, respectively. The first horizontal width W1, the second horizontal width W2, the third horizontal width W3, and the fourth horizontal width W4 may have the same value. The fifth horizontal width W5, the sixth horizontal width W6, the seventh horizontal width W7, and the eighth horizontal width W8 may be greater than the first horizontal width W1, the second horizontal width W2, the third horizontal width W3, and the fourth horizontal width W4, respectively. The eighth horizontal width W8 may be greater than the seventh horizontal width W7, the seventh horizontal width W7 may be greater than the sixth horizontal width W6, and the sixth horizontal width W6 may be greater than the fifth horizontal width W5.

[0102] Referring to Figure 29 , a lower electrode CBEa may be formed to fill the enlarged capacitor hole CPHE. The lower electrode CBEa may pass through the plurality of mold layers MOLa and the plurality of support patterns SPT. The plurality of support patterns SPT may be in contact with the sidewalls of the lower electrode CBEa.

[0103] Referring together to Figure 29 and Figure 30 , the plurality of mold layers MOLa may be removed.

[0104] Referring to Figure 31 , a capacitor dielectric layer CDIa and an upper electrode CTEa may be formed. The capacitor dielectric layer CDIa may cover the surfaces of the plurality of lower electrodes CBEa and the surfaces of the plurality of support patterns SPT, and the upper electrode CTEa may fill the space between the plurality of lower electrodes CBEa and the plurality of support patterns SPT and cover the capacitor dielectric layer CDIa. Accordingly, a plurality of capacitor structures CAPa including the plurality of lower electrodes CBEa, the capacitor dielectric layer CDIa, and the upper electrode CTEa may be formed. Accordingly, a semiconductor memory device 10a may be formed.

[0105] The lower electrode CBEa may include a first electrode portion CBE1 between the lower surface of the lower electrode CBEa and the upper surface of the first support pattern SPT1, a second electrode portion CBE2 between the upper surface of the first support pattern SPT1 and the upper surface of the second support pattern SPT2, a third electrode portion CBE3 between the upper surface of the second support pattern SPT2 and the upper surface of the third support pattern SPT3, and a fourth electrode portion CBE4 between the upper surface of the third support pattern SPT3 and the upper surface of the fourth support pattern SPT4. The region of the first electrode portion CBE1 surrounded by the first support pattern SPT1 may have a first horizontal width W1, and the remaining region thereof may have a fifth horizontal width W5. The region of the second electrode portion CBE2 surrounded by the second support pattern SPT2 may have a second horizontal width W2, and the remaining region thereof may have a sixth horizontal width W6. The region of the third electrode portion CBE3 surrounded by the third support pattern SPT3 may have a third horizontal width W3, and the remaining region thereof may have a seventh horizontal width W7. The region of the fourth electrode portion CBE4 surrounded by the fourth support pattern SPT4 may have a fourth horizontal width W4, and the remaining region thereof may have an eighth horizontal width W8.

[0106] The region of the first electrode portion CBE1 surrounded by the first support pattern SPT1, the region of the second electrode portion CBE2 surrounded by the second support pattern SPT2, the region of the third electrode portion CBE3 surrounded by the third support pattern SPT3, and the region of the fourth electrode portion CBE4 surrounded by the fourth support pattern SPT4 may each have a constant horizontal width from the lowermost end to the uppermost end of each of the above regions. The remaining region of the first electrode portion CBE1 not surrounded by the first support pattern SPT1 may have a constant horizontal width from the lowermost end to the uppermost end (i.e., from the lower surface of the lower electrode CBEa to the lower surface of the first support pattern SPT1). The remaining region of the second electrode portion CBE2 not surrounded by the second support pattern SPT2 may have a constant horizontal width from the lowermost end to the uppermost end (i.e., from the upper surface of the first support pattern SPT1 to the lower surface of the second support pattern SPT2). The remaining region of the third electrode portion CBE3 not surrounded by the third support pattern SPT3 may have a constant horizontal width from the lowermost end to the uppermost end (i.e., from the upper surface of the second support pattern SPT2 to the lower surface of the third support pattern SPT3). The remaining region of the fourth electrode portion CBE4 not surrounded by the fourth support pattern SPT4 may have a constant horizontal width from the lowermost end to the uppermost end (i.e., from the upper surface of the third support pattern SPT3 to the lower surface of the fourth support pattern SPT4).

[0107] Figures 32A to 35Bis a perspective view and a cross-sectional view showing a method of manufacturing a semiconductor memory device according to one or more example embodiments, Figure 36 is a cross-sectional view showing a semiconductor memory device according to one or more example embodiments. Specifically, Figure 32A , Figure 33A , Figure 34A and Figure 35A are perspective views showing a method of manufacturing a semiconductor memory device according to one or more example embodiments, Figure 32B , Figure 33B , Figure 34B and Figure 35B are cross-sectional views showing a method of manufacturing a semiconductor memory device according to one or more example embodiments. Specifically, Figures 32A to 35B is a cross-sectional view showing operations after Figure 3A and Figure 3B .

[0108] Referring together to Figure 32A and Figure 32B , a selective epitaxial growth (SEG) layer SEG may be formed on a channel structure CHS. The SEG layer SEG may be formed by performing selective epitaxial growth using the channel structure CHS as a seed crystal. The SEG layer SEG may have a larger horizontal width and horizontal area than the horizontal width and horizontal area of the channel structure CHS.

[0109] Referring to Figure 33A and Figure 33B , a connection structure CTSb may be formed by implanting impurities into the SEG layer SEG. In some embodiments, the connection structure CTSb may be formed by implanting impurities into the upper portion of the SEG layer SEG and the channel structure CHS that contacts the SEG layer SEG. For example, the connection structure CTSb may be formed by implanting n-type impurities into the upper portion of the channel structure CHS and the SEG layer SEG.

[0110] Referring together to Figure 34A and Figure 34B , a silicide material layer SILb may be formed on the connection structure CTSb. The silicide material layer SILb may have a larger horizontal width and horizontal area than the horizontal width and horizontal area of the channel structure CHS. For example, the silicide material layer SILb may completely cover the upper surface of the connection structure CTSb.

[0111] Referring together to Figure 35A and Figure 35B, MIC can be performed by heating the connection structure CTSb and the silicide material layer SILb and injecting a semiconductor material precursor into the connection structure CTSb and the silicide material layer SILb, so that the first sub-sacrificial semiconductor layer SAC1b can be formed. The first sub-sacrificial semiconductor layer SAC1b can have a cylindrical shape with a constant horizontal width. The horizontal width of the first sub-sacrificial semiconductor layer SAC1b can be greater than the horizontal width of the channel structure CHS.

[0112] Referring to Figure 36 , it can be referred to Figures 22 to 23 , a plurality of support patterns SPTb, a plurality of lower electrodes CBEb, a capacitor dielectric layer CDIb, and an upper electrode CTEb are formed. The plurality of lower electrodes CBEb can fill a plurality of capacitor holes CPHb passing through the plurality of support patterns SPTb, the capacitor dielectric layer CDIb can cover the surfaces of the plurality of lower electrodes CBEb and the surfaces of the plurality of support patterns SPTb, and the upper electrode CTEb can fill the space between the plurality of lower electrodes CBEb and the plurality of support patterns SPTb and can cover the capacitor dielectric layer CDIb. Therefore, a plurality of capacitor structures CAPb including the plurality of lower electrodes CBEb, the capacitor dielectric layer CDIb, and the upper electrode CTEb can be formed. Therefore, the semiconductor memory device 10b can be formed. The plurality of support patterns SPTb can include a first support pattern SPT1b, a second support pattern SPT2b, a third support pattern SPT3b, and a fourth support pattern SPT4b, which are at different vertical levels and are spaced apart from each other in the vertical direction (Z direction).

[0113] The lower electrode CBEb can have a first horizontal width W1b in the region between the lower surface of the lower electrode CBEb and the upper surface of the first support pattern SPT1b in the vertical direction (Z direction), a second horizontal width W2b in the region between the upper surface of the first support pattern SPT1b and the upper surface of the second support pattern SPT2b in the vertical direction (Z direction), a third horizontal width W3b in the region between the upper surface of the second support pattern SPT2b and the upper surface of the third support pattern SPT3b in the vertical direction (Z direction), and a fourth horizontal width W4b in the region between the upper surface of the third support pattern SPT3b and the upper surface of the fourth support pattern SPT4b in the vertical direction (Z direction). The first horizontal width W1b, the second horizontal width W2b, the third horizontal width W3b, and the fourth horizontal width W4b can have the same value. The first horizontal width W1b, the second horizontal width W2b, the third horizontal width W3b, and the fourth horizontal width W4b can be greater than the horizontal width of the channel structure CHS and equal to the horizontal width of the connection structure CTSb. The lower electrode CBEb can have a constant horizontal width from the lowermost end to the uppermost end of the lower electrode CBEb.

[0114] Figures 37 to 44 is a cross-sectional view showing a method of manufacturing a semiconductor memory device according to one or more example embodiments, Figure 45 is a cross-sectional view showing a semiconductor memory device according to one or more example embodiments.

[0115] Referring to Figure 37 , a first sub-sacrificial semiconductor layer SAC1c may be formed on a connection structure CTSc with reference to Figures 34A to 35B , and a first sub-mode layer MOL1c may be formed to cover side surfaces of the first sub-sacrificial semiconductor layer SAC1c with reference to Figure 20 . The connection structure CTSc may be substantially the same as the connection structure CTSb shown in Figure 33A and Figure 33B .

[0116] Referring to Figure 38 , an upper portion of the first sub-mode layer MOL1c may be removed such that an upper portion of the first sub-sacrificial semiconductor layer SAC1c is exposed. Subsequently, a first support pattern SPT1c may be formed on the first sub-mode layer MOL1c to cover side surfaces of an upper portion of the first sub-sacrificial semiconductor layer SAC1c.

[0117] Referring to Figure 39 , a first sub-SEG layer SEG1 may be formed on the first sub-sacrificial semiconductor layer SAC1c. The first sub-SEG layer SEG1 may be formed by performing selective epitaxial growth using the first sub-sacrificial semiconductor layer SAC1c as a seed crystal. The first sub-SEG layer SEG1 may have a larger horizontal width and horizontal area than those of the first sub-sacrificial semiconductor layer SAC1c.

[0118] Referring to Figure 40 , a first sub-induced silicide material layer SILE1c may be formed on an upper surface of the first sub-SEG layer SEG1.

[0119] Referring together to Figure 40 and Figure 41 , MIC may be performed by heating the first sub-induced silicide material layer SILE1c and injecting a semiconductor material precursor into the first sub-induced silicide material layer SILE1c, so that a second sub-sacrificial semiconductor layer SAC2c may be formed on the first sub-sacrificial semiconductor layer SAC1c.

[0120] Referring together to Figure 41 and Figure 42, a second sub-mode layer MOL2c covering the second sub-sacrificial semiconductor layer SAC2c and the first sub-induced silicide material layer SILE1c can be formed. Subsequently, the upper portion of the second sub-mode layer MOL2c and the first sub-induced silicide material layer SILE1c can be removed to expose the upper portion of the second sub-sacrificial semiconductor layer SAC2c. Subsequently, a second support pattern SPT2c can be formed on the second sub-mode layer MOL2c to cover the side surface of the upper portion of the second sub-sacrificial semiconductor layer SAC2c.

[0121] Refer together to Figure 42 and Figure 43 , form a reference to Figure 23 and Figure 25 and Figures 39 to 42 the following layers: a second sub-SEG layer SEG2 on the second sub-sacrificial semiconductor layer SAC2c; a third sub-sacrificial semiconductor layer SAC3c on the second sub-SEG layer SEG2; a third sub-mode layer MOL3c covering a part of the side surface of the third sub-sacrificial semiconductor layer SAC3c and the side surface of the second sub-SEG layer SEG2; a third support pattern SPT3c disposed on the third sub-mode layer MOL3c and covering the side surface of the upper portion of the third sub-sacrificial semiconductor layer SAC3c; a third sub-SEG layer SEG3 on the third sub-sacrificial semiconductor layer SAC3c; a fourth sub-sacrificial semiconductor layer SAC4c on the third sub-SEG layer SEG3; a fourth sub-mode layer MOL4c covering a part of the side surface of the fourth sub-sacrificial semiconductor layer SAC4c and the side surface of the third sub-SEG layer SEG3; and a fourth support pattern SPT4c disposed on the fourth sub-mode layer MOL4c and covering the side surface of the upper portion of the fourth sub-sacrificial semiconductor layer SAC4c. The plurality of sacrificial semiconductor layers SACc may include a first sub-sacrificial semiconductor layer SAC1c, a second sub-sacrificial semiconductor layer SAC2c, a third sub-sacrificial semiconductor layer SAC3c, and a fourth sub-sacrificial semiconductor layer SAC4c. The plurality of support patterns SPTc include a first support pattern SPT1c, a second support pattern SPT2c, a third support pattern SPT3c, and a fourth support pattern SPT4c, and the plurality of mode layers MOLc include a first sub-mode layer MOL1c, a second sub-mode layer MOL2c, a third sub-mode layer MOL3c, and a fourth sub-mode layer MOL4c. The SEG layer SEG, the first sub-SEG layer SEG1, the second sub-SEG layer SEG2, and the third sub-SEG layer SEG3 may be respectively referred to as the first SEG layer, the second SEG layer, the third SEG layer, and the fourth SEG layer.

[0122] Refer together to Figure 43 and Figure 44, the SEG layer SEG, the first sub-SEG layer SEG1, the second sub-SEG layer SEG2, the third sub-SEG layer SEG3, and the plurality of sacrificial semiconductor layers SACc can be removed. Thus, a capacitor via CPHc passing through the plurality of mold layers MOLc and the plurality of support patterns SPTc can be formed.

[0123] In the capacitor via CPHc, the region passing through the first support pattern SPT1c and the region passing through the first sub-mold layer MOL1c may have a first horizontal width W1c, the region passing through the second support pattern SPT2c and the region passing through the second sub-mold layer MOL2c may have a second horizontal width W2c, the region passing through the third support pattern SPT3c and the region passing through the third sub-mold layer MOL3c may have a third horizontal width W3c, and the region passing through the fourth support pattern SPT4c and the region passing through the fourth sub-mold layer MOL4c may have a fourth horizontal width W4c. The first horizontal width W1c may be greater than the horizontal width of the channel structure CHS, the second horizontal width W2c may be greater than the first horizontal width W1c, the third horizontal width W3c may be greater than the second horizontal width W2c, and the fourth horizontal width W4c may be greater than the third horizontal width W3c.

[0124] Referring together Figure 44 and Figure 45 , a lower electrode CBEc can be formed to fill the capacitor via CPHc, and the plurality of mold layers MOLc can be removed. Subsequently, a capacitor dielectric layer CDIc and an upper electrode CTEc can be formed. The capacitor dielectric layer CDIc can cover the surfaces of the plurality of lower electrodes CBEc and the surfaces of the plurality of support patterns SPTc, and the upper electrode CTEc can fill the space between the plurality of lower electrodes CBEc and the plurality of support patterns SPTc and cover the capacitor dielectric layer CDIc. Thus, a plurality of capacitor structures CAPc including the plurality of lower electrodes CBEc, the capacitor dielectric layer CDIc, and the upper electrode CTEc can be formed. Thus, a semiconductor memory device 10c can be formed.

[0125] The lower electrode CBEc may include a first electrode portion CBE1c between the lower surface of the lower electrode CBEc and the upper surface of the first support pattern SPT1c in the vertical direction (Z direction), a second electrode portion CBE2c between the upper surface of the first support pattern SPT1c and the upper surface of the second support pattern SPT2c in the vertical direction (Z direction), a third electrode portion CBE3c between the upper surface of the second support pattern SPT2c and the upper surface of the third support pattern SPT3c in the vertical direction (Z direction), and a fourth electrode portion CBE4c between the upper surface of the third support pattern SPT3c and the upper surface of the fourth support pattern SPT4c in the vertical direction (Z direction). The first electrode portion CBE1c may have a first horizontal width W1c, the second electrode portion CBE2c may have a second horizontal width W2c, the third electrode portion CBE3c may have a third horizontal width W3c, and the fourth electrode portion CBE4c may have a fourth horizontal width W4c. The first electrode portion CBE1c, the second electrode portion CBE2c, the third electrode portion CBE3c, and the fourth electrode portion CBE4c may each have a constant horizontal width from its lowermost end to its uppermost end. The fourth horizontal width W4c, which is the horizontal width of the fourth electrode portion CBE4c, may be greater than the third horizontal width W3c, which is the horizontal width of the third electrode portion CBE3c. The third horizontal width W3c, which is the horizontal width of the third electrode portion CBE3c, may be greater than the second horizontal width W2c, which is the horizontal width of the second electrode portion CBE2c. The second horizontal width W2c, which is the horizontal width of the second electrode portion CBE2c, may be greater than the first horizontal width W1c, which is the horizontal width of the first electrode portion CBE1c. The first horizontal width W1c, which is the horizontal width of the first electrode portion CBE1c, may be greater than the horizontal width of the channel structure CHS.

[0126] Figure 46 is a plan layout showing a semiconductor memory device 2 according to one or more example embodiments.

[0127] Referring to Figure 46 , the semiconductor memory device 2 may include a plurality of word lines WLa extending in a first horizontal direction (X direction), a plurality of bit lines BLa extending in a second horizontal direction (Y direction) different from the first horizontal direction (X direction), a plurality of back gate lines BGa extending in the first horizontal direction (X direction), and a plurality of channel patterns CHa extending in a vertical direction (Z direction).

[0128] The multiple word lines WLa and the multiple back gate lines BGa may be spaced apart from each other in a second horizontal direction (Y direction) and extend parallel to each other in a first horizontal direction (X direction). For example, the multiple word lines WLa and the multiple back gate lines BGa may be alternately arranged in the second horizontal direction (Y direction).

[0129] The multiple bit lines BLa may be spaced apart from each other in the first horizontal direction (X direction) and extend parallel to each other in the second horizontal direction (Y direction). The covering insulating layer BLOa may cover the multiple bit lines BLa. The covering insulating layer BLOa may conformally cover the multiple bit lines BLa, but does not completely fill the space between the multiple bit lines BLa. The shielding conductive layer SLa may cover the multiple bit lines BLa having the covering insulating layer BLOa therebetween. The space between the multiple bit lines BLa that is not completely filled by the covering insulating layer BLOa may be filled with the shielding conductive layer SLa.

[0130] The multiple channel patterns CHa may be arranged in rows in the first horizontal direction (X direction) between a word line WLa and a back gate line BGa that are adjacent to each other among the multiple word lines WLa and the multiple back gate lines BGa. The channel patterns CHa between a pair of adjacent back gate lines BGa among the multiple back gate lines BGa may be arranged in a zigzag pattern in the first horizontal direction (X direction). For example, the channel patterns CHa may be arranged to form a pair of rows extending in the first horizontal direction (X direction) between a pair of adjacent back gate lines BGa among the multiple back gate lines BGa. The channel patterns CHa arranged in a pair of rows between the pair of adjacent back gate lines BGa may be alternately arranged in the pair of rows to form a zigzag pattern in the first horizontal direction (X direction).

[0131] Each of the multiple channel patterns CHa may include a first sidewall facing the back gate line BGa and a second sidewall facing the word line WLa and connected to an edge of the first sidewall. The first sidewall may be flat, and the second sidewall may be curved. That is, in a plan view, the first sidewall may have a straight shape, and the second sidewall may have a curved shape. For example, in a plan view, each of the multiple channel patterns CHa may have a quasi-rectangular shape in which two corners facing the word line WLa are rounded, or may have a shape in which the second sidewall has an arc of a circle or an arc of an ellipse.

[0132] The gate insulating layer Goxa may be located between the channel pattern CHa and the word line WLa, and the back gate insulating layer BGoxa may be located between the channel pattern CHa and the back gate line BGa. In some embodiments, the gate insulating layer Goxa may surround at least a portion of the channel pattern CHa in a plan view. In some embodiments, the back gate insulating layer BGoxa may extend in a first horizontal direction (X direction) along both sides of the back gate line BGa in a second horizontal direction (Y direction). A first sidewall of the channel pattern CHa may be covered with the back gate insulating layer BGoxa, and a second sidewall of the channel pattern CHa may be covered with the gate insulating layer Goxa.

[0133] The plurality of bit lines BLa may be spaced apart from each other in a first horizontal direction (X direction) and extend parallel to each other in a second horizontal direction (Y direction). The plurality of bit lines BLa may extend in the second horizontal direction (Y direction) and be electrically connected to the plurality of channel patterns CHa. For example, the plurality of bit lines BLa may be electrically connected to a first end of each of the two ends of the plurality of channel patterns CHa in a vertical direction (Z direction). One bit line BLa may be electrically connected to only one of the channel patterns CHa disposed between a pair of adjacent back gate lines BGa among the plurality of back gate lines BGa. A pair of bit lines BLa adjacent to each other in the first horizontal direction (X direction) may be electrically connected to the channel patterns CHa disposed in different rows among the channel patterns CHa disposed in the pair of rows between the pair of back gate lines BGa.

[0134] The bit line BLa, the word line WLa, the channel pattern CHa (a portion of which adjacent to the word line WLa intersects the bit line BLa in a plan view), and the gate insulating layer Goxa between the word line WLa and the channel pattern CHa may form a vertical channel transistor.

[0135] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the following claims and their equivalents.

[0136] This application is based on and claims priority to Korean Patent Application No. 10-2023-0168234, filed with the Korean Intellectual Property Office on November 28, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A method for manufacturing a semiconductor memory device, the method comprising: forming a channel structure including a channel pattern on a substrate; forming a silicide material layer including an alloy of a semiconductor material and a metal on the channel structure, the metal including a eutectic component; forming a sacrificial semiconductor layer between the channel structure and the silicide material layer, and forming a mold layer surrounding the sacrificial semiconductor layer; forming a capacitor hole by removing the sacrificial semiconductor layer; forming a lower electrode filling the capacitor hole; removing the mold layer; forming a capacitor dielectric layer covering a surface of the lower electrode; as well as An upper electrode is formed covering the capacitor dielectric layer. 2 . The method according to claim 1 , wherein the sacrificial semiconductor layer has a constant horizontal width from a lowermost end to an uppermost end of the sacrificial semiconductor layer.

3. The method according to claim 1, further comprising, before forming the silicide material layer, forming a connection structure on the channel structure, The sacrificial semiconductor layer has a horizontal width equal to a horizontal width of the connecting structure. The method of claim 1 , wherein the sacrificial semiconductor layer has a cylindrical shape. 5 . The method of claim 1 , wherein forming the sacrificial semiconductor layer comprises forming the sacrificial semiconductor layer by performing metal induced crystallization by implanting a semiconductor material precursor into the channel structure and the silicide material layer while heating the channel structure and the silicide material layer. 6 . The method according to claim 5 , wherein when the metal induced crystallization is performed, the silicide material layer is transformed into an induced silicide material layer having a circular planar shape and a hemispherical shape due to surface tension.

7. The method according to claim 6, wherein the sacrificial semiconductor layer comprises a plurality of sub-sacrificial semiconductor layers, the mold layer comprises a plurality of sub-mold layers, and The forming of the sacrificial semiconductor layer and the forming of the mold layer comprises: A first operation is to form a sub-sacrificial semiconductor layer among the plurality of sub-sacrificial semiconductor layers by performing the metal induced crystallization; A second operation is to form a sub-mold layer surrounding a portion of a side surface of the one sacrificial semiconductor layer among the plurality of sub-mold layers; A third operation is to form a support pattern covering a side surface of an upper portion of the one sub-sacrificial semiconductor layer; as well as The first operation, the second operation, and the third operation are repeated at least twice.

8. The method according to claim 7, wherein the silicide-inducing material layer is removed after forming the one sub-mold layer, and The method further includes forming another silicide material layer on the one sub mold layer before forming another sub mold layer among the plurality of sub mold layers.

9. The method according to claim 7, wherein each of the plurality of sub-sacrificial semiconductor layers has a constant horizontal width from a lowermost end to an uppermost end of each sub-sacrificial semiconductor layer, and A sub-sacrificial semiconductor layer at a higher level among the plurality of sub-sacrificial semiconductor layers has a horizontal width greater than a horizontal width of a sub-sacrificial semiconductor layer at a lower level among the plurality of sub-sacrificial semiconductor layers.

10. The method according to claim 1 , further comprising, before forming the silicide material layer, forming a selective epitaxial growth (SEG) layer on an upper surface of the channel structure, the SEG layer having a horizontal width greater than a horizontal width of the channel structure, The silicide material layer is formed on the SEG layer.

11. A method for manufacturing a semiconductor memory device, the method comprising: forming a plurality of word lines, a plurality of channel structures, and a plurality of bit lines on a substrate, wherein the plurality of word lines extend in a first horizontal direction, wherein the plurality of channel structures are adjacent to the plurality of word lines and arranged in a row in the first horizontal direction, each of the plurality of channel structures comprises a channel pattern extending in a vertical direction, and wherein the plurality of bit lines extend in a second horizontal direction different from the first horizontal direction and are electrically connected to first ends of the plurality of channel patterns; forming a plurality of silicide material layers on the plurality of channel structures respectively, each of the plurality of silicide material layers comprising an alloy of a semiconductor material and a metal, wherein the metal comprises a eutectic component; performing metal induced crystallization to transform the plurality of silicide material layers into a plurality of induced silicide material layers having a circular planar shape; forming a plurality of sacrificial semiconductor layers between the plurality of silicide-inducing material layers and upper surfaces of the plurality of channel structures, and forming a mold layer surrounding the plurality of sacrificial semiconductor layers; forming a plurality of capacitor holes by removing the plurality of sacrificial semiconductor layers; forming a plurality of lower electrodes respectively filling the plurality of capacitor holes and respectively electrically connected to the second ends of the plurality of channel patterns; removing the mold layer; forming a capacitor dielectric layer covering surfaces of the plurality of lower electrodes; as well as An upper electrode is formed covering the capacitor dielectric layer.

12. The method according to claim 11, wherein each of the plurality of sacrificial semiconductor layers comprises a plurality of sub-sacrificial semiconductor layers, the mold layer comprises a plurality of sub-mold layers, and The forming of the plurality of sacrificial semiconductor layers and the forming of the mold layer comprises: A first operation is to form a sub-sacrificial semiconductor layer among the plurality of sub-sacrificial semiconductor layers by performing the metal induced crystallization; A second operation is to form a sub-mold layer surrounding a portion of a side surface of the one sacrificial semiconductor layer among the plurality of sub-mold layers; A third operation is to form a support pattern covering a side surface of an upper portion of the one sub-sacrificial semiconductor layer; as well as The first operation, the second operation, and the third operation are repeated at least three times.

13. The method according to claim 12, wherein each of the plurality of sub-sacrificial semiconductor layers has a constant horizontal width from a lowermost end to an uppermost end of each sub-sacrificial semiconductor layer, and Each of the plurality of lower electrodes has a constant horizontal width from a lowermost end to an uppermost end of each lower electrode.

14. The method according to claim 12, wherein a plurality of the support patterns are formed, the plurality of support patterns respectively covering side surfaces of upper portions of the plurality of sub-sacrificial semiconductor layers, and The plurality of supporting patterns include a plurality of supporting holes, and the plurality of supporting holes are respectively filled with portions of the plurality of sacrificial semiconductor sub-layers. 15 . The method of claim 14 , wherein the plurality of supporting holes of the plurality of supporting patterns have the same horizontal width.

16. The method according to claim 14, wherein: For two supporting patterns adjacent to each other in the vertical direction among the plurality of supporting patterns, supporting holes of a supporting pattern at a higher level have a larger horizontal width than a supporting hole of a supporting pattern at a lower level.

17. The method according to claim 12, wherein each of the plurality of sub-sacrificial semiconductor layers has a constant horizontal width from a lowermost end to an uppermost end of each sub-sacrificial semiconductor layer, and in, For two sub-sacrificial semiconductor layers adjacent to each other in the vertical direction among the plurality of sub-sacrificial semiconductor layers, the sub-sacrificial semiconductor layer at a higher level has a larger horizontal width than that of the sub-sacrificial semiconductor layer at a lower level.

18. A method for manufacturing a semiconductor memory device, the method comprising: forming a plurality of word lines, a plurality of back gate lines, a plurality of channel patterns and a plurality of bit lines on a substrate, wherein the plurality of word lines extend in a first horizontal direction, wherein the plurality of back gate lines extend in the first horizontal direction and are spaced apart from the plurality of word lines in a second horizontal direction different from the first horizontal direction, wherein the plurality of channel patterns are arranged between one word line among the plurality of word lines and one back gate line adjacent to the one word line among the plurality of back gate lines, the plurality of channel patterns extend in a vertical direction, and the plurality of bit lines extend under the plurality of channel patterns in the second horizontal direction different from the first horizontal direction and are electrically connected to first ends of the plurality of channel patterns; forming a plurality of connection structures by implanting impurities into upper portions of the plurality of channel patterns; forming a plurality of silicide material layers on the plurality of connection structures, each of the plurality of silicide material layers comprising an alloy of a semiconductor material and a metal, the metal comprising a eutectic component; forming a plurality of sacrificial semiconductor layers, a mold layer, and a plurality of support patterns on the plurality of connection structures; forming a plurality of capacitor holes by removing the plurality of sacrificial semiconductor layers; forming a plurality of lower electrodes respectively filling the plurality of capacitor holes and respectively electrically connected to the second ends of the plurality of channel patterns; removing the mold layer; forming a capacitor dielectric layer covering surfaces of the plurality of lower electrodes and surfaces of the plurality of support patterns; as well as forming an upper electrode covering the capacitor dielectric layer, wherein each of the plurality of sacrificial semiconductor layers comprises a plurality of sub-sacrificial semiconductor layers having a cylindrical shape, the mold layer comprises a plurality of sub-mold layers, and The forming of the plurality of sacrificial semiconductor layers, the mold layer and the plurality of support patterns comprises: heating the plurality of silicide material layers and transforming the plurality of silicide material layers into a plurality of induced silicide material layers having a circular planar shape; A first operation is to form a sub-sacrificial semiconductor layer among the plurality of sub-sacrificial semiconductor layers between the plurality of induced silicide material layers and upper surfaces of the plurality of connection structures by injecting a semiconductor material precursor and performing metal induced crystallization; A second operation is to form a sub-mold layer surrounding a portion of a side surface of the one sacrificial semiconductor layer among the plurality of sub-mold layers; A third operation is to form a support pattern covering a side surface of an upper portion of the one sub-sacrificial semiconductor layer among the plurality of support patterns; and The first operation, the second operation, and the third operation are repeated at least three times. 19 . The method of claim 18 , wherein each of the plurality of sub-sacrificial semiconductor layers has a constant horizontal width from a lowermost end to an uppermost end of each sub-sacrificial semiconductor layer. 20 . The method of claim 18 , wherein each of the plurality of sub-sacrificial semiconductor layers comprises Ge or SiGe.

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