Semiconductor device and preparation method thereof, and electronic device

Abstract

The invention provides a semiconductor device, a preparation method thereof and an electronic device, and the method comprises the steps: providing a substrate, and forming a first interlayer dielectric layer on the substrate; forming a first pole plate layer, a ferroelectric medium layer and a second pole plate layer on the first interlayer dielectric layer, wherein the second pole plate layer comprises tungsten; forming a patterned first bottom anti-reflection layer, a first oxide hard mask layer, a first metal hard mask layer and a second bottom anti-reflection layer on the second polar plate layer; and etching the second polar plate layer, the ferroelectric dielectric layer and the first polar plate layer by taking the first bottom anti-reflection layer, the first oxide hard mask layer, the first metal hard mask layer and the second bottom anti-reflection layer as masks to form the ferroelectric capacitor. According to the scheme, the second pole plate layer comprises tungsten, the first bottom anti-reflection layer, the first oxide hard mask layer, the first metal hard mask layer and the second bottom anti-reflection layer serve as masks, the second pole plate layer, the ferroelectric medium layer and the first pole plate layer are etched to form the ferroelectric capacitor, and the product performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a semiconductor device, a method for manufacturing the same, and an electronic device. Background Art

[0002] Ferroelectric random access memory (FRAM) is a new type of memory that combines the non-volatility of read-only memory (ROM) and random access memory (RAM), and has advantages such as strong durability, high-speed read / write, and low power consumption. It has been widely used in various fields.

[0003] The core part of the ferroelectric memory is the ferroelectric capacitor. The ferroelectric capacitor in the ferroelectric memory generally adopts a metal / insulator / metal (MIM) structure. The manufacturing process of this MIM structure is generally to deposit a metal layer as the lower electrode plate first, then grow a ferroelectric thin film material as the dielectric layer, then deposit a metal layer as the upper electrode plate, and finally define the MIM structure by photolithography and etching.

[0004] Among them, when a tungsten layer is added to the upper electrode plate of the MIM structure, the remanent polarization intensity and the number of read / write cycles of the product can be effectively improved. However, in the related art, after adding the tungsten layer, it is impossible to etch through the tungsten layer and the MIM structure, resulting in the inability to form a ferroelectric capacitor, and thus the remanent polarization intensity and the number of read / write cycles of the product cannot be improved, and the performance of the product cannot be enhanced. Summary of the Invention

[0005] A series of simplified concepts are introduced in the summary of the invention, which will be further described in detail in the detailed implementation section. The summary of the invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the protection scope of the claimed technical solution.

[0006] In view of the existing problems, on the one hand, the present invention provides a method for manufacturing a semiconductor device, including:

[0007] Providing a substrate, on which a first interlayer dielectric layer is formed;

[0008] Sequentially forming a first electrode plate layer, a ferroelectric dielectric layer, and a second electrode plate layer on the first interlayer dielectric layer, wherein the second electrode plate layer includes tungsten;

[0009] Sequentially forming a patterned first bottom antireflection layer, a first oxide hard mask layer, a first metal hard mask layer, and a second bottom antireflection layer on the second electrode plate layer;

[0010] Using the first bottom antireflection layer, the first oxide hard mask layer, the first metal hard mask layer, and the second bottom antireflection layer as masks, etch the second electrode layer, the ferroelectric dielectric layer, and the first electrode layer to form a ferroelectric capacitor.

[0011] Exemplarily, the first bottom antireflection layer and the second bottom antireflection layer include silicon oxynitride, and the first metal hard mask layer includes titanium nitride.

[0012] Exemplarily, the thickness of the first bottom antireflection layer ranges from 400 to 600 angstroms, the thickness of the first oxide hard mask layer ranges from 100 to 200 angstroms, the thickness of the first metal hard mask layer ranges from 400 to 600 angstroms, and the thickness of the second bottom antireflection layer ranges from 300 to 350 angstroms.

[0013] Exemplarily, the second electrode layer at least includes a top layer and a bottom layer stacked vertically, wherein the top layer includes a tungsten layer and the bottom layer includes a titanium nitride layer.

[0014] Exemplarily, the thickness of the top layer ranges from 1000 to 1700 angstroms.

[0015] Exemplarily, sequentially forming a patterned first bottom antireflection layer, a first oxide hard mask layer, a first metal hard mask layer, and a second bottom antireflection layer on the second electrode layer includes:

[0016] Sequentially forming a first bottom antireflection layer, a first oxide hard mask layer, a first metal hard mask layer, a second bottom antireflection layer, and a patterned photoresist layer on the second electrode layer;

[0017] Using the patterned photoresist layer as a mask, sequentially etch the second bottom antireflection layer, the first metal hard mask layer, the first oxide hard mask layer, and the first bottom antireflection layer.

[0018] Exemplarily, it further includes a transistor formed on the substrate, the first interlayer dielectric layer covers the transistor, and a first conductive plug is formed in the first interlayer dielectric layer to electrically connect the transistor and the ferroelectric capacitor.

[0019] Exemplarily, the first electrode layer includes titanium nitride, and the ferroelectric dielectric layer includes zirconium-doped hafnium oxide.

[0020] Another aspect of the present invention provides a semiconductor device, which is obtained by using the foregoing method for preparation.

[0021] Yet another aspect of the present invention further provides an electronic device, which includes the foregoing semiconductor device.

[0022] The semiconductor device, its manufacturing method, and the electronic device according to the embodiments of the present invention. The formed second electrode layer includes tungsten, and the second electrode layer serves as the upper electrode of the ferroelectric capacitor. By using the first bottom antireflection layer, the first oxide hard mask layer, the first metal hard mask layer, and the second bottom antireflection layer as masks, the second electrode layer, the ferroelectric dielectric layer, and the first electrode layer are etched to form the ferroelectric capacitor, which solves the problem in the related art that the ferroelectric capacitor cannot be formed due to adding a tungsten layer on the upper electrode of the ferroelectric capacitor. Thus, the remanent polarization intensity and the read / write times of the product are improved, and further the performance of the product is enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The following drawings of the present invention are used as a part of the present invention to understand the present invention. The embodiments of the present invention are shown in the drawings and their descriptions are used to explain the principles of the present invention.

[0024] In the drawings:

[0025] Figure 1 The flowchart of the manufacturing method of the semiconductor device according to a specific embodiment of the present invention is shown;

[0026] Figures 2A-2F The cross-sectional schematic diagram of the device obtained by successively implementing the manufacturing method of the semiconductor device according to a specific embodiment of the present invention is shown;

[0027] Figure 3 The circuit netlist diagram of the 1T1C unit structure according to a specific embodiment of the present invention is shown;

[0028] Figure 4 The array layout of the 1T1C unit structure according to a specific embodiment of the present invention is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] Next, the present invention will be described more completely with reference to the accompanying drawings, in which embodiments of the present invention are shown. However, the present invention can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0030] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, a first element, component, region, layer or portion discussed below may be denoted as a second element, component, region, layer or portion without departing from the teachings of the present invention.

[0031] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0032] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0033] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention. As such, variations from the shapes as shown, for example due to manufacturing techniques and / or tolerances, are to be expected. Accordingly, embodiments of the invention should not be limited to the particular shapes of regions shown herein, but include shape deviations, for example due to manufacturing. For example, an implantation region shown as rectangular typically has rounded or curved features and / or an implantation concentration gradient at its edges, rather than a binary change from the implantation region to a non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the invention.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be understood as having a meaning that is consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

[0035] To fully understand the present invention, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed by the present invention. The preferred embodiments of the present invention are described in detail below. However, in addition to these detailed descriptions, the present invention may have other embodiments.

[0036] In the related art, adding a tungsten layer on the upper plate of the MIM structure can effectively improve the remanent polarization intensity and the number of read / write cycles of the product. However, after adding the tungsten layer, due to the physical and chemical properties of tungsten itself, it is impossible to etch through the tungsten layer and the MIM structure, ultimately resulting in the inability to form a ferroelectric capacitor. As a result, in the related art, it is impossible to improve the remanent polarization intensity and the number of read / write cycles of the product by adding a tungsten layer, and thus the performance of the product cannot be improved.

[0037] Therefore, in view of the existence of the foregoing technical problems, the present invention provides a method for manufacturing a semiconductor device, as Figure 1 shown, which mainly includes the following steps:

[0038] Step S1, providing a substrate, on which a first interlayer dielectric layer is formed;

[0039] Step S2, sequentially forming a first electrode layer, a ferroelectric dielectric layer, and a second electrode layer on the first interlayer dielectric layer, wherein the second electrode layer includes tungsten;

[0040] Step S3, form a patterned first bottom anti-reflection layer, a first oxide hard mask layer, a first metal hard mask layer, and a second bottom anti-reflection layer on the second electrode layer in sequence;

[0041] Step S4, using the first bottom anti-reflection layer, the first oxide hard mask layer, the first metal hard mask layer, and the second bottom anti-reflection layer as masks, etch the second electrode layer, the ferroelectric dielectric layer, and the first electrode layer to form a ferroelectric capacitor.

[0042] The manufacturing method of the semiconductor device of the present invention forms a second electrode layer including tungsten, and the second electrode layer serves as the upper electrode of the ferroelectric capacitor. By using the first bottom anti-reflection layer, the first oxide hard mask layer, the first metal hard mask layer, and the second bottom anti-reflection layer as masks to etch the second electrode layer, the ferroelectric dielectric layer, and the first electrode layer to form a ferroelectric capacitor, it solves the problem in the related art that a ferroelectric capacitor cannot be formed due to adding a tungsten layer on the upper electrode of the ferroelectric capacitor, thereby improving the remanent polarization intensity and the read / write times of the product, and further enhancing the performance of the product.

[0043] Embodiment 1

[0044] Next, refer to Figures 1 to 2F for a detailed description of the manufacturing method of the semiconductor device of the present invention. Among them, Figure 1 shows a flowchart of the manufacturing method of the semiconductor device according to a specific embodiment of the present invention, Figures 2A-2F shows a cross-sectional schematic diagram of the device obtained by sequentially implementing the manufacturing method of the semiconductor device according to a specific embodiment of the present invention.

[0045] Exemplarily, the manufacturing method of the semiconductor device of the present invention includes the following steps:

[0046] First, execute Step S1, provide a substrate, and form a first interlayer dielectric layer on the substrate.

[0047] The semiconductor device can be any suitable type of device well-known to those skilled in the art. In this embodiment, the technical solution of the present invention is mainly explained and illustrated by taking the case where the semiconductor device is a ferroelectric memory as an example.

[0048] Specifically, as Figures 2A to 2CAs shown, the substrate 200 is a bulk silicon substrate, which can be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors, and also includes multi-layer structures composed of these semiconductors, etc., or is silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanide on insulator (S-SiGeOI), silicon germanide on insulator (SiGeOI), and germanium on insulator (GeOI), etc.

[0049] In one example, as Figure 2C shown, a first interlayer dielectric layer 201 is formed on the substrate 200. Exemplarily, various deposition methods commonly used in the art can be employed to form the first interlayer dielectric layer 201. For example, it can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), etc. Exemplarily, the material of the first interlayer dielectric layer 201 can be an insulating material such as silicon dioxide, fluorocarbon compound, carbon-doped silicon oxide, or silicon carbonitride, etc. This application does not limit this. Exemplarily, after forming the first interlayer dielectric layer 201, it further includes: performing a planarization process on the first interlayer dielectric layer 201. Exemplarily, non-limiting examples of this planarization method include a mechanical planarization method and a chemical mechanical polishing planarization method.

[0050] Next, step S2 is performed to sequentially form a first electrode layer, a ferroelectric dielectric layer, and a second electrode layer on the first interlayer dielectric layer, wherein the second electrode layer includes tungsten. Specifically, as Figure 2C shown, a first electrode layer 202, a ferroelectric dielectric layer 203, and a second electrode layer 204 are sequentially formed on the first interlayer dielectric layer 201, wherein the second electrode layer 204 includes tungsten. Exemplarily, various deposition methods commonly used in the art can be employed to form the first electrode layer 202, the ferroelectric dielectric layer 203, and the second electrode layer 204. For example, it can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), etc. In this embodiment, atomic layer deposition (ALD) is used to form the first electrode layer 202, the ferroelectric dielectric layer 203, and the second electrode layer 204. Exemplarily, the first electrode layer 202 serves as the lower electrode of the finally formed ferroelectric capacitor in subsequent processes, and the second electrode layer 204 serves as the upper electrode of the finally formed ferroelectric capacitor in subsequent processes. Among them, the upper electrode 204 includes tungsten, which can improve the remanent polarization intensity and the number of read / write cycles of the final product, and thus can improve the overall performance of the product.

[0051] In one example, as Figure 2CAs shown, the second electrode layer 204 at least includes a top layer 2041 and a bottom layer 2042 stacked up and down. Among them, the top layer 2041 includes a tungsten layer, and the bottom layer 2042 includes a titanium nitride layer. Exemplarily, the second electrode layer 204 includes a titanium nitride layer and a tungsten layer located on the titanium nitride layer, which can improve the remanent polarization intensity and the number of read / write cycles of the final product, and thus can improve the overall performance of the product. In other embodiments, the second electrode layer 204 may further include other conductive layers located between the top layer 2041 and the bottom layer 2042, and the present application does not limit this. Exemplarily, the thickness range of the top layer 2041 is 1000 - 1700 angstroms. For example, the thickness of the top layer 2041 can be 1000 angstroms, 1100 angstroms, 1200 angstroms, 1300 angstroms, 1400 angstroms, 1500 angstroms, 1550 angstroms, 1600 angstroms, 1700 angstroms, etc. When the top layer 2041 is a tungsten layer, the thickness range of this tungsten layer is 1000 - 1700 angstroms. Exemplarily, the thickness of the bottom layer 2042 is 250 angstroms. When the bottom layer 2042 is a titanium nitride layer, the thickness of this titanium nitride layer is 250 angstroms. In other embodiments, the bottom layer 2042 can also be any other suitable thickness range.

[0052] In one example, the first electrode layer 202 includes titanium nitride, and the ferroelectric dielectric layer 203 includes zirconium-doped hafnium oxide. Exemplarily, zirconium-doped hafnium oxide (HZO, Hf 1-x Zr x O 2 ) is an extension of hafnium oxide (HfO)-based ferroelectric materials and is a new type of ferroelectric material. Compared with traditional ferroelectric materials, the Hf 1-x Zr x O 2 in HfO 2 (hafnium dioxide) and ZrO 2 (zirconium dioxide), which have been applied to the gate oxide of MOSFET (metal-oxide-semiconductor field-effect transistor) and the dielectric layer of DRAM (dynamic random access memory), so the HZO ferroelectric material can be well compatible with the CMOS (complementary metal-oxide-semiconductor) process. At the same time, it can also show strong ferroelectricity at an ultra-thin thickness of about 10 nm and has excellent scalability. In addition, based on the ultra-thin thickness, Hf 1-x Zr x O 2 also shows significant advantages in terms of ferroelectricity and erase / write speed. Exemplarily, the thickness of the first electrode layer 202 is 250 angstroms, and the thickness range of the ferroelectric dielectric layer 203 is 6 - 10 nm. For example, the thickness of the ferroelectric dielectric layer 203 can be 6 nm, 7 nm, 7.5 nm, 8 nm, 9 nm, 10 nm, etc. In other embodiments, the first electrode layer 202 and the ferroelectric dielectric layer 203 can also be any other suitable thickness range.

[0053] Next, step S3 is performed to sequentially form a patterned first bottom anti-reflection layer, a first oxide hard mask layer, a first metal hard mask layer, and a second bottom anti-reflection layer on the second electrode layer. Figure 2D As shown, a patterned first bottom anti-reflection layer 205 , a first oxide hard mask layer 206 , a first metal hard mask layer 207 and a second bottom anti-reflection layer 208 are sequentially formed on the second electrode layer 204 .

[0054] In one example, if Figure 2C and Figure 2D As shown, a patterned first bottom anti-reflection layer 205, a first oxide hard mask layer 206, a first metal hard mask layer 207, and a second bottom anti-reflection layer 208 are sequentially formed on the second electrode layer 204, including: sequentially forming a first bottom anti-reflection layer 205, a first oxide hard mask layer 206, a first metal hard mask layer 207, a second bottom anti-reflection layer 208, and a patterned photoresist layer 209 on the second electrode layer; sequentially etching the second bottom anti-reflection layer 208, the first metal hard mask layer 207, the first oxide hard mask layer 206, and the first bottom anti-reflection layer 205 using the patterned photoresist layer 209 as a mask to obtain a patterned first bottom anti-reflection layer 205, a first oxide hard mask layer 206, a first metal hard mask layer 207, and a second bottom anti-reflection layer 208. Exemplarily, the area covered by the patterned photoresist layer 209 is the area where a ferroelectric capacitor is predetermined to be formed in a subsequent process. By way of example, various deposition methods commonly used in the art may be used to form the first bottom anti-reflection layer 205, the first oxide hard mask layer 206, the first metal hard mask layer 207, and the second bottom anti-reflection layer 208, for example, they may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). By way of example, dry etching may be used in this step, including but not limited to etching processes such as reactive ion etching (RIE), ion beam etching, and plasma etching.

[0055] In one example, the first bottom anti-reflective layer 205 and the second bottom anti-reflective layer 208 include silicon oxynitride, the first metal hard mask layer 207 includes titanium nitride, and the first oxide hard mask layer 206 is formed by oxygen ion deposition, for example, the first oxide hard mask layer 206 can be formed by physical vapor deposition (PVD).

[0056] In one example, the thickness of the first bottom antireflection layer 205 ranges from 400 to 600 angstroms. For example, the thickness of the first bottom antireflection layer 205 can be 400 angstroms, 500 angstroms, 550 angstroms, 600 angstroms, etc.; the thickness of the first oxide hard mask layer 206 ranges from 100 to 200 angstroms. For example, the thickness of the first oxide hard mask layer 206 can be 100 angstroms, 150 angstroms, 180 angstroms, 200 angstroms, etc.; the thickness of the first metal hard mask layer 207 ranges from 400 to 600 angstroms. For example, the thickness of the first metal hard mask layer 207 can be 400 angstroms, 450 angstroms, 500 angstroms, 600 angstroms, etc.; the thickness of the second bottom antireflection layer 208 ranges from 300 to 350 angstroms. For example, the thickness of the second bottom antireflection layer 208 can be 300 angstroms, 310 angstroms, 320 angstroms, 330 angstroms, 340 angstroms, 350 angstroms, etc. Exemplarily, taking the thickness of the first metal hard mask layer 207 as 500 angstroms as an example, the first metal hard mask layer 207 with a thickness of 250 angstroms can be deposited twice to stack and form the first metal hard mask layer 207 with a thickness of 500 angstroms.

[0057] In one example, when the top layer of the second electrode layer 204 includes a tungsten layer, first forming the first bottom antireflection layer 205 and the first oxide hard mask layer 206 on the second electrode layer 204 can help relieve the stress of the second electrode layer 204, which is beneficial to improving the performance of the finally formed ferroelectric capacitor. Secondly, when subsequently etching the second electrode layer 204, the ferroelectric dielectric layer 203 and the first electrode layer 202 to form a ferroelectric capacitor with the patterned first bottom antireflection layer 205, the first oxide hard mask layer 206, the first metal hard mask layer 207 and the second bottom antireflection layer 208 as masks, the patterned first bottom antireflection layer 205, the first oxide hard mask layer 206, the first metal hard mask layer 207 and the second bottom antireflection layer 208 will also be etched away. Among them, the first metal hard mask layer 207 mainly plays a role in preventing the ferroelectric capacitor from being etched and damaged. Therefore, the thickness of the first metal hard mask layer 207 is generally selected to be 400 - 600 angstroms. An overly thin first metal hard mask layer 207 will cause the ferroelectric capacitor to be etched and damaged. In addition, the second bottom antireflection layer 208 is used to reduce the reflection of light in the photolithography process and facilitate steps such as coating and developing in the photolithography process.

[0058] Finally, perform step S4, and use the first bottom antireflection layer, the first oxide hard mask layer, the first metal hard mask layer and the second bottom antireflection layer as masks to etch the second electrode layer, the ferroelectric dielectric layer and the first electrode layer to form a ferroelectric capacitor. Specifically, as Figure 2EAs shown, using the patterned first bottom anti-reflection layer 205, the first oxide hard mask layer 206, the first metal hard mask layer 207, and the second bottom anti-reflection layer 208 as masks, the second electrode layer 204, the ferroelectric dielectric layer 203, and the first electrode layer 202 are etched to form a ferroelectric capacitor. Exemplarily, dry etching can be selected in this step, including but not limited to etching processes such as reactive ion etching (RIE), ion beam etching, and plasma etching.

[0059] The various embodiments of the method for manufacturing a semiconductor device of the present application have been described above by way of example. The following is an embodiment of a combination of the above embodiments. Specifically, as Figures 2C to 2D shown, first, using the patterned photoresist layer 209 as a mask, the second bottom anti-reflection layer 208, the first metal hard mask layer 207, the first oxide hard mask layer 206, and the first bottom anti-reflection layer 205 are etched in sequence to obtain the patterned first bottom anti-reflection layer 205, the first oxide hard mask layer 206, the first metal hard mask layer 207, and the second bottom anti-reflection layer 208; then, using the patterned first bottom anti-reflection layer 205, the first oxide hard mask layer 206, the first metal hard mask layer 207, and the second bottom anti-reflection layer 208 as masks, the second electrode layer 204, the ferroelectric dielectric layer 203, and the first electrode layer 202 are etched to form a ferroelectric capacitor. Among them, the second electrode layer 204 at least includes a top layer 2041 and a bottom layer 2042 stacked up and down. The top layer 2041 includes a tungsten layer, and the bottom layer 2042 includes a titanium nitride layer. Then, etching the second electrode layer 204, the ferroelectric dielectric layer 203, and the first electrode layer 202 to form a ferroelectric capacitor may further include the following steps: First, etch the top layer 2041 of the second electrode layer 204; then etch the bottom layer 2042 of the second electrode layer 204, the ferroelectric dielectric layer 203, and the first electrode layer 202 to form a ferroelectric capacitor. Exemplarily, dry etching can be selected in this step, including but not limited to etching processes such as reactive ion etching (RIE), ion beam etching, and plasma etching.

[0060] In one example, as Figures 2A to 2D shown, it further includes a transistor formed on the substrate 200. The first interlayer dielectric layer 201 covers the transistor, and a first conductive plug 210 is formed in the first interlayer dielectric layer 201 to electrically connect the transistor and the ferroelectric capacitor. Exemplarily, as Figure 2A shown, it further includes a shallow trench isolation structure 211.

[0061] Specifically, as Figures 2A to 2CAs shown, the transistor includes a gate structure 212, a source region 213, and a drain region 214. The gate structure 212 includes a polysilicon gate layer and a gate dielectric layer, and the gate dielectric layer plays an isolation and protection role. Exemplarily, the gate structure 212 may further include sidewalls located on both sides of the polysilicon gate layer. Exemplarily, a self-aligned silicide layer is further formed on the gate structure 212, the source region 213, and the drain region 214.

[0062] In one example, as Figures 2A to 2C shown, a second interlayer dielectric layer 215 is further formed between the first interlayer dielectric layer 201 and the substrate 200. Exemplarily, various deposition methods commonly used in the art can be employed to form the second interlayer dielectric layer 215. For example, it can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. Exemplarily, the material of the second interlayer dielectric layer 215 can be an insulating material such as silicon dioxide, fluorocarbon compound, carbon-doped silicon oxide, or silicon carbonitride, and the present application does not limit this. Exemplarily, after forming the second interlayer dielectric layer 215, it further includes: planarizing the second interlayer dielectric layer 215. Exemplarily, non-limiting examples of this planarization method include a mechanical planarization method and a chemical mechanical polishing planarization method.

[0063] In one example, as Figures 2A to 2C shown, a first conductive layer 216 and a second conductive layer 217 are further formed in the first interlayer dielectric layer 201, and a second conductive plug 218 and a third conductive plug 219 are further formed in the second interlayer dielectric layer 215. Among them, the second conductive plug 218 electrically connects the first conductive layer 216 and the drain region 214 of the transistor, and the third conductive plug 219 electrically connects the second conductive layer 217 and the source region 213 of the transistor. Then, the ferroelectric capacitor can be electrically connected to the source region 213 of the transistor through the first conductive plug 210, the second conductive layer 217, and the third conductive plug 219.

[0064] In one example, as Figure 2FAs shown, after forming the ferroelectric capacitor, the method further includes: forming a third interlayer dielectric layer 220 that covers the first interlayer dielectric layer 201 and the ferroelectric capacitor; forming a fourth conductive plug 221 in the third interlayer dielectric layer 220; forming a third conductive layer 222 on the third interlayer dielectric layer 220, where the fourth conductive plug 221 electrically connects the third conductive layer 222 and the ferroelectric capacitor. Exemplarily, after forming the third interlayer dielectric layer 220, the method further includes: planarizing the third interlayer dielectric layer 220. Exemplarily, non-limiting examples of the planarization method include a mechanical planarization method and a chemical mechanical polishing planarization method. Exemplarily, after forming the third interlayer dielectric layer 220, the method further includes: performing an annealing process to activate the ferroelectric properties of the ferroelectric dielectric layer 203 in the ferroelectric capacitor.

[0065] In one example, the transistor and the ferroelectric capacitor can jointly form a 1T1C (1 Transistor - 1 Capacitor) cell structure. Among them, the polysilicon gate layer in the gate structure 212 of the transistor serves as the word line (WL, World Line), the first conductive layer 216 serves as the bit line (BL, Bit Line), and the third conductive layer 222 serves as the plate line (PL, PlateLine). The circuit netlist diagram and the array layout of the 1T1C cell structure are respectively as Figure 3 shown in Figure 4 Exemplarily, the ferroelectric capacitor is gated by controlling the WL, and the BL and PL apply positive and negative voltage to the ferroelectric capacitor respectively. Since the middle ferroelectric dielectric layer 203 has ferroelectric properties and forms different ferrodomains (polarizations) in the positive and negative electric field cases, these ferrodomains will not disappear with the cancellation of the external electric field, so that the ferroelectric capacitor stores different charges and realizes the storage function.

[0066] So far, the key steps of the preparation method of the semiconductor device of the present invention have been described. For the complete preparation of the semiconductor device, other steps may also be included, which will not be elaborated here one by one.

[0067] It is worth mentioning that the above steps are only examples, and on the premise of no conflict, the order of the above steps can be adjusted.

[0068] In summary, in the preparation method of the semiconductor device of the present invention, the formed second electrode layer includes tungsten, and the second electrode layer serves as the upper electrode of the ferroelectric capacitor. By using the first bottom antireflection layer, the first oxide hard mask layer, the first metal hard mask layer, and the second bottom antireflection layer as masks to etch the second electrode layer, the ferroelectric dielectric layer, and the first electrode layer to form the ferroelectric capacitor, the problem in the related technology that the ferroelectric capacitor cannot be formed due to adding a tungsten layer on the upper electrode of the ferroelectric capacitor is solved, thereby improving the remanent polarization intensity and the read / write times of the product, and further enhancing the performance of the product.

[0069] Example Two

[0070] The present invention further provides a semiconductor device, which is obtained by the method in the foregoing Example One. Specifically, as Figure 2F shown, the semiconductor device includes a substrate 200, a first interlayer dielectric layer 201 on the substrate 200, and a first electrode layer 202, a ferroelectric dielectric layer 203, and a second electrode layer 204 on the first interlayer dielectric layer 201. The first electrode layer 202, the ferroelectric dielectric layer 203, and the second electrode layer 204 together form a ferroelectric capacitor, wherein the second electrode layer 204 includes tungsten.

[0071] In one example, the substrate 200 is a bulk silicon substrate, which may be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors, and also includes multilayer structures composed of these semiconductors, etc., or is silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanide on insulator (S-SiGeOI), silicon germanide on insulator (SiGeOI), and germanium on insulator (GeOI), etc.

[0072] So far, the introduction of the structure of the semiconductor device of the present invention has been completed. For a complete device, there may also be other component structures, which will not be elaborated one by one here.

[0073] Due to the semiconductor device of the present invention, the second electrode layer includes tungsten, and the second electrode layer serves as the upper electrode of the ferroelectric capacitor, thereby improving the remanent polarization intensity and the read / write times of the product, and further enhancing the performance of the product.

[0074] Example Three

[0075] The present invention further provides an electronic device, which includes the semiconductor device described in Example Two or the semiconductor device prepared by the method described in Example One.

[0076] The electronic device may be any electronic product or device such as a mobile phone, a tablet computer, a notebook computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, etc., or may be an intermediate product having the above semiconductor device, for example: a mobile phone motherboard having the integrated circuit, etc. The electronic device according to the embodiment of the present invention has better performance due to the use of the above semiconductor device.

[0077] Although multiple embodiments are described herein, it should be understood that those skilled in the art can conceive of many other modifications and embodiments, all of which will fall within the spirit and scope of the inventive concept disclosed. More particularly, various modifications and changes can be made in the arrangement and / or components of the combination of the subject matter within the scope of the present disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative means will also be an obvious choice for those skilled in the art.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, the method includes: providing a substrate, on which a first interlayer dielectric layer is formed; successively forming a first electrode layer, a ferroelectric dielectric layer, and a second electrode layer on the first interlayer dielectric layer, wherein the second electrode layer includes tungsten; successively forming a patterned first bottom antireflection layer, a first oxide hard mask layer, a first metal hard mask layer, and a second bottom antireflection layer on the second electrode layer; using the first bottom antireflection layer, the first oxide hard mask layer, the first metal hard mask layer, and the second bottom antireflection layer as masks to etch the second electrode layer, the ferroelectric dielectric layer, and the first electrode layer to form a ferroelectric capacitor.

2. The manufacturing method according to claim 1, characterized in that, the first bottom antireflection layer and the second bottom antireflection layer include silicon oxynitride, and the first metal hard mask layer includes titanium nitride.

3. The manufacturing method according to claim 1, characterized in that, the thickness range of the first bottom antireflection layer is 400 - 600 angstroms, the thickness range of the first oxide hard mask layer is 100 - 200 angstroms, the thickness range of the first metal hard mask layer is 400 - 600 angstroms, and the thickness range of the second bottom antireflection layer is 300 - 350 angstroms.

4. The manufacturing method according to claim 1, characterized in that, the second electrode layer at least includes a top layer and a bottom layer stacked on top of each other, wherein the top layer includes a tungsten layer and the bottom layer includes a titanium nitride layer.

5. The manufacturing method according to claim 4, characterized in that, the thickness range of the top layer is 1000 - 1700 angstroms.

6. The manufacturing method according to claim 1, characterized in that, the successively forming a patterned first bottom antireflection layer, a first oxide hard mask layer, a first metal hard mask layer, and a second bottom antireflection layer on the second electrode layer includes: successively forming a first bottom antireflection layer, a first oxide hard mask layer, a first metal hard mask layer, a second bottom antireflection layer, and a patterned photoresist layer on the second electrode layer; using the patterned photoresist layer as a mask to successively etch the second bottom antireflection layer, the first metal hard mask layer, the first oxide hard mask layer, and the first bottom antireflection layer.

7. The manufacturing method according to claim 1 further includes a transistor formed on the substrate, the first interlayer dielectric layer covers the transistor, and a first conductive plug is formed in the first interlayer dielectric layer to electrically connect the transistor and the ferroelectric capacitor.

8. The manufacturing method according to claim 1, characterized in that, the first electrode layer includes titanium nitride, and the ferroelectric dielectric layer includes zirconium-doped hafnium oxide.

9. A semiconductor device, characterized in that, the semiconductor device is obtained by using the method described in any one of claims 1 - 8.

10. An electronic device, characterized in that, the electronic device includes the semiconductor device described in claim 9.

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