Three-dimensional stacked memory and manufacturing method thereof
By introducing tungsten plugs into the three-dimensional stacked memory, a substructure stacked with the memory cells is formed, and contacting the tungsten plugs through the signal line, the thermal interference problem between each memory cell in the memory is solved, and the reliability of the memory and the accuracy of data reading are improved.
Patent Information
- Application Number
- CN202510220529.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-26
- Publication Date
- 2025-05-30
AI Technical Summary
The thermal interference problem between each memory cell in three-dimensional stacking memory leads to low reliability of the memory.
By introducing a tungsten plug into the memory, a substructure stacked with the memory cell is formed and contacted with the tungsten plug through the signal line, thermal interference is reduced using the low resistance of the tungsten plug.
It effectively reduces thermal interference between each memory cell in the memory, improves the reliability of the memory and the accuracy of data reading.
Smart Images
Figure CN120076340A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and particularly to a three-dimensional stacked memory and a manufacturing method thereof. Background Art
[0002] With the development of information technology, the market demand for memories not only focuses on increasing the capacity, but also requires higher performance and smaller size.
[0003] Currently, a three-dimensional stacked structure in which multiple memory cells are stacked vertically is usually adopted in a memory to improve the storage density of the memory, so as to increase the storage capacity without increasing the chip area. However, heat is generated during the operation of the memory cells. In a high-density memory using a three-dimensional stacked structure, due to the very small spacing between the memory cells, the heat generated by the memory cells will cause obvious thermal interference to adjacent memory cells, affecting the accuracy of data and resulting in low reliability of the memory.
[0004] Therefore, how to suppress the thermal interference between the memory cells in a three-dimensional stacked memory has become a problem to be solved. Summary of the Invention
[0005] Based on the above problems, the present application provides a three-dimensional stacked memory and a manufacturing method thereof, which can reduce the thermal interference between the memory cells in the three-dimensional stacked memory.
[0006] The embodiments of the present application disclose the following technical solutions:
[0007] In a first aspect, an embodiment of the present application provides a three-dimensional stacked memory, which includes: memory cells, tungsten plugs, a first signal line, and a second signal line;
[0008] The memory cells are stacked with the tungsten plugs to form a sub-structure; the sub-structure is located in the cross region of the first signal line and the second signal line;
[0009] The sub-structure includes a first sub-structure and a second sub-structure adjacent along the extending direction of the first signal line and / or along the extending direction of the second signal line; the first sub-structure includes a first memory cell and a second tungsten plug, and the second sub-structure includes a second memory cell and a first tungsten plug;
[0010] The first memory cell is in contact with the first signal line, and the second tungsten plug is in contact with the second signal line; the second memory cell is in contact with the second signal line, and the first tungsten plug is in contact with the first signal line.
[0011] Optionally, the memory further includes a filling layer; the filling layer is filled between adjacent sub-structures.
[0012] Optionally, the memory further includes a spacer layer; the spacer layer covers the sidewalls of the tungsten plugs.
[0013] Optionally, in the first sub-structure, one side of the spacer layer contacts the first storage unit and the other side contacts the second signal line; in the second sub-structure, one side of the spacer layer contacts the second storage unit and the other side contacts the first signal line.
[0014] Optionally, in the extending direction of the second signal line, the size of the first storage unit is greater than or equal to the size of the corresponding second tungsten plug and less than or equal to the sum of the sizes of the corresponding second tungsten plug and the spacer layer; the size of the second storage unit is greater than or equal to the size of the corresponding first tungsten plug and less than or equal to the sum of the sizes of the corresponding first tungsten plug and the spacer layer.
[0015] Optionally, in the extending direction of the first signal line, the size of the first storage unit is greater than or equal to the size of the corresponding second tungsten plug, and the size of the second storage unit is greater than or equal to the size of the corresponding first tungsten plug.
[0016] In a second aspect, an embodiment of the present application provides a method for manufacturing a three-dimensional stacked memory, the method including:
[0017] Deposit a first signal line material and a storage material in sequence to form a first signal line layer and a first storage layer;
[0018] Etch the first signal line layer and the first storage layer to form a plurality of first signal lines and a plurality of first storage units located on a first side of the first signal lines; deposit a first tungsten plug between adjacent first storage units; the first tungsten plug is spaced apart from the first storage units;
[0019] Deposit a second storage layer on a side of the first storage units and the first tungsten plugs facing away from the first signal lines;
[0020] Etch the second storage layer to form second storage units stacked with the first tungsten plugs;
[0021] Deposit a second tungsten plug between adjacent second storage units; the second tungsten plug is spaced apart from the second storage units and stacked with the first storage units;
[0022] Deposit a second signal line layer on a side of the second storage units and the second tungsten plugs facing away from the first signal lines;
[0023] Etch the second signal line layer to obtain second signal lines in contact with the second storage units and the second tungsten plugs; the projection of the second signal lines on the first signal line layer intersects with the first signal lines.
[0024] Optionally, etching the first signal line layer and the first storage layer to form a plurality of first signal lines and a plurality of first storage units located on a first side of the first signal lines includes:
[0025] Etching the first signal line layer and the first storage layer to form a plurality of first signal lines and a first sub-storage layer stacked with the first signal lines;
[0026] Etching the first sub-storage layer to form a plurality of first storage units located on the first side of the first signal lines; the first storage units corresponding to adjacent first signal boxes are arranged in a staggered manner.
[0027] Optionally, after etching the first signal line layer and the first storage layer to form a plurality of first signal lines and a first sub-storage layer stacked with the first signal lines, the method further includes:
[0028] Depositing a first filling layer filled between the stacked structures of the plurality of first signal lines and the first sub-storage layer;
[0029] Depositing a first spacer layer covering the side walls of the grooves between the plurality of first storage units.
[0030] Optionally, depositing a first tungsten plug between adjacent first storage units includes:
[0031] Depositing a tungsten layer on the first side of the first signal line;
[0032] Performing chemical mechanical polishing on the tungsten layer to remove the tungsten layer covering the surfaces of the first storage units, the first spacer layer, and the first filling layer, and retaining the tungsten layer in the grooves of the first spacer layer to form a first tungsten plug.
[0033] Compared with the prior art, the present application has the following beneficial effects:
[0034] An embodiment of the present application provides a three-dimensional stacked memory. The memory includes: memory cells, tungsten plugs, a first signal line, and a second signal line; the memory cells and the tungsten plugs are stacked to form a sub-structure; the sub-structure is located in the intersection area of the first signal line and the second signal line; the sub-structure includes a first sub-structure and a second sub-structure adjacent along the extending direction of the first signal line and / or along the extending direction of the second signal line; the first sub-structure includes a first memory cell and a second tungsten plug, and the second sub-structure includes a second memory cell and a first tungsten plug; the first memory cell is in contact with the first signal line, and the second tungsten plug is in contact with the second signal line; the second memory cell is in contact with the second signal line, and the first tungsten plug is in contact with the first signal line. Thus, each memory cell is adjacent to a tungsten plug. Since the resistance of the tungsten plug is more than 100 times smaller than that of the memory cell, according to the Joule heat generation principle, under the same current, the heat generation of the tungsten plug is more than 100 times smaller than that of the memory cell, thereby avoiding direct thermal interference between the memory cells in the memory and improving the reliability of the memory and the accuracy of the data read from the memory cells. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0036] Figure 1 It is a three-dimensional structure schematic diagram of a three-dimensional stacked memory provided by an embodiment of the present application;
[0037] Figure 2 It is a schematic diagram of the distance between adjacent sub-structures provided by an embodiment of the present application;
[0038] Figure 3 It is a schematic diagram of the distance between the memory cell and the tungsten plug between adjacent sub-structures provided by an embodiment of the present application;
[0039] Figure 4 It is a cross-sectional view of a three-dimensional stacked memory provided by an embodiment of the present application;
[0040] Figure 5 It is a flowchart of a manufacturing method of a three-dimensional stacked memory provided by an embodiment of the present application;
[0041] Figure 6 It is a three-dimensional structure schematic diagram of a bit line layer and a first memory layer provided by an embodiment of the present application;
[0042] Figure 7Schematic diagram of a three-dimensional structure of a bit line and a first sub-storage layer provided by an embodiment of the present application;
[0043] Figure 8 Three-dimensional structure diagram and cross-sectional view of a first storage cell provided by an embodiment of the present application;
[0044] Figure 9 Cross-sectional view of a manufacturing process of a first spacer layer provided by an embodiment of the present application;
[0045] Figure 10 Cross-sectional view of a manufacturing process of a first tungsten plug provided by an embodiment of the present application;
[0046] Figure 11 Schematic diagram of a three-dimensional structure of a first tungsten plug provided by an embodiment of the present application;
[0047] Figure 12 Schematic diagram of a three-dimensional structure of a manufacturing process of a second storage cell provided by an embodiment of the present application;
[0048] Figure 13 Cross-sectional view of a manufacturing process of a second spacer layer provided by an embodiment of the present application;
[0049] Figure 14 Cross-sectional view of a manufacturing process of a second tungsten plug provided by an embodiment of the present application;
[0050] Figure 15 Schematic diagram of a three-dimensional structure of a second tungsten plug provided by an embodiment of the present application;
[0051] Figure 16 Schematic diagram of a three-dimensional structure of a word line layer provided by an embodiment of the present application;
[0052] Figure 17 Schematic diagram of a three-dimensional structure of a word line provided by an embodiment of the present application. Detailed implementation manners
[0053] A three-dimensional stacked memory and a manufacturing method thereof provided by the present application can be used in the semiconductor field. The above is only an example and does not limit the application field of a three-dimensional stacked memory and a manufacturing method thereof provided by the present application.
[0054] Terms such as "first", "second", "third", and "fourth" in the specification, claims, and drawings of the present application are used to distinguish different objects, rather than to limit a specific order.
[0055] In the embodiments of the present application, words such as "as an example" or "for example" are used to represent examples, illustrations or explanations. Any embodiment or design described as "as an example" or "for example" in the embodiments of the present application should not be construed as being more preferred or advantageous than other embodiments or designs. Rather, the use of words such as "as an example" or "for example" is intended to present the relevant concepts in a specific manner.
[0056] The terms used in the embodiments section of the present application are only used to explain the specific embodiments of the present application and are not intended to limit the present application.
[0057] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application.
[0058] See Figure 1 , which is a schematic three-dimensional structure diagram of a three-dimensional stacked memory provided by an embodiment of the present application. The memory includes, but is not limited to, 3D PCM (Phase Change Memory), SOM (Selector Only Memory), NAND, DRAM, etc., and the embodiments of the present application do not limit this. The memory includes: a storage unit 100 (cell), a tungsten plug 200 (W contact), a first signal line 300, and a second signal line 400.
[0059] Among them, the first signal line 300 can be a bit line (Bit Line, BL) or a word line (Word Line, WL); correspondingly, the second signal line can be a word line or a bit line. In the following embodiments of the present application, the first signal line 300 is taken as a bit line and the second signal line 400 is taken as a word line for description.
[0060] The storage unit 100 and the tungsten plug 200 are stacked to form a sub-structure 120; the sub-structure 120 is located in the cross region of the bit line 300 and the word line 400.
[0061] The sub-structure 120 includes a first sub-structure 121 and a second sub-structure 122 adjacent along the extending direction of the bit line 300 and / or along the extending direction of the word line 400; the first sub-structure 121 includes a first storage unit 101 and a second tungsten plug 202, and the second sub-structure 122 includes a second storage unit 102 and a first tungsten plug 201.
[0062] The first storage unit 101 is in contact with the bit line 300, and the second tungsten plug 202 is in contact with the word line 400; the second storage unit 102 is in contact with the word line 400, and the first tungsten plug 201 is in contact with the bit line 300.
[0063] Thus, in the embodiments of the present application, each storage unit 100 is adjacent to a tungsten plug 200. Since the resistance of the tungsten plug 200 is more than 100 times smaller than that of the storage unit 100, according to the Joule heat generation principle, under the same current, the heat generation of the tungsten plug 200 is more than 100 times smaller than that of the storage unit 100, thereby avoiding direct thermal interference between the storage units 100 in the memory and improving the reliability of the memory and the accuracy of the data read from the storage unit 100.
[0064] See Figure 2 , in some embodiments, for storage units adjacent in the projection on the horizontal plane and in different horizontal planes in the vertical direction, direct thermal interference between the storage units 100 in the memory can be avoided, which enables the distance between the sub-structures 120 to be reduced. For example, in the extending direction of the word line and / or the bit line, the size ratio of the length of the storage unit 100 to the distance between adjacent sub-structures 120 can be reduced from 1:3 to 1:2 or even smaller, thereby improving the storage density of the memory on the premise of ensuring the reliability of the memory.
[0065] See Figure 3 , in some embodiments, by adjusting the size of the tungsten plug 200, such as reducing the size of the tungsten plug, the distance between the storage unit 100 and the tungsten plug 200 between adjacent sub-structures 120 can be increased, thereby obtaining more lenient process control requirements, reducing the manufacturing difficulty, and being beneficial to improving the yield and performance of the memory.
[0066] See Figure 4 , this figure is a cross-sectional view of a three-dimensional stacked memory provided by the embodiments of the present application. Among them, a filling layer 500 is filled between adjacent sub-structures 120 to fill the gap between adjacent sub-structures 120 and prevent voids or cracks from appearing inside the memory and affecting the reliability of the memory.
[0067] Optionally, the side wall of the tungsten plug may also be covered with a spacer layer 600. In the first sub-structure 121, one side of the spacer layer 600 contacts the first storage unit 101, and the other side contacts the word line 400; in the second sub-structure 122, one side of the spacer layer 600 contacts the second storage unit 102, and the other side contacts the bit line 300.
[0068] Thus, the spacer layer 600 can separate adjacent conductive paths on the same bit line 300, provide a physical distance between adjacent conductive paths, and reduce the interference between parasitic capacitance and electrical signals.
[0069] Among them, in the extending direction of the second signal line 400, the size of the first storage unit 101 is greater than or equal to the size of the corresponding second tungsten plug 202, and less than or equal to the sum of the size of the corresponding second tungsten plug 202 and the spacer layer 600; the size of the second storage unit 102 is greater than or equal to the size of the corresponding first tungsten plug 201, and less than or equal to the sum of the size of the corresponding first tungsten plug 201 and the spacer layer 600.
[0070] In the extending direction of the first signal line 300, the size of the first storage unit 101 is greater than or equal to the size of the corresponding second tungsten plug 202, and the size of the second storage unit 102 is greater than or equal to the size of the corresponding first tungsten plug 201.
[0071] See Figure 5 , which is a flowchart of a manufacturing method of a three-dimensional stacked memory provided by an embodiment of the present application. The method includes:
[0072] S501: Deposit a first signal line material and a storage material in sequence to form a first signal line layer and a first storage layer as shown in Figure 6 .
[0073] As an example, the first signal line material can be a low-resistance metal material such as aluminum, titanium, copper, or an aluminum-copper alloy; the storage material can be flexibly selected based on the type of the memory. For example, hafnium oxide (HfO 2 ), tantalum oxide (Ta 2 O 5 ) or amorphous silicon and other dielectric materials can be selected as the storage material of the resistive random access memory RRAM, and a phase change material such as germanium antimony telluride alloy (Ge2Sb2Te5, GST) that can quickly convert the phase state can be selected as the storage material of the phase change random access memory PRAM.
[0074] Among them, the first signal line material can be deposited on the surface of a wafer having transistors and / or other underlying structures.
[0075] S502: Etch the first signal line layer and the first storage layer to form a plurality of first signal lines 300 and a plurality of first storage units 101 located on the first side of the first signal lines 300.
[0076] Among them, the first signal line can be a bit line or a word line, and the first signal line layer can be a bit line layer or a word line layer. In the embodiment of the present application, the first signal line layer is taken as the bit line layer and the first signal line is taken as the bit line for description.
[0077] Specifically, based on a predefined pattern, the bit line layer and the first storage layer can be selectively etched, and the unnecessary parts in the bit line layer and the first storage layer can be removed through an etching process to form the bit lines 300 and the first sub-storage layer stacked with the bit lines, as shown inFigure 7 As shown. For example, a mask layer may be formed on a surface of the first storage layer facing away from the bit line layer, the mask layer covering a formation region of the bit line 300. By dry etching or wet etching, the bit line layer and the first storage layer in a region not covered by the mask layer are removed, and thus the bit line 300 and the first sub-storage layer can be obtained.
[0078] Then, the first sub-storage layer is etched to form a plurality of first storage units, as Figure 8 shown in (a). Among them, the first storage units 101 corresponding to adjacent bit lines 300 are arranged in a staggered manner. Specifically, a mask layer covering the surface of the first storage unit 101 in contact with the bit line 300 may be formed, and then through an etching process, the first sub-storage layer in a region not covered by the mask layer is removed, and thus a plurality of first storage units 101 can be obtained. Refer to Figure 8 (b), where A is a cross-sectional view corresponding to AA marked in Figure 8 (a), and B is a cross-sectional view corresponding to BB marked in Figure 8 (a).
[0079] Optionally, after forming the bit line 300 and the first sub-storage layer as Figure 7 shown, a first filling layer 501 filling between a stacked structure of a plurality of bit lines 300 and the first sub-storage layer may be deposited, filling voids left after etching, and a chemical mechanical polishing (CMP) process is used to planarize the surface to ensure uniformity and consistency in subsequent steps.
[0080] Optionally, as Figure 9 shown, after forming a plurality of first storage units 101, a first spacer layer 601 covering sidewalls of grooves between the plurality of first storage units 101 may also be deposited. Specifically, a spacer layer material may be first deposited on a side of the structure after forming the first storage units 101 facing away from the bit line 300, as Figure 9 shown in (a); then, through self-aligned etching or etching the spacer layer material after forming a mask layer, a first spacer layer 601 covering sidewalls of grooves between the plurality of first storage units 101 is formed, as Figure 9 shown in (b).
[0081] S503: Deposit and form a first tungsten plug 201 between adjacent first storage units 101.
[0082] Specifically, refer to Figure 10 , tungsten may be first deposited on a side of the structure obtained after performing step S502 facing away from the bit line 300 to form a tungsten layer, as Figure 10As shown in (a); then, chemical mechanical polishing (CMP) is performed on the tungsten layer to remove the tungsten layer covering the surfaces of the first storage unit 101, the first spacer layer 601, and the first filling layer 501, and only the tungsten layer in the contact area with the bit line 300 is retained to form the first tungsten plug 201, as Figure 10 shown in (b). The three-dimensional structure diagram of the structure after forming the first tungsten plug 201 is shown in Figure 11 , and the first tungsten plug 201 is arranged at an interval from the first storage unit 101.
[0083] S504: A second storage layer is deposited and formed on the side of the first storage unit 101 and the first tungsten plug 201 facing away from the first signal line 300.
[0084] Referring to Figure 12 , the storage layer material can be deposited on the side of the structure obtained after performing step S503 facing away from the bit line 300 to form the second storage layer, as Figure 12 shown in (a).
[0085] S505: The second storage layer is etched to form a plurality of second storage units 102 on the side of the first tungsten plug 301 facing away from the first signal line 300.
[0086] As an example, referring to Figure 12 , the second storage layer is etched to remove the second storage layer in the contact area with the first filling layer 501 to form a second sub-storage layer stacked with the bit line, the first storage unit 101, and the first tungsten plug 201, as Figure 12 shown in (b); then, the filling layer material can be deposited to fill the gaps between the plurality of second sub-storage layers to form the second filling layer 502, and the first filling layer 501 and the second filling layer 502 form the filling layer 500, as Figure 12 shown in (c); finally, the second sub-storage layer is etched to form a plurality of second storage units 102 on the side of the first tungsten plug 201 facing away from the bit line 300, as Figure 12 shown in (d). Among them, the second storage units 102 corresponding to adjacent bit lines 300 are arranged in a staggered manner, and the first storage units 101 and the second storage units 102 corresponding to the same bit line 300 are arranged in a staggered manner.
[0087] Optionally, as Figure 13 shown, after forming the plurality of second storage units 102, a second spacer layer 602 can also be deposited and formed on the side walls of the grooves between the plurality of second storage units 102. Specifically, the spacer layer material can be deposited on the side of the structure after forming the second storage units 102 facing away from the bit line 300 first, as Figure 13 shown in (a); then, the second spacer layer 602 covering the side walls of the grooves between the plurality of second storage units 102 can be formed by self-aligned etching or etching the spacer layer material after forming a mask layer, asFigure 13 As shown in (b), the first spacer layer 601 and the second spacer layer 602 constitute the spacer layer 600.
[0088] S506 : forming a second tungsten plug 202 by deposition between adjacent second storage units 102 .
[0089] Specifically, see Figure 14 , metal tungsten may be deposited again on the side of the structure obtained after step S305 away from the bit line 300 to form a tungsten layer, such as Figure 14 Then, the tungsten layer is subjected to chemical mechanical polishing (CMP), and only the tungsten layer in the contact area with the first storage unit 101 is retained to form a second tungsten plug 202, as shown in FIG. Figure 14 The three-dimensional structure of the structure after the second tungsten plug 202 is formed is shown in FIG. Figure 15 The second tungsten plug 202 overlaps with the first storage unit 101 , and the second tungsten plug 202 is spaced apart from the second storage unit 102 .
[0090] S507: Depositing a second signal line layer on the side of the second storage unit 102 and the second tungsten plug 202 away from the first signal line 300, such as Figure 16 shown.
[0091] The second signal line may be a word line or a bit line, and the second signal line layer may be a word line layer or a bit line layer. In each embodiment provided in the present application, the second signal line layer is a word line layer, and the second signal line is a word line.
[0092] S508: Etching the second signal line layer to obtain a second signal line 400 in contact with the second storage unit 102 and the second tungsten plug 202, such as Figure 17 shown.
[0093] Among them, the projection of the word line (second signal line) 400 formed by etching the word line layer (second signal line layer) on the bit line layer (first signal line layer) intersects with the bit line (first signal line) 300. For example, the projection of the word line 400 on the bit line layer can be perpendicular to the bit line 300.
[0094] Therefore, in the embodiment of the present application, each storage unit 100 is adjacent to the tungsten plug 200. Since the resistance of the tungsten plug 200 is more than 100 times smaller than that of the storage unit 100, according to the Joule heat generation principle, under the same current, the heat generated by the tungsten plug 200 is more than 100 times smaller than that of the storage unit 100, thereby avoiding direct thermal interference between the storage units 100 in the memory, and improving the reliability of the memory and the accuracy of the data read from the storage unit 100.
[0095] It should be noted that the various embodiments in this specification are described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other, and the key points of each embodiment are the differences from other embodiments. In particular, for the device embodiments, since they are basically similar to the method embodiments, they are described relatively simply. For the relevant parts, reference can be made to the description of the method embodiments. The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components referred to as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative work.
[0096] As described above, this is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. A three-dimensional stacked memory, characterized in that: The memory comprises: a storage unit, a tungsten plug, a first signal line and a second signal line; The storage unit and the tungsten plug are stacked to form a substructure; the substructure is located at the intersection of the first signal line and the second signal line; The substructure comprises a first substructure and a second substructure adjacent to each other along an extension direction of the first signal line and / or along an extension direction of the second signal line; the first substructure comprises a first storage unit and a second tungsten plug, and the second substructure comprises a second storage unit and a first tungsten plug; The first storage unit contacts the first signal line, and the second tungsten plug contacts the second signal line; the second storage unit contacts the second signal line, and the first tungsten plug contacts the first signal line.
2. The memory according to claim 1, characterized in that: The memory further comprises a spacer layer; the spacer layer covers the sidewalls of the tungsten plug.
3. The memory according to claim 2, characterized in that: In the first substructure, one side of the spacer layer contacts the first storage unit and the other side contacts the second signal line; in the second substructure, one side of the spacer layer contacts the second storage unit and the other side contacts the first signal line.
4. The memory according to claim 2, characterized in that: In the extension direction of the second signal line, the size of the first storage unit is greater than or equal to the size of the corresponding second tungsten plug, and less than or equal to the sum of the sizes of the corresponding second tungsten plug and the spacer layer; the size of the second storage unit is greater than or equal to the size of the corresponding first tungsten plug, and less than or equal to the sum of the sizes of the corresponding first tungsten plug and the spacer layer.
5. The memory according to claim 2, characterized in that: In the extending direction of the first signal line, the size of the first storage unit is greater than or equal to the corresponding size of the second tungsten plug, and the size of the second storage unit is greater than or equal to the corresponding size of the first tungsten plug.
6. The memory according to claim 1, characterized in that: The memory further comprises a filling layer; the filling layer is filled between adjacent substructures.
7. A method for manufacturing a three-dimensional stacked memory, characterized in that: The method comprises: Depositing a first signal line material and a storage material in sequence to form a first signal line layer and a first storage layer; Etching the first signal line layer and the first storage layer to form a plurality of first signal lines and a plurality of first storage units located on a first side of the first signal lines; Depositing a first tungsten plug between adjacent first storage units; the first tungsten plug is spaced apart from the first storage unit; Depositing a second storage layer on a side of the first storage unit and the first tungsten plug away from the first signal line; Etching the second storage layer to form a second storage unit overlapping the first tungsten plug; Depositing a second tungsten plug between adjacent second storage cells; the second tungsten plug is spaced apart from the second storage cell and overlaps with the first storage cell; Depositing a second signal line layer on a side of the second storage unit and the second tungsten plug away from the first signal line; The second signal line layer is etched to obtain a second signal line contacting the second storage unit and the second tungsten plug; a projection of the second signal line on the first signal line layer intersects with the first signal line.
8. The method according to claim 7, characterized in that The etching of the first signal line layer and the first storage layer to form a plurality of first signal lines and a plurality of first storage units located on a first side of the first signal line includes: Etching the first signal line layer and the first storage layer to form a plurality of first signal lines and a first sub-storage layer stacked with the first signal lines; The first sub-storage layer is etched to form a plurality of first storage units located on a first side of the first signal line; the first storage units corresponding to adjacent first signal lines are arranged in a staggered manner.
9. The method according to claim 8, characterized in that After etching the first signal line layer and the first storage layer to form a plurality of first signal lines and a first sub-storage layer stacked with the first signal lines, the method further includes: Depositing to form a first filling layer filled between the stacked structure of the plurality of first signal lines and the first sub-storage layer; A first spacer layer is deposited to cover the sidewalls of the grooves between the first memory cells.
10. The method according to claim 9, characterized in that The step of depositing a first tungsten plug between adjacent first storage cells comprises: Depositing a tungsten layer on a first side of the first signal line; The tungsten layer is chemically mechanically polished to remove the tungsten layer covering the surfaces of the first storage unit, the first spacer layer and the first filling layer, and the tungsten layer in the groove of the first spacer layer is retained to form a first tungsten plug.