Packaging structure and packaging method

Abstract

The invention discloses a packaging structure and a packaging method, and the packaging structure comprises a plurality of chips which are stacked along the longitudinal direction, each chip comprises a welding surface, and the welding surfaces of the adjacent chips are opposite to each other so as to be welded with each other; and the convex blocks are positioned on the welding surfaces, the convex blocks at corresponding positions on the opposite welding surfaces of the adjacent chips are oppositely arranged, and the front opposite surfaces of the oppositely arranged convex blocks have an area difference. According to the invention, the welding quality of the adjacent chips can be improved, and the reliability of the packaging structure can be improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor packaging, and particularly to a packaging structure and a packaging method. Background Art

[0002] High Bandwidth Memory (HBM) is used for high-speed data transmission between a Graphics Processing Unit (GPU) and a Central Processing Unit (CPU). The uniqueness of HBM is mainly reflected in stacking and interconnection. HBM vertically stacks multiple Dynamic Random-Access Memories (DRAMs) through the use of advanced packaging technologies (such as Through-Silicon Via (TSV) technology, micro-bump technology, etc.), and is interconnected and packaged with the GPU through an interposer layer, achieving high capacity, high bandwidth, low latency, and low power consumption in a relatively small physical space.

[0003] During the HBM stacking process, upper and lower TSV chips are usually welded and interconnected using micro-bumps. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a packaging structure and a packaging method, which are beneficial to improving the welding quality of adjacent chips, and thus beneficial to improving the reliability of the packaging structure.

[0005] To solve the above problems, embodiments of the present invention provide a packaging structure, including: a plurality of chips stacked longitudinally, each chip including a welding surface, and the welding surfaces of adjacent chips face each other for welding; bumps located on the welding surfaces, on the opposite welding surfaces of adjacent chips, the bumps at corresponding positions are arranged opposite to each other, and there is an area difference between the directly opposite surfaces of the oppositely arranged bumps.

[0006] Optionally, among the oppositely arranged bumps, the bump with a smaller directly opposite surface area is the first bump, and the bump with a larger directly opposite surface area is the second bump. On the opposite welding surfaces of adjacent chips, each welding surface includes a first bump and a second bump.

[0007] Optionally, on the opposite welding surfaces of adjacent chips, on each welding surface, the first bumps and the second bumps are alternately distributed.

[0008] Optionally, the packaging structure further includes: solder balls located between the oppositely arranged bumps and in contact with the oppositely arranged bumps for electrical connection.

[0009] Optionally, the packaging structure further includes: a protective layer located between the bumps on the welding surface.

[0010] Optionally, the encapsulation structure further includes: a substrate, and a plurality of chips stacked longitudinally are welded to the substrate.

[0011] Optionally, the encapsulation structure further includes: a plastic encapsulation layer that covers a plurality of chips stacked longitudinally and fills the spaces between adjacent chips and between the chips and the substrate.

[0012] Optionally, a plurality of chips stacked longitudinally form a high-bandwidth memory.

[0013] Correspondingly, an embodiment of the present invention further provides an encapsulation method, including: providing chips, where the chips include welding surfaces; forming bumps on the welding surfaces; stacking a plurality of chips longitudinally, and the welding surfaces of adjacent chips face each other for welding. Among them, on the opposite welding surfaces of adjacent chips, the bumps at corresponding positions are arranged opposite to each other, and the directly opposite surfaces of the oppositely arranged bumps have an area difference.

[0014] Optionally, among the oppositely arranged bumps, the bump with a smaller directly opposite surface area is the first bump, and the bump with a larger directly opposite surface area is the second bump; in the step of forming bumps on the welding surfaces, the welding surfaces all include the first bump and the second bump.

[0015] Optionally, in the step of forming bumps on the welding surfaces, the first bumps and the second bumps are alternately distributed on the welding surfaces.

[0016] Optionally, the step of stacking a plurality of chips longitudinally includes: forming solder balls on the bumps of any one of the opposite welding surfaces of adjacent chips; bringing the solder balls into contact with the bumps on the other welding surface so that the oppositely arranged bumps are electrically connected through the solder balls.

[0017] Optionally, the encapsulation method further includes: providing a substrate; stacking a plurality of chips longitudinally on the substrate.

[0018] Optionally, the encapsulation method further includes: forming a plastic encapsulation layer that covers a plurality of chips stacked longitudinally, and the plastic encapsulation layer also fills the spaces between adjacent chips and between the chips and the substrate.

[0019] Optionally, in the step of stacking a plurality of chips longitudinally, the plurality of chips stacked longitudinally form a high-bandwidth memory.

[0020] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0021] In the packaging structure provided by the embodiments of the present invention, multiple chips are stacked longitudinally. Each chip includes a welding surface, and the welding surfaces of adjacent chips face each other for welding. Bumps are located on the welding surfaces. On the opposite welding surfaces of adjacent chips, the bumps at corresponding positions are arranged oppositely, and there is an area difference between the directly opposite surfaces of the oppositely arranged bumps. In the embodiments of the present invention, on the opposite welding surfaces of adjacent chips, the bumps at corresponding positions are arranged oppositely, and there is an area difference between the directly opposite surfaces of the oppositely arranged bumps. When the welding surfaces of adjacent chips are made to face each other for welding, the area difference increases the operation window for the oppositely arranged bumps at corresponding positions, which is conducive to reducing the alignment deviation probability of the bumps that need to be arranged oppositely, facilitating the alignment of the bumps at corresponding positions, thus being conducive to improving the welding quality of the bumps at corresponding positions, correspondingly conducive to improving the welding quality of adjacent chips, and further conducive to improving the reliability of the packaging structure.

[0022] In an alternative solution, among the oppositely arranged bumps, the bump with a smaller directly opposite surface area is defined as the first bump, and the bump with a larger directly opposite surface area is defined as the second bump. In the step of forming bumps on the welding surface, both the first bump and the second bump are included on the welding surface. In the embodiments of the present invention, on one welding surface, both the first bump with a smaller directly opposite surface area and the second bump with a larger directly opposite surface area are included. This can not only reduce the alignment deviation probability of the bumps that need to be arranged oppositely but also appropriately reduce the occupied area of some bumps on one welding surface, decrease the pitch between adjacent bumps, which is conducive to improving the layout density of the bumps on the welding surface, also conducive to reducing the chip size and improving the integration degree of the packaging structure. Moreover, it is also conducive to increasing the number of bumps formed on one welding surface, thus being conducive to improving the heat dissipation performance of the packaging structure and being conducive to improving the connection flexibility of electrical connection between adjacent chips through the bumps.

[0023] In the packaging method provided by the embodiments of the present invention, multiple chips are stacked longitudinally, and the welding surfaces of adjacent chips face each other for welding. Among them, on the opposite welding surfaces of adjacent chips, the bumps at corresponding positions are arranged oppositely, and there is an area difference between the directly opposite surfaces of the oppositely arranged bumps. In the embodiments of the present invention, on the opposite welding surfaces of adjacent chips, the bumps at corresponding positions are arranged oppositely, and there is an area difference between the directly opposite surfaces of the oppositely arranged bumps. When the welding surfaces of adjacent chips are made to face each other for welding, the area difference increases the operation window for the oppositely arranged bumps at corresponding positions, which is conducive to reducing the alignment deviation probability of the bumps that need to be arranged oppositely, facilitating the alignment of the bumps at corresponding positions, thus being conducive to improving the welding quality of the bumps at corresponding positions, correspondingly conducive to improving the welding quality of adjacent chips, and further conducive to improving the reliability of the packaging structure. Description of the Drawings

[0024] Figure 1 is a schematic structural diagram corresponding to a packaging structure;

[0025] Figure 2 is a schematic structural diagram corresponding to an embodiment of the encapsulation structure of the present invention;

[0026] Figures 3 to 7 is a schematic structural diagram corresponding to each step in an embodiment of the encapsulation method of the present invention. Detailed implementation manners

[0027] Currently, the welding quality of adjacent chips in the encapsulation structure needs to be improved. Now, in combination with an encapsulation structure, the reasons why the welding quality of adjacent chips in the encapsulation structure needs to be improved are analyzed.

[0028] Figure 1 is a schematic structural diagram corresponding to an encapsulation structure.

[0029] Reference Figure 1 , the encapsulation structure includes: chips 20 welded to each other; bumps 30 located on the opposite surfaces of the mutually welded chips 20; solder balls 40 located between the opposite bumps 30.

[0030] In the existing encapsulation structure, the sizes of the bumps 30 are usually the same. Then, during the process of welding the chips 20 to each other, the alignment windows between the bumps 30 to be combined are small, which easily leads to alignment deviation of the bumps 30 of the two chips 20, and correspondingly leads to alignment deviation between the solder balls 40 and the bumps 30, thereby resulting in poor welding between the bumps 30 of the two chips 20 (as shown by the dotted line box in Figure 1 ), which affects the welding quality between adjacent chips 20. In particular, in order to meet the requirements of high integration of the chips 20, the sizes of the bumps 30 of the chips 20 tend to decrease, which more easily leads to alignment deviation of the bumps 30 between the mutually welded chips 20. And if the size of the bumps 30 is increased for this reason, it is also easy to cause an increase in the size of the chips 20, thereby resulting in an increase in the size of the entire encapsulation structure.

[0031] To solve the above technical problems, the present invention provides an encapsulation structure, including: a plurality of chips stacked longitudinally, the chips including welding surfaces, and the welding surfaces of adjacent chips are opposite to each other for welding; bumps located on the welding surfaces, on the opposite welding surfaces of adjacent chips, the bumps at corresponding positions are arranged oppositely, and there is an area difference between the directly opposite surfaces of the oppositely arranged bumps.

[0032] In the embodiments of the present invention, on the opposite welding surfaces of adjacent chips, the bumps at corresponding positions are oppositely arranged, and there is an area difference on the directly opposite surfaces of the oppositely arranged bumps. When the welding surfaces of adjacent chips are opposed to each other for welding, the area difference increases the operation window for the bumps at corresponding positions to be oppositely arranged, which is beneficial to reducing the alignment offset probability of the bumps that need to be oppositely arranged, facilitating the alignment of the bumps at corresponding positions, thus being beneficial to improving the welding quality of the bumps at corresponding positions, correspondingly beneficial to improving the welding quality of adjacent chips, and further beneficial to improving the reliability of the package structure.

[0033] In order to make the above-mentioned objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description will be given to the specific embodiments of the present invention with reference to the accompanying drawings.

[0034] Figure 2 It is a schematic structural diagram corresponding to an embodiment of the package structure of the present invention.

[0035] Refer to Figure 2 , the package structure includes: a plurality of chips 200 stacked longitudinally, the chips 200 include welding surfaces 200a, and the welding surfaces 200a of adjacent chips 200 are opposed to each other for welding; bumps 300 are located on the welding surfaces 200a, on the opposite welding surfaces 200a of adjacent chips 200, the bumps 300 at corresponding positions are oppositely arranged, and there is an area difference on the directly opposite surfaces of the oppositely arranged bumps 300.

[0036] The chips 200 are used to meet the performance requirements of the package structure. Specifically, different functional chips 200 can be selected according to the performance requirements of the package structure.

[0037] In this embodiment, the chips 200 include welding surfaces 200a.

[0038] The welding surface 200a is an operation platform for realizing the mutual welding between the chips 200.

[0039] Specifically, in this embodiment, the welding surfaces 200a of the chips 200 are oppositely arranged to realize the welding between the chips 200.

[0040] In this embodiment, the plurality of chips 200 stacked longitudinally are electrically connected to each other.

[0041] As an example, in this embodiment, a high bandwidth memory (HBM) structure composed of a plurality of chips 200 stacked longitudinally is adopted. By adopting the HBM structure, it is beneficial to meet the requirements for higher information transmission speeds.

[0042] Among them, the multiple vertically stacked chips 200 include a logic chip at the bottommost and memory chips stacked on the logic chip, and the number of memory chips can be one or more. In this embodiment, the number of memory chips is taken as three as an example for illustration. In other embodiments, the number of memory chips can also be other numbers.

[0043] As an example, in this embodiment, the HBM structure composed of the multiple vertically stacked chips 200 is interconnected with external chips through an Interposer. Specifically, the external chips can be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or a System on Chip (SoC).

[0044] The bumps 300 are used to electrically lead out the internal circuits of the chips 200 to achieve electrical connection between the chips 200.

[0045] In this embodiment, on the opposite welding surfaces 200a of adjacent chips 200, the corresponding bumps 300 are oppositely arranged, and there is an area difference on the directly opposite side of the oppositely arranged bumps 300. Then, when the welding surfaces 200a of adjacent chips 200 are opposed to each other for welding, the area difference increases the operation window for the corresponding bumps 300 to be oppositely arranged, which is beneficial to reducing the alignment offset probability of the bumps 300 that need to be oppositely arranged, facilitating the alignment of the corresponding bumps 300, thereby being beneficial to improving the welding quality of the corresponding bumps 300, correspondingly beneficial to improving the welding quality of adjacent chips 200, and further beneficial to improving the reliability of the packaging structure.

[0046] Among them, the corresponding bumps 300 refer to the two bumps 300 that need to be correspondingly interconnected on the opposite welding surfaces 200a when adjacent chips 200 are welded.

[0047] In this embodiment, among the oppositely arranged bumps 300, the bump 300 with a smaller directly opposite area is the first bump 310, and the bump 300 with a larger directly opposite area is the second bump 320. On each of the opposite welding surfaces 200a of adjacent chips 200, both the first bump 310 and the second bump 320 are included.

[0048] Specifically, there is an area difference on the directly opposite side of the oppositely arranged bumps 300. That is, among the oppositely arranged bumps 300, one is the first bump 310 and the other is the second bump 320. Taking any one of the opposite welding surfaces 200a as the first welding surface and the other as the second welding surface, both the first welding surface and the second welding surface include the first bump 310 and the second bump 320. The first bump 310 on the first welding surface is opposite to the second bump 320 on the second welding surface, and the second bump 320 on the first welding surface is opposite to the first bump 310 on the second welding surface.

[0049] In this embodiment, on one welding surface 200a, it includes the first bump 310 with a smaller area on the directly opposite side and the second bump 320 with a larger area on the directly opposite side. Then, while reducing the alignment offset probability of the oppositely arranged bumps 300, it also appropriately reduces the occupied area of some bumps 300 on one welding surface 200a, reduces the pitch between adjacent bumps 300, which is conducive to improving the layout density of the bumps 300 on the welding surface 200a, is also conducive to reducing the size of the chip 200 and improving the integration degree of the packaging structure. Moreover, it is also conducive to increasing the number of bumps 300 formed on one welding surface 200a, which is conducive to improving the connection flexibility of electrical connection between adjacent chips 200 through the bumps 300.

[0050] Among them, the pitch between adjacent bumps 300 refers to the distance between the centers of adjacent bumps 300.

[0051] In this embodiment, in the opposite welding surfaces 200a of adjacent chips 200, on each welding surface 200a, the first bumps 310 and the second bumps 320 are alternately distributed.

[0052] On each welding surface 200a, the first bumps 310 and the second bumps 320 are alternately distributed, the arrangement regularity of the bumps 300 is better, and it is conducive to relatively evenly improving the layout density of the bumps 300 on the welding surface 200a, making the layout uniformity of the bumps 300 on each welding surface 200a better, which is conducive to the welding between chips 200 achieved by aligning through the bumps 300. At the same time, the occupied area of the bumps 300 on each welding surface 200a is relatively unified, which is conducive to making the size uniformity of the chips 200 better, thus being conducive to the stacking of multiple chips 200 in the longitudinal direction, and further making the multiple longitudinally stacked chips 200 better encapsulated to obtain a packaging structure with better reliability.

[0053] It should be noted that in the packaging process of the HBM structure, the upper surface of the topmost chip 200 may not form bumps 300.

[0054] In this embodiment, the packaging structure further includes: solder balls 400, which are located between the oppositely arranged bumps 300 and are in contact with the oppositely arranged bumps 300 for electrical connection.

[0055] The solder balls 400 are used to achieve electrical connection between the opposite bumps 300 of the mutually welded chips 200.

[0056] In this embodiment, the material of the solder balls 400 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0057] In this embodiment, the packaging structure further includes: a protective layer, which is located between the bumps 300 on the welding surface 200a.

[0058] The protective layer is used to protect the welding surface 200a of the chip 200, and is also used to isolate the bumps in the chip 200. The protective layer is also used to relieve stress, avoiding circuit cracking and disconnection caused by thermal stress and mechanical stress, as well as the fracture of the bump welding points.

[0059] The material of the protective layer can be an organic material or an inorganic material. The organic material can be a polymer resin material, specifically including epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin. The inorganic material can be one or several of silicon oxide, silicon nitride, silicon oxynitride, carbon oxysilicon, and carbonitride silicon.

[0060] In this embodiment, the protective layer is a polyimide (PI) layer.

[0061] In other embodiments, the protective layer can also be a passivation layer.

[0062] In this embodiment, the packaging structure further includes: a substrate 100, and a plurality of chips 200 stacked longitudinally are welded to the substrate 100.

[0063] The substrate 100 is used to provide a process operation basis for the welding of the chips 200.

[0064] In this embodiment, the substrate 100 is an interposer.

[0065] Using an interposer to perform interconnection packaging on the stacked plurality of chips 200 is used to lead out the electrical properties of the stacked plurality of chips 200 and achieve electrical connection between the stacked plurality of chips 200 and the outside.

[0066] Correspondingly, in this embodiment, the solder balls 400 are also formed between the bottommost chip 200 and the substrate 100 to achieve electrical connection between the chip 200 and the substrate 100.

[0067] In this embodiment, the encapsulation structure further includes: a plastic encapsulation layer 500, which covers a plurality of vertically stacked chips 200 and fills the spaces between adjacent chips 200 and between the chips 200 and the substrate 100.

[0068] The plastic encapsulation layer 500 covers a plurality of vertically stacked chips 200, which serves to protect the stacked chips 200. The plastic encapsulation layer 500 fills the spaces between adjacent chips 200 and between the chips 200 and the substrate 100, which is used to insulate between adjacent chips 200 and between the chips 200 and the substrate 100. The plastic encapsulation layer 500 is also used to interconnect and form the vertically stacked chips 200.

[0069] In this embodiment, the material of the plastic encapsulation layer 500 includes Liquid epoxy Molding Compound (LMC).

[0070] Figures 3 to 7 It is a schematic structural diagram corresponding to each step in an embodiment of the encapsulation method of the present invention.

[0071] Refer to Figure 3 , provide chips 200, and the chips 200 include a welding surface 200a.

[0072] The chips 200 are used to meet the performance requirements of the encapsulation structure. Specifically, chips 200 with different functions can be selected according to the performance requirements of the encapsulation structure.

[0073] In this embodiment, the chips 200 include a welding surface 200a.

[0074] The welding surface 200a is an operating platform for realizing the mutual welding between the chips 200.

[0075] Specifically, in this embodiment, the welding surfaces 200a of the chips 200 are arranged opposite to each other later to realize the welding between the chips 200.

[0076] In this embodiment, in the step of providing the chips 200, a metal sputtering layer is formed at a preset position on the welding surface 200a of the chips 200.

[0077] The preset position is the position for forming bumps later, and the metal sputtering layer is used for electroplating to form bumps later.

[0078] In this embodiment, in the step of providing the chips 200, a protective layer covering the welding surface 200a is also formed on the chips 200.

[0079] The protective layer is used to protect the surface of the chips 200 and is also used to realize the isolation between bumps later.

[0080] Refer to Figure 4, bumps 300 are formed on the welding surface 200a.

[0081] The bumps 300 are used to electrically lead out the internal circuit of the chip 200 and achieve electrical connection between chips 200.

[0082] For the sake of clear illustration, the following will be described in conjunction with Figure 6 the chips 200 after being welded together.

[0083] In this embodiment, in the subsequent step of stacking multiple chips 200 longitudinally and making the welding surfaces 200a of adjacent chips 200 face each other for welding, on the opposite welding surfaces 200a of adjacent chips 200, the bumps 300 at corresponding positions are arranged oppositely, and there is an area difference on the front faces of the oppositely arranged bumps 300.

[0084] In this embodiment, on the opposite welding surfaces 200a of adjacent chips 200, the bumps 300 at corresponding positions are arranged oppositely, and there is an area difference on the front faces of the oppositely arranged bumps 300. Then, when the welding surfaces 200a of adjacent chips 200 are made to face each other to achieve welding, the area difference increases the operation window for the oppositely arranged bumps 300 at corresponding positions, which is beneficial to reducing the probability of alignment deviation of the bumps 300 that need to be arranged oppositely, facilitating the alignment of the bumps 300 at corresponding positions, thus being beneficial to improving the welding quality of the bumps 300 at corresponding positions, correspondingly beneficial to improving the welding quality of adjacent chips 200, and further beneficial to improving the reliability of the packaging structure.

[0085] Among them, the bumps 300 at corresponding positions refer to the two bumps 300 that need to be interconnected correspondingly on the opposite welding surfaces 200a when the chips 200 are welded together.

[0086] In this embodiment, among the oppositely arranged bumps 300, the bump 300 with a smaller area on the front face is the first bump 310, and the bump 300 with a larger area on the front face is the second bump 320. In the step of forming the bumps 300 on the welding surface 200a, the welding surface 200a includes both the first bump 310 and the second bump 320.

[0087] Specifically, there is an area difference on the front faces of the oppositely arranged bumps 300, that is, among the oppositely arranged bumps 300, one is the first bump 310 and the other is the second bump 320. Taking any one of the opposite welding surfaces 200a as the first welding surface and the other as the second welding surface, that is, both the first welding surface and the second welding surface include the first bump 310 and the second bump 320. The first bump 310 on the first welding surface is opposite to the second bump 320 on the second welding surface, and the second bump 320 on the first welding surface is opposite to the first bump 310 on the second welding surface.

[0088] In this embodiment, on a solder joint surface 200a, it includes a first bump 310 with a relatively small area on the opposite side and a second bump 320 with a relatively large area on the opposite side. Thus, while reducing the alignment offset probability of the bumps 300 that need to be oppositely arranged, it also appropriately reduces the occupied area of some bumps 300 on a solder joint surface 200a, reduces the pitch between adjacent bumps 300, which is conducive to improving the layout density of the bumps 300 on the solder joint surface 200a, is also conducive to reducing the size of the chip 200 and improving the integration degree of the packaging structure. Moreover, it is also conducive to increasing the number of bumps 300 formed on a solder joint surface 200a, which is conducive to improving the heat dissipation performance of the packaging structure and is conducive to improving the connection flexibility of electrical connection between adjacent chips 200 through the bumps 300.

[0089] Among them, the pitch between adjacent bumps 300 refers to the distance between the centers of adjacent bumps 300.

[0090] In this embodiment, in the step of forming the bumps 300 on the solder joint surface 200a, the first bumps 310 and the second bumps 320 are alternately distributed on the solder joint surface 200a.

[0091] On each solder joint surface 200a, the first bumps 310 and the second bumps 320 are alternately distributed, and the arrangement of the bumps 300 has good regularity, which is conducive to relatively uniformly improving the layout density of the bumps 300 on the solder joint surface 200a, making the layout uniformity of the bumps 300 on each solder joint surface 200a better, facilitating the soldering achieved by aligning the chips 200 through the bumps 300. At the same time, the occupied area of the bumps 300 on each solder joint surface 200a is relatively unified, which is conducive to making the size uniformity of the chips 200 better, thus facilitating the stacking of multiple chips 200 in the longitudinal direction, and further enabling better plastic encapsulation of the longitudinally stacked multiple chips 200 to obtain a packaging structure with better reliability.

[0092] In this embodiment, the step of forming the bumps 300 on the solder joint surface 200a includes: patterning the protective layer to form a groove exposing the surface of the chip 200.

[0093] The groove is used to provide a spatial position for forming the bumps 300. Specifically, a groove exposing the metal sputtering layer is formed at a preset position of the chip 200.

[0094] In this embodiment, the protective layer is patterned by an etching process.

[0095] In this embodiment, the bumps 300 are formed in the groove.

[0096] In this embodiment, the bumps 300 are formed in the groove by an electroplating process.

[0097] A graphical mask is used to cover the protective layer, and the grooves expose the metal sputtering layer. An electroplating process is used to form bumps 300 on the surface of the metal sputtering layer. It can be understood that the bumps 300 can cover the edge of the protective layer around the grooves, which is beneficial to the combination of the protective layer and the chip welding surface and the stress relief around the bumps.

[0098] Reference Figure 5 , a substrate 100 is provided.

[0099] The substrate 100 is used to provide a process operation basis for realizing the welding of the chip 200.

[0100] In this embodiment, the substrate 100 is an interposer.

[0101] The interposer is used to interconnect and package multiple stacked chips 200, for electrically leading out the multiple stacked chips 200, and realizing the electrical connection between the multiple stacked chips 200 and the outside.

[0102] Reference Figure 6 , multiple chips 200 are stacked longitudinally, and the welding surfaces 200a of adjacent chips 200 face each other for welding. Among them, on the opposite welding surfaces 200a of adjacent chips 200, the bumps 300 at corresponding positions are arranged oppositely, and there is an area difference on the directly opposite surfaces of the oppositely arranged bumps 300.

[0103] In this embodiment, the multiple longitudinally stacked chips 200 are electrically connected to each other.

[0104] As an example, in this embodiment, in the step of stacking multiple chips 200 longitudinally, the multiple longitudinally stacked chips 200 form a High Bandwidth Memory (HBM) structure. By adopting the HBM structure, it is beneficial to meet the requirements for higher information transmission speed.

[0105] Among them, the multiple longitudinally stacked chips 200 include a logic chip located at the bottom and memory chips stacked on the logic chip. The number of memory chips can be one or more. In this embodiment, the number of memory chips is taken as three as an example for illustration. In other embodiments, the number of memory chips can also be other numbers.

[0106] It should be noted that in the HBM structure packaging process, bumps 300 may not be formed on the upper surface of the topmost chip 200.

[0107] In this embodiment, the step of stacking multiple chips 200 longitudinally includes: forming solder balls 400 on the bumps 300 of any one of the opposite welding surfaces 200a of adjacent chips 200.

[0108] The solder ball 400 is used to realize the electrical connection between the opposing bumps 300 of the chips 200 to be mutually soldered.

[0109] In this embodiment, the material of the solder ball 400 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride.

[0110] In this embodiment, the solder ball 400 is brought into contact with the bump 300 on another welding surface 200a, so that the oppositely arranged bumps 300 are electrically connected through the solder ball 400.

[0111] Specifically, adjacent chips 200 are soldered through the solder ball 400.

[0112] In this embodiment, a plurality of chips 200 are longitudinally stacked on the substrate 100.

[0113] As an example, in this embodiment, the HBM structure formed by a plurality of longitudinally stacked chips 200 is interconnected with an external chip through an Interposer. Specifically, the external chip can be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or a system on chip (SoC).

[0114] Correspondingly, in this embodiment, the encapsulation method further includes: forming solder balls 400 between the lowermost chip 200 and the substrate 100 to realize the electrical connection between the lowermost chip 200 and the substrate 100 by using the solder balls 400.

[0115] Reference Figure 7 , the encapsulation method further includes: forming a plastic encapsulation layer 500 that covers the plurality of longitudinally stacked chips 200, and the plastic encapsulation layer 500 is filled between adjacent chips 200 and between the chips 200 and the substrate 100.

[0116] The plastic encapsulation layer 500 covers the plurality of longitudinally stacked chips 200 and is used to protect the stacked plurality of chips 200. The plastic encapsulation layer 500 is filled between adjacent chips 200 and between the chips 200 and the substrate 100 and is used to insulate between adjacent chips 200 and between the chips 200 and the substrate 100. The plastic encapsulation layer 500 is also used to interconnect and form the plurality of longitudinally stacked chips 200.

[0117] In this embodiment, the material of the plastic encapsulation layer 500 includes Liquid epoxy Molding Compound (LMC).

[0118] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A packaging structure, characterized in that: include: A plurality of chips stacked in a longitudinal direction, wherein the chips include welding surfaces, and the welding surfaces of adjacent chips are opposite to each other for welding; The bumps are located on the welding surface. The bumps at corresponding positions on the relative welding surfaces of the adjacent chips are arranged relatively, and the opposite sides of the relatively arranged bumps have an area difference.

2. The packaging structure according to claim 1, characterized in that: Among the bumps arranged opposite to each other, the bumps with smaller areas facing each other are first bumps, and the bumps with larger areas facing each other are second bumps. Among the relative welding surfaces of adjacent chips, each welding surface includes the first bump and the second bump.

3. The packaging structure according to claim 2, characterized in that: On each of the opposing welding surfaces of the adjacent chips, the first bumps and the second bumps are alternately distributed.

4. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a solder ball located between the oppositely disposed bumps and in contact with the oppositely disposed bumps for electrical connection.

5. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a protection layer located between the bumps on the welding surface.

6. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a substrate, on which the plurality of chips stacked in a longitudinal direction are welded.

7. The packaging structure according to claim 6, characterized in that: The packaging structure further includes: a plastic packaging layer, covering the plurality of chips stacked vertically and filling between adjacent chips and between the chip and the substrate.

8. The packaging structure according to claim 1, characterized in that: A plurality of the chips stacked vertically constitute a high bandwidth memory.

9. A packaging method, characterized in that: include: Providing a chip, the chip comprising a welding surface; forming a bump on the welding surface; The plurality of chips are stacked in the longitudinal direction, and the welding surfaces of adjacent chips are opposed to each other for welding, wherein on the opposing welding surfaces of adjacent chips, the bumps at corresponding positions are opposed to each other, and the opposite faces of the opposing bumps have an area difference.

10. The packaging method according to claim 9, characterized in that: Among the convex blocks arranged opposite to each other, the convex block with a smaller area facing each other is a first convex block, and the convex block with a larger area facing each other is a second convex block; In the step of forming bumps on the welding surface, the welding surface includes the first bump and the second bump.

11. The packaging method according to claim 10, characterized in that: In the step of forming bumps on the welding surface, the first bumps and the second bumps are alternately distributed on the welding surface.

12. The packaging method according to claim 9, characterized in that: The step of stacking a plurality of the chips in the longitudinal direction comprises: forming solder balls on bumps of any one of the soldering surfaces opposite to the soldering surfaces in adjacent chips; The solder ball is brought into contact with a bump on another of the soldering surfaces, so that the bumps arranged opposite to each other are electrically connected through the solder ball.

13. The packaging method according to claim 9, characterized in that: The packaging method further comprises: providing a substrate; A plurality of the chips are stacked on the substrate along a longitudinal direction.

14. The packaging method according to claim 13, characterized in that: The packaging method further comprises: forming a plastic encapsulation layer covering a plurality of chips stacked vertically, wherein the plastic encapsulation layer is also filled between adjacent chips and between the chip and the substrate.

15. The packaging method according to claim 9, characterized in that: In the step of stacking the plurality of chips in the longitudinal direction, the plurality of chips stacked in the longitudinal direction constitute a high bandwidth memory.

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