Packaging structure and packaging method

Abstract

The invention discloses a packaging structure and a packaging method. The packaging structure comprises a substrate; the chips are longitudinally stacked and bonded on the substrate, and protective layers are formed on the upper surfaces and the lower surfaces of the chips; the diversion trench is located in the protective layer and comprises a main diversion trench penetrating through the protective layer in the mold flow direction and branch diversion trenches arranged on the side portion of the main diversion trench in the mold flow direction, and each branch diversion trench comprises a first branch diversion trench with one end communicated with the main diversion trench and the other end extending towards the inclined front of the mold flow direction. According to the invention, the plastic packaging quality of the packaging structure can be improved, and the reliability of the packaging structure can be improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor packaging, and in particular to a packaging structure and a packaging method. Background Art

[0002] High Bandwidth Memory (HBM) is used for high-speed data transmission between a Graphics Processing Unit (GPU) and a Central Processing Unit (CPU). The uniqueness of HBM is mainly reflected in stacking and interconnection. HBM vertically stacks multiple Dynamic Random-Access Memories (DRAMs) by using advanced packaging technologies (such as Through-Silicon Via (TSV) technology, micro-bump technology, etc.), and is interconnected and packaged with the GPU through an interposer, achieving high capacity, high bandwidth, low latency, and low power consumption in a relatively small physical space.

[0003] During the HBM stacking process, some materials are usually required to protect the chips and interconnections, as well as to ensure the mechanical stability and electrical performance of the stacking structure. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a packaging structure and a packaging method, which are beneficial to improving the plastic packaging quality of the packaging structure, and thus beneficial to improving the reliability of the packaging structure.

[0005] To solve the above problems, embodiments of the present invention provide a packaging structure, including: a substrate; a plurality of chips stacked longitudinally and bonded to the substrate, with protective layers formed on the upper and lower surfaces of the chips; a diversion groove located in the protective layer, the diversion groove including a main diversion groove penetrating the protective layer along the mold flow direction, and branch diversion grooves arranged on the side of the main diversion groove along the mold flow direction, the branch diversion grooves including a first branch diversion groove with one end connected to the main diversion groove and the other end extending obliquely forward in the mold flow direction.

[0006] Optionally, taking the edge of the protective layer parallel to the mold flow direction as the side edge, the branch diversion groove further includes a second branch diversion groove with one end connected to the side edge and the other end extending obliquely forward in the mold flow direction.

[0007] Optionally, the width of the branch diversion groove gradually decreases from the connected end to the other end.

[0008] Optionally, the extension direction of the branch diversion groove forms an angle of 25° - 65° with the mold flow direction.

[0009] Optionally, the branch diversion grooves on the same side are arranged in parallel along the mold flow direction.

[0010] Optionally, the first diversion groove and the second diversion groove are separated by a protective layer.

[0011] Optionally, the encapsulation structure further includes: bumps, which are located in the protective layers on the upper and lower surfaces of the chip and penetrate through the protective layer.

[0012] Optionally, the edge of the protective layer is recessed inward relative to the corresponding edge of the chip.

[0013] Optionally, the size of the inward recess of the edge of the protective layer relative to the corresponding edge of the chip is 1 / 4 to 3 / 4 of the minimum distance from the bump at the edge of the chip to the corresponding edge of the chip.

[0014] Optionally, at the edge of the protective layer, the side wall of the protective layer presents a ramp shape that slopes inward from near the chip to away from the chip.

[0015] Optionally, the encapsulation structure further includes: a molding compound layer, which covers a plurality of vertically stacked chips and fills the spaces between adjacent chips and between the chips and the substrate.

[0016] Correspondingly, an embodiment of the present invention further provides an encapsulation method, including: providing a chip; forming a protective layer covering the upper and lower surfaces of the chip; patterning the protective layer to form diversion grooves, the diversion grooves including a main diversion groove that penetrates through the protective layer along the mold flow direction and branch diversion grooves that are arranged on the side of the main diversion groove along the mold flow direction, the branch diversion grooves including a first branch diversion groove with one end connected to the main diversion groove and the other end extending obliquely forward in the mold flow direction; providing a substrate; and bonding a plurality of chips stacked vertically to the substrate.

[0017] Optionally, in the step of forming the protective layer on the upper and lower surfaces of the chip, the edge of the protective layer parallel to the mold flow direction is used as the side edge; in the step of patterning the protective layer to form diversion grooves, the branch diversion grooves further include a second branch diversion groove with one end connected to the side edge and the other end extending obliquely forward in the mold flow direction.

[0018] Optionally, in the step of patterning the protective layer to form diversion grooves, the width of the branch diversion grooves gradually decreases from the connected end to the other end.

[0019] Optionally, in the step of patterning the protective layer to form diversion grooves, the branch diversion grooves on the same side are arranged parallel to each other along the mold flow direction.

[0020] Optionally, in the step of patterning the protective layer to form diversion grooves, the first branch diversion groove and the second branch diversion groove are separated by a protective layer.

[0021] Optionally, in the step of patterning the protective layer to form diversion grooves, it further includes: removing a part of the width of the protective layer from the edge of the protective layer.

[0022] Optionally, in the step of forming the diversion channels in the graphical protection layer, it further includes: at the edge of the graphical protection layer, such that the side wall of the protection layer presents a ramp shape that slopes inwards from near the chip to away from the chip.

[0023] Optionally, in the step of forming the diversion channels in the graphical protection layer, it further includes: forming a groove exposing the chip surface in the graphical protection layer; after forming the diversion channels in the graphical protection layer, it further includes: forming a bump in the groove.

[0024] Optionally, after bonding a plurality of chips stacked longitudinally to the substrate, the packaging method further includes: forming a plastic encapsulation layer covering the plurality of chips stacked longitudinally, and the plastic encapsulation layer also fills between adjacent chips and between the chips and the substrate.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0026] In the packaging structure provided by the embodiment of the present invention, a plurality of chips stacked longitudinally are bonded to the substrate, protection layers are formed on the upper surface and the lower surface of the chips, the diversion channels are located in the protection layers, the diversion channels include a main diversion channel that penetrates the protection layer along the mold flow direction, and branch diversion channels arranged on the side of the main diversion channel along the mold flow direction. The branch diversion channels include a first branch diversion channel with one end connected to the main diversion channel and the other end extending obliquely forward in the mold flow direction; in the embodiment of the present invention, forming the diversion channels in the protection layer is beneficial to the filling of the encapsulant between adjacent chips during the plastic encapsulation process of the stacked plurality of chips. In the diversion channels, the main diversion channel penetrates the protection layer along the mold flow direction, which is beneficial to increasing the filling window of the plastic encapsulation and guiding the encapsulant into the space between adjacent chips. One end of the first branch diversion channel is connected to the main diversion channel and the other end extends obliquely forward in the mold flow direction, so the first branch diversion channel extends into the internal area of the chip along the mold flow direction, that is, the first branch diversion channel extends into the internal area of the chip along the flow direction of the encapsulant, which is beneficial to the flow filling of the encapsulant between adjacent chips, thus facilitating the reduction of the filling difficulty of the encapsulant between adjacent chips, beneficial to improving the plastic encapsulation quality of the packaging structure, and further beneficial to improving the reliability of the packaging structure.

[0027] In the encapsulation method provided by the embodiments of the present invention, a protective layer covering the upper surface and the lower surface of the chip is formed, and the protective layer is patterned to form a diversion channel. The diversion channel includes a main diversion channel penetrating the protective layer along the mold flow direction, and branch diversion channels arranged on the side of the main diversion channel along the mold flow direction. The branch diversion channel includes a first branch diversion channel with one end communicating with the main diversion channel and the other end extending obliquely forward in the mold flow direction. In the embodiments of the present invention, forming a diversion channel in the protective layer is beneficial to the filling of the encapsulant between adjacent chips during the encapsulation of multiple stacked chips. In the diversion channel, the main diversion channel penetrates the protective layer along the mold flow direction, which is beneficial to increasing the filling window of the encapsulation, guiding the encapsulant into the space between adjacent chips. One end of the first branch diversion channel communicates with the main diversion channel, and the other end extends obliquely forward in the mold flow direction, so the first branch diversion channel extends along the mold flow direction, that is, the first branch diversion channel extends along the flow direction of the encapsulant, which is beneficial to the flow filling of the encapsulant between adjacent chips, thereby facilitating the reduction of the filling difficulty of the encapsulant between adjacent chips, improving the encapsulation quality of the encapsulation structure, and further improving the reliability of the encapsulation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 2 is a schematic structural diagram corresponding to an embodiment of the encapsulation structure of the present invention;

[0029] Figures 3 to 13 is a schematic structural diagram corresponding to each step in an embodiment of the encapsulation method of the present invention. DETAILED DESCRIPTION

[0030] As can be seen from the background art, during the HBM stacking process, some materials are usually used to protect the chips and interconnections, and to ensure the mechanical stability and electrical performance of the stacked structure. Currently, liquid epoxy molding compound (LMC) is usually used to fill the gaps between chips and between chips and the substrate to encapsulate the chips and the substrate to achieve insulation and molding. However, the current encapsulation filling effect is not good.

[0031] To solve the above technical problems, the present invention provides an encapsulation structure, including: a substrate; a plurality of longitudinally stacked chips bonded to the substrate, with a protective layer formed on the upper surface and the lower surface of the chips; a diversion channel located in the protective layer, the diversion channel including a main diversion channel penetrating the protective layer along the mold flow direction, and branch diversion channels arranged on the side of the main diversion channel along the mold flow direction, the branch diversion channel including a first branch diversion channel with one end communicating with the main diversion channel and the other end extending obliquely forward in the mold flow direction.

[0032] In the embodiment of the present invention, a diversion groove is formed in the protective layer, which is beneficial to the filling of the encapsulant between adjacent chips during the encapsulation process of multiple stacked chips. In the diversion groove, the main diversion groove penetrates the protective layer along the mold flow direction, which is beneficial to increasing the filling window of the encapsulation, guiding the encapsulant into the space between adjacent chips. One end of the first branch diversion groove is connected to the main diversion groove, and the other end extends obliquely forward in the direction of the mold flow. Then, the first branch diversion groove extends along the mold flow direction, that is, the first branch diversion groove extends along the flow direction of the encapsulant, which is beneficial to the flow filling of the encapsulant between adjacent chips, thus facilitating the reduction of the filling difficulty of the encapsulant between adjacent chips, improving the encapsulation quality of the packaging structure, and further enhancing the reliability of the packaging structure.

[0033] In order to make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0034] Figures 1 to 2 It is a schematic structural diagram corresponding to an embodiment of the packaging structure of the present invention.

[0035] With reference to Figure 1 and Figure 2 , Figure 2 For Figure 1 a top view of any surface of the chip in Figure 2 , the packaging structure includes: a substrate 100; a plurality of chips 200 stacked longitudinally and bonded to the substrate 100, and a protective layer 300 is formed on the upper and lower surfaces of the chips 200; a diversion groove 400 is located in the protective layer 300. The diversion groove 400 includes a main diversion groove 410 that penetrates the protective layer 300 along the mold flow direction (as shown by the X direction in Figure 2 ), and branch diversion grooves 420 arranged on the side of the main diversion groove 410 along the mold flow direction. The branch diversion grooves 420 include a first branch diversion groove 430 with one end connected to the main diversion groove 410 and the other end extending obliquely forward in the direction of the mold flow.

[0036] The substrate 100 is used to provide a process operation basis for the bonding of the chips 200.

[0037] In this embodiment, the substrate 100 is an interposer.

[0038] The interposer is used for interconnecting and packaging a plurality of stacked chips 200 to electrically lead out the stacked chips 200 and achieve the electrical connection between the stacked chips 200 and the outside.

[0039] The chips 200 are used to meet the performance requirements of the packaging structure. Specifically, chips 200 with different functions can be selected according to the performance requirements of the packaging structure.

[0040] In this embodiment, multiple vertically stacked chips 200 are electrically connected to each other.

[0041] As an example, in this embodiment, a High Bandwidth Memory (HBM) structure formed by multiple vertically stacked chips 200 is adopted. By using the HBM structure, it is beneficial to meet the requirements for higher information transmission speeds.

[0042] Among them, the multiple vertically stacked chips 200 include a logic chip at the bottom and memory chips stacked on the logic chip. The number of memory chips can be one or more. In this embodiment, an example where the number of memory chips is three is used for illustration. In other embodiments, the number of memory chips can also be other values.

[0043] As an example, in this embodiment, the HBM structure formed by multiple vertically stacked chips 200 is interconnected with external chips through an interposer. Specifically, the external chips can be central processing unit (CPU) chips, graphics processing unit (GPU) chips, or system-on-chip (SoC) chips.

[0044] In this embodiment, protective layers 300 are formed on the upper and lower surfaces of the chip 200.

[0045] The chip 200 is electrically connected through its upper and lower surfaces. The protective layer 300 is used to protect the upper and lower surfaces of the chip 200, and also to isolate the bumps on the surface of the chip 200. The protective layer 300 also serves to relieve stress and prevent the solder joints from cracking and breaking due to thermal stress and mechanical stress.

[0046] In this embodiment, the material of the protective layer 300 can be an organic material, and the organic material can be a polymer resin material, specifically including epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin.

[0047] In this embodiment, the protective layer is a polyimide (PI) layer.

[0048] In other embodiments, the protective layer 300 can also be a passivation layer. The material of the protective layer 300 can also be an inorganic material, and the inorganic material can be one or several of silicon oxide, silicon nitride, silicon oxynitride, carbon oxide silicon, and carbon nitride silicon.

[0049] It should be noted that in this embodiment, protective layers 300 are formed on the upper surface and the lower surface of the chip 200. In the longitudinally stacked chips 200, the protective layers 300 of adjacent chips 200 face each other, and there is a gap that needs to be filled with encapsulation material between the protective layers 300 of adjacent chips 200.

[0050] It should also be noted that in the HBM structure packaging process, the upper surface of the topmost chip 200 may not form a protective layer 300, and the upper surface and the lower surface of the bottommost logic chip may also not form a protective layer 300.

[0051] In this embodiment, the edge of the protective layer 300 is recessed inward relative to the corresponding edge of the chip 200.

[0052] Among them, the corresponding edge of the chip 200 refers to the edge of the chip 200 on the same side as the edge of the protective layer 300.

[0053] The edge of the protective layer 300 is recessed inward relative to the corresponding edge of the chip 200, that is, the protective layer 300 does not cover the edge of the chip 200. When encapsulating a plurality of longitudinally stacked chips 200, when the encapsulation material flows from the outside to the gap between adjacent chips 200, the inflow window is larger, which is conducive to the encapsulation material entering the gap between adjacent chips 200 for filling.

[0054] In this embodiment, the packaging structure further includes: bumps 220, which are located in the protective layers 300 on the upper surface and the lower surface of the chip 200 and penetrate the protective layers 300.

[0055] The bumps 220 are used to electrically lead out the internal circuit of the chip 200, realizing the electrical connection between the chip 200 and the chip 200, and between the chip 200 and the substrate 100.

[0056] It should also be noted that the topmost chip 200 may not be a TSV chip and there are no bumps on its upper surface.

[0057] In this embodiment, the size d of the recess of the edge of the protective layer 300 inward relative to the corresponding edge of the chip 200 is 1 / 4 to 3 / 4 of the minimum distance from the bump 220 on the edge of the chip 200 to the corresponding edge of the chip 200, so that the encapsulation material inflow window at the edges of longitudinally adjacent chips 200 is larger, and there is still enough area of the protective layer 300 on the upper surface and the lower surface of the chip 200, which is conducive to ensuring the protection effect of the protective layer 300 on the upper surface and the lower surface of the chip 200.

[0058] In this embodiment, at the edge of the protective layer 300, the side wall 302 of the protective layer 300 presents a ramp shape that slopes inward from near the chip 200 to away from the chip 200.

[0059] The side wall 302 of the protective layer 300 presents a slope shape that slopes inward from near the chip 200 to away from the chip 200, which means that the side wall of the protective layer 300 presents an acute slope.

[0060] At the edge of the protective layer 300, the side wall 302 of the protective layer 300 presents a slope shape that slopes inward from near the chip 200 to away from the chip 200. Then, in a plurality of longitudinally stacked chips 200, at the edges of the adjacent chips 200 relative to the protective layer 300, the sloped edges of the protective layer 300 that are opposite to each other form a trumpet shape, further increasing the molding compound inflow window at the edges of the longitudinally adjacent chips 200, which is further beneficial for the molding compound to enter between the adjacent chips 200 for filling.

[0061] The flow guiding groove 400 is used to guide the molding compound when molding a plurality of longitudinally stacked chips 200.

[0062] Among them, one end of the first branch flow guiding groove 430 is connected to the main flow guiding groove 410, and the other end extends obliquely forward in the mold flow direction, which means that the included angle between the extending direction of the first branch flow guiding groove 430 and the mold flow direction is an acute angle.

[0063] In this embodiment, forming the flow guiding groove 400 in the protective layer 300 is beneficial for the molding compound to fill between the adjacent chips 200 during the molding process of the stacked chips 200. In the flow guiding groove 400, the main flow guiding groove 410 penetrates the protective layer 300 along the mold flow direction, which is beneficial for increasing the filling window of the molding compound and guiding the molding compound into the space between the adjacent chips 200. One end of the first branch flow guiding groove 430 is connected to the main flow guiding groove 410, and the other end extends obliquely forward in the mold flow direction. Then, the first branch flow guiding groove 430 extends towards the inner area of the chip along the mold flow direction, that is, the first branch flow guiding groove 430 extends towards the inner area of the chip along the flow direction of the molding compound, which is beneficial for the molding compound to flow and fill between the adjacent chips 200, thus being beneficial for reducing the filling difficulty of the molding compound between the adjacent chips 200, being beneficial for improving the molding quality of the packaging structure, and further being beneficial for improving the reliability of the packaging structure.

[0064] Among them, the mold flow direction is the preset flow direction of the molding compound in the packaging molding process.

[0065] In this embodiment, taking the edge of the protective layer 300 parallel to the mold flow direction as the side edge 301, the branch flow guiding groove 420 further includes a second branch flow guiding groove 440 with one end connected to the side edge 301 and the other end extending obliquely forward in the mold flow direction.

[0066] The second branch flow guiding groove 440 is used to guide the molding compound from the side edge 301 of the protective layer 300 to the middle position of the protective layer 300.

[0067] One end of the second branch flow guiding groove 440 is connected to the side edge 301, and the other end extends obliquely forward in the mold flow direction. Then, the second branch flow guiding groove 440 extends towards the inner area of the chip along the mold flow direction, that is, the second branch flow guiding groove 440 extends towards the inside of the chip along the flow direction of the encapsulant, which is beneficial to the flow filling of the encapsulant between adjacent chips 200, and thus is beneficial to reducing the filling difficulty of the encapsulant between adjacent chips 200.

[0068] In this embodiment, the width of the branch flow guiding groove 420 gradually decreases from the connected end to the other end.

[0069] Among them, for the first branch flow guiding groove 430, the connected end refers to the end where the first branch flow guiding groove 430 is connected to the main flow guiding groove 410. For the second branch flow guiding groove 440, the connected end refers to the end where the second branch flow guiding groove 440 is connected to the side edge 301.

[0070] Since the width of the branch flow guiding groove 420 gradually decreases from the connected end to the other end, during the encapsulation process, as the encapsulant guided by the branch flow guiding groove in the opposite direction advances, the width of the branch flow guiding groove 420 gradually decreases along the extension direction, which is beneficial to uniformly filling the encapsulant in the inner area of the chip. Moreover, bumps penetrating the protective layer 300 will be formed on the upper and lower surfaces of the chip 200. The fact that the width of the branch flow guiding groove 420 gradually decreases from the connected end to the other end is also beneficial to ensuring the coverage area of the protective layer 300 around the bumps of the chip 200, and thus is beneficial to ensuring the stress relief effect of the protective layer 300.

[0071] In this embodiment, the included angle α between the extension direction of the branch flow guiding groove 420 and the mold flow direction is 25° - 65°, which makes the branch flow guiding groove 420 have a sufficient inclination tendency relative to the mold flow direction, so that the extension direction of the branch flow guiding groove 420 conforms to the mold flow direction, and is also beneficial to reducing the forming process difficulty of the branch flow guiding groove 420.

[0072] In this embodiment, the branch flow guiding grooves 420 on the same side are arranged in parallel along the mold flow direction.

[0073] Since the branch flow guiding grooves 420 on the same side are arranged in parallel along the mold flow direction, the arrangement of the branch flow guiding grooves 420 is relatively regular, which is beneficial to better uniformity of the gap filling between longitudinally adjacent chips 200 during the encapsulation process.

[0074] In this embodiment, the first branch flow guiding groove 430 and the second branch flow guiding groove 440 are separated by the protective layer 300.

[0075] The first diversion channel 430 and the second diversion channel 440 are separated by the protective layer 300, that is, the first diversion channel 430 and the second diversion channel 440 are not connected. During the plastic encapsulation process, the diversion of the plastic encapsulant by the first diversion channel 430 and the second diversion channel 440 is independent of each other, and the situation where the flow directions at the end of the plastic encapsulant interfere with each other will not occur, which is conducive to the filling of the plastic encapsulant between the chips 200.

[0076] In this embodiment, the encapsulation structure further includes: a plastic encapsulation layer 500, which covers a plurality of longitudinally stacked chips 200 and fills between adjacent chips 200 and between the chips 200 and the substrate 100.

[0077] The plastic encapsulation layer 500 covers a plurality of longitudinally stacked chips 200 and is used to protect the stacked chips 200. The plastic encapsulation layer 500 fills between adjacent chips 200 and between the chips 200 and the substrate 100 and is used for insulating and fixing between adjacent chips 200 and between the chips 200 and the substrate 100.

[0078] Specifically, in this embodiment, during the plastic encapsulation process, the plastic encapsulant flows along the mold flow direction into a plurality of longitudinally stacked chips 200, covers the plurality of longitudinally stacked chips 200, and fills between adjacent chips 200 and between the chips 200 and the substrate 100 to form the plastic encapsulation layer 500. Correspondingly, the plastic encapsulation layer 500 also fills in the diversion channels 400.

[0079] In this embodiment, the material of the plastic encapsulation layer 500 includes Liquid epoxy Molding Compound (LMC).

[0080] Figures 3 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of the encapsulation method of the present invention.

[0081] Combined with reference Figure 3 and Figure 4 , Figure 4 is Figure 3 a top view of any surface of the chip, providing the chip 200.

[0082] The chip 200 is used to meet the performance requirements of the encapsulation structure. Specifically, different functional chips 200 can be selected according to the performance requirements of the encapsulation structure.

[0083] In this embodiment, in the step of providing the chip 200, a metal layer is sputtered on the upper surface and the lower surface of the chip 200, and a metal sputtered coating 210 is formed at a preset position through an etching process.

[0084] The preset position is the position for forming bumps subsequently, and the metal sputtered coating 210 is used for electroplating to form bumps subsequently.

[0085] Combined reference Figure 5 and Figure 6 , Figure 6 is Figure 5 a top view of any surface of the chip, forming a protective layer 300 covering the upper and lower surfaces of the chip 200.

[0086] The chip 200 is electrically connected through the upper and lower surfaces. The protective layer 300 is used to protect the upper and lower surfaces of the chip 200, and is also used to isolate the bumps in the chip 200. The protective layer 300 is also used to relieve stress, avoiding circuit cracking and open circuit caused by thermal stress and mechanical stress.

[0087] In this embodiment, in the step of forming the protective layer 300 covering the upper and lower surfaces of the chip 200, the edge of the protective layer 300 parallel to the mold flow direction is used as the side edge 301, which is used as the reference edge for subsequent patterning of the protective layer 300.

[0088] In this embodiment, a deposition process is used to form the protective layer 300 covering the upper and lower surfaces of the chip 200.

[0089] Specifically, in this embodiment, the deposition process includes chemical vapor deposition (CVD) process, physical vapor deposition (PVD) process, molecular beam epitaxy (MBE) process, etc.

[0090] In this embodiment, in the step of forming the protective layer 300 covering the upper and lower surfaces of the chip 200, the protective layer 300 is a polyimide (PI) layer.

[0091] In other embodiments, in the step of forming the protective layer covering the upper and lower surfaces of the chip, the protective layer can also be a passivation layer.

[0092] Combined reference Figure 7 and Figure 8 , Figure 8 is Figure 7 a top view of any surface of the chip. The patterned protective layer 300 forms a flow guiding groove 400. The flow guiding groove 400 includes a main flow guiding groove 410 penetrating through the protective layer 300 along the mold flow direction (such as Figure 8 shown by the X direction in

[0093] ), and branch flow guiding grooves 420 arranged on the side of the main flow guiding groove 410 along the mold flow direction. The branch flow guiding grooves 420 include a first branch flow guiding groove 430 with one end connected to the main flow guiding groove 410 and the other end extending obliquely forward in the mold flow direction.

[0094] Among them, one end of the first branch flow guide groove 430 is connected to the main flow guide groove 410, and the other end extends obliquely forward in the mold flow direction, which means that the included angle between the extension direction of the first branch flow guide groove 430 and the mold flow direction is an acute angle.

[0095] In this embodiment, forming the flow guide groove 400 in the protective layer 300 is beneficial to the filling of the encapsulant between adjacent chips 200 during the encapsulation process of stacking multiple chips 200. In the flow guide groove 400, the main flow guide groove 410 penetrates the protective layer 300 along the mold flow direction, which is beneficial to increasing the filling window of the encapsulation and guiding the encapsulant into the space between adjacent chips 200. One end of the first branch flow guide groove 430 is connected to the main flow guide groove 410, and the other end extends obliquely forward in the mold flow direction. Then, the first branch flow guide groove 430 extends towards the inner area of the chip along the mold flow direction, that is, the first branch flow guide groove 430 extends towards the inner area of the chip along the flow direction of the encapsulant, which is beneficial to the flow filling of the encapsulant between adjacent chips 200, thus facilitating the reduction of the filling difficulty of the encapsulant between adjacent chips 200, improving the encapsulation quality of the packaging structure, and further enhancing the reliability of the packaging structure.

[0096] Among them, the mold flow direction is the preset flow direction of the encapsulant in the encapsulation process.

[0097] In this embodiment, in the step of forming the flow guide groove 400 in the patterned protective layer 300, the branch flow guide groove 420 further includes a second branch flow guide groove 440 with one end connected to the side edge 301 and the other end extending obliquely forward in the mold flow direction.

[0098] The second branch flow guide groove 440 is used to divert the encapsulant from the side edge 301 of the protective layer 300 to the middle position of the protective layer 300.

[0099] One end of the second branch flow guide groove 440 is connected to the side edge 301 and the other end extends obliquely forward in the mold flow direction. Then, the second branch flow guide groove 440 extends towards the inner area of the chip along the mold flow direction, that is, the second branch flow guide groove 440 extends towards the inner area of the chip along the flow direction of the encapsulant, which is beneficial to the flow filling of the encapsulant between adjacent chips 200, thus facilitating the reduction of the filling difficulty of the encapsulant between adjacent chips 200.

[0100] In this embodiment, in the step of forming the flow guide groove 400 in the patterned protective layer 300, the width of the branch flow guide groove 420 gradually decreases from the connected end to the other end.

[0101] Among them, for the first branch flow guide groove 430, the connected end refers to the end where the first branch flow guide groove 430 is connected to the main flow guide groove 410. For the second branch flow guide groove 440, the connected end refers to the end where the second branch flow guide groove 440 is connected to the side edge 301.

[0102] The width of the branch diversion groove 420 gradually decreases from one end connected to the other end. During the encapsulation process, as the encapsulant flowing through the branch diversion grooves in the opposite directions advances, the width of the branch diversion groove 420 gradually decreases along the extension direction, conforming to the flow rate of the encapsulant, which is conducive to uniform filling of the encapsulant in the internal area of the chip. Moreover, bumps penetrating the protective layer 300 will be formed on the upper and lower surfaces of the chip 200. The width of the branch diversion groove 420 gradually decreasing from one end connected to the other end is also conducive to ensuring the coverage area of the protective layer 300 around the bumps of the chip 200, thereby facilitating the stress relief effect of the protective layer 300.

[0103] In this embodiment, in the step of forming the diversion groove 400 in the patterned protective layer 300, the included angle α between the extension direction of the branch diversion groove 420 and the mold flow direction is 25° to 65°, so that the branch diversion groove 420 has a sufficient inclination tendency relative to the mold flow direction, enabling the branch diversion groove 420 to extend towards the internal area of the chip along the mold flow direction, and also facilitating the reduction of the formation process difficulty of the branch diversion groove 420.

[0104] In this embodiment, in the step of forming the diversion groove 400 in the patterned protective layer 300, the branch diversion grooves 420 on the same side are arranged in parallel along the mold flow direction.

[0105] The branch diversion grooves 420 on the same side are arranged in parallel along the mold flow direction, so that the arrangement of the branch diversion grooves 420 is relatively regular, which is conducive to better uniformity of the gap filling between the longitudinally adjacent chips 200 during the encapsulation process.

[0106] In this embodiment, in the step of forming the diversion groove 400 in the patterned protective layer 300, the first branch diversion groove 430 and the second branch diversion groove 440 are separated by the protective layer 300.

[0107] The first branch diversion groove 430 and the second branch diversion groove 440 are separated by the protective layer 300, that is, the first branch diversion groove 430 and the second branch diversion groove 440 are not connected. During the encapsulation process, the diversion of the encapsulant by the first branch diversion groove 430 and the second branch diversion groove 440 is independent of each other, and there will be no situation where the flow directions at the end of the encapsulant interfere with each other, thereby facilitating the filling of the encapsulant between the chips.

[0108] In this embodiment, in the step of forming the diversion groove 400 in the patterned protective layer 300, it further includes: removing a part of the protective layer 300 with a width d from the edge of the protective layer 300.

[0109] Remove the protective layer 300 with a partial width d from the edge of the protective layer 300, that is, the protective layer 300 is not covered at the edge of the chip 200. Then, when encapsulating multiple longitudinally stacked chips 200 later, when the encapsulant flows from the outside into the gap between adjacent chips 200, the inflow window is larger, which is beneficial for the encapsulant to enter the gap between adjacent chips 200 for filling.

[0110] In this embodiment, in the step of removing the protective layer 300 with a partial width d from the edge of the protective layer 300, the width d of the removed protective layer 300 is 1 / 4 to 3 / 4 of the minimum distance from the bump 220 at the edge of the chip 200 to the corresponding edge of the chip 200. This makes the encapsulant inflow window at the edges of longitudinally adjacent chips 200 larger, and also ensures that there is still sufficient area of the protective layer 300 on the upper and lower surfaces of the chip 200, which is beneficial for ensuring the protective effect of the protective layer 300 on the upper and lower surfaces of the chip 200.

[0111] In this embodiment, in the step of forming the diversion groove 400 by patterning the protective layer 300, it further includes: at the edge of the patterned protective layer 300, so that the side wall 302 of the protective layer 300 presents a slope shape that slopes inward from near the chip 200 to far from the chip 200.

[0112] The side wall 302 of the protective layer 300 presenting a slope shape that slopes inward from near the chip 200 to far from the chip 200 means that the side wall of the protective layer 300 presents an acute slope.

[0113] At the edge of the protective layer 300, the side wall 302 of the protective layer 300 presents a slope shape that slopes inward from near the chip 200 to far from the chip 200. Then, in multiple longitudinally stacked chips 200, at the relative edges of adjacent chips 200 with respect to the protective layer 300, the relative sloped edges of the protective layer 300 form a horn shape, further increasing the encapsulant inflow window at the edges of longitudinally adjacent chips 200, and further facilitating the encapsulant to enter the gap between adjacent chips 200 for filling.

[0114] In this embodiment, in the step of forming the diversion groove 400 by patterning the protective layer 300, it further includes: patterning the protective layer 300 to form a groove 450 exposing the surface of the chip 200.

[0115] The groove 450 is used to provide a spatial position for forming bumps. Specifically, a groove 450 exposing the metal sputtering layer 210 is formed at a preset position of the chip 200.

[0116] In this embodiment, the protective layer 300 is patterned by an etching process.

[0117] Refer to Figure 9 , Figure 9 For Figure 8Corresponding top view. After the graphical protection layer 300 forms the diversion groove 400, it further includes: forming bumps 220 in the grooves 450.

[0118] The bumps 220 are used to electrically lead out the internal circuit of the chip 200, realizing the electrical connection between the chip 200 and the chip 200, as well as between the chip 200 and the substrate 100.

[0119] In this embodiment, the bumps 220 are formed in the grooves 450 by an electroplating process.

[0120] Specifically, in this embodiment, only a metal sputtering layer is formed on the surface of the chip 200 exposed by the diversion groove 400 and the groove 450 in the protection layer 300 at the position of the groove 450. Therefore, when using the electroplating process, the bumps 220 are only formed in the grooves 450, and the diversion grooves 400 will not be filled.

[0121] Refer to Figure 10 , a substrate 100 is provided.

[0122] The substrate 100 is used to provide a process operation basis for realizing the bonding of the chip 200.

[0123] In this embodiment, the substrate 100 is an interposer.

[0124] Using the interposer to interconnect and package multiple stacked chips 200 is used to electrically lead out the multiple stacked chips 200, realizing the electrical connection between the multiple stacked chips 200 and the outside.

[0125] Refer to Figure 11 , multiple chips 200 are longitudinally stacked and bonded to the substrate 100.

[0126] In this embodiment, the multiple longitudinally stacked chips 200 are electrically connected to each other.

[0127] As an example, in this embodiment, the multiple longitudinally stacked chips 200 form a High Bandwidth Memory (HBM) structure. By adopting the HBM structure, it is beneficial to meet the requirements for higher information transmission speed.

[0128] Among them, the multiple longitudinally stacked chips 200 include a logic chip located at the bottom and memory chips stacked on the logic chip. The number of memory chips can be one or more. In this embodiment, the number of memory chips is taken as three as an example for illustration. In other embodiments, the number of memory chips can also be other numbers.

[0129] As an example, in this embodiment, an HBM structure composed of a plurality of vertically stacked chips 200 is interconnected with external chips through an interposer. Specifically, the external chips can be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or a system-on-chip (SoC).

[0130] It should be noted that in this embodiment, protective layers 300 are formed on the upper and lower surfaces of the chips 200. In the vertically stacked chips 200, the protective layers 300 of adjacent chips 200 face each other, and there is a gap to be filled with encapsulation material between the protective layers 300 of adjacent chips 200.

[0131] It should also be noted that in the HBM structure packaging process, the protective layer 300 may not be formed on the upper surface of the topmost chip 200, and the protective layer 300 may not be formed on the upper and lower surfaces of the bottommost logic chip either.

[0132] With reference to Figure 12 and Figure 13 , Figure 13 For Figure 12 a top view of any surface of the chip, after bonding a plurality of vertically stacked chips 200 to the substrate 100, the packaging method further includes: forming a molding compound layer 500 that covers the vertically stacked plurality of chips 200, and the molding compound layer 500 also fills the space between adjacent chips 200 and between the chips 200 and the substrate 100.

[0133] The molding compound layer 500 covers the vertically stacked plurality of chips 200 and serves to protect the stacked chips 200. The molding compound layer 500 fills the space between adjacent chips 200 and between the chips 200 and the substrate 100 to insulate between adjacent chips 200 and between the chips 200 and the substrate 100. The molding compound layer 500 also serves to interconnect and form the vertically stacked plurality of chips 200.

[0134] Specifically, in this embodiment, during the molding process, the molding compound flows in the mold flow direction into the vertically stacked plurality of chips 200, covers the vertically stacked plurality of chips 200, and fills the space between adjacent chips 200 and between the chips 200 and the substrate 100 to form the molding compound layer 500. Correspondingly, the molding compound layer 500 also fills the flow guide grooves 400.

[0135] In this embodiment, the material of the molding compound layer 500 includes liquid epoxy molding compound (LMC).

[0136] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A packaging structure, characterized in that: include: substrate; A plurality of chips stacked vertically are bonded to the substrate, and a protective layer is formed on the upper and lower surfaces of the chips; A guide groove is located in the protective layer, and the guide groove includes a main guide groove that penetrates the protective layer along the mold flow direction, and a branch guide groove arranged on the side of the main guide groove along the mold flow direction, and the branch guide groove includes a first branch guide groove, one end of which is connected to the main guide groove and the other end of which extends obliquely forward in the mold flow direction.

2. The packaging structure according to claim 1, characterized in that: The edge of the protective layer parallel to the mold flow direction is taken as the side edge, and the branch guide groove further includes a second branch guide groove, one end of which is connected to the side edge and the other end of which extends obliquely forward in the mold flow direction.

3. The packaging structure according to claim 1 or 2, characterized in that: The width of the branch diversion groove gradually decreases from one connected end to the other end.

4. The packaging structure according to claim 1 or 2, characterized in that: The included angle between the extension direction of the branch guide groove and the mold flow direction is 25° to 65°.

5. The packaging structure according to claim 1 or 2, characterized in that: The branch guide grooves are arranged in parallel along the mold flow direction.

6. The packaging structure according to claim 2, characterized in that: The first branch guide groove and the second branch guide groove are separated by the protective layer.

7. The packaging structure according to claim 1, characterized in that: The packaging structure further includes bumps, which are located in the protection layers on the upper and lower surfaces of the chip and penetrate through the protection layers.

8. The packaging structure according to claim 7, characterized in that: The edge of the protection layer is recessed inward relative to the corresponding edge of the chip.

9. The packaging structure according to claim 8, characterized in that: The dimension of the edge of the protection layer being recessed inward relative to the corresponding edge of the chip is 1 / 4 to 3 / 4 of the minimum distance from the bump at the edge of the chip to the corresponding edge of the chip.

10. The packaging structure according to claim 1, wherein: At the edge of the protection layer, the side wall of the protection layer is in a slope shape from close to the chip to away from the chip and inward.

11. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: a plastic packaging layer, which covers the plurality of chips stacked vertically and is filled between adjacent chips and between the chip and the substrate.

12. A packaging method, characterized in that: include: Provide chips; forming a protective layer covering the upper and lower surfaces of the chip; The protective layer is patterned to form a guide groove, wherein the guide groove includes a main guide groove penetrating the protective layer along a mold flow direction, and a branch guide groove arranged on the side of the main guide groove along the mold flow direction, wherein the branch guide groove includes a first branch guide groove having one end connected to the main guide groove and the other end extending obliquely forward in the mold flow direction; providing a substrate; A plurality of the chips are stacked and bonded on the substrate along a longitudinal direction.

13. The packaging method according to claim 12, characterized in that: In the step of forming a protective layer on the upper surface and the lower surface of the chip, the edge of the protective layer parallel to the mold flow direction is taken as the side edge; In the step of patterning the protective layer to form a guide groove, the branch guide groove further includes a second branch guide groove having one end connected to the side edge and the other end extending obliquely forward in the mold flow direction.

14. The packaging method according to claim 12 or 13, characterized in that: In the step of patterning the protection layer to form the guide groove, the width of the branch guide groove gradually decreases from one connected end to the other end.

15. The packaging method according to claim 12 or 13, characterized in that: In the step of patterning the protective layer to form guide grooves, the branch guide grooves on the same side are arranged in parallel along the mold flow direction.

16. The packaging method according to claim 13, characterized in that: In the step of patterning the protective layer to form the guide groove, the first branch guide groove and the second branch guide groove are separated by the protective layer.

17. The packaging method according to claim 12, characterized in that: The step of patterning the protective layer to form the guide groove further includes: removing a portion of the width of the protective layer from the edge of the protective layer.

18. The packaging method according to claim 12, characterized in that: The step of patterning the protective layer to form the guide groove further includes: patterning the edge of the protective layer so that the side wall of the protective layer presents a slope from close to the chip to away from the chip and inward.

19. The packaging method according to claim 12, characterized in that: The step of patterning the protective layer to form a guide groove further includes: patterning the protective layer to form a groove exposing the surface of the chip; After patterning the protection layer to form the guide groove, the method further includes: forming a bump in the groove.

20. The packaging method according to claim 12, characterized in that: After the plurality of chips are stacked and bonded on the substrate in a longitudinal direction, the packaging method further comprises: forming a plastic encapsulation layer covering the plurality of chips stacked in a longitudinal direction, wherein the plastic encapsulation layer is also filled between adjacent chips and between the chip and the substrate.

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