Photoelectric co-packaging high-density 3D stacked fan-out packaging structure

Abstract

The invention provides a photoelectric co-packaging high-density 3D stacked fan-out packaging structure, which comprises a first glass-based intermediate layer, a second glass-based intermediate layer, a glass substrate and a PCB, an HBM chip and a Si Photonics chip are embedded in the first glass-based intermediate layer, an SOIC chip is embedded in the front surface of the second glass-based intermediate layer, and the front surface of the second glass-based intermediate layer is provided with an SOIC chip. An LSI chip, an IVR chip and an EDTA chip which are adjacently arranged in the horizontal direction are embedded into the back surface of the second glass-based intermediate layer, the first glass-based intermediate layer is inversely arranged on the second glass-based intermediate layer and then inversely arranged on the glass substrate and the PCB, micro-channels are respectively arranged on the first glass-based intermediate layer, the second glass-based intermediate layer, the glass substrate and the PCB, and the micro-channels are communicated with one another. According to the invention, the 3D stacking interconnection density and transmission rate are improved, the signal delay is reduced, the packaging volume is reduced, and the high-density, high-speed and low-delay interconnection requirements of high-frequency and high-speed electronic equipment are met; and meanwhile, the novel liquid cooling micro-channel is adopted to assist the heat dissipation cover to dissipate heat, so that a better heat dissipation effect is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of advanced packaging products, and more specifically to an optoelectronic co-packaging high-density 3D stacked fan-out packaging structure. Background Art

[0002] In the field of semiconductor packaging technology, the demand for ultra-low signal loss factor, ultra-high density, ultra-high speed, ultra-low latency, and ultra-many interconnected chips in high-frequency field equipment chips such as communications, high-speed computing, and AI supercomputing has increased. Therefore, 3D packaging has become the focus of current industry attention. Compared with 2.5D packaging, the principle of 3D packaging is to make a transistor structure on the chip, and use perforations to connect the electronic signals of different chips above and below, so as to directly stack memory or other chips vertically on it. 3D packaging has a smaller area and lower power consumption, and is used for ultra-large bandwidth. However, how to solve the insulation problem under ultra-high density wiring, the heat accumulation problem of ultra-high density chips, and realize ultra-multi-chip packaging have become important challenges.

[0003] On the one hand, in the traditional 3D optoelectronic co-packaging structure, the photonic integrated circuit (PIC) and the electronic integrated circuit (EIC) are stacked vertically. The chip in the middle is limited by the packaging structure and can only conduct heat between chips. The heat dissipation efficiency is low, and the heat accumulation inside the chip is serious, which affects the chip's working efficiency. Since the EIC is stacked directly on top of the PIC, the heat generated by the EIC will be transferred to the PIC, which will affect the performance of some optical devices. In addition, the traditional heat dissipation method only contacts the top of the chip, and only the top of the chip that contacts can effectively dissipate heat.

[0004] In traditional 2D-MCM optoelectronic packaging, the number of interconnections between EIC and PIC is limited (wire bonding can only be performed on the adjacent side of PIC and EIC). Therefore, the 2D-MCM solution is not suitable for application scenarios with a high number of IOs.

[0005] In the traditional 2.5D optoelectronic packaging structure, the high-speed signal interconnecting the EIC and PIC needs to pass through two bumps, which will have a certain impact on the broadband performance of the signal.

[0006] On the other hand, existing silicon interposer circuit signal transmission has insulation problems, with large signal attenuation, loss and large incident signal loss. The silicon-based interposer process is complex and leads to high costs. Due to the large warping, it is impossible to have ultra-thin thickness and large size, which affects the packaging capacity of ultra-large size and ultra-multiple chips, and the cost is relatively high.

[0007] Furthermore, traditional embedded packaging is mainly embedded in substrates and PCBs, and is limited by the process capabilities of substrates and PCBs, resulting in low interconnection density, long transmission paths, low transmission rates, large signal delays, and large packaging volumes. It cannot meet the high-density, high-speed, and low-latency interconnection requirements of high-frequency and high-speed electronic devices.

[0008] Therefore, there is an urgent need for a new 3D packaging structure to solve the above problems. Summary of the Invention

[0009] To solve the above problems, the present invention provides an optoelectronic co-packaged high-density 3D stacked fan-out packaging structure, which realizes 3D stacking and interconnection of chips through glass-based via technology and embedded packaging technology. It can achieve high-density I / O interconnection between EIC and PIC at a relatively low cost, realize an ultra-short transmission path between chips, improve the 3D stacking interconnection density and transmission rate, reduce signal delay, reduce the packaging volume, and meet the high-density, high-speed, and low-latency interconnection requirements of high-frequency and high-speed electronic devices; at the same time, a new liquid-cooled microchannel-assisted heat dissipation cover is used for heat dissipation, which has a good heat dissipation effect.

[0010] The present invention provides an optoelectronic co-packaged high-density 3D stacked fan-out packaging structure, which includes a first glass-based interposer, a second glass-based interposer, a glass substrate, and a PCB board. The first glass-based interposer is embedded with an HBM chip and a SiPhotonics chip. The front of the second glass-based interposer is embedded with a SOIC chip, and the SOIC chip is composed of a SOC chip and an IC chip stacked vertically. The back of the second glass-based interposer is embedded with an LSI chip, an IVR chip, and an EDTC chip arranged adjacent to each other horizontally. After the first glass-based interposer is flip-chip mounted on the second glass-based interposer, it is then flip-chip mounted on the glass substrate and the PCB board. Microchannels are respectively arranged on the first glass-based interposer, the second glass-based interposer, the glass substrate, and the PCB board, and the microchannels are interconnected with each other.

[0011] Preferably, the first glass-based interposer is provided with a first microchannel, an HBM chip pre-set cavity, a Si Photonics chip pre-set cavity, and a plurality of first conductive vias. The HBM chip pre-set cavity and the Si Photonics chip pre-set cavity are arranged adjacent to each other horizontally on the front of the first glass-based interposer. The first microchannel is arranged below the HBM chip pre-set cavity and the SiPhotonics chip pre-set cavity. The first microchannel is provided with a plurality of first connection ports extending to the back of the first glass-based interposer. The HBM chip is embedded in the HBM chip pre-set cavity, and the SiPhotonics chip is embedded in the Si Photonics chip pre-set cavity. The HBM chip and the Si Photonics chip are interconnected through the first conductive vias.

[0012] Preferably, the first glass-based interposer is divided into a bonded first base glass layer and a first top glass layer. A first microchannel is provided on the first base glass layer, and an HBM chip pre-set cavity and an Si Photonics chip pre-set cavity are provided on the first top glass layer. A first conductive through-hole is formed at the same position of the first base glass layer and the first top glass layer.

[0013] Preferably, the second glass-based interposer is provided with a second microchannel, an SOIC chip pre-set cavity, an LSI chip pre-set cavity, an IVR chip pre-set cavity, an EDTC chip pre-set cavity, and a plurality of second conductive through-holes. Each chip pre-set cavity is embedded with a corresponding chip, and interconnection is achieved through the second conductive through-holes. The second microchannel is arranged in the middle of the double-sided chip layer of the second glass-based interposer. The second microchannel is provided with a plurality of second connection ports extending to the front of the second glass-based interposer, and the second connection ports are communicated with the first connection ports. The second microchannel is also provided with a third connection port extending to the back of the second glass-based interposer.

[0014] Preferably, the glass substrate is provided with a substrate circuit layer, a substrate microchannel, and a substrate conductive through-hole; substrate circuit layers are provided on both the front and back of the glass substrate. The substrate microchannel is horizontally arranged in the middle of the glass substrate. The substrate microchannel is provided with a first substrate connection port extending to the front of the glass substrate and a second substrate connection port extending to the back of the glass substrate. The first substrate connection port is correspondingly communicated with the third connection port; a capacitor is connected to the substrate circuit layer on the front of the glass substrate.

[0015] Preferably, the PCB board is provided with a coolant inlet and a coolant outlet. The substrate circuit layer on the back of the glass substrate is connected to the PCB board. There are two second substrate connection ports, which respectively correspond to communicate with the coolant inlet and the coolant outlet. The coolant inlet is communicated with a coolant supply device.

[0016] Preferably, the first glass-based interposer, the second glass-based interposer, and the glass substrate are all made of glass.

[0017] Compared with the prior art, the beneficial effects of the present invention are: The present invention realizes 3D stacking interconnection of chips through glass-based through-hole technology and embedded packaging technology, can achieve high-density I / O interconnection between EIC and PIC at a relatively low cost, realize an ultra-short transmission path between chips, improve the 3D stacking interconnection density and transmission rate, reduce signal delay, and reduce the package volume.

[0018] The present invention manufactures microchannels in a first glass-based interposer, a second glass-based interposer, and a glass substrate. The microchannels pass through the entire 3D package and are connected. The microchannels are in direct contact with the backs of each chip. Liquid cooling is used to directly dissipate heat from the chip in the middle of the 3D package, thereby improving the heat dissipation capacity of the package and thus improving chip performance. The requirements for ultra-high density and high heat generation chip design and packaging of high-frequency and high-speed electronic equipment are met, and the working performance of high-performance chips is improved.

[0019] The present invention uses glass insulator as the base material of the interposer and substrate of 3D packaging. Compared with silicon-based materials, the glass adapter plate has the advantage of being easy to obtain large-size ultra-thin panel glass and not requiring the deposition of an insulating layer. The production cost of the glass adapter plate is only about 1 / 8 of that of the silicon-based interposer. The ultra-thin adapter plate does not require a thinning process, and the packaging process is simple, which can effectively reduce the cost of 3D packaging. The glass substrate substrate loss and parasitic effects are greatly reduced, ensuring the integrity of the transmission signal and reducing the signal loss factor. Based on this advantage, a higher density of wiring interconnection is achieved, and it has excellent electrical, thermal, and mechanical properties. It has good mechanical stability. Even when the thickness of the adapter plate is less than 100µm, the warping performance is good, and it has the advantage of low warping. It can achieve ultra-large area packaging with ultra-large size and ultra-thin packaging thickness, thereby achieving ultra-multi-chip packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic diagram of a stacked packaging structure in the present invention; Figure 2 is a schematic structural diagram of the first glass-based interposer in the present invention; Figure 3 is a schematic structural diagram of the second glass-based interposer in the present invention; Figure 4 It is a schematic diagram of the structure of the SOIC chip in the present invention; Figure 5 is a schematic structural diagram of a glass substrate in the present invention; Figure 6 It is a structural schematic diagram of the PCB board in the present invention; Figure 7 is a schematic diagram of a structure in which a second glass-based interposer is invertedly mounted on a first glass-based interposer in the present invention; Figure 8 Yes Figure 7 Schematic diagram of the structure that is flipped on a glass substrate.

[0021] Label description: PCB board 1; coolant inlet 101; coolant outlet 102; glass substrate 2; base glass layer 21; top glass layer 22; substrate circuit layer 201; substrate microchannel 202; substrate conductive via 203; first substrate connection port 204; second substrate connection port 205; first glass-based interposer 3; first base glass layer 31; first top glass layer 32; first microchannel 301; HBM chip pre-set cavity 302; Si Photonics chip pre-set cavity 303; first conductive via 304; first connection port 305; second glass-based interposer 4; second base glass layer 41; second top glass layer 42; second microchannel 401; SOIC chip pre-set cavity 402; LSI chip pre-set cavity 403; IVR chip pre-set cavity 404; EDTC chip pre-set cavity 405; second conductive via 406; second connection port 407; third connection port 408; copper pillar 409; RDL circuit layer 410; HBM chip 5; SiPhotonics chip 6; SOIC chip 7; SOC chip 701; IC chip 702; LSI chip 8; IVR chip 9; EDTC chip 10. Detailed implementation manners

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Components of the embodiments of the present invention described and illustrated herein can be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0024] In the present invention, the first glass-based interposer 3, the second glass-based interposer 4, and the glass substrate 2 are all made of glass. Glass insulators are used as the interposer and the base material of the substrate for 3D packaging. Compared with silicon-based materials, using a glass-based interposer, compared with a silicon-based interposer, benefiting from the easy availability of large-size ultra-thin panel glass and the need not to deposit an insulating layer, the manufacturing cost of the glass interposer is only about 1 / 8 of that of the silicon-based interposer. The ultra-thin interposer does not require a thinning process, and the packaging process flow is simple, which can effectively reduce the 3D packaging cost.

[0025] As Figure 1As shown in the figure, the present invention provides an optoelectronic co-packaged high-density 3D stacked fan-out package structure, which includes a first glass-based interposer 3, a second glass-based interposer 4, a glass substrate 2, and a PCB board 1.

[0026] The first glass-based interposer 3 is embedded with an HBM chip 5 and a Si Photonics chip 6. The front side of the second glass-based interposer 4 is embedded with a SOIC chip 7, and the SOIC chip 7 is composed of a SOC chip 701 and an IC chip 702 stacked vertically. The back side of the second glass-based interposer 4 is embedded with an LSI chip 8, an IVR chip 9, and an EDTC chip 10 arranged adjacent to each other horizontally. After the first glass-based interposer 3 is flip-chip mounted on the second glass-based interposer 4, it is then flip-chip mounted on the glass substrate 2 and the PCB board 1. Microchannels are respectively arranged on the first glass-based interposer 3, the second glass-based interposer 4, the glass substrate 2, and the PCB board 1, and the microchannels are interconnected with each other.

[0027] As Figure 2 shown in FIGS. 2a, 2b, 2c, 2d, and 2e, the first glass-based interposer 3 is provided with a first microchannel 301, an HBM chip pre-set cavity 302, a Si Photonics chip pre-set cavity 303, and a plurality of first conductive vias 304. In this embodiment, the first glass-based interposer 3 is divided into a bonded first base glass layer 31 and a first top glass layer 32. Before bonding, the first microchannel 301 is formed on the first base glass layer 31 by drilling or etching technology, and the HBM chip pre-set cavity 302 and the Si Photonics chip pre-set cavity 303 are formed on the first top glass layer 32 by drilling or etching technology. The first conductive vias 304 are formed at the same positions on the first base glass layer 31 and the first top glass layer 32. The HBM chip pre-set cavity 302 and the Si Photonics chip pre-set cavity 303 are arranged adjacent to each other horizontally on the front side (on the first top glass layer 32) of the first glass-based interposer 3. The first microchannel 301 is arranged below the HBM chip pre-set cavity 302 and the Si Photonics chip pre-set cavity 303 (it can also be arranged on the first base glass layer 31). The first microchannel 301 is provided with a plurality of first connection ports 305 extending to the back side (the first base glass layer 31) of the first glass-based interposer 3, and the first connection ports 305 are prepared by drilling or etching technology. Multiple first connection ports 305 can be set as needed. The HBM chip 5 is embedded in the HBM chip pre-set cavity 302, and the Si Photonics chip 6 is embedded in the Si Photonics chip pre-set cavity 303. The HBM chip 5 and the Si Photonics chip 6 are interconnected through the first conductive vias 304. According to actual needs, the length of the first connection port 305 can be increased to facilitate subsequent connection.

[0028] AsFigure 3 As shown in 3a, 3b, 3c, 3d, and 3e, in specific implementation, the second glass-based interposer 4 is also composed of a bonded second substrate glass layer 41 and a second top glass layer 42. The second microchannel 401, LSI chip 8, IVR chip 9, and EDTC chip 10 are embedded in the second substrate glass layer 41, and the SOIC chip 7 is embedded in the second top glass layer 42.

[0029] The second glass-based interposer 4 is provided with a second microchannel 401, a SOIC chip preformed cavity 402, an LSI chip preformed cavity 403, an IVR chip preformed cavity 404, an EDTC chip preformed cavity 405, and a plurality of second conductive vias 406. Each chip preformed cavity embeds a corresponding chip and realizes interconnection through the second conductive vias 406. The formation of each chip preformed cavity and the second microchannel 401 is the same as that of the first glass-based interposer 3 and will not be elaborated here. The second microchannel 401 is arranged in the middle of the double-sided chip layer of the second glass-based interposer 4. The second microchannel 401 is provided with a plurality of second connection ports 407 extending to the front of the second glass-based interposer 4. The second connection ports 407 communicate with the first connection ports 305. The second microchannel 401 is also provided with third connection ports 408 extending to the back of the second glass-based interposer 4. The second connection ports 407 and third connection ports 408 are prepared by drilling or etching technology.

[0030] As Figure 4 shown in 4a, 4b, 4c, and 4d, the SOIC chip 7 is composed of a SOC chip 701 and an IC chip 702 stacked vertically. The specific preparation process is as follows: First, metal bumps are formed on the SOC chip 701 and the IC chip 702 respectively. The SOC chip 701 is flip-chip mounted on the top of the IC chip 702. Copper pillars 409 are prepared on the remaining metal bumps of the IC chip 702 by photolithography electroplating process, and the SOC chip 701 and all metal bumps and copper pillars 409 are coated with a molding compound 703. After molding, the SOIC chip 7 is formed and then embedded into the SOIC chip preformed cavity 402 of the second top glass layer 42 to form the structure as Figure 3 shown in e.

[0031] After the LSI chip 8, IVR chip 9, and EDTC chip 10 are embedded in the LSI chip preformed cavity 403, IVR chip preformed cavity 404, and EDTC chip preformed cavity 405 of the second substrate glass layer 41, a dielectric layer and an RDL circuit layer 410 interconnected with the metal bumps and copper pillars 409 of the SOIC chip 7 are prepared on the surface of the second top glass layer 42 by photolithography electroplating process. Finally, metal bumps are prepared on the surface of the RDL circuit layer 410 for subsequent interconnection with the circuit layer of the glass substrate 2.

[0032] As Figure 5As shown in the figure, the glass substrate 2 is provided with a substrate circuit layer 201, a substrate microchannel 202, and a substrate conductive via 203. In a specific implementation, the glass substrate 2 is also composed of a bonded base glass layer 21 and a top glass layer 22. Substrate circuit layers 201 are provided on both the front side (the surface of the base glass layer 21) and the back side (the surface of the top glass layer 22) of the glass substrate 2. The two substrate circuit layers 201 are interconnected through the substrate conductive vias 203. The substrate microchannel 202 is horizontally arranged in the middle of the glass substrate 2 (it can be arranged on the base glass layer 21, or on the top glass layer 22, or the substrate microchannel 202 can be formed by combining partial grooves provided on the base glass layer 21 and the top glass layer 22). The substrate microchannel 202 is provided with a first substrate connection port 204 extending to the substrate circuit layer 201 on the surface of the base glass layer 21, and a second substrate connection port 205 extending to the substrate circuit layer 201 on the surface of the top glass layer 22. The first substrate connection port 204 corresponds to and communicates with the third connection port 408. The first substrate connection port 204 and the second substrate connection port 205 are prepared by drilling or etching techniques.

[0033] As Figure 6 shown, the PCB board 1 is provided with a coolant inlet 101 and a coolant outlet 102. The substrate circuit layer 201 on the back side of the glass substrate 2 is connected to the PCB board 1. There are two second substrate connection ports 205, which respectively correspond to and communicate with the coolant inlet 101 and the coolant outlet 102. The coolant inlet 101 is connected to a coolant supply device.

[0034] After the first glass-based interposer 3, the second glass-based interposer 4, the glass substrate 2, and the PCB board 1 are prepared, first, the first glass-based interposer 3 is flip-chip mounted on the second glass-based interposer 4, so that the second connection port 407 communicates with the first connection port 305. Through a bottom filling device, the Bump connection area is filled with Fill, as Figure 7 shown in 7a; then, a dielectric layer, an RDL circuit layer, and metal bumps are processed on the surface of the second glass-based interposer 4 through photolithography and electroplating processes, and the height of the third connection port 408 is increased as needed, as Figure 7 shown in 7b.

[0035] Then, it is flip-chip mounted on the glass substrate 2 again, so that the first substrate connection port 204 corresponds to and communicates with the third connection port 408; a capacitor 206 is connected to the substrate circuit layer 201 on the surface of the base glass layer 21. Components are mounted on the back side of the glass substrate 2 by backside ball mounting, and then solder balls are welded to the back side of the glass substrate 2 through a ball mounting process, as Figure 8 shown.

[0036] Finally, the above-mentioned glass substrate 2 is integrally welded to the PCB board 1, and the two second substrate connection ports 205 respectively correspond to and communicate with the coolant inlet 101 and the coolant outlet 102. The coolant inlet 101 and the coolant outlet 102 are connected to a coolant supply device, such as an external circulation pump body (not shown in the figure), to form a stacked package structure as shown in Figure 1 The blue part in Figure 1 is the microchannel structure for heat dissipation. In the stacked package structure, the external circulation pump body causes the coolant to be introduced from the coolant inlet 101 into the second substrate connection port 205 on the left side of the back surface of the glass substrate 2, flow into the cooling channels in the first glass-based interposer 3 and the second glass-based interposer 4, and finally flow out from the second substrate connection port 205 on the right side of the back surface of the glass substrate 2 and out from the coolant outlet 102.

Claims

1. An optoelectronic co-packaging high-density 3D stacked fan-out packaging structure, characterized in that: The invention comprises a first glass-based interposer, a second glass-based interposer, a glass substrate and a PCB board, wherein an HBM chip and a SiPhotonics chip are embedded in the first glass-based interposer, an SOIC chip is embedded on the front of the second glass-based interposer, and the SOIC chip is composed of a SOC chip and an IC chip stacked in a vertical direction, and an LSI chip, an IVR chip and an EDTC chip arranged adjacent to each other in a horizontal direction are embedded on the back of the second glass-based interposer, the first glass-based interposer is inverted onto the second glass-based interposer, and then is inverted onto the glass substrate and the PCB board, and microchannels are respectively arranged on the first glass-based interposer, the second glass-based interposer, the glass substrate and the PCB board, and the microchannels are interconnected.

2. The packaging structure according to claim 1, characterized in that: The first glass-based interposer is provided with a first microchannel, an HBM chip preset cavity, a Si Photonics chip preset cavity and a plurality of first conductive through holes. The HBM chip preset cavity and the Si Photonics chip preset cavity are arranged adjacent to each other in a horizontal direction on the front side of the first glass-based interposer. The first microchannel is arranged below the HBM chip preset cavity and the Si Photonics chip preset cavity. The first microchannel is provided with a plurality of first connection ports extending to the back side of the first glass-based interposer. An HBM chip is embedded in the HBM chip preset cavity, and a Si Photonics chip is embedded in the Si Photonics chip preset cavity. The HBM chip and the Si Photonics chip are interconnected through the first conductive through holes.

3. The packaging structure according to claim 2, characterized in that: The first glass-based intermediate layer is divided into a bonded first base glass layer and a first top glass layer, the first base glass layer is provided with a first microchannel, the first top glass layer is provided with an HBM chip pre-cavity and a Si Photonics chip pre-cavity, and a first conductive through hole is formed at the same position of the first base glass layer and the first top glass layer.

4. The packaging structure according to claim 3, characterized in that: The second glass-based interposer is provided with a second microchannel, a SOIC chip pre-cavity, an LSI chip pre-cavity, an IVR chip pre-cavity, an EDTC chip pre-cavity and a plurality of second conductive through holes, each chip pre-cavity is embedded with a corresponding chip, and interconnected through the second conductive through holes, the second microchannel is arranged in the middle of the double-sided chip layer of the second glass-based interposer, the second microchannel is provided with a plurality of second connection ports extending to the front side of the second glass-based interposer, the second connection port is connected to the first connection port, and the second microchannel is also provided with a third connection port extending to the back side of the second glass-based interposer.

5. The packaging structure according to claim 4, characterized in that: The glass substrate is provided with a substrate circuit layer, a substrate microchannel and a substrate conductive through hole; the glass substrate is provided with a substrate circuit layer on the front and back sides, the substrate microchannel is horizontally arranged in the middle of the glass substrate, the substrate microchannel is provided with a first substrate connection port extending to the front side of the glass substrate, and is also provided with a second substrate connection port extending to the back side of the glass substrate, the first substrate connection port is correspondingly connected to the third connection port; a capacitor is connected to the substrate circuit layer on the front side of the glass substrate.

6. The packaging structure according to claim 5, characterized in that: The PCB board is provided with a coolant inlet and a coolant outlet, the substrate circuit layer on the back of the glass substrate is connected to the PCB board, and the second substrate connection port is provided with two corresponding coolant inlet and coolant outlet, and the coolant inlet is connected to the coolant supply device.

7. The packaging structure according to claim 6, characterized in that: The first glass-based intermediary layer, the second glass-based intermediary layer and the glass substrate are all made of glass.

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