Silicon through hole capacitor and preparation method thereof

Abstract

The invention discloses a silicon through hole capacitor and a preparation method thereof. The method comprises the following steps: selecting a high-resistance silicon substrate; metal connection is formed on the high-resistance silicon substrate to serve as a positive electrode and a negative electrode of the capacitor, and patterning of an ion implantation area is carried out on the high-resistance silicon substrate; forming an insulating layer on the outer surface of the high-resistance silicon substrate as a barrier layer for etching the through hole, and forming the through hole in the high-resistance silicon substrate through an etching process; injecting a dopant into the hole wall of the through hole through an ion injection process in the ion injection region to form a heavily doped region serving as an electrode of the capacitor; an isolation layer and a seed layer are deposited in the through hole, a metal column is formed by electroplating a metal material, the isolation layer serves as an intermediate medium of the capacitor, and the seed layer is used for providing conductivity for electroplating; and forming a metal redistribution layer on the metal connection to serve as a positive and negative electrode connection end of the capacitor. The on-chip integrated capacitor can be combined with a transistor process, and the size of the on-chip integrated capacitor is greatly reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of microsystem integration, and particularly relates to a through-silicon via capacitor and a preparation method thereof. Background Art

[0002] Through-silicon via (TSV) is a commonly used three-dimensional interconnection technology in semiconductor manufacturing. TSVs are tiny holes vertically passing through a silicon wafer, usually filled with copper, tungsten or other conductive materials, and these holes can be used to achieve electrical connections between chip layers. The three-dimensional integration technology based on the through-silicon via process is an important means to accelerate the integration of circuits and microsystems. High-density capacitors are very important components in the design of integrated microsystem analog and power chips. However, during the three-dimensional heterogeneous system integration process, the size of on-chip integrated passive devices is relatively large, occupying a large planar area of the system.

[0003] Traditional on-chip capacitors are usually planar metal-insulator-metal (MIM) structures that occupy a large device area. Currently, capacitors in three-dimensional heterogeneous system integration designs use a planar structure, and TSVs are used for interconnection with other devices, which only reduces a very small part of the area, or use small-sized coaxial TSVs with multi-layer metal deposition. The coaxial via diameter is much larger than that of ordinary vias, and multi-layer metal electrical connection processes are required. Existing on-chip capacitors have disadvantages such as low density and poor quality, and cannot meet the actual application requirements of high-speed and highly integrated microsystems. Summary of the Invention

[0004] The purpose of the present invention is to provide a through-silicon via capacitor and a preparation method thereof. By heavily doping ions inside the vias of a high-resistance silicon substrate, a through-silicon via capacitor can be obtained, which can be combined with the transistor process and greatly reduce the size of on-chip integrated capacitors.

[0005] To achieve the above purpose, one aspect of the present invention provides a preparation method of a through-silicon via capacitor, including:

[0006] Step S1: Select a high-resistance silicon substrate with a conductivity of 0.001 - 0.01 S / m;

[0007] Step S2: Form metal connections on the high-resistance silicon substrate as the positive and negative electrodes of the capacitor, and pattern the ion implantation regions on the high-resistance silicon substrate;

[0008] Step S3: Form an insulating layer on the outer surface of the high-resistance silicon substrate as a barrier layer for etching vias, and form vias in the high-resistance silicon substrate through an etching process;

[0009] Step S4: Inject dopants into the inner wall of the vias through ion implantation in the ion implantation area to form a heavily doped region, which serves as one electrode of the capacitor. The conductivity of the heavily doped region is 10 5 ~10 6 S / m;

[0010] Step S5: Deposit an isolation layer and a seed layer in the vias, and form metal posts by electroplating a metal material. Among them, the isolation layer serves as the intermediate dielectric of the capacitor, and the seed layer is used to provide conductivity for electroplating;

[0011] Step S6: Form a metal redistribution layer on the metal connection as the positive and negative connection ends of the capacitor.

[0012] Preferably, a thinning process is also included for the high-resistance silicon substrate between Step S5 and Step S6.

[0013] Preferably, the insulating layer is composed of an insulating medium, and the insulating medium includes SiO with a relative dielectric constant of 3.9 2 .

[0014] Preferably, the dopant is phosphorus or boron.

[0015] Preferably, the material of the isolation layer is silicon oxide, BCB or silicon nitride.

[0016] Preferably, the seed layer is composed of titanium and copper. Among them, titanium serves as a barrier layer to prevent copper ions from diffusing into the high-resistance silicon substrate, and copper serves as a conductive layer covering the inner wall of the vias.

[0017] Preferably, the heavily doped region is formed in the dead zone of the silicon through hole.

[0018] Another aspect of the present invention provides a silicon through-hole capacitor prepared by using the above method.

[0019] According to the silicon through-hole capacitor and its preparation method in the above aspect of the present invention, a silicon through-hole capacitor is obtained by heavily doping ions inside the vias of a high-resistance silicon substrate, which can be combined with the transistor process and greatly reduce the size of the on-chip integrated capacitor. Description of the Drawings

[0020] In order to more clearly illustrate the technical solutions of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts:

[0021] Figure 1 is a flowchart of a method for preparing a silicon through-hole capacitor according to an embodiment of the present invention;

[0022] Figure 2 It is a schematic structural diagram of a through-silicon via capacitor according to an embodiment of the present invention;

[0023] Figure 3 It is a schematic diagram of the parallel structure of a through-silicon via capacitor according to an embodiment of the present invention. Detailed implementation manners

[0024] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0025] An embodiment of the present invention provides a method for manufacturing a through-silicon via capacitor. As Figure 1 shown, the method for manufacturing a through-silicon via capacitor according to the embodiment of the present invention includes steps S1 to S6.

[0026] Step S1: Select a high-resistance silicon substrate

[0027] First, select a high-resistance silicon substrate with a conductivity of 0.001 - 0.01 S / m. Using a high-resistance silicon substrate can effectively reduce the loss of substrate conductance, ensure that the capacitor has a low leakage current during operation, and thus improve the performance of the capacitor.

[0028] Step S2: Patterning of metal connections and ion implantation regions

[0029] Form metal connections on the high-resistance silicon substrate as the positive and negative electrodes of the capacitor to connect to an external circuit. And through photolithography, pattern the ion implantation regions on the high-resistance silicon substrate to ensure that subsequent ion implantation is only carried out in specific regions, thereby precisely controlling the position and shape of the heavily doped regions.

[0030] Step S3: Form an insulating layer and etch through-holes

[0031] Form an insulating layer on the outer surface of the high-resistance silicon substrate as a barrier layer for etching through-holes. Then, through etching, form through-holes of TSV in the high-resistance silicon substrate in the TSV etching region on the outer surface of the high-resistance silicon substrate. The insulating layer is composed of an insulating medium, and the insulating medium is, for example, SiO 2 , with a relative dielectric constant of 3.9.

[0032] Step S4: Ion implantation to form heavily doped regions

[0033] In the ion implantation region defined in step S2, dopants are implanted into the pore walls of the vias through an ion implantation process to form a heavily doped region, which serves as one electrode of the capacitor. The concentration of the implanted ions forms a peak distribution in the semiconductor, which is mainly determined by the ion mass and the implantation energy. The dopants are, for example, phosphorus, boron, etc. The implanted dopants form a shallow heavily doped region, the size of which ranges from 0.1 μm to several microns, and the specific dimensions are determined according to process requirements. The high-concentration implantation of dopants changes the conductive characteristics of the high-resistance silicon, significantly reducing its resistivity. The conductivity of the heavily doped region is approximately between 10 5 ~10 6 S / m, comparable to that of metals. Preferably, the heavily doped region is formed in the dead zone of the TSV, so as not to further expand the usage area of the TSV. The dead zone of the TSV is also called the Keep-Out Zone. Considering circuit stability, etc., CMOS circuit elements are not placed within a certain range around the TSV.

[0034] Step S5: Deposit an isolation layer, a seed layer and electroplate a metal material to form a metal pillar.

[0035] Deposit an isolation layer and a seed layer inside the via. The isolation layer serves as the intermediate dielectric of the capacitor and is formed of an insulating material, such as silicon oxide (SiO 2 ), BCB or silicon nitride (Si 3 N 4 ), to isolate the conductive material from the high-resistance silicon substrate. By adjusting the thickness of the isolation layer, the equivalent dielectric thickness of the equivalent capacitor can be changed, thereby changing the capacitance value. The seed layer serves to provide conductivity and ensure smooth electroplating. It is usually composed of titanium and copper. Among them, titanium acts as a barrier layer to prevent copper ions from diffusing into the high-resistance silicon substrate, while copper serves as a conductive layer covering the inner wall of the via. Finally, a metal pillar is formed by electroplating a metal material, serving as the other electrode of the capacitor. The metal material is preferably copper because it has good conductivity and thermal conductivity.

[0036] Step S6: Form a metal redistribution layer (RDL) as the connection terminals of the positive and negative electrodes of the capacitor

[0037] Form one or more patterned metal RDLs on the metal connections on the outer surface of the high-resistance silicon substrate as the connection terminals (positive and negative electrode interfaces) of the positive and negative electrodes of the capacitor, for connecting the TSV to the external circuit. The insulating layers between the RDLs and between the RDL and the silicon substrate can prevent metal short circuits and are also beneficial to the patterning process of the metal RDL.

[0038] Steps S2, S4 and S6 work together to ensure that the electrode structure, conductive performance and external connection of the TSV capacitor can be precisely realized, thus ensuring the performance and reliability of the capacitor.

[0039] Preferably, between steps S5 and S6, the method according to an embodiment of the present invention further includes a substrate thinning step, in which the high-resistance silicon substrate is thinned according to actual manufacturing requirements. The thinning process can be achieved by methods such as mechanical grinding or chemical mechanical polishing (CMP) to ensure that the thickness of the substrate meets the design requirements.

[0040] An embodiment of the present invention also provides a through-silicon via capacitor prepared by the method according to the above embodiments of the present invention. As Figure 2 shown, the through-silicon via capacitor according to an embodiment of the present invention includes a high-resistance silicon substrate 1, a heavily doped region 2, an isolation layer 3, a metal pillar 4, a metal connection 5, a metal redistribution layer 6, and an insulating layer 7. Among them, the metal pillar 5 serves as one electrode of the capacitor, the heavily doped region 2 serves as the other electrode of the capacitor, the isolation layer 3 serves as the intermediate dielectric of the capacitor, the metal redistribution layer 6 on the upper surface of the high-resistance silicon substrate 1 serves as the positive electrode interface, and the metal redistribution layer 6 on the lower surface serves as the negative electrode interface 9, where the negative electrode interface 9 is grounded.

[0041] As an extended structure of the capacitor, a parallel structure as shown in Figure 3 the example can be formed. By stacking the lower part of the silicon substrate, the negative electrode is connected to the ground terminal, the positive electrode is connected to a transistor device or a circuit, and multiple heavily doped TSV capacitors are connected in series and parallel through RDL patterning, thereby increasing or decreasing the device capacitance value. As shown in Figure 3 , for two heavily doped TSV capacitors, a parallel structure capacitance C≈C1 + C2 can be achieved.

[0042] In summary, the preparation method of the through-silicon via capacitor according to an embodiment of the present invention adopts a via process and combines with a regional doping process of silicon to form a basic capacitor structure. By optimizing the device connection design, a capacitor structure with low cost, high capacitance density, and adjustable size can be obtained, which can be used as a decoupling capacitor device for high-speed circuits and power supply circuits. The through-silicon via capacitor and its preparation method according to an embodiment of the present invention have the following beneficial effects:

[0043] 1) Low price and simple process, and can be combined with the transistor manufacturing process. The combination of the TSV process and the CMOS transistor process is one of the key technologies for realizing 3D integrated circuits. The preparation method of the through-silicon via capacitor of the present invention can be combined with the CMOS transistor process.

[0044] 2) The through-silicon via capacitor of the present invention is small in size, without multi-layer metal deposition inside the via wall, reducing the diameter of the etched opening; and by controlling the heavily doped region in the dead zone of the TSV, the overall area of the entire circuit board can be controlled.

[0045] Only some exemplary embodiments of the present invention have been described by way of illustration. Without doubt, for those of ordinary skill in the art, the described embodiments can be modified in various different ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and description are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a through silicon via capacitor, characterized in that: include: Step S1: Selecting a high-resistance silicon substrate with a conductivity of 0.001-0.01S / m; Step S2: forming metal connections on the high-resistance silicon substrate as positive and negative electrodes of the capacitor, and patterning the ion implantation area on the high-resistance silicon substrate; Step S3: forming an insulating layer on the outer surface of the high-resistance silicon substrate as a barrier layer for etching through holes, and forming through holes in the high-resistance silicon substrate through an etching process; Step S4: In the ion implantation area, dopants are implanted into the hole wall of the through hole by an ion implantation process to form a heavily doped area, which serves as an electrode of the capacitor. The conductivity of the heavily doped area is 10 5 ~10 6 S / m; Step S5: depositing an isolation layer and a seed layer in the through hole, and forming a metal column by electroplating a metal material, wherein the isolation layer serves as an intermediate medium of the capacitor, and the seed layer is used to provide conductivity for electroplating; Step S6: forming a metal redistribution layer on the metal connection to serve as the positive and negative connection terminals of the capacitor.

2. The method according to claim 1, characterized in that Between step S5 and step S6, the high-resistance silicon substrate is thinned.

3. The method according to claim 1 or 2, characterized in that The insulating layer is composed of an insulating medium, and the insulating medium includes SiO2 with a relative dielectric constant of 3.

9.

4. The method according to claim 1 or 2, characterized in that: The dopant is phosphorus or boron.

5. The method according to claim 1 or 2, characterized in that: The material of the isolation layer is silicon oxide, BCB or silicon nitride.

6. The method according to claim 1 or 2, characterized in that: The seed layer is composed of titanium and copper, wherein titanium acts as a barrier layer to prevent copper ions from diffusing into the high-resistance silicon substrate, and copper acts as a conductive layer to cover the inner wall of the through hole.

7. The method according to claim 1 or 2, characterized in that: The heavily doped region is formed in the dead area of ​​the TSV.

8. A through silicon via capacitor, characterized in that: The method is prepared by any one of claims 1 to 7.

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