Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention provides a manufacturing method of a semiconductor device, and the method comprises the steps: forming at least one fin-shaped structure on the surface of a substrate, and enabling the fin-shaped structure to comprise a first semiconductor layer and a second semiconductor layer which are alternately stacked; etching the substrate below the fin-shaped structure from at least one side along the preset horizontal direction so as to form a groove below the fin-shaped structure; filling the groove to form an insulating part; removing one of the first semiconductor layer and the second semiconductor layer; a gate structure is formed around the other of the first semiconductor layer and the second semiconductor layer. The embodiment of the invention also provides a semiconductor device.

Description

Technical Field

[0001] The present disclosure belongs to, but is not limited to, the field of semiconductor manufacturing technology, and particularly relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] With the continuous development of semiconductor manufacturing processes, the critical dimensions of semiconductor devices have been continuously reduced. However, the reduction of the gate width leads to the so-called short-channel effects, which can cause Drain Induced Barrier Lowering (DIBL for short), making the semiconductor device unable to turn off.

[0003] To address this challenge, currently, Fin Field-Effect Transistor (FinFET for short) and Gate-All-Around Field-Effect Transistor (GAAFET for short) have been proposed. In the 3nm and finer processes, GAAFET shows greater advantages compared to FinFET. For example, better control of leakage current, smaller DIBL, higher performance, larger device density, and so on.

[0004] Conventional GAAFETs, such as Figure 1 and Figure 2 shown, include a substrate 11, a plurality of channel regions 12 formed on the substrate 11, and a gate structure 13 disposed around the channel regions 12. All sides of the channel regions 12 are surrounded by the gate structure 13, so that a smaller DIBL can be obtained. In this GAAFET structure, a parasitic gate capacitance will be formed between the bottom of the gate structure 13 and the substrate 11. When an on or off voltage is applied to the gate structure 13, the parasitic gate capacitance will be charged, thereby affecting the on or off speed of the GAAFET and reducing the high-frequency switching characteristics of the GAAFET. Summary of the Invention

[0005] Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof to solve the problem of poor high-frequency switching characteristics of semiconductor devices in related technologies.

[0006] To solve the above technical problem, embodiments of the present disclosure provide a manufacturing method of a semiconductor device, including:

[0007] Forming at least one fin structure on the surface of the substrate, the fin structure including alternately stacked first semiconductor layers and second semiconductor layers;

[0008] Etch the substrate below the fin structure from at least one side along a preset horizontal direction to form a groove below the fin structure;

[0009] Fill and form an insulating portion in the groove;

[0010] Remove one of the first semiconductor layer and the second semiconductor layer;

[0011] Form a gate structure around the other of the first semiconductor layer and the second semiconductor layer.

[0012] In some embodiments, the lattice constant of the material of the semiconductor layer at the bottommost of the fin structure is different from that of the material of the substrate, so as to apply stress to the top of the substrate to form a strain layer. The etching of the substrate below the fin structure from at least one side along a preset horizontal direction to form a groove below the fin structure includes:

[0013] Isotropically etch the substrate with a preset etching gas to selectively remove at least part of the strain layer, and the preset horizontal direction is a first horizontal direction parallel to the arrangement direction of the fin structure.

[0014] In some embodiments, the preset etching gas includes a fluorine-containing gas and an auxiliary etching gas, and the auxiliary etching gas includes oxygen element and nitrogen element.

[0015] In some embodiments, the fluorine-containing gas includes CF 4 、C 4 F 8 、C 3 F 6 、CHF 3 、CH 2 F 2 、CH 3 F, etc. at least one; and / or

[0016] The auxiliary etching gas includes N 2 、O 2 、NO、NO 2 at least one of them.

[0017] In some embodiments, the content ratio range of fluorine element to oxygen element is 0.1 to 10; or

[0018] The content ratio range of fluorine element to nitrogen element is 0.1 to 10.

[0019] In some embodiments, before etching the substrate below the fin structure from at least one side along a preset horizontal direction to form a groove below the fin structure, it further includes:

[0020] Source and drain regions are formed on both sides of the fin structure along a second horizontal direction, which is perpendicular to the first horizontal direction.

[0021] In some embodiments, before forming the source and drain regions on both sides of the fin structure along the second horizontal direction, the method further includes:

[0022] A protective layer covering the fin structure and the substrate is formed on both sides and the top surface of the fin structure along the first horizontal direction.

[0023] After forming the source and drain regions on both sides of the fin structure along the second horizontal direction, and before etching the substrate below the fin structure from at least one side along a preset horizontal direction to form a groove below the fin structure, the method further includes:

[0024] Anisotropic etching is performed on the protective layer to remove the protective layer covering the top of the fin structure and the substrate, so as to expose the strain layer from the bottom side of the fin structure.

[0025] In some embodiments, etching the substrate below the fin structure from at least one side along a preset horizontal direction to form a groove below the fin structure includes:

[0026] The substrate is etched to partially remove the substrate in contact with the fin structure, and the preset horizontal direction is a second horizontal direction perpendicular to the arrangement direction of the fin structure.

[0027] In some embodiments, before etching the substrate, the method further includes:

[0028] Protective layers are formed on both sides of the fin structure in the second horizontal direction.

[0029] The etching of the substrate includes:

[0030] Anisotropic etching is performed on at least a part of the exposed substrate to expose the side wall of the substrate not covered by the protective layer.

[0031] Isotropic etching is performed on the exposed substrate to form a convex portion facing the fin structure and the grooves arranged side by side on both sides of the convex portion along the second horizontal direction.

[0032] In some embodiments, after filling and forming an insulating portion in the grooves, the method further includes:

[0033] Sources and drains are formed on both sides of the fin structure along the second horizontal direction.

[0034] In some embodiments, the substrate and one of the first semiconductor layer and the second semiconductor layer are made of the same material; or,

[0035] the substrate is Si, one of the first semiconductor layer and the second semiconductor layer is Si, and the other is SiGe.

[0036] In some embodiments, the material of the insulating portion includes at least one of silicon dioxide, silicon nitride, hafnium oxide, aluminum oxide, and zinc oxide.

[0037] As another technical solution, the present invention further provides a semiconductor device, including:

[0038] a substrate;

[0039] at least one channel region formed on the substrate;

[0040] a gate structure formed around each of the channel regions; wherein

[0041] the substrate has a protruding portion facing the gate structure, and the protruding portion is in contact with a partial lower surface of the gate structure;

[0042] the semiconductor device further includes an insulating portion, the insulating portion is arranged side by side with the protruding portion, an upper surface of the insulating portion is flush with an upper surface of the protruding portion, and is in contact with a partial lower surface of the gate structure.

[0043] In some embodiments, the insulating portions are arranged side by side on two sides of the protruding portion along a preset horizontal direction.

[0044] In some embodiments, the semiconductor device further includes a source electrode and a drain electrode, the source electrode and the drain electrode are respectively located on two sides of the gate structure along a second horizontal direction;

[0045] the preset horizontal direction is parallel to the second horizontal direction; or,

[0046] the preset horizontal direction is perpendicular to the second horizontal direction.

[0047] In some embodiments, a thickness of the insulating portion in a vertical direction is 0.5 to 1.5 times a thickness of the channel region in the vertical direction; or,

[0048] the thickness of the insulating portion in the vertical direction is 0.8 to 1.2 times the thickness of the channel region in the vertical direction.

[0049] In some embodiments, a shape of a positive projection of the insulating portion on a vertical plane is a wedge shape; or

[0050] The orthographic projection shape of the bottom of the insulating part on the vertical plane is arc-shaped. Description of the Drawings

[0051] Figure 1 It is a schematic vertical cross-sectional view of a GAAFET in the related art parallel to the arrangement direction of the source region and the drain region;

[0052] Figure 2 It is a schematic vertical cross-sectional view of a GAAFET in the related art perpendicular to the arrangement direction of the source region and the drain region;

[0053] Figure 3 It shows a schematic vertical cross-sectional view of a GAAFET in another related art perpendicular to the arrangement direction of the source region and the drain region;

[0054] Figure 4 It is a partial schematic view of a cross-section of a semiconductor device provided by an embodiment of the present invention perpendicular to the second horizontal direction;

[0055] Figure 5 It is a partial schematic view of a cross-section of another semiconductor device provided by an embodiment of the present invention parallel to the second horizontal direction;

[0056] Figure 6 It is a flowchart of a manufacturing method of a semiconductor device provided by an embodiment of the present invention;

[0057] Figure 7 It is a structural diagram of a semiconductor device provided by an embodiment of the present invention after completing step S111;

[0058] Figure 8 It is a structural diagram of a semiconductor device provided by an embodiment of the present invention after completing step S112;

[0059] Figure 9 It is a structural diagram of a semiconductor device provided by an embodiment of the present invention after completing step S113;

[0060] Figure 10 It is a scanning electron microscope image of a semiconductor device provided by an embodiment of the present invention after completing step S120;

[0061] Figure 11 It is a structural diagram of a semiconductor device provided by an embodiment of the present invention after completing step S114;

[0062] Figure 12 It is a structural diagram of a semiconductor device provided by an embodiment of the present invention after completing step S115;

[0063] Figure 13 It is a structural diagram of a semiconductor device provided by an embodiment of the present invention after completing step S1211;

[0064] Figure 14 Structural diagram of a semiconductor device provided by an embodiment of the present invention for completing step S1212;

[0065] Figure 15 Structural diagram of a semiconductor device provided by an embodiment of the present invention for completing step S1213;

[0066] Figure 16 Structural diagram of a semiconductor device provided by an embodiment of the present invention for completing step S1214;

[0067] Figure 17 Structural diagram of a semiconductor device provided by an embodiment of the present invention for completing step S1215;

[0068] Figure 18 Structural diagram of a semiconductor device provided by an embodiment of the present invention for completing step S1216;

[0069] Figure 19 Structural diagram of a semiconductor device provided by an embodiment of the present invention for completing step S1217;

[0070] Figure 20 Structural diagram of a semiconductor device provided by an embodiment of the present invention for completing step S1218;

[0071] Figure 21 Structural diagram of a semiconductor device provided by an embodiment of the present invention for completing step S1219;

[0072] Figure 22 Structural diagram of a semiconductor device provided by an embodiment of the present invention for completing step S1220;

[0073] Figure 23 Cross-sectional view of a semiconductor device provided by an embodiment of the present invention for completing step S1220 along a direction parallel to the first horizontal direction;

[0074] Figure 24 Structural diagram of a semiconductor device provided by an embodiment of the present invention for completing step S1221;

[0075] Figure 25 Cross-sectional view of a semiconductor device provided by an embodiment of the present invention for completing step S1221 along a direction parallel to the first horizontal direction;

[0076] Figure 26 Structural diagram of a semiconductor device provided by an embodiment of the present invention for completing step S120;

[0077] Figure 27 Cross-sectional view of a semiconductor device provided by an embodiment of the present invention for completing step S120 along a direction parallel to the second horizontal direction;

[0078] Figure 28 A cross-sectional view along a direction parallel to the first horizontal direction for a semiconductor device provided by an embodiment of the present invention to complete step S120;

[0079] Figure 29 Another cross-sectional view along a direction parallel to the first horizontal direction for a semiconductor device provided by an embodiment of the present invention to complete step S120;

[0080] Figure 30 A cross-sectional view along a direction parallel to the second horizontal direction for a semiconductor device provided by an embodiment of the present invention to complete step S130;

[0081] Figure 31 A structural diagram for a semiconductor device provided by an embodiment of the present invention to complete step S140;

[0082] Figure 32 A cross-sectional view along a direction parallel to the second horizontal direction for a semiconductor device provided by an embodiment of the present invention to complete step S150;

[0083] Figure 33 A structural diagram for another semiconductor device provided by an embodiment of the present invention to complete step S1215';

[0084] Figure 34 A structural diagram for another semiconductor device provided by an embodiment of the present invention to complete step S1216';

[0085] Figure 35 A structural diagram for another semiconductor device provided by an embodiment of the present invention to complete step S1201;

[0086] Figure 36 A cross-sectional view along a direction parallel to the second horizontal direction for another semiconductor device provided by an embodiment of the present invention to complete step S1201;

[0087] Figure 37 A structural diagram for another semiconductor device provided by an embodiment of the present invention to complete step S1202;

[0088] Figure 38 A cross-sectional view along a direction parallel to the second horizontal direction for another semiconductor device provided by an embodiment of the present invention to complete step S1202;

[0089] Figure 39 A structural diagram for another semiconductor device provided by an embodiment of the present invention to complete step S130;

[0090] Figure 40 A cross-sectional view along a direction parallel to the second horizontal direction for another semiconductor device provided by an embodiment of the present invention to complete step S130;

[0091] Figure 41 Another cross-sectional view parallel to the second horizontal direction of the semiconductor device provided by the embodiment of the present invention for completing step S131;

[0092] Figure 42 Another cross-sectional view parallel to the second horizontal direction of the semiconductor device provided by the embodiment of the present invention for completing step S132;

[0093] Figure 43 Another cross-sectional view parallel to the second horizontal direction of the semiconductor device provided by the embodiment of the present invention for completing step S133. Detailed implementation manners

[0094] To make the objectives, technical solutions, and advantages of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are some but not all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0095] Those skilled in the art should understand that the embodiments of the present disclosure are only illustrations of the structures and methods that can implement the claimed subject matter of the present disclosure in various forms. In addition, each example given in combination with various embodiments is intended to be illustrative, not restrictive. In addition, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show details of specific components. Therefore, the specific structural and functional details in the embodiments of the present disclosure should not be construed as restrictive, but merely as a representative basis for teaching those skilled in the art to adopt the methods and structures of the embodiments of the present disclosure in different ways. It should also be noted that the same and corresponding elements are denoted by the same reference numerals.

[0096] In the following description, numerous specific details are set forth, such as specific structures, components, materials, dimensions, processing steps, and techniques, in order to provide an understanding of the various embodiments of the present disclosure. However, those skilled in the art should understand that the various embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present disclosure.

[0097] For the purposes described below, the terms "upper", "right", "left", "vertical", "horizontal", "top", "bottom" and their derivatives shall relate to the orientation in the structures and methods disclosed in the accompanying drawings of the specification. It should be understood that when an element, such as a layer, region or substrate, is referred to as being on another element, the element can be directly on the other element or there can also be intermediate elements. Conversely, when an element is referred to as being directly on another element, there are no intermediate elements between the two. It should also be understood that when an element is referred to as being under another element, the element can be directly under the other element or there can be intermediate elements. Conversely, when an element is referred to as being directly under another element, there are no intermediate elements between the two.

[0098] The GAAFET in the related art, such as Figure 1 and Figure 2 shown, Figure 1 is a vertical cross-sectional view of the GAAFET in the related art parallel to the arrangement direction of the source region and the drain region 15. Figure 2 is a vertical cross-sectional view of the GAA FET in the related art perpendicular to the arrangement direction of the source region and the drain region 15. The GAAFET includes a substrate 11, a plurality of channel regions 12 formed on the substrate 11, and a gate structure 13 disposed around the channel regions 12, wherein the gate structure 13 includes a gate dielectric layer and a gate electrode layer surrounding the channel regions 12. In this GAAFET structure, a parasitic gate capacitance is formed between the bottom of the gate structure 13 and the substrate 11. When an on or off voltage is applied to the gate structure 13, the parasitic gate capacitance will be charged, thereby affecting the on or off speed of the GAAFET and reducing the high-frequency switching characteristics of the GAAFET.

[0099] To solve this problem, in another related art, as Figure 3 shown, an insulating layer 14 is provided between the bottom of the gate structure 13 of the GAAFET and the substrate 11, thereby suppressing the parasitic gate capacitance to improve the high-frequency switching characteristics of the GAAFET. The inventors of the present disclosure found that the heat generated by the GAAFET needs to be efficiently released. In the case where the insulating layer 14 is not provided, the heat can be conducted from the bottom gate structure 13 to the substrate 11. However, in the case where the insulating layer 14 is provided, since the insulating layer 14 is usually made of insulating materials such as silicon nitride, silicon oxide or silicon oxynitride, the heat conduction efficiency is poor, and the heat generated by the GAAFET cannot be effectively conducted from the insulating layer 14 to the substrate 11, resulting in an increase in the temperature of the GAAFET and a decrease in the electron / hole mobility, which will instead affect the performance of the GAAFET.

[0100] To solve the above problems, please refer to Figure 4, a semiconductor device proposed in an embodiment of the present disclosure. Its main concept is that the substrate 100 has a protruding portion 101 facing the gate structure 300. The protruding portion 101 is in contact with a part of the lower surface of the gate structure 300 and is used as a heat conduction layer, so that the heat generated by the GAAFET can be conducted to the substrate 100 through the protruding portion 101; the remaining lower surface of the gate structure 300 is in contact with the insulating portion 102, reducing the influence of the parasitic gate capacitance to improve the high-frequency switching characteristics of the GAAFET. In the embodiment of the present disclosure, the insulating portion 102 and the protruding portion 101 are arranged side by side between the gate structure 300 and the substrate 100, so that the high-frequency switching characteristics and heat dissipation can be taken into account, and the contact area ratio of the protruding portion 101 and the insulating portion 102 to the gate structure 300 can be adjusted according to the requirements of the semiconductor device. When the heat dissipation requirement of the semiconductor device is high, the contact area ratio of the protruding portion 101 to the gate structure 300 is increased. When the high-frequency switching characteristic requirement is high, the contact area ratio of the insulating portion 102 to the gate structure 300 is increased.

[0101] Hereinafter, the technical solutions provided in the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0102] An embodiment of the present disclosure provides a semiconductor device, including: a substrate 100, at least one channel region 201, and a gate structure 300. At least one channel region 201 is formed on the substrate 100; the gate structure 300 is formed around each channel region 201; wherein, the substrate 100 has a protruding portion 101 facing the gate structure 300, and the protruding portion 101 is in contact with a part of the lower surface of the gate structure 300. The semiconductor device further includes an insulating portion 102, which is arranged side by side with the protruding portion 101. The upper surface of the insulating portion 102 is flush with the upper surface of the protruding portion 101 and is in contact with a part of the lower surface of the gate structure 300.

[0103] In the embodiment of the present disclosure, by arranging the insulating portion 102 and the protruding portion 101 side by side between the gate structure 300 and the substrate 100, the high-frequency switching characteristics and heat dissipation can be taken into account, and the contact area ratio of the protruding portion 101 and the insulating portion 102 to the gate structure 300 can be adjusted according to the requirements of the semiconductor device. When the heat dissipation requirement of the semiconductor device is high, the contact area ratio of the protruding portion 101 to the gate structure 300 is increased. When the high-frequency switching characteristic requirement is high, the contact area ratio of the insulating portion 102 to the gate structure 300 is increased.

[0104] Moreover, the above-mentioned protruding portion 101 is a part of the substrate 100, so that the heat conduction of the GAAFET can be realized by using the structure of the substrate 100 itself without adding an additional film layer, which can not only simplify the structure, but also simplify the manufacturing process of the semiconductor device and reduce the cost.

[0105] In some embodiments, the substrate 100 may be made of Si. One or more buffer layers (not shown) may also be formed on the surface of the substrate 100. The buffer layer may be used to gradually change the lattice constant from the lattice constant of the substrate 100 to the lattice constant of the source / drain region. For example, the lattice constants of multiple buffer layers gradually change from the substrate 100 to the source / drain region to reduce the difference in lattice constants between two adjacent film layers (including the substrate 100 and the adjacent buffer layer, each adjacent buffer layer, and the source / drain region and the adjacent buffer layer). The buffer layer may be formed of an epitaxially grown single-crystalline semiconductor material, such as but not limited to Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP.

[0106] On this basis, since the protruding portion 101 is a part of the substrate 100, the protruding portion 101 is also made of Si, and this material can better achieve heat conduction for the GAAFET compared to the material of the insulating portion 102.

[0107] In some embodiments, in order to achieve the effect of suppressing parasitic gate capacitance (and leakage current control ability), the material of the insulating portion 102 may include at least one of silicon dioxide (SiO 2 ), silicon nitride (SiNx), hafnium oxide (HfOx), aluminum oxide (AlOx), and zinc oxide (ZeOx).

[0108] In some embodiments, for ease of processing, the insulating portions 102 are arranged side by side on both sides of the protruding portion 101 along a preset horizontal direction. The preset horizontal direction is parallel to the surface of the substrate 100. The surface of the substrate 100 is, for example, parallel to the horizontal plane. In this way, during the process of fabricating the protruding portion 101 and the insulating portion 102, first, the surface of the substrate 100 is etched from both sides along the preset horizontal direction to form the protruding portion 101 and the grooves on both sides of the protruding portion 101; then the insulating portion 102 is filled in the grooves, and thus the protruding portion 101 and the insulating portion 102 arranged side by side can be fabricated.

[0109] In some embodiments, the thickness of the insulating portion 102 in the vertical direction is 0.5 to 1.5 times the thickness of the channel region 201 in the vertical direction. Preferably, the thickness of the insulating portion 102 in the vertical direction is 0.8 to 1.2 times the thickness of the channel region 201 in the vertical direction.

[0110] It should be noted that, as Figure 4 shown, if the etching method of the surface of the substrate 100 is different, the orthographic projection shapes of the protruding portion 101 and the insulating portion 102 formed on the substrate 100 in the vertical plane (i.e., the shape of the groove for filling the insulating portion 102) may be different. For example, asFigure 4 As shown, the width of the protruding portion 101 in the X1 direction becomes smaller closer to the gate structure 300. That is, the orthographic projection shape on the vertical plane of the insulating portion 102 (i.e., perpendicular to the surface of the substrate 100) is wedge-shaped, and the depth of the orthographic projection shape of the insulating portion 102 on the vertical plane in the Z direction becomes larger farther away from the protruding portion 101. For another example, as Figure 5 shown, the orthographic projection shape on the vertical plane of the insulating portion 102 (i.e., perpendicular to the surface of the substrate 100) is arc-shaped, and the depth of the orthographic projection shape of the insulating portion 102 on the vertical plane in the Z direction becomes larger farther away from the protruding portion 101.

[0111] Furthermore, in some embodiments, as Figure 5 shown, the semiconductor device further includes a source region and a drain region 400, and the source region and the drain region 400 are respectively located on both sides of the gate structure 300 along the second horizontal direction (i.e., parallel to Figure 5 the X2 direction in ). In this case, the above-mentioned preset horizontal direction is, for example, perpendicular to the second horizontal direction. That is, as Figure 4 shown, the insulating portions 102 are arranged side by side on both sides of the protruding portion 101 along the first horizontal direction (i.e., parallel to Figure 4 the X1 direction in ), and the first horizontal direction is perpendicular to the second horizontal direction. In some other embodiments, in order to cut off the leakage current generated by the parasitic gate capacitance, preferably, as Figure 5 shown, the above-mentioned preset horizontal direction is parallel to the second horizontal direction (i.e., parallel to Figure 5 the X2 direction in ), that is, the insulating portions 102 are arranged side by side on both sides of the protruding portion 101 along the second horizontal direction. In this way, the insulating portions 102 located on both sides of the protruding portion 101 can cut off the leakage current generated by the parasitic gate capacitance, so that on the basis of achieving the suppression effect on the parasitic gate capacitance, better leakage current control ability can be obtained.

[0112] It should be noted that the insulating portion 102 and the protruding portion 101 adopt different arrangement directions, and the order of the manufacturing steps of the insulating portion 102 and the protruding portion 101 and the manufacturing steps of the source region and the drain region 400 may be different. For example, if the insulating portions 102 are arranged side by side on both sides of the protruding portion 101 along the first horizontal direction (i.e., parallel to Figure 4 the X1 direction in ), while the source region and the drain region 400 are respectively located on both sides of the gate structure 300 along the second horizontal direction (i.e., parallel to Figure 5On both sides of the X2 direction in the figure), the manufacturing steps of the source region and the drain region 400 can be carried out first, and then the manufacturing steps of the insulating portion 102 and the protruding portion 101 can be carried out. On the contrary, if the insulating portion 102 is arranged side by side on both sides of the protruding portion 101 along the second horizontal direction, and the source region and the drain region 400 are respectively located on both sides of the gate structure 300 along the second horizontal direction, the manufacturing steps of the insulating portion 102 and the protruding portion 101 can be carried out first, and then the manufacturing steps of the source region and the drain region 400 can be carried out. In addition, the processing methods of the insulating portion 102 and the protruding portion 101 with different arrangement directions may also be different, which will be described in detail later.

[0113] It should be noted that the embodiments of the present disclosure are not limited to the above side-by-side manner of the insulating portion 102 and the protruding portion 101. In practical applications, the insulating portion 102 can also be arranged side by side on one side of the protruding portion 101 along a preset horizontal direction (such as parallel to the first horizontal direction or the second horizontal direction), or the insulating portion 102 can also be arranged side by side on at least one side of the protruding portion 101 along the first horizontal direction and at least one side of the protruding portion 101 along the second horizontal direction. As long as the insulating portion 102 and the protruding portion 101 are arranged side by side between the gate structure 300 and the substrate 100, the high-frequency switching characteristics and heat dissipation can be taken into account to ensure the performance of the GAAFET.

[0114] As Figure 3 In the related art shown, in the process of manufacturing the insulating layer 14, a sacrificial region is formed on the surface of the substrate 11, and after manufacturing the fin structure, the sacrificial region is removed to form a cavity for filling and forming the insulating layer 14 between the substrate 11 and the fin structure. However, in the related art, in the step of forming the sacrificial region, not only is it necessary to increase the photolithography step to form a photoresist pattern on the substrate 11, but also ion implantation needs to be performed on the substrate surface, which not only increases the processing procedures, but also the ion implantation equipment is expensive, resulting in a high processing cost.

[0115] To solve the above problems, please refer to Figure 6 The embodiments of the present disclosure also provide a manufacturing method of a semiconductor device, which includes:

[0116] S110. Form at least one fin structure on the surface of the substrate, and the fin structure includes alternately stacked first semiconductor layers and second semiconductor layers;

[0117] Specifically, the above step S110, that is, forming a fin structure on the surface of the substrate, may include:

[0118] S111. As Figure 7 shown, alternately stacked first semiconductor layers 210 and second semiconductor layers 220 are formed on the surface of the substrate 100.

[0119] In some embodiments, the substrate 100 is made of the same material as one of the first semiconductor layer 210 and the second semiconductor layer 220. Further, in some embodiments, the first semiconductor layer 210 and the second semiconductor layer 220 are made of Si, Si compounds, SiGe, Ge, or Ge compounds. In Figure 7 the example of

[0120] In Figure 7 it is shown that there are four layers of the first semiconductor layer 210 and three layers of the second semiconductor layer 220. However, the embodiments of the present disclosure are not limited thereto, and more or fewer first semiconductor layers 210 and second semiconductor layers 220 are feasible. In some embodiments, each of the first semiconductor layer 210 and the second semiconductor layer 220 is formed into 2 to 20 layers. By adjusting the number of the first semiconductor layer 210 and / or the second semiconductor layer 220, the drive current of the GAAFET device can be adjusted.

[0121] The first semiconductor layer 210 and the second semiconductor layer 220 are epitaxially formed above the substrate 100. The thickness of the first semiconductor layer 210 and the thickness of the second semiconductor layer 220 may be the same or different. Also, the thickness of each layer in the first semiconductor layer 210 may be the same or different; the thickness of each layer in the second semiconductor layer 220 may be the same or different. The embodiments of the present disclosure do not make any limitation thereto. In some embodiments, the thickness of the first semiconductor layer 210 is in the range of 2 nm to 20 nm. In some embodiments, the thickness of the second semiconductor layer 220 is in the range of 2 nm to 20 nm.

[0122] S112, as Figure 8 shown, a patterned hard mask layer 231 is formed above the alternately stacked first semiconductor layer 210 and second semiconductor layer 220;

[0123] It should be noted that the entire film layer of the hard mask layer 231 covers the upper surface of the uppermost first semiconductor layer 210 before patterning. Then, a photoresist pattern is formed using a mask plate, and the redundant part of the hard mask layer 231 is etched away at the patterning time to obtain Figure 8 the patterned hard mask layer 231 as shown. The hard mask layer 231 may be a silicon oxide layer or a silicon nitride layer or a stack of a silicon oxide layer and a silicon nitride layer.

[0124] S113, as Figure 9 shown, using the patterned hard mask layer 231, the first semiconductor layer 210, the second semiconductor layer 220, and the substrate 100 are etched to obtain a fin structure 200, and at the same time, isolation trenches 103 are formed in the substrate 100 on both sides of the fin structure 200;

[0125] As Figure 9 shown, in this step, multiple fin structures 200 can be obtained, and the arrangement directions of the multiple fin structures 200 are parallel to the first horizontal direction (i.e., parallel to the Figure 9 X1 direction in Figure 9 ). Only one fin structure 200 is shown. Moreover, after the etching of the alternately stacked first semiconductor layer 210 and second semiconductor layer 220 is completed, the underlying substrate 100 can be further etched to form isolation trenches 103 in the substrate 100 between two adjacent fin structures 200, facilitating the formation of a shallow trench isolation (STI) structure 232 as shown in Figure 11 subsequently in the isolation trenches 103 for electrically isolating adjacent GAA-FETs.

[0126] S120. Etch the substrate under the fin structure from at least one side along a preset horizontal direction to form a groove under the fin structure;

[0127] The above groove is used to fill and form an insulating part in a subsequent step. Compared with the related art in the step of forming a sacrificial region, not only is it necessary to add a photolithography step to form a photoresist pattern on the substrate, but also ion implantation is required on the substrate surface, which not only increases the processing procedures, but also the ion implantation equipment is expensive, resulting in a higher processing cost.

[0128] In some embodiments, the material of the lowermost semiconductor layer of the fin structure 200 (such as the material of the first semiconductor layer 210 as shown in Figure 9 ) has a different lattice constant from the material of the substrate 100 to apply stress to the top of the substrate 100 to form a strained layer. Specifically, the top region of the substrate 100 close to the fin structure 200 (referred to as the Sub-Fin region, i.e., the strained layer) is greatly affected by the stress of the material of the lowermost semiconductor layer of the fin structure 200, and this strained layer has a higher etching rate compared to other regions of the substrate 100 during the isotropic etching process. Based on the above principle, the above step S120 specifically includes:

[0129] Perform isotropic etching on the substrate 100 using a preset etching gas to selectively remove at least part of the above strained layer.

[0130] In the above step S120, the preset horizontal direction is the first horizontal direction parallel to the arrangement direction of the fin structure 200 (i.e., parallel to the Figure 9in the X1 direction). Since the strain layer of the substrate 100 has a higher etching rate than other regions of the substrate 100, the groove depth can be more precisely controlled, avoiding excessive groove depth, and thus meeting the strict requirements of the process for the groove depth. As Figure 10 shown, in the embodiment where the substrate 100 is Si and the first semiconductor layer 210 is SiGe, after completing the above step S120, the groove morphology as shown in Figure 10 can be obtained. Specifically, the depth of the groove 105 in the vertical plane of the shape is larger as it is farther from the protrusion 101 in the direction parallel to X1. The width of the protrusion 101 in the X1 direction is smaller closer to the fin structure 200. On this basis, the first semiconductor layer 210 at the bottom of the fin structure 200 is basically not etched, indicating that there is a large etching selectivity between the substrate 100 and the first semiconductor layer 210.

[0131] In the above step S120, the preset etching gas used for isotropic etching satisfies: the etching selectivity between the substrate 100 and the semiconductor layer at the bottom of the fin structure 200 is greater than a predetermined value, so that the above groove 105 can be formed on the substrate 100 without damaging the semiconductor layer at the bottom of the fin structure 200. For example, the substrate 100 is Si, and the bottommost first semiconductor layer 210 is adjacent to the substrate 100 and is SiGe. In some embodiments, the preset etching gas includes a fluorine-containing gas and an auxiliary etching gas, and the auxiliary etching gas includes oxygen and nitrogen elements. The fluorine-containing gas is the main etching gas, which generates fluoride ions and fluorine-containing radicals after being excited to react with the substrate 100 to achieve etching, and the auxiliary etching gas is used to adjust the etching selectivity between the substrate 100 and the semiconductor layer, so as to achieve selective etching of the substrate 100.

[0132] Further, in some embodiments, the fluorine-containing gas includes CF 4 、C 4 F 8 、C 3 F 6 、CHF 3 、CH 2 F 2 、CH 3 F, at least one of them.

[0133] In some embodiments, the auxiliary etching gas includes N 2 、O 2 、NO、NO 2 , at least one of them.

[0134] By Figure 10It can be clearly seen that on the basis of adopting the above-mentioned fluorine-containing gas, by adding the above-mentioned auxiliary etching gas, the etching selectivity of Si relative to SiGe can be well improved, and while removing Si, the loss of SiGe can be ensured to be small. Moreover, the inventors of the present disclosure found that the oxygen element and nitrogen element in the preset etching gas can well adjust the etching rate and etching selectivity of the substrate 100. When the content of the oxygen element in the preset etching gas increases, the etching rates of both SiGe and Si increase, but the etching selectivity between Si and SiGe changes little; while when the content of the nitrogen element in the preset etching gas increases, the etching rate of Si accelerates and the etching selectivity of Si relative to SiGe increases. When the content of the nitrogen element in the preset etching gas decreases, the etching of both Si and SiGe is inhibited, and the etching selectivity of Si relative to SiGe decreases. Based on this, preferably, the content ratio range of the fluorine element to the oxygen element in the preset etching gas is 0.1 to 10. Within this range, a faster etching rate and better etching selectivity can be obtained. Preferably, the content ratio range of the fluorine element to the nitrogen element in the preset etching gas is 0.1 to 10. Within this range, the etching selectivity of Si relative to SiGe can be well improved, and while removing Si, the loss of SiGe can be ensured to be small.

[0135] Before the above step S120, it further includes:

[0136] A source region and a drain region are formed on both sides of the fin structure along the second horizontal direction; the second horizontal direction is perpendicular to the first horizontal direction.

[0137] That is to say, in the subsequent above step S120, the direction in which the groove 105 and the protrusion 101 shown in Figure 10 are arranged side by side is perpendicular to the arrangement direction of the source region and the drain region 400.

[0138] In a specific example, before the above step S120 and after the above step S113, it further includes:

[0139] S114, as shown in Figure 11 , a shallow trench isolation structure 232 is formed in the isolation trenches 103 on both sides of the fin structure 200;

[0140] S115, as shown in Figure 12 , on both sides and the top surface of the fin structure 200 along the first horizontal direction (i.e., parallel to the Figure 12 X1 direction in

[0141] The protective layer 233 specifically covers the top surface of the fin structure 200 and the side surfaces along both sides in the first horizontal direction, as well as the top surface of the shallow trench isolation structure 232. The protective layer 233 can protect the side surfaces of the fin structure 200 from being laterally etched during the etching process of the substrate 100 in the subsequent step S120. The protective layer 233 may include a silicon nitride-based material formed by CVD (including LPCVD and PECVD), PVD, ALD, or other suitable processes, such as silicon nitride, SiON, SiOCN, or SiCN and their combinations. In some embodiments, the protective layer 233 is made of silicon nitride, for example, it can be formed by ALD process, so as to ensure good density of the protective layer 233 to protect the fin structure 200 from being laterally etched during the etching process of the substrate 100 in the subsequent step S120.

[0142] In a specific embodiment, after completing step S115, steps S1211 to S1220 are further performed, specifically:

[0143] S1211, as Figure 13 shown, a dummy gate structure 234, an etch stop layer 235, and a hard mask layer 236 are sequentially formed on the protective layer 233;

[0144] S1212, as Figure 14 shown, the hard mask layer 236, the etch stop layer 235, and the dummy gate structure 234 are sequentially patterned and etched;

[0145] S1213, as Figure 15 shown, a first isolation wall 237 is formed on two side surfaces of the patterned dummy gate structure 234 along the second horizontal direction (i.e., the X2 direction parallel to Figure 15 ), and the top surface of the hard mask layer 236;

[0146] S1214, as Figure 16 shown, the first isolation wall 237 and the hard mask layer 236 are etched to remove the part of the first isolation wall 237 on the top surface of the hard mask layer 236 and the hard mask layer 236, and retain the side part 2371 of the first isolation wall covering the side surface of the dummy gate structure 234;

[0147] S1215, as Figure 17 shown, the parts of the protective layer 233 and the fin structure (i.e., the first semiconductor layer 210 and the second semiconductor layer 220) located on both sides of the side part 2371 of the first isolation wall are etched away;

[0148] S1216, as Figure 18 shown, from the fin structure along the second horizontal direction (i.e., parallel to Figure 18On both sides in the X2 direction), etch away a predetermined thickness of one of the first semiconductor layer 210 and the second semiconductor layer 220;

[0149] For example, Figure 18 It shows that a predetermined thickness of the first semiconductor layer 210 is removed to form a space 2101.

[0150] S1217, as Figure 19 As shown, fill the space 2101 formed after removing a predetermined thickness of one of the first semiconductor layer 210 and the second semiconductor layer 220 with a second isolation wall 238;

[0151] S1218, as Figure 20 As shown, form source and drain regions 400 on both sides of the fin structure along the second horizontal direction (i.e., parallel to Figure 20 the X2 direction);

[0152] S1219, as Figure 21 As shown, form an interlayer dielectric layer 239 on the etch stop layer 235 and the source and drain regions 400;

[0153] S1220, as Figure 22 and Figure 23 As shown, remove the portion of the interlayer dielectric layer 239 corresponding to the dummy gate structure 234 and the dummy gate structure 234, exposing the protective layer 233 covering both sides and the top surface of the fin structure 200 along the first horizontal direction (i.e., parallel to Figure 22 and Figure 23 the X1 direction in) and the top surface of the shallow trench isolation structure 232;

[0154] Since the above steps S1211 to S1220 are conventional process steps, they will not be described in detail here.

[0155] In some embodiments, before the above step S120 and after completing step S1220, the following step S1221 is performed.

[0156] S1221, as Figure 24 and Figure 25 As shown, perform anisotropic etching on the protective layer 233 to remove the protective layer 233 covering the top of the fin structure 200 and the shallow trench isolation structure 232, so that the strain layer 104 of the substrate 100 located under the fin structure can be exposed from the bottom side of the fin structure 200, that is, the corner portion between the side surface of the fin structure 200 and the top surface of the shallow trench isolation structure 232 on the substrate 100; the corner portion is the Figure 23 position pointed by the arrow in;

[0157] In the above step S1221, as Figure 25As shown, the fin-shaped structure covered by the retaining protection layer 233 is arranged along a first horizontal direction (ie, parallel to Figure 25 Protective layer side walls 2331 on both sides (in the X1 direction).

[0158] In this step, a process gas with a high etching rate, high upper electrode RF power and lower electrode RF power can be used to perform the anisotropic etching, so that the portion of the protective layer 233 covering the top surface of the fin-shaped structure 200 and the shallow trench isolation structure 232 can be etched away, while retaining the protective layer sidewall 2331 covering the fin-shaped structure 200 and exposing the strained layer 104 under the fin-shaped structure.

[0159] By using a high lower electrode RF power, downward acceleration energy and direction can be provided for the plasma, and by using a high upper electrode RF power, more plasma can be generated. At the same time, a process gas with a high etching rate is used to enhance the directionality of anisotropic etching, so that while etching away the portion of the protective layer 233 covering the top surface of the fin-shaped structure 200 and the shallow trench isolation structure 232 to expose the strained layer 104, the sidewall 2331 of the protective layer located on the fin-shaped structure can be avoided as much as possible from being etched laterally, so that the fin-shaped structure can be protected in the subsequent step S120. It should be understood by those skilled in the art that the so-called upper electrode RF power generally refers to the RF power applied to the RF coil located at the top of the process chamber. In some embodiments, the RF coil can also be located on the side of the process chamber to ionize the process gas to generate plasma; the so-called lower electrode RF power generally refers to the RF power applied to the lower electrode assembly of the process chamber. The lower electrode assembly includes a wafer carrier device for generating an RF bias to improve the directionality of the plasma.

[0160] The above step S1221 can be performed in one step or in two steps. In the first step, the portion of the protective layer 233 covering the top surface of the fin-shaped structure 200 and the shallow trench isolation structure 232 is etched away; in the second step, a portion of the shallow trench isolation structure 232 is anisotropically etched to expose the side wall of the strained layer 104 located below the fin-shaped structure.

[0161] In some embodiments, the protective layer 233 is silicon nitride, the substrate 100 is silicon, and the process gas may include chlorine or fluorinated carbon gas. The fluorinated carbon gas may be, for example, CF 4 or CHF 3 Of course, in the etching process, the process gas may also include a protective gas to provide protection for the sidewall 2331 of the protective layer. The protective gas may include N 2 , CH 4 More specifically, the radio frequency power range of the upper electrode is, for example, 100W to 3000W, and the radio frequency power range of the lower electrode is, for example, 50W to 1000W.

[0162] After completing the above step S1221, the above step S120 is performed. In some embodiments, as Figure 26 and Figure 27 shown, the strain layer 104 under the fin structure is etched from both sides along the first horizontal direction (i.e., parallel to the Figure 26 and Figure 27 X1 direction in ), to form a groove 105 under the fin structure. In some examples, as Figure 28 shown, in the above step S120, at least part of the strain layer 104 is etched to form a groove 105 along the first horizontal direction (i.e., parallel to the Figure 28 X1 direction in ) under the fin structure. That is, the side walls of the exposed strain layer 104 are laterally etched from both sides along the first horizontal direction to form the groove 105 for filling and forming an insulating portion in subsequent steps. In the embodiments shown in Figure 27 and Figure 28 , the strain layer 104 is completely etched to form a groove 105 that penetrates both sides of the fin structure. Compared with the related art shown in Figure 2 , in the process flow of manufacturing the insulating portion in the present application, an isotropic etching method is used to form the groove without forming a sacrificial region on the substrate surface. This can not only save the photolithography step and reduce the processing procedures, but also does not require ion implantation on the substrate surface, thereby greatly saving the processing cost. When the groove 105 penetrates both sides of the fin structure, the insulating portion filled in the groove 105 is usually made of an insulating material such as silicon nitride, silicon oxide, or silicon oxynitride, and the heat conduction efficiency is poor. The heat generated by the GAAFET cannot be effectively transferred from the insulating portion to the substrate, resulting in an increase in the temperature of the GAA FET, a decrease in the electron / hole mobility, and instead affecting the performance of the GAAFET. To solve this problem, in some other examples, as Figure 29 shown, in the above step S120, part of the strain layer 104 is etched to form a protrusion 101 facing the fin structure 200 and grooves 105 arranged side by side along the first horizontal direction on both sides of the protrusion 101. That is, from along the first horizontal direction (i.e., parallel to the Figure 29On both sides in the X1 direction), the sidewalls of the exposed strained layer 104 are laterally etched, but no grooves penetrating both sides of the fin structure are formed. Instead, a part of the substrate 100 is retained to form a protrusion 101 located between the two side grooves 105. The protrusion 101 is used to contact a part of the lower surface of the gate structure 300 to be fabricated later for heat conduction of the GAAFET. The two side grooves 105 are used to fill and form an insulating portion 102 in subsequent steps, so that the insulating portion 102 and the protrusion 101 arranged side by side can be formed between the gate structure 300 to be fabricated later and the substrate 100. In this way, both high-frequency switching characteristics and heat dissipation can be taken into account, and according to the requirements of the semiconductor device, the ratio of the contact areas of the protrusion 101 and the insulating portion 102 with the gate structure 300 can be adjusted. When the heat dissipation requirement of the semiconductor device is relatively high, the ratio of the contact area of the protrusion 101 with the gate structure 300 is increased. When the requirement for high-frequency switching characteristics is relatively high, the ratio of the contact area of the insulating portion 102 with the gate structure 300 is increased.

[0163] S130, as Figure 30 shown, an insulating portion 102 is filled and formed in the groove 105;

[0164] As described above, an insulating portion 102 can be filled and formed in the groove 105 as shown in Figure 28 and Figure 29 shown.

[0165] In some embodiments, in order to achieve the suppression effect of the parasitic gate capacitance by the insulating portion 102, the material of the insulating portion 102 may include at least one of silicon dioxide (SiO 2 ), silicon nitride (SiNx), hafnium oxide (HfOx), aluminum oxide (AlOx), and zinc oxide (ZeOx).

[0166] After completing the above step S130, the sidewall 2331 of the protective layer shown in Figure 26 is removed, and then step S140 is performed.

[0167] S140, as Figure 31 shown, one of the first semiconductor layer 210 and the second semiconductor layer 220 is removed;

[0168] For example, Figure 31 shows the structure after the first semiconductor layer 210 is removed, so that a number of vacancies are formed in the region corresponding to the gate structure 300.

[0169] In some embodiments, the substrate 100 is made of the same material as one of the first semiconductor layer 210 and the second semiconductor layer 220.

[0170] In some embodiments, the substrate 100 is Si, one of the first semiconductor layer 210 and the second semiconductor layer 220 is Si, and the other is SiGe.

[0171] For GAAFETs with Si, SiGe, or Ge-based channels, generally, Si is used for n-channel GAA FETs, while SiGe or Ge is used for p-channel GAAFETs. In the case of SiGe p-channel GAFETs, a higher Ge concentration can improve transistor performance. Those skilled in the art can remove the first semiconductor layer 210 and the second semiconductor layer 220 according to requirements.

[0172] S150, such as Figure 32 As shown, a gate structure 300 is formed around the other of the first semiconductor layer 210 and the second semiconductor layer 220.

[0173] In some embodiments, as Figure 4 shown, taking the first semiconductor layer 210 as an example, the gate structure 300 includes a gate dielectric layer 302 disposed around the second semiconductor layer 220 and a gate electrode layer 301 disposed around the gate dielectric layer 302. The first semiconductor layer 210 surrounded by the gate structure 300 constitutes the channel region 201 of the GAAFET.

[0174] In some embodiments, the gate dielectric layer 302 may include one or more layers of dielectric materials (such as silicon oxide, silicon nitride, or high-k dielectric materials), other suitable dielectric materials, and / or combinations thereof. The high-k dielectric materials may include, for example, HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, titanium oxide, hafnium oxide-aluminum oxide (HfO 2 -Al 2 O 3 ) alloys, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, an interface layer may also be formed between the channel region 201 and the gate dielectric layer 302. The gate dielectric layer 302 can be formed by CVD, ALD, or any suitable method. In an alternative embodiment, the thickness of the gate dielectric layer 302 is in the range of about 1 nm to about 6 nm.

[0175] In some embodiments, the gate electrode layer 302 may include one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, alloys thereof, other suitable materials, and / or combinations thereof. The gate electrode layer can be formed by CVD, ALD, electroplating, or other suitable methods.

[0176] In the above embodiments, the insulating portions 102 are arranged side by side on both sides of the protruding portion 101 along the first horizontal direction (i.e., parallel to Figure 4 the X1 direction), and the first horizontal direction is parallel to the arrangement direction of the fin structures 200 and perpendicular to the second horizontal direction (i.e., the arrangement direction of the source region and the drain region 400). Although this solution can achieve the effect of suppressing the parasitic gate capacitance, however, since the direction in which the insulating portion 102 is arranged side by side with the protruding portion 101 is perpendicular to the arrangement direction of the source region and the drain region 400, this makes it impossible for the insulating portion 102 to cut off the leakage current generated by the parasitic gate capacitance.

[0177] In order to cut off the leakage current generated by the parasitic gate capacitance, in some other embodiments, the above step S120 includes:

[0178] Etching the substrate 100 to partially remove the substrate 100 in contact with the fin structures 200;

[0179] The above preset horizontal direction is the second horizontal direction perpendicular to the arrangement direction of the fin structures 200, that is, as Figure 5 shown, the insulating portions 102 are arranged side by side on both sides of the protruding portion 101 along the second horizontal direction (i.e., parallel to Figure 5 the X2 direction). In this way, the insulating portions 102 located on both sides of the protruding portion 101 can cut off the leakage current generated by the parasitic gate capacitance, so that on the basis of achieving the effect of suppressing the parasitic gate capacitance, better leakage current control ability can be achieved.

[0180] Compared with the above embodiments, the manufacturing method of the semiconductor device provided in this embodiment also includes steps S111 to S115. After completing step S115, steps S1211 to S1217 will also be performed. These steps have been described in the above embodiments and will not be repeated here. On this basis, different from the above embodiments, after completing step S1217, this embodiment further includes:

[0181] S1215’: As Figure 33 shown, forming a protective layer 233’ on both sides of the fin structure in the second horizontal direction (i.e., parallel to Figure 33 the X2 direction);

[0182] Specifically, the above protective layer 233’ covers the dummy gate structure 234, the side portions 2371 of the first isolation wall, the shallow trench isolation structure 232, and the substrate 100 on both sides of the fin structure in the second horizontal direction. The manufacturing step of the protective layer 233’ (i.e., step S1215’) can be performed in Figure 19After a space formed by removing a predetermined thickness from one of the first semiconductor layer 210 and the second semiconductor layer 220 shown is filled with the second isolation wall 238 (i.e., step S1217), the protective layer 233' is used to protect the fin structure 200 from being laterally etched during the subsequent etching of the substrate 100 in step S120.

[0183] S1216': As Figure 34 shown, anisotropic etching is performed on the protective layer 233' to remove the portions of the protective layer 233' covering the shallow trench isolation structure 232 and the substrate 100, so as to expose the top surfaces of the substrate 100 and the shallow trench isolation structure 232, and the portion of the protective layer 233' covering the sidewalls of the fin structure is retained as a sidewall protective layer.

[0184] After completing the above step S1216', the above step S120 is performed. In some embodiments, this step S120 specifically includes:

[0185] S1201: As Figure 35 and Figure 36 shown, anisotropic etching is performed on at least a part of the exposed substrate 100 to expose the sidewall 106 of the substrate 100 not covered by the protective layer 233';

[0186] S1202: As Figure 37 and Figure 38 shown, isotropic etching is performed on the exposed substrate 100 to form a protrusion 101 facing the fin structure 200 and grooves 105 arranged side by side on both sides of the protrusion 101 along the second horizontal direction (i.e., parallel to Figure 38 the X2 direction).

[0187] The above grooves 105 are used to fill and form an insulating portion 102 in a subsequent step. Compared with the related art in the step of forming a sacrificial region, not only is it necessary to add a photolithography step to form a photoresist pattern on the substrate 100, but also ion implantation needs to be performed on the surface of the substrate 100, which not only increases the processing procedures, but also the ion implantation equipment is expensive, resulting in a higher processing cost.

[0188] In the above step S1202, lateral etching is performed on the sidewalls 106 of the exposed substrate 100 from both sides along the second horizontal direction, but grooves penetrating both sides of the fin structure are not formed, but a part of the substrate 100 is retained to form a protrusion 101 located between the grooves 105 on both sides. As Figure 5 shown, the protrusion 101 is used to contact a part of the lower surface of the gate structure 300 to be fabricated later, so as to conduct heat for the GAAFET. The grooves 105 on both sides are used to fill and form as Figure 5The insulating portion 102 shown, so that an insulating portion 102 and a protruding portion 101 arranged side by side can be formed between the subsequently fabricated gate structure 300 and the substrate 100, so that a balance can be achieved between the suppression effect on parasitic gate capacitance (and leakage current control ability) and the heat conduction effect on the GAA FET, avoiding affecting the performance of the GAA FET due to one of these two effects being too poor.

[0189] S130, as Figure 39 and Figure 40 shown, an insulating portion 102 is formed by filling in the groove 105;

[0190] Step S130 can be divided into two steps. First, a film layer of the insulating portion 102 is covered both in the groove 105 and on the protective layer 233'; second, the portions of the film layer of the insulating portion 102 on both sides of the protective layer 233 along the second horizontal direction are etched away, and the portion in the groove 105 below the fin structure 200 is retained.

[0191] After completing the above step S130, the protective layer 233' is removed.

[0192] After removing the protective layer 233', it further includes:

[0193] S131, as Figure 41 shown, source regions and drain regions 400 are formed on both sides of the fin structure 200 along the second horizontal direction (i.e., the X2 direction parallel to Figure 41 ).

[0194] That is to say, the direction in which the formed insulating portion 102 and the protruding portion 101 are arranged side by side is parallel to the arrangement direction of the source regions and drain regions 400 (i.e., the X2 direction parallel to Figure 41 ).

[0195] In a specific embodiment, after completing the above step S131, the manufacturing method of the semiconductor device further includes:

[0196] S132, as Figure 42 shown, an interlayer dielectric layer 239 is formed on the dummy gate structure 234 and the source regions and drain regions 400;

[0197] S133, as Figure 43 shown, the portion of the interlayer dielectric layer 239 corresponding to the dummy gate structure 234 and the dummy gate structure 234 are removed.

[0198] After completing step S133, step S140 and step S150 are performed, and these two steps are the same as those in the above embodiment and will not be elaborated here.

[0199] In the method for manufacturing a semiconductor device according to an embodiment of the present disclosure, there is no need to form a sacrificial region on the surface of the substrate 100. This can not only save the photolithography step and reduce the processing procedures, but also eliminate the need for ion implantation on the surface of the substrate 100, thereby significantly saving the processing cost.

[0200] In the foregoing embodiments of the present disclosure, the differences between the various embodiments are mainly described. As long as the different optimization features between the various embodiments are not contradictory, they can be combined to form a more optimal embodiment. For the sake of brevity of the description, they will not be elaborated herein.

[0201] The above are only the embodiments of the present disclosure and are not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included within the scope of the claims of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, wherein: include: forming at least one fin-shaped structure on a surface of a substrate, wherein the fin-shaped structure includes first semiconductor layers and second semiconductor layers that are alternately stacked; Etching the substrate below the fin-shaped structure from at least one side along a preset horizontal direction to form a groove below the fin-shaped structure; Filling the groove to form an insulating portion; removing one of the first semiconductor layer and the second semiconductor layer; A gate structure is formed around the other of the first semiconductor layer and the second semiconductor layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the semiconductor layer at the bottom of the fin-shaped structure is different from the lattice constant of the material of the substrate so as to apply stress to the top of the substrate to form a strained layer, and the substrate below the fin-shaped structure is etched from at least one side along a preset horizontal direction to form a groove below the fin-shaped structure, comprising: The substrate is isotropically etched using a preset etching gas to selectively remove at least a portion of the strained layer, wherein the preset horizontal direction is a first horizontal direction parallel to an arrangement direction of the fin-shaped structures.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The preset etching gas includes a fluorine-containing gas and an auxiliary etching gas, and the auxiliary etching gas includes oxygen and nitrogen.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The fluorine-containing gas includes at least one of CF4, C4F8, C3F6, CHF3, CH2F2, and CH3F; and / or The auxiliary etching gas includes at least one of N2, O2, NO, and NO2.

5. The method for manufacturing a semiconductor device according to claim 3, wherein: The ratio of fluorine to oxygen is in the range of 0.1 to 10; or The content ratio of fluorine element to nitrogen element ranges from 0.1 to 10.

6. The method for manufacturing a semiconductor device according to any one of claims 2 to 5, wherein: Before etching the substrate below the fin-shaped structure from at least one side along a preset horizontal direction to form a groove below the fin-shaped structure, the method further includes: A source region and a drain region are formed on both sides of the fin-shaped structure along a second horizontal direction, and the second horizontal direction is perpendicular to the first horizontal direction.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: Before forming the source region and the drain region on both sides of the fin-shaped structure along the second horizontal direction, the method further includes: Forming a protection layer covering the fin-shaped structure and the substrate on both sides and a top surface of the fin-shaped structure along the first horizontal direction; After forming the source region and the drain region on both sides of the fin-shaped structure along the second horizontal direction, and before etching the substrate below the fin-shaped structure from at least one side along the preset horizontal direction to form a groove below the fin-shaped structure, the method further includes: The protection layer is anisotropically etched to remove the protection layer covering the fin-shaped structure and the top of the substrate, so as to expose the strain layer from the bottom side of the fin-shaped structure.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The etching of the substrate below the fin-shaped structure from at least one side along a preset horizontal direction to form a groove below the fin-shaped structure comprises: The substrate is etched to partially remove the substrate in contact with the fin-shaped structure, and the preset horizontal direction is a second horizontal direction perpendicular to the arrangement direction of the fin-shaped structure.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: Before etching the substrate, the method further comprises: forming a protective layer on both sides of the fin-shaped structure in the second horizontal direction; The etching of the substrate comprises: Performing anisotropic etching on at least a portion of the exposed substrate to expose a sidewall of the substrate that is not covered by the protective layer; The exposed substrate is isotropically etched to form a protrusion facing the fin-shaped structure and the grooves located side by side on both sides of the protrusion along the second horizontal direction.

10. The method for manufacturing a semiconductor device according to claim 8, wherein: After the insulating portion is filled in the groove, the method further comprises: A source and a drain are formed on both sides of the fin structure along the second horizontal direction.

11. The method for manufacturing a semiconductor device according to claim 1, wherein: The substrate and one of the first semiconductor layer and the second semiconductor layer are made of the same material; or, The substrate is Si, one of the first semiconductor layer and the second semiconductor layer is Si, and the other is SiGe.

12. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the insulating portion includes at least one of silicon dioxide, silicon nitride, hafnium oxide, aluminum oxide, and zinc oxide.

13. A semiconductor device, wherein: include: substrate; at least one channel region formed on the substrate; A gate structure formed around each of the channel regions; in The substrate has a protrusion facing the gate structure, and the protrusion contacts a portion of the lower surface of the gate structure; The semiconductor device further comprises an insulating portion, which is arranged side by side with the protruding portion, wherein an upper surface of the insulating portion is flush with an upper surface of the protruding portion and contacts a portion of a lower surface of the gate structure.

14. The semiconductor device according to claim 13, wherein: The insulating parts are arranged side by side on two sides of the protruding part along a preset horizontal direction.

15. The semiconductor device according to claim 14, wherein: The semiconductor device further comprises a source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively located on two sides of the gate structure along the second horizontal direction; The preset horizontal direction is parallel to the second horizontal direction; or, The preset horizontal direction is perpendicular to the second horizontal direction.

16. The semiconductor device according to claim 13, wherein: The thickness of the insulating portion in the vertical direction is 0.5 to 1.5 times the thickness of the channel region in the vertical direction; or, The thickness of the insulating portion in the vertical direction is 0.8 to 1.2 times the thickness of the channel region in the vertical direction.

17. The semiconductor device according to claim 13, wherein: The orthographic projection shape of the insulating portion on the vertical plane is a wedge shape; or The orthographic projection shape of the bottom of the insulating portion on the vertical plane is an arc shape.

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