Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present disclosure provide a semiconductor device manufacturing method, at least one fin structure is formed on a substrate surface, the fin structure includes first semiconductor layers and second semiconductor layers which are alternately stacked; a substrate under the fin structure is etched from at least one side along a preset horizontal direction to form a groove under the fin structure; an insulating part is formed by filling in the groove; one of the first semiconductor layers and the second semiconductor layers is removed; and a gate structure is formed around the other one of the first semiconductor layers and the second semiconductor layers. Embodiments of the present disclosure also provide a semiconductor device.

Description

Technical Field

[0001] This disclosure belongs to, but is not limited to, the field of semiconductor manufacturing technology, and specifically relates to a semiconductor device and its manufacturing method. Background Technology

[0002] As semiconductor manufacturing processes continue to advance, the critical dimensions of semiconductor devices are shrinking. However, the shrinking gate width leads to the so-called short-channel effects, which cause drain-induced barrier lowering (DIBL), making it impossible for the semiconductor device to be turned off.

[0003] To address this challenge, FinFET and Gate-All-Around Field-Effect Transistor (GAAFET) have been proposed. In 3nm and finer process technologies, GAAFET exhibits significant advantages over FinFET, such as better control of leakage current, smaller DIBL (Displacement Diode), higher performance, and greater device density.

[0004] Conventional GAAFETs, such as Figure 1 and Figure 2 As shown, it includes a substrate 11, a plurality of channel regions 12 formed on the substrate 11, and a gate structure 13 disposed around the channel regions 12. All sides of the channel regions 12 are surrounded by the gate structure 13, thereby enabling a smaller DIBL. In this GAAFET structure, a parasitic gate capacitance is formed between the bottom of the gate structure 13 and the substrate 11. When a turn-on or turn-off voltage is applied to the gate structure 13, this parasitic gate capacitance is charged, thereby affecting the turn-on or turn-off speed of the GAAFET and reducing the high-frequency switching characteristics of the GAAFET. Summary of the Invention

[0005] This disclosure provides a semiconductor device and a method for manufacturing the same, in order to solve the problem of poor high-frequency switching characteristics of semiconductor devices in the related art.

[0006] To address the aforementioned technical problems, this disclosure provides a method for manufacturing a semiconductor device, comprising:

[0007] At least one fin-shaped structure is formed on the surface of a substrate, the fin-shaped structure comprising alternating stacked first and second semiconductor layers;

[0008] The substrate beneath the fin structure is etched from at least one side along a predetermined horizontal direction to form a groove beneath the fin structure;

[0009] An insulating portion is formed by filling the groove;

[0010] Remove one of the first semiconductor layer and the second semiconductor layer;

[0011] A gate structure is formed around the other of the first semiconductor layer and the second semiconductor layer.

[0012] In some embodiments, the material of the lowermost semiconductor layer of the fin structure has a different lattice constant than the material of the substrate, so as to apply stress to the top of the substrate to form a strain layer. Etching the substrate below the fin structure from at least one side along a predetermined horizontal direction to form a groove below the fin structure includes:

[0013] The substrate is isotropically etched using a preset etching gas to selectively remove at least a portion of the strain layer, wherein the preset horizontal direction is a first horizontal direction parallel to the arrangement direction of the fin structure.

[0014] In some embodiments, the preset etching gas includes a fluorine-containing gas and an auxiliary etching gas, wherein the auxiliary etching gas includes oxygen and nitrogen.

[0015] In some embodiments, the fluorine-containing gas includes at least one of CF4, C4F8, C3F6, CHF3, CH2F2, and CH3F; and / or

[0016] The auxiliary etching gas includes at least one of N2, O2, NO, and NO2.

[0017] In some embodiments, the ratio of fluorine to oxygen content ranges from 0.1 to 10; or

[0018] The ratio of fluorine to nitrogen content ranges from 0.1 to 10.

[0019] In some embodiments, prior to etching the substrate beneath the fin structure from at least one side along a predetermined horizontal direction to form a groove beneath the fin structure, the method further includes:

[0020] Source and drain regions are formed on both sides of the fin-shaped structure along a second horizontal direction, which is perpendicular to the first horizontal direction.

[0021] In some embodiments, before forming the source and drain regions on both sides of the fin structure along the second horizontal direction, the method further includes:

[0022] A protective layer covering the fin structure and the substrate is formed on both sides and the top surface of the fin structure along the first horizontal direction;

[0023] After forming source and drain regions on both sides of the fin structure along the second horizontal direction, and before etching the substrate below the fin structure from at least one side along a predetermined horizontal direction to form a groove below the fin structure, the method further includes:

[0024] The protective layer is anisotropically etched to remove the protective layer covering the top of the fin structure and the substrate, thereby exposing the strain layer from the bottom side of the fin structure.

[0025] In some embodiments, etching the substrate below the fin structure from at least one side along a predetermined horizontal direction to form a groove below the fin structure includes:

[0026] The substrate is etched to partially remove the substrate that is in contact with the fin structure, wherein the preset horizontal direction is a second horizontal direction perpendicular to the arrangement direction of the fin structure.

[0027] In some embodiments, prior to etching the substrate, the method further includes:

[0028] A protective layer is formed on both sides of the fin-shaped structure in the second horizontal direction;

[0029] The etching of the substrate includes:

[0030] Anisotropic etching is performed on at least a portion of the exposed substrate to expose the sidewalls of the substrate not covered by the protective layer;

[0031] The exposed substrate is isotropically etched to form a protrusion facing the fin structure and a groove located side by side on both sides of the protrusion along the second horizontal direction.

[0032] In some embodiments, after the insulating portion is formed by filling the groove, the method further includes:

[0033] A source and a drain are formed on both sides of the fin-shaped structure along the second horizontal direction.

[0034] In some embodiments, the substrate is made of the same material as one of the first semiconductor layer and the second semiconductor layer; or...

[0035] The substrate is Si, and one of the first semiconductor layer and the second semiconductor layer is Si, while the other is SiGe.

[0036] In some embodiments, the material of the insulating portion includes at least one of silicon dioxide, silicon nitride, hafnium oxide, aluminum oxide, and zinc oxide.

[0037] As another technical solution, the present invention also provides a semiconductor device, comprising:

[0038] Substrate;

[0039] At least one channel region is formed on the substrate;

[0040] A gate structure is formed around each of the channel regions; wherein

[0041] The substrate has a protrusion facing the gate structure, the protrusion being in contact with a portion of the lower surface of the gate structure;

[0042] The semiconductor device further includes an insulating portion, which is arranged side by side with the protrusion. The upper surface of the insulating portion is flush with the upper surface of the protrusion and contacts a portion of the lower surface of the gate structure.

[0043] In some embodiments, the insulating portions are arranged side by side on both sides of the protrusion along a predetermined horizontal direction.

[0044] In some embodiments, the semiconductor device further includes a source and a drain, the source and the drain being located on opposite sides of the gate structure along a second horizontal direction;

[0045] The preset horizontal direction is parallel to the second horizontal direction; or...

[0046] The preset horizontal direction is perpendicular to the second horizontal direction.

[0047] In some embodiments, the thickness of the insulating portion in the vertical direction is 0.5 to 1.5 times the thickness of the channel region in the vertical direction; or,

[0048] The thickness of the insulation portion in the vertical direction is 0.8 to 1.2 times the thickness of the channel region in the vertical direction.

[0049] In some embodiments, the orthographic projection of the insulating portion onto a vertical plane is wedge-shaped; or

[0050] The bottom of the insulating part has an arc-shaped orthographic projection on a vertical plane. Attached Figure Description

[0051] Figure 1 This is a vertical cross-sectional view of a GAAFET in a related technology, with the arrangement direction parallel to the source and drain regions.

[0052] Figure 2This is a vertical cross-sectional view of a GAAFET in a related technology, perpendicular to the arrangement direction of the source and drain regions.

[0053] Figure 3 A vertical cross-sectional schematic diagram of a GAAFET arranged perpendicular to the source and drain regions is shown in another related technology;

[0054] Figure 4 A partial schematic diagram of a semiconductor device in a cross-section perpendicular to a second horizontal direction, provided as an embodiment of the present invention;

[0055] Figure 5 A partial schematic diagram of a cross-section parallel to the second horizontal direction for another semiconductor device provided in an embodiment of the present invention;

[0056] Figure 6 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0057] Figure 7 This is a structural diagram of a semiconductor device completing step S111 according to an embodiment of the present invention;

[0058] Figure 8 This is a structural diagram of a semiconductor device completing step S112 according to an embodiment of the present invention;

[0059] Figure 9 This is a structural diagram of a semiconductor device completing step S113 according to an embodiment of the present invention;

[0060] Figure 10 An electron microscope scanning image of a semiconductor device completing step S120, provided in an embodiment of the present invention;

[0061] Figure 11 This is a structural diagram of a semiconductor device completing step S114 according to an embodiment of the present invention;

[0062] Figure 12 This is a structural diagram of a semiconductor device completing step S115 according to an embodiment of the present invention;

[0063] Figure 13 This is a structural diagram of a semiconductor device completing step S1211 according to an embodiment of the present invention;

[0064] Figure 14 This is a structural diagram of a semiconductor device completing step S1212 according to an embodiment of the present invention;

[0065] Figure 15 This is a structural diagram of a semiconductor device completing step S1213 according to an embodiment of the present invention;

[0066] Figure 16This is a structural diagram of a semiconductor device completing step S1214 according to an embodiment of the present invention;

[0067] Figure 17 This is a structural diagram of a semiconductor device completing step S1215 according to an embodiment of the present invention;

[0068] Figure 18 This is a structural diagram of a semiconductor device completing step S1216 according to an embodiment of the present invention;

[0069] Figure 19 This is a structural diagram of a semiconductor device completing step S1217 according to an embodiment of the present invention;

[0070] Figure 20 This is a structural diagram of a semiconductor device completing step S1218 according to an embodiment of the present invention;

[0071] Figure 21 This is a structural diagram of a semiconductor device completing step S1219 according to an embodiment of the present invention;

[0072] Figure 22 This is a structural diagram of a semiconductor device completing step S1220 according to an embodiment of the present invention;

[0073] Figure 23 A cross-sectional view along a first horizontal direction showing the completion of step S1220 of a semiconductor device according to an embodiment of the present invention;

[0074] Figure 24 This is a structural diagram of a semiconductor device completing step S1221 according to an embodiment of the present invention;

[0075] Figure 25 A cross-sectional view along a first horizontal direction showing the completion of step S1221 of a semiconductor device according to an embodiment of the present invention;

[0076] Figure 26 This is a structural diagram of a semiconductor device completing step S120 according to an embodiment of the present invention;

[0077] Figure 27 A cross-sectional view along a second horizontal direction showing the completion of step S120 of a semiconductor device according to an embodiment of the present invention;

[0078] Figure 28 A cross-sectional view along a first horizontal direction showing the completion of step S120 of a semiconductor device according to an embodiment of the present invention;

[0079] Figure 29 Another cross-sectional view along a first horizontal direction for a semiconductor device to complete step S120, as provided in an embodiment of the present invention;

[0080] Figure 30 A cross-sectional view along a second horizontal direction showing the completion of step S130 of a semiconductor device according to an embodiment of the present invention;

[0081] Figure 31 This is a structural diagram of a semiconductor device completing step S140 according to an embodiment of the present invention;

[0082] Figure 32 A cross-sectional view along a second horizontal direction showing the completion of step S150 of a semiconductor device according to an embodiment of the present invention;

[0083] Figure 33 A structural diagram of another semiconductor device completing step S1215' provided in an embodiment of the present invention;

[0084] Figure 34 A structural diagram of another semiconductor device completing step S1216' provided in an embodiment of the present invention;

[0085] Figure 35 This is a structural diagram of another semiconductor device completing step S1201 according to an embodiment of the present invention;

[0086] Figure 36 A cross-sectional view along a second horizontal direction for another semiconductor device to complete step S1201 according to an embodiment of the present invention;

[0087] Figure 37 This is a structural diagram of another semiconductor device completing step S1202 according to an embodiment of the present invention;

[0088] Figure 38 A cross-sectional view along a second horizontal direction for another semiconductor device to complete step S1202 according to an embodiment of the present invention;

[0089] Figure 39 This is a structural diagram of another semiconductor device completing step S130 according to an embodiment of the present invention;

[0090] Figure 40 A cross-sectional view along a second horizontal direction for completing step S130 of another semiconductor device provided in an embodiment of the present invention;

[0091] Figure 41 A cross-sectional view along a second horizontal direction for completing step S131 of another semiconductor device provided in an embodiment of the present invention;

[0092] Figure 42 A cross-sectional view along a second horizontal direction for another semiconductor device to complete step S132 according to an embodiment of the present invention;

[0093] Figure 43 A cross-sectional view along a second horizontal direction for completing step S133 of another semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0094] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0095] Those skilled in the art should understand that the embodiments disclosed herein are merely illustrative of the structures and methods claimed in this disclosure that can be implemented in various forms. Furthermore, each example given in conjunction with the various embodiments is intended to be illustrative and not restrictive. Additionally, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show detail of particular components. Therefore, the specific structural and functional details in the embodiments of this disclosure should not be construed as restrictive, but merely as a representative basis for teaching those skilled in the art to employ the methods and structures of the embodiments of this disclosure in different ways. It should also be noted that identical and corresponding elements are denoted by the same reference numerals.

[0096] In the following description, numerous specific details, such as particular structures, components, materials, dimensions, processing steps, and techniques, are set forth in order to provide an understanding of various embodiments of this disclosure. However, those skilled in the art will understand that various embodiments of this disclosure can be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring this disclosure.

[0097] For the purposes described below, the terms “up,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives should be understood in relation to the orientation in the structures and methods disclosed in the accompanying drawings. It should be understood that when an element, as a layer, region, or substrate, is referred to as being on another element, that element may be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being directly on another element, there are no intermediate elements between them. It should also be understood that when an element is referred to as being under another element, that element may be directly under the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being directly under another element, there are no intermediate elements between them.

[0098] GAAFET in related technologies, such as Figure 1 and Figure 2 As shown, Figure 1 This is a vertical cross-sectional view of the GAAFET in the related technology, parallel to the arrangement direction of the source and drain regions 15. Figure 2 This is a vertical cross-sectional view of a GAA FET in the related art, perpendicular to the arrangement direction of the source and drain regions 15. The GAA FET includes a substrate 11, a plurality of channel regions 12 formed on the substrate 11, and a gate structure 13 disposed around the channel regions 12, wherein the gate structure 13 includes a gate dielectric layer and a gate electrode layer surrounding the channel regions 12. In this GAA FET structure, a parasitic gate capacitance is formed between the bottom of the gate structure 13 and the substrate 11. When a turn-on or turn-off voltage is applied to the gate structure 13, the parasitic gate capacitance is charged, thereby affecting the turn-on or turn-off speed of the GAA FET and reducing the high-frequency switching characteristics of the GAA FET.

[0099] To solve this problem, another related technology, such as Figure 3 As shown, an insulating layer 14 is disposed between the bottom of the gate structure 13 of the GAAFET and the substrate 11 to suppress parasitic gate capacitance and improve the high-frequency switching characteristics of the GAAFET. The inventors of this disclosure have discovered that the heat generated by the GAAFET needs to be efficiently released. Without the insulating layer 14, heat can be conducted to the substrate 11 through the bottom gate structure 13. However, with the insulating layer 14, since it is typically made of insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride, its thermal conductivity is poor. Therefore, the heat generated by the GAAFET cannot be effectively conducted from the insulating layer 14 to the substrate 11, resulting in an increase in the temperature of the GAAFET and a decrease in electron / hole mobility, which in turn affects the performance of the GAAFET.

[0100] To resolve the above issues, please refer to Figure 4 The main concept of the semiconductor device proposed in this disclosure is that the substrate 100 has a protrusion 101 facing the gate structure 300. The protrusion 101 contacts a portion of the lower surface of the gate structure 300 and serves as a heat-conducting layer, allowing the heat generated by the GAAFET to be conducted to the substrate 100 through the protrusion 101. The remaining lower surface of the gate structure 300 contacts the insulating portion 102, reducing the influence of parasitic gate capacitance and improving the high-frequency switching characteristics of the GAAFET. This disclosure, by providing the insulating portion 102 and the protrusion 101 side-by-side between the gate structure 300 and the substrate 100, can balance high-frequency switching characteristics and heat dissipation. Furthermore, the contact area ratio between the protrusion 101 and the insulating portion 102 and the gate structure 300 can be adjusted according to the needs of the semiconductor device. When the heat dissipation requirements of the semiconductor device are high, the contact area ratio between the protrusion 101 and the gate structure 300 is increased; when the high-frequency switching characteristics are high, the contact area ratio between the insulating portion 102 and the gate structure 300 is increased.

[0101] The technical solutions provided by the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0102] This disclosure provides a semiconductor device including: a substrate 100, at least one channel region 201, and a gate structure 300. At least one channel region 201 is formed on the substrate 100; the gate structure 300 is formed around each channel region 201. The substrate 100 has a protrusion 101 facing the gate structure 300, and the protrusion 101 contacts a portion of the lower surface of the gate structure 300. The semiconductor device also includes an insulating portion 102, which is disposed side-by-side with the protrusion 101. The upper surface of the insulating portion 102 is flush with the upper surface of the protrusion 101 and contacts a portion of the lower surface of the gate structure 300.

[0103] This embodiment of the present disclosure provides an insulating portion 102 and a protrusion 101 arranged side by side between the gate structure 300 and the substrate 100. This arrangement can balance high-frequency switching characteristics with heat dissipation. Furthermore, the contact area ratio between the protrusion 101 and the insulating portion 102 and the gate structure 300 can be adjusted according to the requirements of the semiconductor device. When the heat dissipation requirements of the semiconductor device are high, the contact area ratio between the protrusion 101 and the gate structure 300 is increased. When the high-frequency switching characteristics are high, the contact area ratio between the insulating portion 102 and the gate structure 300 is increased.

[0104] Moreover, since the protrusion 101 is part of the substrate 100, the heat conduction of the GAAFET can be achieved using the structure of the substrate 100 itself without the need to add an additional film layer. This not only simplifies the structure but also simplifies the manufacturing process of semiconductor devices and reduces costs.

[0105] In some embodiments, the substrate 100 may be made of Si. One or more buffer layers (not shown) may also be formed on the surface of the substrate 100. The buffer layers may be used to gradually change the lattice constant from the lattice constant of the substrate 100 to the lattice constant of the source / drain region. For example, the lattice constants of multiple buffer layers may gradually change from the substrate 100 to the source / drain region to reduce the difference in lattice constants between any two adjacent layers (including the substrate 100 and an adjacent buffer layer, each adjacent buffer layer, and the source / drain region and an adjacent buffer layer). The buffer layers may be formed from epitaxially grown single-crystal semiconductor materials, such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP.

[0106] Based on this, since the protrusion 101 is part of the substrate 100 and is also made of Si, this material can achieve better thermal conductivity for the GAAFET compared to the material of the insulating part 102.

[0107] In some embodiments, in order to achieve the effect of suppressing parasitic gate capacitance (and leakage current control capability), the material of the insulating part 102 may include at least one of silicon dioxide (SiO2), silicon nitride (SiNx), hafnium oxide (HfOx), aluminum oxide (AlOx) and zinc oxide (ZeOx).

[0108] In some embodiments, for ease of processing, insulating portions 102 are arranged side-by-side on both sides of the protrusion 101 along a predetermined horizontal direction. This predetermined horizontal direction is parallel to the surface of the substrate 100. The surface of the substrate 100 is, for example, parallel to a horizontal plane. Thus, in the process of fabricating the protrusion 101 and the insulating portion 102, the surface of the substrate 100 is first etched from both sides along the predetermined horizontal direction to form the protrusion 101 and the grooves located on both sides of the protrusion 101; then the insulating portion 102 is formed by filling the grooves, thereby creating the protrusion 101 and the insulating portion 102 arranged side-by-side.

[0109] In some embodiments, the thickness of the insulating portion 102 in the vertical direction is 0.5 to 1.5 times the thickness of the channel region 201 in the vertical direction. Preferably, the thickness of the insulating portion 102 in the vertical direction is 0.8 to 1.2 times the thickness of the channel region 201 in the vertical direction.

[0110] It should be noted that, as Figure 4 As shown, if the etching method on the surface of the substrate 100 is different, the orthographic projection shape of the protrusion 101 and the insulating portion 102 formed on the substrate 100 in the vertical plane (i.e., the shape of the groove used to fill the insulating portion 102) may be different, for example, as Figure 4 As shown, the width of the protrusion 101 in the X1 direction is smaller the closer it is to the gate structure 300. That is, the orthographic projection shape of the insulating portion 102 on the vertical plane (i.e., the surface perpendicular to the substrate 100) is wedge-shaped, and the depth of the orthographic projection shape of the insulating portion 102 on the vertical plane in the Z direction is larger the further away from the protrusion 101. For example, as... Figure 5 As shown, the orthographic projection shape of the insulating portion 102 on the vertical surface (i.e., the surface perpendicular to the substrate 100) is arc-shaped, and the depth of the orthographic projection shape of the insulating portion 102 on the vertical surface in the Z direction is larger the further away from the protrusion 101.

[0111] Furthermore, in some embodiments, such as Figure 5 As shown, the semiconductor device also includes a source region and a drain region 400, which are located along the second horizontal direction (i.e., parallel to the gate structure 300) of the gate structure 300. Figure 5 On both sides of the X2 direction (in the middle). In this case, the aforementioned preset horizontal direction is, for example, perpendicular to the second horizontal direction, i.e., as... Figure 4 As shown, the insulating portions 102 are arranged side by side on the protrusion 101 along the first horizontal direction (i.e., parallel to). Figure 4 On both sides of the X1 direction (in the diagram), the first horizontal direction is perpendicular to the second horizontal direction. In other embodiments, to cut off the leakage current generated by the parasitic gate capacitance, preferably, as shown in the diagram... Figure 5 As shown, the aforementioned preset horizontal direction is parallel to the second horizontal direction (i.e., parallel to...). Figure 5 In the X2 direction, that is, the insulating portions 102 are arranged side by side on both sides of the protrusion 101 along the second horizontal direction. In this way, the insulating portions 102 located on both sides of the protrusion 101 can cut off the leakage current generated by the parasitic gate capacitance, thereby achieving better leakage current control capability while suppressing the parasitic gate capacitance.

[0112] It should be noted that since the insulating portion 102 and the protrusion 101 are arranged in different directions, the manufacturing steps of the insulating portion 102 and the protrusion 101 may differ from the manufacturing steps of the source region and the drain region 400. For example, if the insulating portion 102 is arranged side by side on the protrusion 101 along the first horizontal direction (i.e., parallel to...), the manufacturing steps may differ. Figure 4 The source and drain regions 400 are located on either side of the gate structure 300 along the second horizontal direction (i.e., parallel to the X1 direction). Figure 5 If the source and drain regions 400 are located on both sides of the gate structure 300 along the second horizontal direction (X2 direction), the fabrication steps for the insulating portion 102 and the protrusion 101 can be performed first, followed by the fabrication steps for the insulating portion 102 and the protrusion 101. Conversely, if the insulating portion 102 is arranged side by side on both sides of the protrusion 101 along the second horizontal direction, and the source and drain regions 400 are located on both sides of the gate structure 300 along the second horizontal direction, the fabrication steps for the insulating portion 102 and the protrusion 101 can be performed first, followed by the fabrication steps for the source and drain regions 400. In addition, the processing methods for the insulating portion 102 and the protrusion 101 with different arrangement directions may also be different, which will be described in detail later.

[0113] It should be noted that the embodiments disclosed herein are not limited to the side-by-side arrangement of the insulating portion 102 and the protrusion 101 described above. In practical applications, the insulating portion 102 may also be arranged side-by-side on one side of the protrusion 101 along a preset horizontal direction (e.g., parallel to the first or second horizontal direction), or the insulating portion 102 may also be arranged side-by-side on at least one side of the protrusion 101 along the first horizontal direction and at least one side along the second horizontal direction. As long as the insulating portion 102 and the protrusion 101 are arranged side-by-side between the gate structure 300 and the substrate 100, both high-frequency switching characteristics and heat dissipation can be taken into account to ensure the performance of the GAAFET.

[0114] like Figure 3 In the related technologies shown, during the fabrication of the insulating layer 14, a sacrificial region is formed on the surface of the substrate 11. After fabricating the fin structure, the sacrificial region is removed to form a cavity between the substrate 11 and the fin structure for filling the cavity where the insulating layer 14 is formed. However, because the related technologies require not only an additional photolithography step to form a photoresist pattern on the substrate 11 during the sacrificial region formation step, but also ion implantation on the substrate surface, this not only increases the number of processing steps but also results in high processing costs due to the expensive ion implantation equipment.

[0115] To resolve the above issues, please refer to Figure 6 This disclosure also provides a method for manufacturing a semiconductor device, comprising:

[0116] S110. Form at least one fin-shaped structure on the surface of a substrate, the fin-shaped structure comprising alternating stacked first semiconductor layers and second semiconductor layers;

[0117] Specifically, step S110 above, i.e., forming a fin-shaped structure on the substrate surface, may include:

[0118] S111, such as Figure 7 As shown, an alternately stacked first semiconductor layer 210 and second semiconductor layer 220 are formed on the surface of substrate 100.

[0119] In some embodiments, the substrate 100 and one of the first semiconductor layer 210 and the second semiconductor layer 220 are made of the same material. Further, in some embodiments, the first semiconductor layer 210 and the second semiconductor layer 220 are made of Si, Si compounds, SiGe, Ge, or Ge compounds. Figure 7 In the example, substrate 100 is Si, first semiconductor layer 210 is SiGe, and second semiconductor layer 220 is Si.

[0120] exist Figure 7 The illustration shows four first semiconductor layers 210 and three second semiconductor layers 220; however, the embodiments disclosed herein are not limited to this, and more or fewer first semiconductor layers 210 and second semiconductor layers 220 are feasible. In some embodiments, each of the first semiconductor layer 210 and the second semiconductor layer 220 is formed as two to 20 layers. The drive current of the GAAFET device can be adjusted by adjusting the number of first semiconductor layers 210 and / or second semiconductor layers 220.

[0121] A first semiconductor layer 210 and a second semiconductor layer 220 are epitaxially formed over the substrate 100. The thickness of the first semiconductor layer 210 and the thickness of the second semiconductor layer 220 may be the same or different. Furthermore, the thickness of each layer in the first semiconductor layer 210 may be the same or different; the thickness of each layer in the second semiconductor layer 220 may be the same or different. This disclosure does not limit the specific thickness of these layers. In some embodiments, the thickness of the first semiconductor layer 210 is in the range of 2 nm to 20 nm. In some embodiments, the thickness of the second semiconductor layer 220 is in the range of 2 nm to 20 nm.

[0122] S112, such as Figure 8 As shown, a patterned hard mask layer 231 is formed over an alternately stacked first semiconductor layer 210 and second semiconductor layer 220;

[0123] It should be noted that the hard mask layer 231 covers the upper surface of the topmost first semiconductor layer 210 in its entirety before patterning. Then, a photoresist pattern is formed using a mask, and the excess portion of the hard mask layer 231 is etched away during patterning to obtain... Figure 8 The patterned hard mask layer 231 shown. The hard mask layer 231 can be a silicon oxide layer, a silicon nitride layer, or a stack of silicon oxide and silicon nitride layers.

[0124] S113, such as Figure 9 As shown, the first semiconductor layer 210, the second semiconductor layer 220 and the substrate 100 are etched using a patterned hard mask layer 231 to obtain a fin structure 200, while isolation trenches 103 are formed in the substrate 100 on both sides of the fin structure 200.

[0125] like Figure 9 As shown, in this step, multiple fin structures 200 can be obtained, and the arrangement direction of the multiple fin structures 200 is parallel to the first horizontal direction (i.e., parallel to the first horizontal direction). Figure 9 (in the X1 direction). Figure 9 Only one fin structure 200 is shown. Furthermore, after etching of the alternately stacked first semiconductor layer 210 and second semiconductor layer 220 is completed, etching of the underlying substrate 100 can continue to form isolation trenches 103 within the substrate 100 between each pair of adjacent fin structures 200, facilitating subsequent formation of structures such as... Figure 11 The shallow trench isolation (STI) structure 232 shown is used to electrically isolate adjacent GAA-FETs.

[0126] S120. Etch the substrate below the fin structure from at least one side along a predetermined horizontal direction to form a groove below the fin structure.

[0127] The aforementioned grooves are used to fill and form insulating portions in subsequent steps. Compared to related technologies, the process of forming the sacrificial region not only requires an additional photolithography step to form a photoresist pattern on the substrate, but also ion implantation on the substrate surface. This not only increases the number of processing steps, but also makes the ion implantation equipment expensive, resulting in higher processing costs.

[0128] In some embodiments, the material of the lowest semiconductor layer of the fin structure 200 (e.g., Figure 9 The material of the first semiconductor layer 210 shown has a different lattice constant than that of the substrate 100, so as to apply stress to the top of the substrate 100 to form a strain layer. Specifically, the top region of the substrate 100 near the fin structure 200 (called the Sub-Fin region, i.e., the strain layer) is more affected by the stress of the material of the bottommost semiconductor layer of the fin structure 200, and this strain layer has a higher etching rate than other regions of the substrate 100 during isotropic etching. Based on the above principle, the above step S120 specifically includes:

[0129] The substrate 100 is isotropically etched using a preset etching gas to selectively remove at least a portion of the strained layer.

[0130] In step S120 above, the preset horizontal direction is a first horizontal direction that is parallel to the arrangement direction of the fin-shaped structure 200 (i.e., parallel to...). Figure 9 (in the X1 direction). Because the strain layer of substrate 100 has a higher etching rate than other areas of substrate 100, the trench depth can be controlled more precisely, avoiding excessive trench depth and thus meeting the stringent requirements of the process for trench depth. Figure 10 As shown, in the embodiment where the substrate 100 is Si and the first semiconductor layer 210 is SiGe, after completing the above step S120, the following can be obtained: Figure 10 Specifically, the depth of the groove 105 in the vertical plane increases further away from the protrusion 101 along the direction parallel to X1. The width of the protrusion 101 in the X1 direction decreases as it approaches the fin structure 200. Furthermore, the first semiconductor layer 210 at the bottom of the fin structure 200 is essentially unetched, indicating a large etching selectivity between the substrate 100 and the first semiconductor layer 210.

[0131] In step S120 above, the preset etching gas used for isotropic etching satisfies the following condition: the etching selectivity ratio between the substrate 100 and the lowermost semiconductor layer of the fin structure 200 is greater than a predetermined value, thereby ensuring that the aforementioned groove 105 is formed on the substrate 100 without damaging the lowermost semiconductor layer of the fin structure 200. For example, the substrate 100 is Si, and the lowermost first semiconductor layer 210 is adjacent to the substrate 100 and is SiGe. In some embodiments, the preset etching gas includes a fluorine-containing gas and an auxiliary etching gas, the auxiliary etching gas including oxygen and nitrogen. The fluorine-containing gas is the main etching gas, which, after being excited, generates fluoride ions and fluorine-containing free radicals that react with the substrate 100 to achieve etching. The auxiliary etching gas is used to adjust the etching selectivity ratio between the substrate 100 and the semiconductor layer, thereby achieving selective etching of the substrate 100.

[0132] Furthermore, in some embodiments, the fluorine-containing gas includes at least one of CF4, C4F8, C3F6, CHF3, CH2F2, and CH3F.

[0133] In some embodiments, the auxiliary etching gas includes at least one of N2, O2, NO, and NO2.

[0134] Depend on Figure 10 It can be clearly seen that, based on the aforementioned fluorine-containing gas, the addition of the aforementioned auxiliary etching gas can significantly improve the etching selectivity of Si relative to SiGe, ensuring minimal loss of SiGe while removing Si. Furthermore, the inventors of this disclosure have discovered that the oxygen and nitrogen elements in the preset etching gas can effectively regulate the etching rate and etching selectivity of the substrate 100. When the oxygen content in the preset etching gas increases, the etching rates for both SiGe and Si increase, but the etching selectivity between Si and SiGe remains relatively unchanged. Conversely, when the nitrogen content in the preset etching gas increases, the etching rate for Si accelerates and the etching selectivity of Si relative to SiGe increases. When the nitrogen content in the preset etching gas decreases, the etching of both Si and SiGe is suppressed, and the etching selectivity of Si relative to SiGe decreases. Therefore, preferably, the ratio of fluorine to oxygen in the preset etching gas is in the range of 0.1 to 10. Within this range, a faster etching rate and a better etching selectivity can be obtained. Preferably, the ratio of fluorine to nitrogen in the etching gas is set to 0.1 to 10. Within this range, the etching selectivity of Si relative to SiGe can be significantly improved, ensuring minimal loss of SiGe while removing Si.

[0135] Before step S120 above, the following is also included:

[0136] Source and drain regions are formed on both sides of the fin-shaped structure along the second horizontal direction; the second horizontal direction is perpendicular to the first horizontal direction.

[0137] In other words, the result formed in the subsequent step S120 is as follows: Figure 10 The direction in which the groove 105 and the protrusion 101 are arranged side by side is perpendicular to the arrangement direction of the source region and the drain region 400.

[0138] In a specific example, before step S120 and after step S113, the following is also included:

[0139] S114, such as Figure 11 As shown, shallow groove isolation structures 232 are formed in the isolation grooves 103 on both sides of the fin structure 200;

[0140] S115, such as Figure 12 As shown, in the fin structure 200 along the first horizontal direction (i.e., parallel to...) Figure 12 A protective layer 233 is formed on both sides and the top surface of the fin structure 200 and the substrate 100 in the X1 direction.

[0141] The protective layer 233 specifically covers the top surface of the fin structure 200 and the side surfaces on both sides along the first horizontal direction, as well as the top surface of the shallow trench isolation structure 232. The protective layer 233 protects the side surfaces of the fin structure 200 from lateral etching during the subsequent etching process of the substrate 100 in step S120. The protective layer 233 may comprise a silicon nitride-based material formed by CVD (including LPCVD and PECVD), PVD, ALD, or other suitable processes, such as silicon nitride, SiON, SiOCN, or SiCN, and combinations thereof. In some embodiments, the protective layer 233 is made of silicon nitride, for example, by an ALD process, thereby ensuring good density of the protective layer 233 to protect the fin structure 200 from lateral etching during the subsequent etching process of the substrate 100 in step S120.

[0142] In a specific embodiment, after completing step S115, steps S1211 to S1220 are also performed, specifically as follows:

[0143] S1211, such as Figure 13 As shown, a pseudo gate structure 234, an etch barrier layer 235, and a hard mask layer 236 are sequentially formed on the protective layer 233.

[0144] S1212, such as Figure 14 As shown, the hard mask layer 236, the etch barrier layer 235 and the pseudo gate structure 234 are patterned and etched sequentially.

[0145] S1213, such as Figure 15 As shown, in the graphical pseudo-gate structure 234 along the second horizontal direction (i.e., parallel to...) Figure 15 The two sides (in the X2 direction) and the top surface of the hard mask layer 236 form a first isolation wall 237;

[0146] S1214, such as Figure 16 As shown, the first isolation wall 237 and the hard mask layer 236 are etched to remove the portion of the first isolation wall 237 on the top surface of the hard mask layer 236 and the hard mask layer 236, while retaining the side portion 2371 of the first isolation wall covering the side of the pseudo gate structure 234.

[0147] S1215, such as Figure 17 As shown, the protective layer 233 and the portions of the fin structure (i.e., the first semiconductor layer 210 and the second semiconductor layer 220) located on both sides of the side 2371 of the first isolation wall are etched away.

[0148] S1216, such as Figure 18 As shown, from the fin-shaped structure along the second horizontal direction (i.e., parallel to) Figure 18 On both sides of the X2 direction, a predetermined thickness of one of the first semiconductor layer 210 and the second semiconductor layer 220 is etched away.

[0149] For example, Figure 18 The first semiconductor layer 210 is removed to a predetermined thickness to form a space 2101.

[0150] S1217, such as Figure 19 As shown, a second isolation wall 238 is filled in the space 2101 formed after a predetermined thickness of one of the first semiconductor layer 210 and the second semiconductor layer 220 is removed.

[0151] S1218, such as Figure 20 As shown, along the second horizontal direction of the fin-shaped structure (i.e., parallel to...) Figure 20 Source and drain regions are formed on both sides of the X2 direction (400°).

[0152] S1219, such as Figure 21 As shown, an interlayer dielectric layer 239 is formed on the etch barrier layer 235 and the source and drain regions 400;

[0153] S1220, such as Figure 22 and Figure 23 As shown, the portion of the interlayer dielectric layer 239 corresponding to the pseudo-gate structure 234 and the pseudo-gate structure 234 are removed, exposing the covering fin structure 200 along the first horizontal direction (i.e., parallel to). Figure 22 and Figure 23 Protective layer 233 on both sides and top surface of the shallow trench isolation structure 232 in the X1 direction;

[0154] Since steps S1211 to S1220 are routine process steps, they will not be described in detail here.

[0155] In some embodiments, step S1221 is performed before step S120 and after step S1220 is completed.

[0156] S1221, such as Figure 24 and Figure 25 As shown, anisotropic etching is performed on the protective layer 233 to remove the protective layer 233 covering the top of the fin structure 200 and the shallow trench isolation structure 232. This exposes the strain layer 104 of the substrate 100 located below the fin structure from the bottom side of the fin structure 200, i.e., the corner portion between the side of the fin structure 200 and the top surface of the shallow trench isolation structure 232 on the substrate 100; the corner portion is... Figure 23 The location indicated by the arrow in the image.

[0157] In step S1221 above, such as Figure 25 As shown, the protective layer 233 retains the covering fin structure along the first horizontal direction (i.e., parallel to). Figure 25 The protective layer sidewalls 2331 on both sides of the X1 direction.

[0158] In this step, a high etching rate process gas, high upper electrode RF power, and high lower electrode RF power can be used to perform the anisotropic etching, thereby etching away the portion of the protective layer 233 covering the top surface of the fin structure 200 and the shallow trench isolation structure 232, while retaining the protective layer sidewall 2331 covering the fin structure 200 and exposing the strain layer 104 beneath the fin structure.

[0159] Employing high lower electrode RF power provides downward acceleration energy and direction for the plasma, while high upper electrode RF power generates more plasma. Simultaneously, using a high-etching-rate process gas enhances the directionality of anisotropic etching. This allows for the etching away of the portion of the protective layer 233 covering the top surface of the fin structure 200 and the shallow trench isolation structure 232 to expose the strain layer 104, while minimizing lateral etching of the protective layer sidewalls 2331 on the fin structure. This provides protection for the fin structure in subsequent step S120. Those skilled in the art will understand that upper electrode RF power typically refers to the RF power applied to the RF coil located at the top of the process chamber. In some embodiments, the RF coil may also be located on the side of the process chamber to ionize the process gas and generate plasma. Lower electrode RF power typically refers to the RF power applied to the lower electrode assembly of the process chamber, which includes a wafer carrier device for generating an RF bias voltage, thereby improving the directionality of the plasma.

[0160] The above step S1221 can be performed in one step or in two steps. In the first step, the protective layer 233 covering part of the top surface of the fin structure 200 and the shallow trench isolation structure 232 is etched away. In the second step, the shallow trench isolation structure 232 is anisotropically etched to expose the sidewall of the strain layer 104 located below the fin structure.

[0161] In some embodiments, the protective layer 233 is silicon nitride, the substrate 100 is silicon, and the process gas may include chlorine or a fluorocarbon gas. The fluorocarbon gas may, for example, be CF4 or CHF3. Of course, during the etching process, the process gas may also include a protective gas to provide protection for the sidewalls 2331 of the protective layer; this protective gas may include at least one of N2 and CH4. More specifically, the upper electrode RF power range is, for example, 100W to 3000W, and the lower electrode RF power range is, for example, 50W to 1000W.

[0162] After completing step S1221, step S120 is performed. In some embodiments, such as... Figure 26 and Figure 27 As shown, from along the first horizontal direction (i.e., parallel to) Figure 26 and Figure 27 The strain layer 104 beneath the fin structure is etched on both sides (in the X1 direction) to form a groove 105 beneath the fin structure. In some examples, such as Figure 28 As shown, in step S120 above, at least a portion of the strain layer 104 is etched to form a first horizontal direction (i.e., parallel to) below the fin structure. Figure 28A groove 105 is formed in the X1 direction. That is, the exposed sidewalls of the strain layer 104 are laterally etched from both sides along the first horizontal direction to form the groove 105, which will be filled in subsequent steps to form an insulating portion. Figure 27 and Figure 28 In the embodiment shown, the strain layer 104 is completely etched to form a groove 105 extending through both sides of the fin-shaped structure. Compared to... Figure 2 The related technology shown in this application uses isotropic etching to form the groove in the fabrication process of the insulating part, without forming a sacrificial region on the substrate surface. This not only saves photolithography steps and reduces processing steps, but also eliminates the need for ion implantation on the substrate surface, thus significantly reducing processing costs. When the groove 105 extends through both sides of the fin structure, the insulating part filling the groove 105 is typically made of insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride, which have poor thermal conductivity. The heat generated by the GAAFET cannot be effectively conducted from the insulating part to the substrate, resulting in an increase in the GAAFET temperature and a decrease in electron / hole mobility, which in turn affects the performance of the GAAFET. To solve this problem, in other examples, such as... Figure 29 As shown, in step S120 above, a portion of the strain layer 104 is etched to form a protrusion 101 facing the fin structure 200, and grooves 105 arranged side-by-side on both sides of the protrusion 101 along a first horizontal direction. That is, from along the first horizontal direction (i.e., parallel to...) Figure 29 Laterally etch the sidewalls of the exposed strain layer 104 on both sides (in the X1 direction), but do not form grooves that penetrate both sides of the fin structure. Instead, a portion of the substrate 100 is retained to form a protrusion 101 located between the two grooves 105. This protrusion 101 is used to contact a portion of the lower surface of the subsequently fabricated gate structure 300 to conduct heat to the GAAFET. The two grooves 105 are used to fill and form insulating portions 102 in subsequent steps, so that the insulating portions 102 and protrusions 101 can be formed side by side between the subsequently fabricated gate structure 300 and the substrate 100. This can balance high-frequency switching characteristics and heat dissipation. Moreover, the contact area ratio between the protrusions 101 and the insulating portions 102 and the gate structure 300 can be adjusted according to the requirements of the semiconductor device. When the heat dissipation requirements of the semiconductor device are high, the contact area ratio between the protrusions 101 and the gate structure 300 is increased. When the high-frequency switching characteristics are high, the contact area ratio between the insulating portions 102 and the gate structure 300 is increased.

[0163] S130, such as Figure 30 As shown, an insulating portion 102 is formed by filling the groove 105;

[0164] As mentioned above, it is possible to Figure 28 and Figure 29The groove 105 shown is filled to form an insulating part 102.

[0165] In some embodiments, in order to achieve the effect of the insulating portion 102 suppressing parasitic gate capacitance, the material of the insulating portion 102 may include at least one of silicon dioxide (SiO2), silicon nitride (SiNx), hafnium oxide (HfOx), aluminum oxide (AlOx) and zinc oxide (ZeOx).

[0166] After completing step S130 above, remove Figure 26 The protective layer sidewall 2331 shown is then processed, and step S140 is then performed.

[0167] S140, such as Figure 31 As shown, one of the first semiconductor layer 210 and the second semiconductor layer 220 is removed;

[0168] For example, Figure 31 The structure after removing the first semiconductor layer 210 is shown, thereby forming a number of vacancies in the region corresponding to the gate structure 300.

[0169] In some embodiments, the substrate 100 is made of the same material as one of the first semiconductor layer 210 and the second semiconductor layer 220.

[0170] In some embodiments, the substrate 100 is Si, and one of the first semiconductor layer 210 and the second semiconductor layer 220 is Si, while the other is SiGe.

[0171] For Si, SiGe, or Ge-based channel GAAFETs, typically Si is used for n-channel GAAFETs, while SiGe or Ge is used for p-channel GAAFETs. In the case of SiGe p-channel GAAFETs, a higher Ge concentration can improve transistor performance. Those skilled in the art can remove the first semiconductor layer 210 and the second semiconductor layer 220 as needed.

[0172] S150, such as Figure 32 As shown, a gate structure 300 is formed around the other of the first semiconductor layer 210 and the second semiconductor layer 220.

[0173] In some embodiments, such as Figure 4 As shown, taking the first semiconductor layer 210 as an example, the gate structure 300 includes a gate dielectric layer 302 disposed around the second semiconductor layer 220 and a gate electrode layer 301 disposed around the gate dielectric layer 302. The first semiconductor layer 210 surrounded by the gate structure 300 constitutes the channel region 201 of the GAAFET.

[0174] In some embodiments, the gate dielectric layer 302 may comprise one or more layers of a dielectric material (such as silicon oxide, silicon nitride, or a high-k dielectric material), other suitable dielectric materials, and / or combinations thereof. High-k dielectric materials may include, for example, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, an interface layer may also be formed between the channel region 201 and the gate dielectric layer 302. The gate dielectric layer 302 may be formed by CVD, ALD, or any suitable method. In an optional embodiment, the thickness of the gate dielectric layer 302 is in the range of about 1 nm to about 6 nm.

[0175] In some embodiments, the gate electrode layer 302 may comprise one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, alloys thereof, other suitable materials, and / or combinations thereof. The gate electrode layer may be formed by CVD, ALD, electroplating, or other suitable methods.

[0176] In the above embodiment, the insulating portions 102 are arranged side by side on the protrusion 101 along the first horizontal direction (i.e., parallel to the first horizontal direction). Figure 4 On both sides of the X1 direction, the first horizontal direction is parallel to the arrangement direction of the fin structure 200 and perpendicular to the second horizontal direction (i.e., the arrangement direction of the source and drain regions 400). Although this solution can achieve the effect of suppressing parasitic gate capacitance, since the direction in which the insulating part 102 and the protrusion 101 are arranged side by side is perpendicular to the arrangement direction of the source and drain regions 400, the insulating part 102 cannot cut off the leakage current generated by the parasitic gate capacitance.

[0177] In order to cut off the leakage current generated by the parasitic gate capacitance, in some embodiments, step S120 above includes:

[0178] The substrate 100 is etched to partially remove the portion of the substrate 100 that is in contact with the fin structure 200;

[0179] The aforementioned preset horizontal direction is a second horizontal direction perpendicular to the arrangement direction of the fin-shaped structure 200, that is, as shown in the figure. Figure 5 As shown, the insulating portions 102 are arranged side by side on the protrusion 101 along the second horizontal direction (i.e., parallel to). Figure 5 The insulating portions 102 located on both sides of the protrusion 101 in the X2 direction can cut off the leakage current generated by the parasitic gate capacitance, thereby achieving better leakage current control capability while suppressing the parasitic gate capacitance.

[0180] Compared with the above embodiments, the semiconductor device manufacturing method provided in this embodiment also includes steps S111 to S115. After completing step S115, steps S1211 to S1217 are performed. These steps have been described in the above embodiments and will not be repeated here. Based on this, unlike the above embodiments, this embodiment further includes the following after completing step S1217:

[0181] S1215', as shown Figure 33 As shown, in the second horizontal direction of the fin structure (i.e., parallel to...) Figure 33 A protective layer 233' is formed on both sides in the X2 direction;

[0182] Specifically, the aforementioned protective layer 233' covers the pseudo-gate structure 234, the side portion 2371 of the first isolation wall, the shallow trench isolation structure 232, and the substrate 100 on both sides of the fin structure along the second horizontal direction. The fabrication step of the protective layer 233' (i.e., step S1215') can be performed in... Figure 19 The process is performed after the space formed by removing a predetermined thickness from one of the first semiconductor layer 210 and the second semiconductor layer 220 is filled with a second isolation wall 238 (i.e., step S1217). The protective layer 233' is used to protect the fin structure 200 from being laterally etched during the etching process of the substrate 100 in the subsequent step S120.

[0183] S1216', as shown Figure 34 As shown, the protective layer 233' is anisotropically etched to remove the portion of the protective layer 233' covering the shallow trench isolation structure 232 and the substrate 100, so as to expose the top surface of the substrate 100 and the shallow trench isolation structure 232, while retaining the portion of the protective layer 233' covering the sidewall of the fin structure as a sidewall protective layer.

[0184] After completing step S1216', step S120 is performed. In some embodiments, step S120 specifically includes:

[0185] S1201, such as Figure 35 and Figure 36 As shown, at least a portion of the exposed substrate 100 is anisotropically etched to expose the sidewalls 106 of the substrate 100 that are not covered by the protective layer 233'.

[0186] S1202, such as Figure 37 and Figure 38 As shown, isotropic etching is performed on the exposed substrate 100 to form a protrusion 101 facing the fin structure 200 and along the second horizontal direction (i.e., parallel to the second horizontal direction). Figure 38 The grooves 105 are located side by side on both sides of the protrusion 101 in the X2 direction.

[0187] The aforementioned groove 105 is used to fill and form the insulating portion 102 in subsequent steps. Compared with related technologies, the process of forming the sacrificial region not only requires an additional photolithography step to form a photoresist pattern on the substrate 100, but also requires ion implantation on the surface of the substrate 100. This not only increases the number of processing steps, but also makes the ion implantation equipment expensive, resulting in higher processing costs.

[0188] In step S1202 above, the sidewalls 106 of the exposed substrate 100 are etched laterally from both sides along the second horizontal direction, but a groove penetrating both sides of the fin-shaped structure is not formed. Instead, a portion of the substrate 100 is retained to form a protrusion 101 located between the two side grooves 105, such as... Figure 5 The protrusion 101 shown is designed to contact a portion of the lower surface of the subsequently fabricated gate structure 300 to conduct heat to the GAAFET. The side recesses 105 are designed to be filled in subsequent steps to form features such as... Figure 5 The insulating portion 102 shown allows for the formation of the insulating portion 102 and the protrusion 101 arranged side by side between the gate structure 300 and the substrate 100 in subsequent fabrication. This achieves a balance between the suppression effect on parasitic gate capacitance (and leakage current control capability) and the thermal conductivity effect on the GAA FET, avoiding the performance of the GAA FET being affected by either of these effects being too poor.

[0189] S130, such as Figure 39 and Figure 40 As shown, an insulating portion 102 is formed by filling the groove 105;

[0190] Step S130 can be divided into two steps. First, the insulating portion 102 is covered in both the groove 105 and the protective layer 233'. Second, the portion of the insulating portion 102 located on both sides of the protective layer 233 along the second horizontal direction is etched away, while the portion of the groove 105 located below the fin structure 200 is retained.

[0191] After completing step S130 above, remove the protective layer 233'.

[0192] After removing the protective layer 233', the following is also included:

[0193] S131, such as Figure 41 As shown, in the fin structure 200 along the second horizontal direction (i.e., parallel to...) Figure 41 The source and drain regions are formed on both sides of the X2 direction (400).

[0194] In other words, the direction in which the formed insulating portion 102 and the protrusion 101 are arranged side by side is parallel to the arrangement direction of the source region and the drain region 400 (i.e., parallel to the direction of arrangement). Figure 41 (in the X2 direction).

[0195] In one specific embodiment, after completing step S131 above, the semiconductor device manufacturing method further includes:

[0196] S132, such as Figure 42 As shown, an interlayer dielectric layer 239 is formed on the pseudo-gate structure 234 and the source and drain regions 400;

[0197] S133, such as Figure 43 As shown, the portion of the interlayer dielectric layer 239 corresponding to the pseudo gate structure 234 is removed, and the pseudo gate structure 234 is removed.

[0198] After completing step S133, steps S140 and S150 are performed. These two steps are the same as those in the above embodiment and will not be described again here.

[0199] In the semiconductor device manufacturing method of the present disclosure embodiment, there is no need to form a sacrificial region on the surface of the substrate 100. This not only saves photolithography steps and reduces processing steps, but also eliminates the need for ion implantation on the surface of the substrate 100, thereby significantly reducing processing costs.

[0200] The above embodiments of this disclosure focus on describing the differences between the various embodiments. As long as the different optimization features between the various embodiments are not contradictory, they can be combined to form a better embodiment. For the sake of brevity, they will not be described in detail here.

[0201] The above description is merely an embodiment of this disclosure and is not intended to limit the scope of this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of the claims of this disclosure.

Claims

1. A method of manufacturing a semiconductor device, wherein, include: At least one fin-shaped structure is formed on the surface of a substrate, the fin-shaped structure comprising alternating stacked first and second semiconductor layers; The substrate beneath the fin structure is etched from at least one side along a predetermined horizontal direction to form a groove beneath the fin structure; An insulating portion is formed by filling the groove; Remove one of the first semiconductor layer and the second semiconductor layer; A gate structure is formed around the other of the first semiconductor layer and the second semiconductor layer; The upper surface of the insulating portion is in contact with at least a portion of the lower surface of the gate structure, and the projection of the other of the first semiconductor layer and the second semiconductor layer toward the substrate surface overlaps with the upper surface of the insulating portion.

2. The method of manufacturing a semiconductor device according to claim 1, wherein The material of the lowest semiconductor layer of the fin structure has a different lattice constant than that of the substrate material to apply stress to the top of the substrate and form a strain layer. The etching of the substrate below the fin structure from at least one side along a predetermined horizontal direction to form a groove below the fin structure includes: The substrate is isotropically etched using a preset etching gas to selectively remove at least a portion of the strain layer, wherein the preset horizontal direction is a first horizontal direction parallel to the arrangement direction of the fin structure.

3. The method of manufacturing a semiconductor device according to claim 2, wherein The preset etching gas includes a fluorine-containing gas and an auxiliary etching gas, wherein the auxiliary etching gas includes oxygen and nitrogen.

4. The method of manufacturing a semiconductor device according to claim 3, wherein The fluorine-containing gas includes at least one of CF4, C4F8, C3F6, CHF3, CH2F2, and CH3F; and / or The auxiliary etching gas includes at least one of N2, O2, NO, and NO2.

5. The method of manufacturing a semiconductor device according to claim 3, wherein The ratio of fluorine to oxygen content ranges from 0.1 to 10; or The ratio of fluorine to nitrogen content ranges from 0.1 to 10.

6. The method for manufacturing a semiconductor device according to any one of claims 2-5, wherein, Before etching the substrate below the fin structure from at least one side along a predetermined horizontal direction to form a groove below the fin structure, the method further includes: Source and drain regions are formed on both sides of the fin-shaped structure along a second horizontal direction, which is perpendicular to the first horizontal direction.

7. The method of manufacturing a semiconductor device according to claim 6, wherein Before the source and drain regions are formed on both sides of the fin-shaped structure along the second horizontal direction, the following is also included: A protective layer covering the fin structure and the substrate is formed on both sides and the top surface of the fin structure along the first horizontal direction; After forming source and drain regions on both sides of the fin structure along the second horizontal direction, and before etching the substrate below the fin structure from at least one side along the predetermined horizontal direction to form a groove below the fin structure, the method further includes: The protective layer is anisotropically etched to remove the protective layer covering the top of the fin structure and the substrate, thereby exposing the strain layer from the bottom side of the fin structure.

8. The method of manufacturing a semiconductor device according to claim 1, wherein The etching of the substrate beneath the fin structure from at least one side along a predetermined horizontal direction to form a groove beneath the fin structure includes: The substrate is etched to partially remove the substrate that is in contact with the fin structure, wherein the preset horizontal direction is a second horizontal direction perpendicular to the arrangement direction of the fin structure.

9. The method of manufacturing a semiconductor device according to claim 8, wherein Prior to etching the substrate, the method further includes: A protective layer is formed on both sides of the fin-shaped structure in the second horizontal direction; The etching of the substrate includes: Anisotropic etching is performed on at least a portion of the exposed substrate to expose the sidewalls of the substrate not covered by the protective layer; The exposed substrate is isotropically etched to form a protrusion facing the fin structure and a groove located side by side on both sides of the protrusion along the second horizontal direction.

10. The method of manufacturing a semiconductor device according to claim 8, wherein After filling the groove to form an insulating portion, the method further includes: A source and a drain are formed on both sides of the fin-shaped structure along the second horizontal direction.

11. The method of manufacturing a semiconductor device according to claim 1, wherein The substrate is made of the same material as one of the first semiconductor layer and the second semiconductor layer.

12. The method of manufacturing a semiconductor device according to claim 11, wherein The substrate is Si, and one of the first semiconductor layer and the second semiconductor layer is Si, while the other is SiGe.

13. The method of manufacturing a semiconductor device according to claim 1, wherein The insulating material includes at least one of silicon dioxide, silicon nitride, hafnium oxide, aluminum oxide, and zinc oxide.

14. A semiconductor device, wherein, include: Substrate; At least one channel region is formed on the substrate; A gate structure is formed around each of the channel regions; in The substrate has a protrusion facing the gate structure, the protrusion being in contact with a portion of the lower surface of the gate structure; The semiconductor device further includes an insulating portion, which is arranged side by side with the protrusion. The upper surface of the insulating portion is flush with the upper surface of the protrusion and contacts a portion of the lower surface of the gate structure. The projection of the channel region toward the substrate surface overlaps with the upper surface of the insulating portion.

15. The semiconductor device of claim 14, wherein, The insulating parts are arranged side by side on both sides of the protrusion along a predetermined horizontal direction.

16. The semiconductor device of claim 15, wherein, The semiconductor device further includes a source and a drain, the source and the drain being located on opposite sides of the gate structure along the second horizontal direction, respectively; The preset horizontal direction is parallel to the second horizontal direction; or... The preset horizontal direction is perpendicular to the second horizontal direction.

17. The semiconductor device according to claim 14, wherein, The thickness of the insulating portion in the vertical direction is 0.5 to 1.5 times the thickness of the channel region in the vertical direction; or, The thickness of the insulation portion in the vertical direction is 0.8 to 1.2 times the thickness of the channel region in the vertical direction.

18. The semiconductor device of claim 14, wherein, The orthographic projection of the insulating portion onto the vertical plane is wedge-shaped; or The bottom of the insulating part has an arc-shaped orthographic projection on a vertical plane.

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