FD-SOI device structure capable of reducing self-heating effect and preparation method of FD-SOI device structure

Abstract

The invention belongs to the technical field of semiconductor design and manufacturing, and relates to an FD-SOI device structure capable of reducing a self-heating effect and a preparation method thereof. According to the FD-SOI device structure, the BOX window is filled with silicon, and a metal-semiconductor contact structure, namely a Schottky barrier, is formed on the surface of the buried copper layer. According to the structure, under the condition that bias voltage is externally applied, the possibility that carriers penetrate through a BOX window can be greatly inhibited, so that the electric leakage effect is effectively inhibited, and the characteristics of the device can be regulated and controlled by changing different bias voltages. The measure is crucial for improving the working efficiency of the device and reducing the energy consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor design and manufacturing, and relates to an FD-SOI device structure for reducing self-heating effect and a preparation method thereof. Background Art

[0002] As the advanced semiconductor manufacturing process has fully shifted to below 28 nanometers, the industry's pursuit of high performance, low power consumption, and high integration has continuously promoted technological innovation. Against this background, FD-SOI (Fully Depleted Silicon-On-Insulator) technology has stood out with its unique advantages and attracted much attention in the industry. FD-SOI can not only provide excellent performance and lower power consumption, but also simplifies the manufacturing process, making it an ideal choice for next-generation mobile and Internet of Things (IoT) applications.

[0003] FD-SOI technology is a planar process technology, and its core lies in two main technological innovations: First, a very thin insulating layer, namely the buried oxide layer, is fabricated on the silicon substrate; Second, a very thin silicon film is used as the transistor channel. The thickness of this silicon film can be as thin as a few nanometers. Since the channel is so thin, there is no need to perform a doping process on the channel, and a depletion layer is naturally formed in the entire channel region, which is the so-called "fully depleted" characteristic. This structural design makes FD-SOI transistors superior to traditional bulk silicon technology in terms of electrostatic control, because the thinner channel is easier to be fully depleted, reducing the number of carriers, thereby improving the switching speed and reducing the subthreshold swing. In addition, the presence of the buried oxide layer significantly reduces the parasitic capacitance between the source and the drain, effectively suppressing the flow of electrons from the source to the drain. This not only reduces unnecessary current flow, but also significantly reduces the leakage current that causes performance degradation, thereby improving the overall energy efficiency of the device.

[0004] However, FD-SOI technology also has to face a significant challenge in the pursuit of high performance and low power consumption - the self-heating effect. This problem stems from the unique properties of the ultra-thin insulating layer. When the transistor is in operation, the generated heat cannot be effectively dissipated through the substrate like traditional bulk silicon. Instead, due to the low thermal conductivity of the buried oxide layer, the heat is confined inside the transistor, resulting in a temperature rise, namely the so-called self-heating effect. This self-heating phenomenon may cause a series of negative consequences: It will reduce the operating speed of the transistor because higher temperatures will lead to a decrease in carrier mobility; at the same time, it will also increase power consumption because both the static current and the dynamic current will increase at high temperatures. More seriously, long-term high-temperature operation may affect the reliability and lifespan of the device, accelerate material aging, and even may cause permanent damage.

[0005] The Chinese patent application document (Publication No.: CN101621009A) discloses a method for fabricating a body contact structure of a partially depleted SOI device, which can effectively solve the floating body effect in the partially depleted SOI device, but fails to solve the self-heating effect of the FD-SOI (fully depleted SOI device) due to the relatively thin thickness of the channel silicon layer. Summary of the Invention

[0006] The object of the present invention is to address the above-mentioned problems existing in the prior art and propose an FD-SOI device structure for reducing the self-heating effect. The buried oxide layer window is used for heat dissipation. However, since a Schottky barrier metal-semiconductor contact is formed between the metal conductor and the intrinsic silicon, a leakage current effect will occur under the action of the barrier. Therefore, in the present invention, a certain reverse voltage bias treatment can be performed on the buried copper layer in the back-gate lead-out structure to generate carriers with equal magnitudes and opposite directions, so that the static current is zero, thereby changing the barrier to reach a new equilibrium and effectively preventing the leakage current effect.

[0007] The object of the present invention can be achieved by the following technical solutions:

[0008] An FD-SOI device structure for reducing the self-heating effect, the FD-SOI device structure includes STI trenches and a silicon substrate, a buried copper layer, a BOX oxide isolation layer, an SOI layer, and source-drain-gate electrodes stacked in sequence;

[0009] Wherein, at least one STI trench is etched into the buried copper layer and / or the silicon substrate, the BOX oxide isolation layer contains a buried oxide layer window, and a back-gate lead-out structure is provided from the buried copper layer to the SOI layer.

[0010] In the above-mentioned FD-SOI device structure for reducing the self-heating effect, the buried oxide layer window is filled with silicon to be flush with the upper surface of the SOI layer and form a metal-semiconductor contact structure with the surface of the buried copper layer.

[0011] The filled silicon in the BOX window of the present invention forms a metal-semiconductor contact structure with the lower buried copper layer. When the filled silicon contacts the lower buried copper layer, a so-called metal-semiconductor contact structure is formed between the two. This structure is essentially a Schottky barrier, which is naturally formed at the interface between the metal and the semiconductor.

[0012] By using the technical means of combining silicon filling and epitaxial growth, it is also possible to provide additional mechanical support for the buried copper layer without affecting the integrity of the original device structure, enhancing the stability of the overall structure. At the same time, this method also allows for convenient integration into the existing production line without changing the original process flow, contributing to the practical application and development of new technologies.

[0013] Preferably, the buried oxide layer window is in an inverted trapezoidal structure.

[0014] Further preferably, the upper surface of the buried oxide layer window is 25 - 40 nm in length, the lower bottom surface is 5 - 20 nm in length, and the height is determined according to the thickness of the buried oxide layer.

[0015] Further preferably, the height of the buried oxide layer window is 20 - 30 nm.

[0016] In order to further optimize thermal management and ensure that heat can be transferred out of the device evenly and efficiently, the present invention also introduces an inverted trapezoidal structure for the window. Traditional vertical rectangular windows have limitations in heat conduction because they provide a relatively small heat dissipation surface area, restricting the effective diffusion of heat flow. The inverted trapezoidal structure, on the other hand, expands the interface area in contact with the SOI layer by increasing the top width, while keeping the bottom narrow to adapt to existing processes and design rules. This change in shape not only increases the cross-sectional area of the heat conduction path, facilitating the rapid transfer of heat from the transistor channel region to the buried copper layer, but also helps to form a more uniform temperature distribution, avoiding local overheating.

[0017] In the above-mentioned FD-SOI device structure for reducing self-heating effect, the back-gate lead-out structure is to etch a channel from the SOI layer alone into the buried copper layer, and copper metal is deposited in this channel to form the back-gate lead-out structure.

[0018] The core design of the back-gate lead-out structure of the buried copper layer in the present invention lies in using a metal material such as copper with high electrical conductivity and high thermal conductivity as part of the heat dissipation path. This layer of copper not only provides additional electrostatic shielding to prevent the influence of external electromagnetic interference on the device, but more importantly, it acts as an efficient heat conduction channel. Due to the extremely high thermal conductivity of copper, it can quickly conduct the heat generated during operation to the substrate. In this way, the buried copper layer effectively reduces the local hot spot temperature and reduces the performance degradation caused by self-heating effect.

[0019] By combining the use of the back-gate lead-out structure of the buried copper layer and the inverted trapezoidal structure of the window, the present invention produces a synergistic effect, greatly improving the overall heat dissipation efficiency of the FD-SOI device. The buried copper layer, as a powerful heat sink, can quickly take away the heat generated during the operation of the transistor; while the inverted trapezoidal window ensures that this heat can be efficiently and evenly distributed over a larger area and finally conducted to the external environment. In this way, even when operating under high-frequency or high-load conditions, the device can maintain within a relatively ideal temperature range, ensuring its stability and reliability. In addition, this design scheme also helps to reduce power consumption. By reducing unnecessary leakage current and increasing the switching speed, the entire circuit can operate at a lower working voltage, thereby reducing energy consumption. This is particularly important for application scenarios with high energy efficiency requirements such as mobile devices and the Internet of Things (IoT).

[0020] Preferably, the copper metal channel area is 0.15 - 0.25 of the buried copper layer.

[0021] In the above-mentioned FD-SOI device structure for reducing self-heating effect, the thickness of the silicon substrate is 120 - 150 nm.

[0022] In the above-mentioned FD-SOI device structure for reducing self-heating effect, the thickness of the buried copper layer is 10 - 15 nm. The present invention needs to control the thickness of the buried copper layer. If it is too thick, it will seriously affect the compactness of the device structure because copper metal will also generate heat under the action of negative voltage bias. If it is too thin, it will lead to a relatively large self-resistance and generate more heat, which is not conducive to the dissipation of heat of the FD-SOI device.

[0023] In the above-mentioned FD-SOI device structure for reducing self-heating effect, the BOX oxidation isolation layer is silicon dioxide with a thickness of 20 - 30 nm.

[0024] In the above-mentioned FD-SOI device structure for reducing self-heating effect, the SOI layer is single-crystalline silicon with a thickness of 50 - 200 angstroms.

[0025] The present invention also provides a preparation method of the above-mentioned FD-SOI device structure for reducing self-heating effect, and the method includes the following steps:

[0026] S1. Deposit a layer of copper on the upper surface of the silicon substrate, and then form the BOX oxidation isolation layer and the SOI layer by precipitation in sequence;

[0027] S2. Etch the SOI layer and the BOX oxide layer by photolithography to form BOX window trenches;

[0028] S3. Fill silicon in the BOX window trenches until it is flush with the SOI surface and forms a Schottky contact structure with the surface of the buried copper layer to obtain a buried oxide layer window;

[0029] S4. Etch a channel separately to the buried copper layer, and deposit copper metal in the channel to form a back-gate lead-out structure;

[0030] S5. Etch channels to form STI trenches, and at least one channel is etched to the buried copper layer and / or the silicon substrate, and then fill the STI trenches with silicon dioxide;

[0031] S6. Finally, establish the source, drain, and gate electrodes.

[0032] Preferably, establishing the source, drain, and gate electrodes specifically includes the following steps:

[0033] S1. Form a silicon dioxide LK gate oxide dielectric on the surface of the SOI layer by in-situ steam generation method, then form a hafnium oxide HK gate oxide dielectric by atomic layer deposition method, and deposit polysilicon and silicon nitride as hard films to complete the polysilicon gate deposition;

[0034] S2. On the basis of polysilicon gate deposition, define the gate position through photolithography, and then etch the remaining parts to obtain a polysilicon gate.

[0035] S3. Then deposit silicon nitride by ALD method, and etch the silicon nitride by anisotropic method to obtain the first sidewall.

[0036] S4. Then form lightly doped source / drain by low-energy ion implantation method, restore the SOI to single crystal by rapid thermal annealing method, and then use the SOI single crystal as a seed layer to form a raised source / drain (RSD) by epitaxial method.

[0037] S5. After the RSD is formed, deposit silicon dioxide by ALD method again, and form the second sidewall by anisotropic etching.

[0038] S6. On the basis of the second sidewall, form the doping of the source / drain by low-energy ion implantation method, then remove the hard mask and the polysilicon gate, and finally deposit metal.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] 1. The buried copper layer of the FD-SOI device structure of the present invention serves as an efficient heat conduction channel. Utilizing its high electrical conductivity and high thermal conductivity characteristics, it can quickly conduct the heat generated during the operation of the transistor to the substrate or other cooling devices. This effectively reduces the local hot spot temperature, reduces the performance degradation caused by self-heating effect, and ensures that the device can still maintain within a relatively ideal temperature range when operating under high-frequency or high-load conditions.

[0041] 2. The FD-SOI device structure of the present invention fills silicon in the BOX window and forms a Schottky barrier, that is, a metal-semiconductor contact structure, on the surface of the buried copper layer. This structure can not only greatly inhibit the possibility of carriers passing through the BOX window under the application of an external bias voltage, thereby effectively suppressing the leakage effect, but also can regulate the characteristics of the device by changing different bias voltages. This measure is crucial for improving the working efficiency of the device and reducing energy consumption.

[0042] 3. The FD-SOI device structure of the present invention adopts a method combining silicon filling and epitaxial growth. Without affecting the integrity of the original device structure, it provides additional mechanical support for the buried copper layer and enhances the stability of the overall structure. This method also allows new technologies to be seamlessly integrated into existing production lines, facilitating practical application and development.

[0043] 4. The FD-SOI device structure of the present invention introduces an inverted trapezoidal BOX window structure, which expands the interface area in contact with the buried copper layer by increasing the bottom width, while keeping the top narrower to adapt to the existing process and design rules. This change in shape not only increases the cross-sectional area of the heat conduction path, promotes the rapid transfer of heat from the transistor channel region to the buried copper layer, but also helps to form a more uniform temperature distribution and avoid local overheating.

[0044] 5. The FD-SOI device structure of the present invention suppresses the leakage effect and improves the switching speed under the action of opposite bias voltages, enabling the entire circuit to operate at a lower operating voltage, thereby reducing energy consumption. This is particularly important for application scenarios with high energy efficiency requirements such as mobile devices and the Internet of Things (IoT), helping to extend battery life and improve the overall system performance.

[0045] 6. The preparation method provided by the present invention includes a series of steps starting from depositing a copper layer on a silicon substrate until finally establishing source, drain, and gate electrodes and forming sidewalls. The entire process not only ensures the successful introduction of new materials and structures but also is as compatible as possible with the existing manufacturing process, simplifying the production process. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 is a flowchart for preparing the FD-SOI device structure with reduced self-heating effect according to the present invention.

[0047] Figure 2, including Figures 2a - 2e , shows the preparation process of the FD-SOI device structure in Embodiment 1; 101 - silicon substrate, 102 - back-gate lead-out structure, 103 - BOX oxide isolation layer, 104 - SOI layer, 105 - buried oxide layer window, 106 - STI trench, 107 - gate oxide dielectric, 108 - first-layer sidewall, 109 - silicon nitride, 110, 111 - source / drain RSD, 112 - second-layer sidewall, 113 - deposited metal.

[0048] Figure 3 is the Schottky barrier energy band diagram formed by the metal buried copper layer (102) and the silicon layer (105) when the FD-SOI device structure with reduced self-heating effect prepared in Embodiment 1 is biased. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0049] The technical solution of the present invention will be further described below in conjunction with the accompanying drawings. In each of the drawings, the same parts are denoted by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. Some parts commonly used in the art may also not be shown. Unless otherwise specified, the raw materials used in the specific embodiments of the present invention are all commonly used raw materials in the art, and the methods used in the examples are all conventional methods in the art. It should be understood that when referring to the positional relationship or quantity of the constituent elements in the following embodiments, terms such as "upper" and "lower" are used for illustrative purposes only and are not restrictive. Without departing from the scope of the present invention, other approximate or similar examples can be used.

[0050] The above object of the present invention is achieved by the following technical solutions: A FD-SOI device structure for reducing self-heating effect, prepared according to the Figure 1 method shown to prepare a FD-SOI device structure for reducing self-heating effect. The FD-SOI device structure for self-heating effect includes STI trenches and a silicon substrate, a buried copper layer, a BOX oxidation isolation layer, a SOI layer, and source-drain-gate electrodes stacked in sequence. The BOX oxidation isolation layer contains a buried oxide layer window, and a back-gate lead-out structure is provided from the buried copper layer to the SOI layer.

[0051] Example 1:

[0052] S1. The deposition of the background substrate is as shown in Figure 2a - 1 Figure 01, and its thickness is 125 nm. A copper layer is buried on the upper surface of the background substrate for subsequent heat dissipation as shown in Figure 2a - 1 Figure 02, and its thickness is 15 nm. When depositing the BOX oxidation isolation layer, a structure as shown in Figure 2a - 1 Figure 03 is formed. The material of the oxidation isolation layer is silicon dioxide, and its thickness is 25 nm.

[0053] S2. When depositing to form the SOI substrate, the top layer is a single crystal silicon layer, and the thickness of the top silicon layer is 150 angstroms as shown in Figure 2b - 1 Figure 04;

[0054] S3. First, use the photolithography method to open the top silicon and BOX regions to be etched, and etch the SOI and BOX layers until the surface of the buried copper layer to form a buried oxide layer window; the upper bottom surface of this window is 28 nm long, the lower bottom surface is 19 nm long, and the height is the thickness of the buried oxide layer, specifically 25 nm, as shown in 2b-105;

[0055] S4. By the method of silicon filling, using the buried copper layer as the filling bottom, epitaxially grow silicon until it is flush with the lower bottom surface of the SOI. The filled silicon in the BOX window and the lower buried copper layer form a Schottky contact structure, as shown in Figure 2c - 1 Figure 05;

[0056] S5. First, open the area to be etched through a lithography method, then form STI trenches through an etching method to define the active region, and then fill the STI trenches with silicon dioxide using a high aspect ratio process method, as shown in 2d-106 in the attached figure;

[0057] S6. Etch a small channel separately into the buried copper layer, deposit copper metal in this channel to form a back gate lead-out structure, as shown in 2d-102 in the attached figure, and the area of this channel is 0.2 of the buried copper layer;

[0058] S7. After forming STI and completing the definition of the active region, perform backplane doping through a high-energy ion implantation method. The dose of ion implantation is 5.00e 12 ~5.00e 13 , the implantation energy is 30 keV, the tilt is 7°, and the rotation is 20°. Then form a silicon dioxide LK (low-k) gate oxide dielectric through an in-situ steam generation (ISSG) method, and form a hafnium oxide HK (high-k) gate oxide dielectric through an atomic layer deposition (ALD) method. The thickness of the hafnium oxide gate oxide dielectric is 5 nm, as shown in the attached Figure 2e - 1 figure 07.

[0059] S8. Deposit polysilicon, simply etch the polysilicon and then deposit a layer of silicon nitride as a hard mask, which completes the deposition of the polysilicon gate. On the basis of forming the polysilicon gate deposition, define the gate position through a lithography method, and then etch the remaining parts to obtain the polysilicon gate. Then deposit a layer of silicon nitride through the ALD method, and etch the silicon nitride anisotropically (as shown in Figure 2e - 1 figure 09), to obtain the first layer of spacer as shown in Figure 2e - 1 figure 08, and the thickness of the first layer of sidewall is 10 nm.

[0060] S9. Then form lightly doped source / drain through a low-energy ion implantation method. The dose of ion implantation is 5.00e 13 , the energy is 6 keV, and the angle is 5°; the temperature for annealing activation is 950 °C and the time is 2 min. Then restore the SOI to single crystal through a rapid thermal annealing method. Then, using the SOI single crystal as a seed layer, form a Raised Source / Drain (RSD) through an epitaxial method. The height of the raised source / drain is 25 nm, and the height is as shown in Figure 2e - 1 figure 10, 2e-111 structure.

[0061] S10. After etching to form the RSD, after depositing the second sidewall - silicon dioxide by the ALD method, the remaining silicon dioxide is etched by an anisotropic etching method to form the second sidewall as shown in Figure 2e - 1 Figure 12, where the thickness of the second layer of sidewall is 22 nm. Based on the second sidewall, doping of the source and drain is formed by a low-energy ion implantation method, where the ion implantation dose is 5.00e 15 , the energy is 18 keV, and the angle is 5°; the annealing activation temperature is 1000 °C and the time is 30 s.

[0062] S11. Then, the hard mask and polysilicon gate are removed by an etching method. Finally, metal is deposited to complete the manufacture of the metal gate as shown in Figure 2e - 1 Figure 13, where the thickness of the gate is 30 nm.

[0063] Figure 3 The energy band diagram of the Schottky barrier formed between the metal buried copper layer and the silicon layer when the FD-SOI device structure for reducing self-heating effect prepared in Example 1 is biased. From the energy band distribution in the figure, it can be seen that the barrier between the metal buried copper layer and the intrinsic silicon can form a reduced Schottky barrier under the action of the reverse bias voltage, thereby eliminating the leakage current effect caused by the difference in work function between the metal conductor and the intrinsic silicon. Due to the difference in work function between the metal buried copper layer and the intrinsic silicon, an energy band diagram as shown in Figure 3 will be formed. Under the action of the Schottky barrier, carriers can flow from one side of the intrinsic silicon to the other side. In the present invention, the Schottky barrier effect composed of the filled silicon and the buried copper layer can be suppressed when an external applied voltage is applied. Therefore, when an appropriate reverse bias voltage is applied, the barrier height decreases, which makes the static current zero and reaches an equilibrium state, thereby greatly suppressing the occurrence of the leakage current effect. This design can not only suppress current leakage, but also regulate the characteristics of the device by applying different bias voltages, which plays a key role in improving the working efficiency of the device and reducing energy consumption.

[0064] Example 2:

[0065] The difference from Example 1 is only that the upper bottom length of the buried oxide layer window is 19 nm, the lower bottom length is 28 nm, and the height is the thickness of the buried oxide layer, specifically 25 nm, that is, the buried oxide layer window is a trapezoidal structure.

[0066] Due to the relatively small size of the upper base surface, the trapezoidal structure provides a relatively small heat dissipation surface area, which limits the effective diffusion of heat flow. This means that under the same conditions, the heat dissipation efficiency of the trapezoidal structure is lower than that of the inverted trapezoidal structure, resulting in the formation of local hot spots, which in turn affects the stability and lifespan of the device. For the trapezoidal structure, due to its relatively large lower base surface size and large contact area, it is not conducive to the formation of an ideal Schottky barrier. Especially in application scenarios where leakage current needs to be reduced, such a structure will result in a relatively large contact area between the buried copper layer and the intrinsic silicon, thereby increasing unnecessary leakage current. Due to the low heat dissipation efficiency and poor Schottky barrier effect, the trapezoidal structure will also cause the device operating temperature to rise, performance to decline, and power consumption to increase. These factors combined will reduce the operating efficiency of the entire circuit and affect the performance of the final product.

[0067] Example 3:

[0068] The difference from Example 1 is only that no buried copper layer is provided in step S1.

[0069] In the case where no buried copper layer is provided, the heat generated inside the device cannot be effectively transferred out, resulting in a local temperature increase, namely the so-called self-heating effect. The self-heating effect will reduce the operating speed of the transistor because a higher temperature will cause the carrier mobility to decline. At the same time, it will also increase the dynamic and static currents, further increasing the power consumption. Operating at a high temperature for a long time may accelerate material aging and even cause permanent damage, seriously affecting the reliability and lifespan of the device. In addition to providing a heat conduction path, the buried copper layer also acts as an electrostatic shielding layer to protect the device from external electromagnetic interference. In the absence of a buried copper layer, the device is more vulnerable to external EMI (Electromagnetic Interference), which may cause problems such as signal distortion and malfunction, especially in high-frequency communication and sensitive circuit environments.

[0070] Comparative Example 1:

[0071] The difference from Example 1 is only that the BOX oxide isolation layer does not contain a buried oxide layer window.

[0072] In the case where no buried oxide layer window is set, the heat generated by the SOI layer cannot be effectively dissipated to the substrate or the external environment through a direct path. Since the SOI layer itself is very thin and has limited heat conduction ability, the heat generated during operation is likely to accumulate in local areas. This accumulated heat will trigger a serious self-heating effect, causing the operating temperature of the transistor to rise rapidly. High temperature will lead to a decrease in carrier mobility, thus reducing the operating speed of the transistor. At the same time, the self-heating effect will also increase the dynamic and static currents, further increasing the power consumption. Operating at a high temperature for a long time may accelerate material aging and even cause permanent damage, seriously affecting the reliability and lifespan of the device. The existence of the buried oxide layer window provides a direct path for heat to conduct to the buried copper layer or the substrate. Without this window, the heat can only slowly diffuse through the relatively thick and poorly thermally conductive BOX oxide isolation layer. This not only increases the thermal resistance but also reduces the overall heat dissipation efficiency, affects the operating efficiency of the device, and leads to an increase in power consumption, especially in low-power applications, which is a serious problem. Moreover, there are differences in the thermal expansion coefficients between different materials. When heat is generated inside the device, these materials will expand or contract at different rates. If the heat cannot be effectively dissipated, it will lead to local thermal stress concentration, causing problems such as material delamination and cracks, and further affecting the mechanical stability and reliability of the device.

[0073] Comparative Example 2:

[0074] The difference from Example 1 is only that there is no back-gate lead-out structure from the buried copper layer to the SOI layer.

[0075] One of the design intents of the back-gate extraction structure is to effectively prevent electrons from flowing from one side to the other by applying a reverse bias voltage across the Schottky barrier between the buried copper layer and the SOI layer. Without the back-gate extraction structure, it is impossible to reduce the Schottky barrier formed between the metal buried copper layer and the intrinsic silicon under the influence of the bias voltage, resulting in a relatively obvious leakage effect. Due to the lack of an effective bias voltage, carriers are more likely to pass through the BOX window region and enter the buried copper layer or other regions, thereby increasing unnecessary leakage current. This not only affects the operating efficiency of the device but also may lead to an increase in power consumption, especially in low-power applications, which is a serious problem. In addition, the higher leakage current will also shorten the service life of the device and may cause reliability problems. Besides providing a heat conduction path, the back-gate extraction structure also acts as an electrostatic shielding layer to protect the device from external electromagnetic interference (EMI). Without the back-gate extraction structure, the device is more vulnerable to external electromagnetic interference, which will cause problems such as signal distortion and malfunction, especially in high-frequency communication and sensitive circuit environments. Since the leakage current cannot be effectively controlled, more energy will be converted into heat, resulting in an increase in the operating temperature of the device. High temperature will reduce the carrier mobility, slow down the operating speed, and increase the dynamic and static currents, further increasing the power consumption. Operating at a high temperature for a long time will accelerate the material aging and even cause permanent damage, seriously affecting the reliability and life of the device.

[0076] In summary, the FD-SOI device structure of the present invention fills silicon in the BOX window and forms a metal-semiconductor contact structure, i.e., a Schottky barrier, with the surface of the buried copper layer. This structure can form carriers with equal magnitudes and opposite directions under the application of an external reverse bias voltage, greatly suppressing the possibility of carriers passing through the BOX window, thereby effectively reducing unnecessary leakage current. This measure is crucial for improving the operating efficiency of the device and reducing energy consumption.

[0077] For the points not exhausted in the numerical values of the technical scope claimed by the present invention in the embodiments herein and the new technical solutions formed by the equivalent replacement of single or multiple technical features in the technical solutions of the embodiments, they are also within the scope claimed by the present invention; at the same time, in all the embodiments listed or unlisted in the present invention, the various parameters in the same embodiment only represent an example (i.e., a feasible solution) of its technical solution, and there is no strict coordination and limitation relationship between the various parameters. Among them, the various parameters can be mutually replaced without violating the axioms and the requirements of the present invention, except as otherwise specifically stated.

[0078] The technical means disclosed by the solution of the present invention are not limited to the technical means disclosed by the above-mentioned technical means, but also include technical solutions formed by any combination of the above technical features. The above is the specific implementation manner of the present invention. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements are also regarded as the protection scope of the present invention.

[0079] The specific embodiments described herein are merely illustrative of the spirit of the present invention. Those skilled in the art to which the present invention pertains can make various modifications or supplements to the described specific embodiments or use similar ways of substitution, but will not deviate from the spirit of the present invention or exceed the scope defined by the appended claims.

Claims

1. A FD-SOI device structure for reducing self-heating effect, characterized in that: The FD-SOI device structure includes an STI trench and a silicon substrate, a buried copper layer, a BOX oxide isolation layer, an SOI layer and a source-drain gate stacked in sequence; Wherein, at least one STI trench is etched into the buried copper layer and / or the silicon substrate, the BOX oxidation isolation layer contains a buried oxide layer window, and a back gate lead-out structure is provided from the buried copper layer to the SOI layer.

2. The FD-SOI device structure for reducing self-heating effect according to claim 1, characterized in that: The buried oxide layer window is filled with silicon until it is flush with the upper surface of the SOI layer and forms a gold semi-contact structure with the surface of the buried copper layer.

3. The FD-SOI device structure for reducing self-heating effect according to claim 2, characterized in that: The buried oxide layer window is an inverted trapezoidal structure.

4. The FD-SOI device structure for reducing self-heating effect according to claim 1, characterized in that: The back gate lead-out structure is to etch a channel from the SOI layer to the buried copper layer separately, and deposit copper metal in the channel to form the back gate lead-out structure.

5. The FD-SOI device structure for reducing self-heating effect according to claim 1, characterized in that: The thickness of the silicon substrate is 120-150nm.

6. The FD-SOI device structure for reducing self-heating effect according to claim 1, characterized in that: The buried copper layer thickness is 10-15nm.

7. The FD-SOI device structure for reducing self-heating effect according to claim 1, characterized in that: The BOX oxide isolation layer is silicon dioxide with a thickness of 20-30nm.

8. The FD-SOI device structure for reducing self-heating effect according to claim 1, characterized in that: The SOI layer is single crystal silicon with a thickness of 50-200 angstroms.

9. A method for preparing a FD-SOI device structure with reduced self-heating effect as claimed in claim 1, characterized in that: The method comprises the following steps: S1, burying a copper layer on the surface of the silicon substrate, and then precipitating to form a BOX oxide isolation layer and an SOI layer in sequence; S2, etching the SOI layer and the BOX oxide layer by photolithography to form a BOX window groove; S3, filling the BOX window groove with silicon until it is flush with the SOI surface and forms a gold semi-contact structure with the buried copper layer surface to obtain a buried oxide layer window; S4, etching a channel separately onto the buried copper layer, and depositing copper metal in the channel to form a back gate lead-out structure; S5, etching channels to form STI grooves, wherein at least one channel is etched onto the buried copper layer and / or into the silicon substrate, and then the STI grooves are filled with silicon dioxide; S6. Finally, the source, drain, gate and sidewall are formed.

10. The method for preparing a FD-SOI device structure with reduced self-heating effect according to claim 9, characterized in that: Establishing the source, drain and gate specifically includes the following steps: S1, forming a silicon dioxide LK gate oxide dielectric on the surface of the SOI layer by an in-situ water vapor generation method, and then forming a hafnium oxide HK gate oxide dielectric by an atomic layer deposition method, and depositing polysilicon and silicon nitride as a hard film to complete polysilicon gate deposition; S2. Based on the polysilicon gate deposition, the gate position is defined by photolithography, and then the remaining part is etched to obtain the polysilicon gate; S3, then depositing silicon nitride by an ALD method, and then etching the silicon nitride by an anisotropic method to obtain a first layer of sidewalls; S4. Then, a lightly doped source and drain are formed by a low-energy ion implantation method, and then the SOI is restored to a single crystal by a rapid thermal annealing method. Then, the SOI single crystal is used as a seed layer, and a raised source and drain RSD is formed by an epitaxial method. S5. After RSD is formed, silicon dioxide is deposited again using the ALD method, and a second layer of sidewalls is formed by anisotropic etching. S6. On the basis of the second sidewall, the source and drain doping is formed by a low-energy ion implantation method, and then the hard film and polysilicon gate are removed, and finally metal is deposited.

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