Semiconductor device and oxide semiconductor thin film

Abstract

A semiconductor device and an oxide semiconductor thin film are provided. The semiconductor device includes: an oxide semiconductor layer having an amorphous phase and including tin (Sn) and a metal element different from the tin (Sn), in which a content of the tin (Sn) is greater than 50 atom% of a total content of the tin (Sn) and the metal element different from the tin (Sn); a first electrode and a second electrode disposed on the oxide semiconductor layer and spaced apart from each other; a gate spaced apart from the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode.

Description

[0001] Cross - reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10 - 2023 - 0171824, filed on November 30, 2023, and Korean Patent Application No. 10 - 2024 - 0147900, filed on October 25, 2024, with the Korean Intellectual Property Office, the entire disclosures of which are incorporated herein by reference. Technical field

[0003] Various example embodiments generally relate to a semiconductor thin film including tin and / or a semiconductor device including the semiconductor thin film. Background art

[0004] A transistor corresponds to a semiconductor device for switching an electrical signal and is used in various integrated circuit devices including a memory, a driver integrated circuit (IC), and a logic device. To increase the integration degree of the integrated circuit device, the space occupied by the transistors included in the integrated circuit device has been rapidly reduced, and thus, research has been conducted to reduce the size of the transistors while maintaining their performance.

[0005] Oxide semiconductor devices have been studied for many years as transparent semiconductor devices having a wide bandgap of about 3.0 eV or more. Oxide semiconductor devices used as large - area display driving devices have excellent characteristics such as a low off - current and a high on / off ratio. Oxide semiconductor devices having these advantages can be applied to memory or logic devices, or oxide semiconductor devices can be stacked on silicon (Si) - based devices to increase the integration degree.

[0006] However, the performance of oxide semiconductor devices can deteriorate due to short - channel effects caused by scaling down. Summary of the invention

[0007] Provided are an oxide semiconductor thin film including tin (Sn) as a component and / or a semiconductor device including the oxide semiconductor thin film.

[0008] Alternatively or additionally, provided are an oxide semiconductor thin film that can maintain an amorphous phase even at high temperatures and a semiconductor device including the oxide semiconductor thin film.

[0009] Additional aspects will be set forth in part in the following description, and in part will be apparent from the description, or may be learned by practice of the various example embodiments presented.

[0010] According to an aspect of the present disclosure, a semiconductor device includes: an oxide semiconductor layer having an amorphous phase and including tin (Sn) and a metal element different from (Sn), wherein the content of tin (Sn) is greater than 50 atomic % of the total content of tin (Sn) and the metal element different from (Sn); a first electrode and a second electrode disposed on the oxide semiconductor layer and spaced apart from each other; a gate spaced apart from the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate.

[0011] The metal element different from (Sn) may include at least one of indium (In), gallium (Ga), zinc (Zn), aluminum (Al), or hafnium (Hf).

[0012] The metal element different from (Sn) may include zinc (Zn), wherein the content of zinc (Zn) is 10 atomic % or less.

[0013] In the oxide semiconductor layer, the content of zinc (Zn) may be 0 atomic %.

[0014] The content of tin may be less than 80 atomic %.

[0015] The oxide semiconductor layer may have an amorphous phase at 350 °C to 700 °C.

[0016] The metal element different from (Sn) may include indium, wherein the content ratio of tin to indium is greater than 1 and less than or equal to 4.

[0017] The content of indium may be 20 atomic % or greater.

[0018] The metal element different from (Sn) may include gallium, wherein the content of gallium may be 30 atomic % or less.

[0019] The metal element different from (Sn) may include indium (In) and gallium (Ga), wherein the content of gallium may be 30 atomic % or less.

[0020] And, the content of indium may be 20 atomic % or greater.

[0021] The oxide semiconductor layer may have a Hall mobility of 15 cm 2 / Vs or greater.

[0022] The oxide semiconductor layer may have a resistivity of 10 -1 Ωcm or less.

[0023] The oxide semiconductor layer may have a thickness of 20 nm or less.

[0024] The gate insulating layer may include at least one of hafnium (Hf), zirconium (Zr), aluminum (Al), and / or silicon (Si).

[0025] The gate electrode may include at least one of a metal, a metal nitride, and / or a transparent conductive oxide (TCO).

[0026] Alternatively or additionally, according to various exemplary embodiments, the oxide semiconductor thin film includes tin (Sn), indium (In), and gallium (Ga), wherein the content of tin is greater than the sum of the contents of indium and gallium, and the oxide semiconductor thin film has an amorphous phase.

[0027] Among the elements other than oxygen, the content of tin may be greater than 50 atomic % and less than 80 atomic %.

[0028] Among the elements other than oxygen, the content of gallium may be 30 atomic % or less.

[0029] Among the elements other than oxygen, the content of indium may be 20 atomic % or greater. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects, features, and advantages of some embodiments will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0031] Figure 1 is a graph showing X-ray diffraction (XRD) results of nine types of InSnO thin films according to some exemplary embodiments;

[0032] Figure 2 is a graph showing changes in carrier concentration, Hall mobility, and resistivity according to the content of tin in an InSnO thin film;

[0033] Figure 3 is a graph showing XRD results after heat-treating an InSnO thin film and four types of InSnGaO thin films at 400 °C for 3 hours in an air atmosphere;

[0034] Figure 4 is a graph showing XRD results after heat-treating an InSnO thin film and four types of InSnGaO thin films at 600 °C;

[0035] Figure 5 is a graph showing changes in carrier concentration, Hall mobility, and resistivity according to the content of gallium in three types of InSnGaO thin films;

[0036] Figure 6 is a graph showing the IV characteristics according to the heat-treatment temperature of a transistor including an oxide semiconductor thin film according to some exemplary embodiments;

[0037] Figure 7 is a graph showing a semiconductor device including an oxide semiconductor according to some exemplary embodiments;

[0038] Figure 8 A diagram showing a semiconductor device according to other example embodiments;

[0039] Figure 9 A diagram showing a semiconductor device according to other example embodiments;

[0040] Figure 10 A diagram showing a semiconductor device according to other example embodiments;

[0041] Figure 11 A diagram showing a semiconductor device according to other example embodiments;

[0042] Figure 12 A circuit diagram showing a complementary metal-oxide-semiconductor (CMOS) inverter according to some example embodiments;

[0043] Figure 13 A circuit diagram showing a CMOS static random access memory (SRAM) device according to some example embodiments;

[0044] Figure 14 A circuit diagram showing a CMOS NAND circuit according to some example embodiments;

[0045] Figure 15 A block diagram showing an electronic system according to some example embodiments; and

[0046] Figure 16 A block diagram showing an electronic system according to some example embodiments. Detailed Description

[0047] Some example embodiments will now be described in detail, the examples of which are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, the various example embodiments of the present invention may have different forms and should not be construed as limited to the descriptions set forth herein. Therefore, the various example embodiments are described below only by referring to the accompanying drawings to illustrate aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one (kind) of..." when before or after a list of elements modify the entire list of elements and not the individual elements of the list.

[0048] Hereinafter, an oxide semiconductor thin film including tin and a semiconductor device including the oxide semiconductor thin film according to various example embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals always denote the same elements, and in the drawings, for clarity and convenience of illustration, the dimensions of the elements may be exaggerated.

[0049] The singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. When a part "comprises" an element, it may further comprise additional elements without excluding the presence of other elements, unless otherwise stated. For clarity of illustration, the dimensions or thicknesses of the elements may be exaggerated. It will also be understood that when a material layer is referred to as being "on" another layer or substrate, the material layer may be directly on the other layer or substrate, or an intermediate layer may also be present therebetween. The materials of the layers in the following various exemplary embodiments are only examples, and thus, other materials may be used.

[0050] In addition, in the specification, the term "… unit" or "module" indicates a unit for processing at least one function or operation, and may be implemented by hardware, software, or a combination of hardware and software.

[0051] The specific acts described in the various exemplary embodiments of the present invention are examples and are not intended to limit the scope of the present disclosure in any way. For the sake of brevity, conventional electronic devices, control systems, software, and other functional aspects of the system may not be described in detail.

[0052] In addition, the lines or members connecting the elements shown in the attached drawings are only illustrative of functional connections and / or physical or circuit connections. In an actual device, the connections between the elements may be represented by many alternative or additional functional connections, physical connections, or circuit connections.

[0053] The terms "a", "an", and "the" and similar referents used in the context of describing the present disclosure should be construed to cover both the singular and the plural.

[0054] The expression "at least one (kind)" before or after a list of elements will limit the entire list of elements, rather than individual elements of the list. For example, the expression "at least one (kind) of A, B, and C" or "at least one (kind) selected from A, B, and C" may indicate only A, only B, only C, or a combination thereof (e.g., ABC, AB, BC, or AC).

[0055] When "about" or "substantially" is used in combination with a numerical value, the relevant numerical value may include manufacturing or operating tolerances around the stated numerical value (e.g., ±10%). In addition, when the terms "substantially" or "essentially" are used in combination with a geometric shape, it may be intended that the precision of the geometric shape is not required and the tolerance for the shape is within the scope of the present disclosure. In addition, whether the numerical value or shape is limited by "about" or "substantially", the numerical value or shape should be construed to include manufacturing or operating tolerances around the stated numerical value or shape (e.g., ±10%).

[0056] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0057] One or more of the elements disclosed below may include or be implemented as follows: processing circuitry, such as hardware including logic circuits; a hardware / software combination, such as a processor that executes software; or a combination thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0058] The use of any and all examples or exemplary language provided herein is merely intended to better describe the present disclosure and does not impose a limitation on the scope of the present disclosure unless otherwise stated.

[0059] The oxide semiconductor has excellent characteristics such as low off-current, low subthreshold swing, and high on / off ratio, and can thus be used in a memory device or a logic device.

[0060] The oxide semiconductor thin film according to some example embodiments may include an oxide semiconductor having an amorphous phase and including a plurality of metal elements, wherein the content of tin (Sn) among the plurality of metal elements is the largest. In addition to tin, the oxide semiconductor may further include indium (In), gallium (Ga), zinc (Zn), aluminum (Al), and hafnium (Hf). For example, the oxide semiconductor may be or may include InSnO, InGaSnO, InSnZnO, GaSnZnO, or ZnSnO. The thickness of the oxide semiconductor thin film according to various example embodiments may be about 30 nm or less, about 20 nm or less, or about 10 nm or less.

[0061] Tin (Sn) has a 5s orbital and thus has a high electron mobility. However, since tin has a high bond dissociation energy with oxygen of about 528 kJ / mol, tin can reduce oxygen diffusion. Therefore, even when heat is applied to the oxide semiconductor, the metal ions can maintain a thermally stable state by reducing compositional changes and can maintain electrical properties. However, since tin has a high bond dissociation energy with oxygen, the probability of forming oxygen vacancies is low, and thus the charge carrier concentration may be low. To supplement the above characteristics, an element having a low bond dissociation energy with oxygen may be added to the oxide including tin.

[0062] Even when the oxide semiconductor thin film includes a plurality of different elements other than oxygen, the content of tin among the plurality of elements may be greater than or equal to about 50 atomic %, greater than or equal to about 53 atomic %, less than or equal to about 69 atomic %, less than or equal to about 75 atomic %, less than about 80 atomic %, and less than about 85 atomic %. Here, the term "content" may refer to the content among metal elements other than oxygen.

[0063] The oxide semiconductor thin film may include tin (Sn) and a first metal element X different from tin. The first metal element X may be any one of indium (In), gallium (Ga), zinc (Zn), aluminum (Al), and hafnium (Hf). The content ratio of tin to the first metal element may be greater than about 1 and less than or equal to 4.

[0064] Indium (In) has a low bond dissociation energy with oxygen, and thus, it can easily form oxygen vacancies to increase the charge carrier concentration in the oxide and can form an electron conduction path well through the 5s orbital.

[0065] InSnO (a combination of indium and tin) is widely used as an electrode due to its high charge carrier concentration and / or electron mobility, but when the thickness of the oxide is reduced, InSnO may have semiconductor properties and can be used as a channel. In the oxide semiconductor thin film, the content of indium may be greater than or equal to 20 atomic % and less than about 50 atomic %.

[0066] The oxide semiconductor thin film may further include gallium (Ga). The oxide semiconductor thin film including gallium can better maintain the amorphous phase than the oxide semiconductor thin film not including gallium. However, the carrier concentration decreases in proportion to the content of gallium. When the content of gallium is too high, the thin film may have insulating properties, and thus, the content of gallium needs to be limited. For example, the content of gallium may be 30 atomic % or less.

[0067] On the other hand, zinc (Zn) is a thermally unstable material. The recrystallization temperature of zinc is about 50 °C or lower. Zinc can even be recrystallized by heat from about 200 °C to about 300 °C, thereby changing the electrical properties of the thin film. In addition, zinc has the following problems: the diffusion rate of zinc increases through heat, and zinc can diffuse into other materials such as an insulating layer, thereby increasing the conductivity of the insulating layer. The oxide semiconductor thin film according to some example embodiments can maintain semiconductor properties by reducing the content of zinc (Zn).

[0068] When the semiconductor thin film according to some example embodiments includes zinc (Zn), the content of zinc may be about 30 atomic % or less or about 10 atomic % or less. Alternatively, the content of zinc may be about 0 atomic %.

[0069] The oxide semiconductor film may include tin, a first element different from tin, and a second element. The content of tin may be greater than the sum of the content of the first element and the content of the second element. The content of the first element and the content of the second element may each be about 30 atomic % or less. For example, when the oxide semiconductor film further includes indium and gallium, the content of tin may be greater than the sum of the content of indium and the content of gallium. In this case, the content of gallium may be about 30 atomic % or less or the content of indium may be about 30 atomic % or less. The content of indium may be about 20 atomic % or greater. Alternatively, when the oxide semiconductor film includes indium and zinc, the content of tin may be greater than the sum of the content of indium and the content of zinc. The content of indium may be about 20 atomic % or greater, and the content of zinc may be about 30 atomic % or less. The oxide semiconductor film may include 4 or more types of metals including tin.

[0070] To identify the electrical properties of an oxide semiconductor film including tin and indium, a total of 9 types of films were fabricated along the line connecting indium and tin, including In 2 O 3 films, SnO 2 films, and 7 types of InSnO films. The composition ratios of indium and tin in the 7 types of InSnO films were 0.15:0.85, 0.31:0.69, 0.47:0.53, 0.63:0.37, 0.75:0.25, 0.80:0.20, and 0.84:0.16, respectively. The thickness of each film was about 30 nm. The 9 types of films were heat-treated in an air atmosphere at 400 °C for 3 hours, and then X-ray diffraction (XRD), carrier concentration, Hall mobility, and resistivity were measured.

[0071] Figure 1 FIG. showing the XRD results of 9 types of InSnO films according to each exemplary embodiment.

[0072] Referring to Figure 1 , it was found that the crystallinity changed according to the content of indium and tin. For example, in the XRD analysis, the SnO 2 film had peaks at 2θ values of about 27 degrees and about 38.5 degrees. This may mean that the SnO 2 film had a tetragonal phase. It was found that the In 2 O 3 film had a peak at a 2θ value of about 31 degrees. This may mean that the In 2 O 3 film had a cubic phase.

[0073] When In 2 O 3 was added to SnO 2When the content of indium in the InSnO film was 15 atomic %, it was found that the peak at a 2θ value of about 27 degrees widened and the peak at about 38.5° degrees became a peak at 38.1 degrees. Therefore, the position and shape of the peak slightly changed, but the peak still existed. This may mean that the InSnO film in which the content of indium was 15 atomic % had a polycrystalline structure with a tetragonal phase. It was found that even by adding In 2 O 3 Add SnO 2 In the InSnO thin film in which the tin content is about 37 atomic %, the position of the peak is slightly changed, but there is still a sharp peak around 31°. This may mean that the InSnO thin film in which the tin content is about 37 atomic % or less has polycrystalline with a cubic phase.

[0074] It can be found that the InSnO thin film having the composition In:Sn=47:53 and the composition In:Sn=31:69 does not have a sharp peak. For example, it can be found that the InSnO thin film in which the content of Sn is about 53 atomic % to 69 atomic % has an amorphous phase.

[0075] Figure 2 Graphs showing changes in carrier concentration, Hall mobility, and resistivity according to the tin content in an InSnO thin film.

[0076] Reference Figure 2 It was found that the Hall mobility changes rapidly according to the change of the tin content. In particular, it was found that when the tin content is greater than 50 atomic % and less than or equal to 80 atomic %, the Hall mobility is 30 cm 2 / Vs or more and the resistivity is 10 -3 Ωcm or more and 10 -1 Ωcm or less. It was found that an InSnO thin film in which the content of Sn is greater than 50 atomic % and less than 80 atomic % has semiconductor properties having high Hall mobility.

[0077] Considering the mechanism of oxide semiconductors in which electrons move through s orbitals, when indium and tin are mixed in an amorphous state, electrons can move freely through s orbitals. However, when the InSnO film has a polycrystalline phase, electron mobility may be reduced due to grain boundary scattering. Therefore, when tin and indium are combined so that the content of Sn is greater than about 50 atomic % and less than about 80 atomic %, the oxide semiconductor film having an amorphous phase may have a high Hall mobility.

[0078] It was found that the InSnO thin film in which the Sn content was greater than about 50 atomic % and less than about 80 atomic % maintained an amorphous phase and high Hall mobility even when heat-treated at 400° C. for 3 hours, and therefore had high thermal stability at 400° C.

[0079] The oxide semiconductor thin film including tin as a main component according to some exemplary embodiments may further include at least one of gallium (Ga), zinc (Zn), aluminum (Al), and hafnium (Hf). Generally, gallium can increase the thermal stability of the semiconductor thin film. Since the diffusion rate of zinc (Zn) increases with heat, the content of zinc may be 10 atomic % or less.

[0080] To identify the electrical properties of an oxide semiconductor layer including indium, tin, and gallium, four types of InSnGaO thin films with composition ratios of In:Sn:Ga of about 25:58:17, about 20:52:28, about 17:46:37, and about 16:42:42 were fabricated by atomic layer deposition (ALD).

[0081] Figure 3 A graph showing XRD results after heat-treating InSnO thin film and four types of InSnGaO thin films at 400 °C for 3 hours in an air atmosphere.

[0082] Referring to Figure 3 , as a result of checking crystallinity using XRD, no peaks were found at 2θ values of about 27 degrees, about 31 degrees, and about 38.5 degrees. It was found that even when gallium was included, the four types of InSnGaO remained in an amorphous phase.

[0083] Figure 4 A graph showing XRD results after heat-treating InSnO thin film and four types of InSnGaO thin films at 600 °C according to each exemplary embodiment.

[0084] Referring to Figure 4 , as a result of checking crystallinity using XRD, in the InSnO thin film (ITO) without gallium, peaks were found at 2θ values of about 24 degrees and about 38.5 degrees. This may mean that even when heat-treated at a high temperature such as about 600 °C, the InSnO thin film may have a polycrystalline phase. However, in the four types of InSnGaO thin films including gallium, no peaks were found. This may mean that the InSnGaO thin film ensures thermal stability due to gallium.

[0085] Figure 5 A graph showing changes in carrier concentration, Hall mobility, and resistivity according to the contents of gallium, tin, and indium in three types of InSnGaO thin films according to each exemplary embodiment. Figure 5 Results for three types of InSnGaO thin films with composition ratios of In:Sn:Ga of about 25:58:17, about 20:52:28, and about 17:46:37 are shown.

[0086] Referring to Figure 5, it was found that as the content of tin decreased and the content of gallium increased, the carrier concentration and Hall mobility decreased, and the resistivity increased. It was found that when the content of tin was about 50 atomic % or less or the content of gallium was greater than about 30 atomic %, the Hall mobility decreased or the resistivity increased. This may mean that the electrical properties of the oxide semiconductor film are related to the contents of tin and gallium. When the content of tin is greater than the sum of the contents of indium and gallium, the Hall mobility is 15 cm 2 / Vs or greater and the resistivity is 10 -1 Ωcm or less, and thus, it may exhibit semiconductor properties. When the content of tin is greater than about 50 atomic % or the content of gallium is about 30 atomic % or less, the Hall mobility is 15 cm 2 / Vs or greater and the resistivity is 10 -1 Ωcm or less, and thus, it may exhibit semiconductor properties.

[0087] Figure 6 FIG. is a graph showing the IV characteristics according to the heat treatment temperature of a transistor including an oxide semiconductor film according to some exemplary embodiments. An oxide semiconductor film having an In:Sn:Ga composition ratio of 0.25:0.64:0.11 was formed as a channel layer having a thickness of about 4.5 nm, and then heat-treated at about 600 °C and about 700 °C for about 30 minutes. Figure 6 Shows the IV characteristics of transistors heat-treated at different temperatures.

[0088] Referring to Figure 6 , from the IV characteristics of the transistor heat-treated at about 600 °C, it was found that the transistor heat-treated at about 600 °C had a field-effect mobility of about 7.7 cm at a subthreshold voltage swing of 75 mV / dec 2 / Vs and had a threshold voltage of about -0.2 V. It was found that the transistor heat-treated at 600 °C had excellent thermal stability.

[0089] , from the IV characteristics of the transistor heat-treated at about 700 °C, it was found that the transistor heat-treated at about 700 °C had a field-effect mobility of about 5.2 cm at a subthreshold voltage swing of about 86 mV / dec 2 / Vs and had a threshold voltage of about -0.1 V. It was found that the transistor heat-treated at about 700 °C could still operate stably, even though its thermal stability deteriorated slightly compared to the transistor heat-treated at 600 °C.

[0090] According to various exemplary embodiments, an oxide semiconductor film including tin as a main component may have semiconductor properties due to its high Hall mobility, and thus can be used as a channel layer of a semiconductor device.

[0091] Figure 7A diagram showing a semiconductor device including an oxide semiconductor according to some example embodiments. Referring to Figure 7 , the semiconductor device 100 may include a substrate 101, a first electrode 110 disposed on the substrate 101, an oxide semiconductor layer 120 disposed on the first electrode 110, and a second electrode 130 disposed on the oxide semiconductor layer 120.

[0092] The substrate 101 may be or may include an insulating substrate, or a semiconductor substrate having a surface on which an insulating layer is formed. Alternatively, the substrate 101 may be or may include a semiconductor substrate. The semiconductor substrate may include, for example, Si, Ge, SiGe, or III-V group semiconductor materials. The substrate 101 may be, for example, a silicon substrate having a silicon oxide formed on its surface, but the present disclosure is not limited thereto.

[0093] The first electrode 110 may include a metal material. The first electrode 110 may include at least one selected from tungsten (W), cobalt (Co), nickel (Ni), iron (Fe), titanium (Ti), molybdenum (Mo), chromium (Cr), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), silver (Ag), gold (Au), aluminum (Al), copper (Cu), tin (Sn), antimony (Sb), vanadium (V), ruthenium (Ru), platinum (Pt), zinc (Zn), and / or magnesium (Mg). The first electrode 110 may be spaced apart from the substrate 101.

[0094] The oxide semiconductor layer 120 may be provided as an ultra-thin film. For example, the thickness of the oxide semiconductor layer 120 may be about 30 nm or less, about 20 nm or less, or about 10 nm or less. The length of the oxide semiconductor layer 120 may be less than about 1 μm. The oxide semiconductor layer 120 may be an oxide semiconductor thin film including tin as a main component as described above. For example, the oxide semiconductor layer 120 may include various elements other than oxygen and may have an amorphous phase, in which the content of tin (Sn) among the various elements is the largest. The content of tin may be greater than about 50 atomic %, greater than or equal to about 53 atomic %, less than or equal to about 75 atomic %, and less than about 80 atomic %. Here, the term "content" may refer to the content among the elements other than oxygen in the oxide semiconductor layer 120.

[0095] The oxide semiconductor layer 120 may include any one of indium (In), gallium (Ga), zinc (Zn), aluminum (Al), and hafnium (Hf). For example, when the oxide semiconductor layer 120 further includes indium, the content ratio of tin to indium may be greater than about 1 and less than or equal to 4. In the oxide semiconductor layer 120, the content of indium may be greater than or equal to about 20 atomic % and less than about 50 atomic %. The oxide semiconductor layer 120 may further include gallium with a content of 30 atomic % or less. Alternatively, when the oxide semiconductor layer 120 further includes indium and gallium, the content of tin may be greater than the sum of the content of indium and the content of gallium. In this case, the content of gallium may be about 30 atomic % or less, or the content of indium may be about 30 atomic % or less. The content of indium may be about 20 atomic % or greater. The oxide semiconductor layer 120 may maintain an amorphous phase at a temperature of about 350°C to 700°C or about 350°C to 600°C.

[0096] The oxide semiconductor layer 120 may be arranged such that the longitudinal direction of the oxide semiconductor layer 120 is a direction perpendicular to the substrate 101 (z-axis direction). In the present specification, the term "longitudinal direction" refers to the direction in which the length of the corresponding element is long when observed in the drawings.

[0097] The second electrode 130 may be disposed on the oxide semiconductor layer 120. The first electrode 110 and the second electrode 130 may be spaced apart from each other in a direction perpendicular to the substrate 101 (z-axis direction). For example, the first electrode 110, the oxide semiconductor layer 120, and the second electrode 130 may be aligned with each other in a direction perpendicular to the substrate 101 or in the thickness direction of the first electrode 110 (z-axis direction).

[0098] The gate 150 may be disposed at one side of the oxide semiconductor layer 120. The gate insulating layer 140 may be disposed between the oxide semiconductor layer 120 and the gate 150. The gate 150 may include at least one of a metal, a metal nitride, and a transparent conductive oxide (TCO). The gate insulating layer 140 may include an oxide containing at least one of hafnium (Hf), zirconium (Zr), aluminum (Al), and / or silicon (Si).

[0099] The gate 150 may be arranged such that the longitudinal direction (z-axis direction) of the gate 150 is a direction perpendicular to the substrate 101. The oxide semiconductor layer 120, the gate insulating layer 140, and the gate 150 may be aligned with each other in a direction parallel to the substrate 101 (x-axis direction).

[0100] The molding (die) insulating layer 160 may be disposed on the substrate 101 to fill the empty space. The first electrode 110 may be spaced apart from the substrate 101 through the molding insulating layer 160.

[0101] Figure 8FIG. showing a semiconductor device 100b according to other exemplary embodiments. In Figure 8 , elements denoted by the same reference numerals as those in Figure 7 have substantially the same configurations and effects as those described with reference to Figure 7 , and thus detailed descriptions thereof are omitted.

[0102] Figure 8 The semiconductor device 100b of may include a first electrode 110, an oxide semiconductor layer 120, and a second electrode 130 disposed in a direction (z-axis direction) perpendicular to the substrate 101. A gate insulating layer 140 may be disposed around the oxide semiconductor layer 120, and a gate 150 may be disposed around the gate insulating layer 140. The gate 150 may be disposed around the oxide semiconductor layer 120 such that the area where the gate 150 and the oxide semiconductor layer 120 face each other increases, and the short-channel effect is suppressed.

[0103] Figure 9 FIG. showing a semiconductor device 100c according to other exemplary embodiments.

[0104] Referring to Figure 9 , the semiconductor device 100c may include a substrate 101, a first electrode 110 disposed on the substrate 101, and a second electrode 130 spaced apart from the first electrode 110. The first electrode 110 and the second electrode 130 may be spaced apart from each other in a direction (z-axis direction) perpendicular to the substrate 101.

[0105] The oxide semiconductor layer 120 may be disposed outside the space between the first electrode 110 and the second electrode 130. The oxide semiconductor layer 120 may include a first portion 120a parallel to the substrate 101, a second portion 120b bent and extending from the first portion 120a in a direction perpendicular to the substrate 101, and a third portion 120c bent and extending from the second portion 120b in a direction opposite to the first portion 120a. The second portion 120b may be disposed on the sides of the first electrode 110 and the second electrode 130, and the third portion 120c may contact the second electrode 130. The oxide semiconductor layer 120 may correspond to the above-described oxide semiconductor thin film.

[0106] The gate 150 may have a shape similar to that of the oxide semiconductor layer 120 and may be spaced apart from the oxide semiconductor layer 120. In other words, the gate 150 may include a first portion 150a parallel to the substrate 101, a second portion 150b bent and extending from the first portion 150a in a direction perpendicular to the first substrate 101, and a third portion 150c bent and extending from the second portion 150b in a direction opposite to the first portion 150a. A gate insulating layer 140 may be disposed between the oxide semiconductor layer 120 and the gate 150.

[0107] Figure 10 A diagram showing a semiconductor device 100d according to some example embodiments.

[0108] Figure 10 The semiconductor device 100d may include a first electrode 110 and an oxide semiconductor layer 120 disposed on the first electrode 110. Materials for the first electrode 110 and the oxide semiconductor layer 120 have been described above, and thus, detailed descriptions thereof are omitted.

[0109] The oxide semiconductor layer 120 may have a U-shaped cross-sectional shape. The oxide semiconductor layer 120 may include a bottom portion 123 in contact with the first electrode 110, a first vertical extension portion 121 extending from one end of the bottom portion 123 in a direction perpendicular to the first electrode 110 (z-axis direction), and a second vertical extension portion 122 extending from the other end of the bottom portion 123 in a direction perpendicular to the first electrode 110 (z-axis direction).

[0110] The first gate 151 may be spaced apart from the first vertical extension portion 121, and the second gate 152 may be spaced apart from the second vertical extension portion 122. The first gate insulating layer 141 may be disposed between the first vertical extension portion 121 and the first gate 151, and the second gate insulating layer 142 may be disposed between the second vertical extension portion 122 and the second gate 152.

[0111] The first gate 151 and / or the second gate 152 may extend in a second horizontal direction (y-axis direction). The first gate 151 and the second gate 152 may be spaced apart from each other. For example, the first gate 151 and the second gate 152 may be spaced apart in a first horizontal direction (x-axis direction). The first gate 151 and / or the second gate 152 may form a word line WL. An electrical signal input to the first gate 151 may be different from an electrical signal input to the second gate 152. The first gate 151 may control a channel of the first vertical extension portion 121, and the second gate 152 may control a channel of the second vertical extension portion 122.

[0112] The insulating spacer 171 may be disposed between the first gate 151 and the second gate 152 spaced apart from each other. The insulating spacer 171 may be conformally disposed on the opposing sidewalls of the first gate 151 and the second gate 152 and / or on the top surface of the oxide semiconductor layer 120. For example, the insulating spacer 171 may be conformally disposed on the top surface of the bottom portion 123. The insulating spacer 171 may have a top surface disposed in the same plane as the top surfaces of the first gate 151 and the second gate 152. The insulating spacer 171 may include, for example, silicon nitride. The buried insulating layer 172 may be disposed on the insulating spacer 171 to fill the space between the first gate 151 and the second gate 152 spaced apart from each other. The buried insulating layer 172 may include, for example, silicon oxide. The upper insulating layer 173 may be disposed on the top surfaces of the first gate 151, the second gate 152, and / or the buried insulating layer 172. The top surface of the upper insulating layer 173 may be at the same level as the top surface of the molded insulating layer 160.

[0113] The second electrode 130 may be disposed on the oxide semiconductor layer 120. The second electrode 130 may function as a landing pad. The second electrode 130 may include a first sub-electrode 131 and a second sub-electrode 132. The first sub-electrode 131 may be electrically connected to the first vertically extending portion 121. The second sub-electrode 132 may be electrically connected to the second vertically extending portion 122. The first sub-electrode 131 and the second sub-electrode 132 may not be electrically connected to each other.

[0114] The second electrode 130 may include an upper portion and a lower portion. The upper portion of the second electrode 130 may be the portion of the second electrode 130 disposed at a level higher than the top surface of the molded insulating layer 160. The lower portion of the second electrode 130 may be the portion of the second electrode 130 disposed in the recess of the second electrode 130 defined between the molded insulating layer 160 and the upper insulating layer 173.

[0115] In some exemplary embodiments, the upper portion of the second electrode 130 may have a first width in a first horizontal direction (x-axis direction), and the lower portion of the second electrode 130 may have a second width less than the first width in the first horizontal direction (x-axis direction). The lower portion of the second electrode 130 may be disposed in the recess of the second electrode 130, and the upper portion of the second electrode 130 may be disposed on the lower portion of the second electrode 130 and may have a bottom surface disposed on the top surfaces of the molded insulating layer 160 and the upper insulating layer 173, and thus, the second electrode 130 may have a T-shaped vertical cross-sectional shape.

[0116] The bottom surface of the lower portion of the second electrode 130 may contact the top surface of the first vertically extending portion 121 and / or the second vertically extending portion 122. For example, the bottom surface of the first sub-electrode and / or the bottom surface of the second sub-electrode may contact the top surface of the first vertically extending portion 121 and / or the second vertically extending portion 122. Both side walls of the lower portion of the second electrode 130 may be aligned with both side walls of the first vertically extending portion 121 and the second vertically extending portion 122. The bottom surface of the lower portion of the second electrode 130 may be at a level higher than the top surface of the first gate 151 and / or the second gate 152, and a portion of the side wall of the lower portion of the second electrode 130 may be covered by the first gate insulating layer 141 and / or the second gate insulating layer 142.

[0117] The insulating layer 174 surrounding the second electrode 130 may be disposed on the top surfaces of the molding insulating layer 160 and the upper insulating layer 173. The semiconductor device 100d may have a vertical channel transistor (VCT) structure including a vertical channel region extending in a direction (z-axis direction) perpendicular to the first electrode 110.

[0118] Figure 11 FIG. showing a semiconductor device 100e according to other exemplary embodiments. Referring to Figure 11 , the semiconductor device 100e may include a substrate 101, and a first electrode 110 and a second electrode 130 disposed on the substrate 101 and spaced apart from each other. The first electrode 110 and the second electrode 130 may be spaced apart from each other in a direction (x-axis direction) parallel to the substrate 101.

[0119] An oxide semiconductor layer 120 may be disposed between the first electrode 110 and the second electrode 130. The oxide semiconductor layer 120 may include a first portion parallel to the substrate 101, a second portion bent and extending in a direction perpendicular to the first substrate 101 from the first portion, and a third portion bent and extending in a direction opposite to the first portion from the second portion. For example, the second portion may be spaced apart from the third portion. The second portion may overlap a portion of the first electrode 110 in the thickness direction of the substrate 101, and the third portion may overlap a portion of the second electrode 130 in the thickness direction of the substrate 101. For example, the second portion may overlap a portion of the first electrode 110 in a direction perpendicular to the first substrate 101, and the third portion may overlap the second electrode 130 in a direction perpendicular to the first substrate 101. The oxide semiconductor layer 120 may correspond to the above-described oxide semiconductor thin film.

[0120] Figure 12 FIG. showing a circuit diagram of a complementary metal oxide semiconductor (CMOS) inverter 200 according to some exemplary embodiments.

[0121] The CMOS inverter 200 includes a CMOS transistor 210. The CMOS transistor 210 includes a P-channel MOS (PMOS) transistor 220 and an N-channel MOS (NMOS) transistor 230 connected between a power supply terminal Vdd and a ground terminal. The CMOS transistor 210 may include a semiconductor device according to various example embodiments described with reference to Figures 7 to 11 the description.

[0122] Figure 13 FIG. is a circuit diagram showing a CMOS static random access memory (SRAM) device 300 according to some example embodiments.

[0123] The CMOS SRAM device 300 includes a pair of drive transistors 310. Each drive transistor 310 includes a PMOS transistor 320 and an NMOS transistor 330 connected between a power supply terminal Vdd and a ground terminal. The CMOS SRAM device 300 may further include a pair of transfer transistors 340. The source of the transfer transistor 340 is cross-connected to a common node of the PMOS transistor 320 and the NMOS transistor 330 that constitute the drive transistor 310. The power supply terminal Vdd is connected to the source of the PMOS transistor 320, and the ground terminal is connected to the source of the NMOS transistor 330. The word line WL may be connected to the gates of the pair of transfer transistors 340, and the bit line BL and the inverted bit line BL' may be connected to the drains of the pair of transfer transistors 340, respectively.

[0124] At least one of the drive transistors 310 and the transfer transistors 340 of the CMOS SRAM device 300 may include a semiconductor device according to various example embodiments described with reference to Figures 7 to 11 the description.

[0125] Figure 14 FIG. is a circuit diagram showing a CMOS NAND circuit 400 according to some example embodiments.

[0126] The CMOS NAND circuit 400 includes a pair of CMOS transistors to which different input signals are sent. The CMOS NAND circuit 400 may include a semiconductor device according to various example embodiments described with reference to Figures 7 to 11 the description.

[0127] Figure 15 FIG. is a block diagram showing an electronic system 500 according to some example embodiments.

[0128] The electronic system 500 includes a memory 510 and a memory controller 520. The memory controller 520 can control data to be read from the memory 510 and / or data to be written to the memory 510 in response to requests from a host 530. At least one of the memory 510 and the memory controller 520 may include a semiconductor device according to various example embodiments described with reference to Figures 7 to 11 described.

[0129] Figure 16 FIG. is a block diagram showing an electronic system 600 according to some example embodiments.

[0130] The electronic system 600 can form a wireless communication device or a device capable of transmitting and / or receiving information in a wireless environment. The electronic system 600 may include a controller 610, an input / output (I / O) device 620, a memory 630, and a wireless interface 640 connected to each other via a bus 650.

[0131] The controller 610 may include at least one of a microprocessor, a digital signal processor, or a similar processor device. The I / O device 620 may include at least one of a keypad, a keyboard, or a display. The memory 630 can be used to store commands executed by the controller 610. For example, the memory 630 can be used to store user data. The electronic system 600 can use the wireless interface 640 to send / receive data via a wireless communication network. The wireless interface 640 may include an antenna and / or a wireless transceiver. The electronic system 600 may include a semiconductor device according to various example embodiments described with reference to Figures 7 to 11 described.

[0132] According to some example embodiments, a semiconductor device can exhibit good electrical properties in an ultra-small structure, and thus can be applied to integrated circuit devices, and miniaturization, low power consumption, and high performance can be achieved.

[0133] Although semiconductor thin films, semiconductor devices including the same, and electronic devices have been described with reference to various example embodiments shown in the drawings, these are examples, and those of ordinary skill in the art will understand that various changes in form and detail can be made therein without departing from the scope of the present disclosure. Although many matters have been described in detail in the above description, they should be understood as examples of specific example embodiments and not as limiting the scope of the present disclosure. The scope of the present disclosure should not be limited by the above example embodiments, but should be defined by the appended claims.

[0134] When a semiconductor device according to some example embodiments uses an amorphous oxide semiconductor including tin as a main component as a channel material, the Hall mobility can increase. Accordingly, the subthreshold swing of the semiconductor device can be reduced.

[0135] An amorphous oxide semiconductor including tin as a main component according to some example embodiments is a semiconductor material having a wide bandgap and can be used in highly integrated memory devices or logic devices.

[0136] It should be understood that the example embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of features or aspects within each example embodiment should typically be considered applicable to other similar features or aspects in other example embodiments. Although one or more example embodiments have been described with reference to the accompanying drawings, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims.

Claims

1. Semiconductor devices, including: an oxide semiconductor layer having an amorphous phase and including tin (Sn) and a metal element other than tin (Sn), wherein a content of tin (Sn) is greater than 50 atomic % of a total content of tin (Sn) and the metal element other than tin (Sn); a first electrode and a second electrode on the oxide semiconductor layer and spaced apart from each other; a gate spaced apart from the oxide semiconductor layer; as well as A gate insulating layer is between the oxide semiconductor layer and the gate. 2 . The semiconductor device according to claim 1 , wherein the metal element other than tin includes at least one of indium (In), gallium (Ga), zinc (Zn), aluminum (Al), or hafnium (Hf). 3 . The semiconductor device according to claim 1 , wherein the metal element other than tin (Sn) includes zinc (Zn), wherein a content of zinc (Zn) is 10 atomic % or less.

4. The semiconductor device according to claim 1, wherein: In the oxide semiconductor layer, the content of zinc (Zn) is 0 atomic %.

5. The semiconductor device according to claim 1, wherein the content of tin is less than 80 atomic %. 6 . The semiconductor device according to claim 1 , wherein the oxide semiconductor layer has an amorphous phase at 350° C. to 700° C.

7. The semiconductor device according to claim 1, wherein the metal element other than tin includes indium, The content ratio of tin to indium is greater than 1 and less than or equal to 4.

8. The semiconductor device according to claim 7, wherein a content of indium is 20 atomic % or more.

9. The semiconductor device according to claim 1, wherein the metal element other than tin includes gallium, wherein The gallium content is 30 atomic % or less.

10. The semiconductor device according to claim 1, wherein The metal element other than tin includes indium (In) and gallium (Ga), and The gallium content is 30 atomic % or less.

11. The semiconductor device according to claim 10, wherein a content of indium is 20 atomic % or more.

12. The semiconductor device according to claim 1, wherein the oxide semiconductor layer has a thickness of 15 cm 2 / Vs or greater Hall mobility.

13. The semiconductor device according to claim 1, wherein the oxide semiconductor layer has 10 -1 Resistivity of Ωcm or less. 14 . The semiconductor device according to claim 1 , wherein the oxide semiconductor layer has a thickness of 20 nm or less. 15 . The semiconductor device according to claim 1 , wherein the gate insulating layer includes at least one of hafnium (Hf), zirconium (Zr), aluminum (Al), or silicon (Si). 16 . The semiconductor device of claim 1 , wherein the gate comprises at least one of a metal, a metal nitride, or a transparent conductive oxide (TCO).

17. Oxide semiconductor thin film, comprising: Tin (Sn), Indium (In) and Gallium (Ga), The content of tin is greater than the sum of the content of indium and the content of gallium, and the oxide semiconductor film has an amorphous phase.

18. The oxide semiconductor thin film according to claim 17, wherein Among the elements other than oxygen, the content of tin is greater than 50 atomic % and less than 80 atomic %.

19. The oxide semiconductor thin film according to claim 17, wherein Among elements other than oxygen, the content of gallium is 30 atomic % or less.

20. The oxide semiconductor thin film according to claim 17, wherein Among the elements other than oxygen, the content of indium is 20 atomic % or more.

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