Bipolar SnO thin film transistor compatible with BEOL and free of hysteresis and method

Abstract

The invention belongs to the technical field of semiconductor devices, and provides a BEOL-compatible and hysteresis-free bipolar SnO TFT (Thin Film Transistor) and a preparation method of the BEOL-compatible and hysteresis-free bipolar SnO TFT. The transistor comprises a substrate, a bottom gate electrode, a stacked gate insulation structure, a semiconductor channel layer, a source electrode, a drain electrode and a stacked passivation structure, the bottom gate electrode is arranged on the upper surface of the substrate; the laminated gate insulation structure comprises a first gate insulation layer and a second gate insulation layer which are sequentially arranged from bottom to top; the semiconductor channel layer is arranged on the upper surface of the second gate insulating layer; the source electrode and the drain electrode are respectively arranged at two ends of the upper surface of the semiconductor channel layer; the stack passivation structure comprises a first passivation layer, a second passivation layer, a third passivation layer and a fourth passivation layer which are sequentially arranged from bottom to top; the first passivation layer is arranged on the upper surfaces of the source electrode, the drain electrode and the semiconductor channel layer. The whole preparation process is compatible with BEOL, the competitiveness of the SnO TFTs in oxide semiconductors is improved, and the application field and prospect of the SnO TFTs are widened.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to a bipolar SnO thin film transistor compatible with BEOL and without hysteresis and a method thereof. Background Art

[0002] The statements in this part merely provide background technical information related to the present invention and do not necessarily constitute prior art.

[0003] Among numerous thin film transistor (TFTs) material systems, oxide TFTs present great development potential in various application scenarios due to a series of remarkable advantages such as high mobility, good transparency, and the ability to be prepared at low temperature. Among numerous oxide semiconductors, bipolar tin monoxide (SnO) TFTs have irreplaceable important value in some special circuit designs and multifunctional device applications because of their unique electrical properties, which can simultaneously achieve electron conduction and hole conduction.

[0004] However, currently, bipolar SnO TFTs face many problems to be solved urgently, among which the hysteresis phenomenon is particularly prominent. It is worth noting that compared with silicon-based semiconductor TFTs, oxide TFTs generally have a large hysteresis phenomenon, which will reduce the noise margin and increase the delay variation in CMOS logic applications based on oxide semiconductors, thus hindering their further development. The hysteresis phenomenon severely restricts the development of SnO and many oxide semiconductor materials in various fields. For example, in the display field, hysteresis will slow down the response speed of pixels and cause ghosting when the image switches, seriously affecting the display quality; in sensor applications, hysteresis will lead to inaccurate measurement results and cannot reflect the change of the measured physical quantity in real time and accurately; in the storage field, hysteresis may damage the accuracy of the data stored in the memory, which may cause serious consequences for industries with extremely high requirements for data accuracy such as finance and healthcare. In addition, hysteresis is also an embodiment of device stability. The existence of hysteresis reduces the stability of the device, resulting in great difficulties in precisely controlling the device, limiting the application of oxide TFTs in high-speed and high-precision electronic devices, and hindering the further development of related technologies. Therefore, it is of great practical significance and urgent market demand to develop SnO TFTs without hysteresis phenomenon. Summary of the Invention

[0005] To solve the technical problems existing in the above-mentioned background art, the present invention provides a bipolar SnO TFTs compatible with BEOL and without hysteresis, and a method thereof. Through the stacked design of the gate insulating layer and interface heat treatment, plasma treatment of the SnO back channel, stacked design of the device passivation layer, and high-temperature annealing treatment of the whole device, SnO TFTs without hysteresis, high hole mobility, high on / off current ratio, and low subthreshold swing are finally obtained.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] The first aspect of the present invention provides a bipolar SnO TFTs compatible with BEOL and without hysteresis.

[0008] A bipolar SnO TFTs compatible with BEOL and without hysteresis includes: a substrate, a bottom gate electrode, a stacked gate insulating structure, a semiconductor channel layer, a source electrode, a drain electrode, and a stacked passivation structure;

[0009] The bottom gate electrode is disposed on the upper surface of the substrate;

[0010] The stacked gate insulating structure includes a first gate insulating layer and a second gate insulating layer arranged in sequence from bottom to top; the first gate insulating layer is disposed on the upper surfaces of the bottom gate electrode and the substrate;

[0011] The semiconductor channel layer is disposed on the upper surface of the second gate insulating layer;

[0012] The source electrode and the drain electrode are respectively disposed at both ends of the upper surface of the semiconductor channel layer;

[0013] The stacked passivation structure includes a first passivation layer, a second passivation layer, a third passivation layer, and a fourth passivation layer arranged in sequence from bottom to top; the first passivation layer is disposed on the upper surfaces of the source electrode, the drain electrode, and the semiconductor channel layer.

[0014] As an implementation manner, the first gate insulating layer is a hafnium oxide thin film, and the second gate insulating layer is an aluminum oxide thin film.

[0015] As an implementation manner, the thicknesses of both the first gate insulating layer and the second gate insulating layer are 2 - 50 nm.

[0016] As an implementation manner, the first passivation layer is silicon nitride, the second passivation layer is aluminum oxide, the third passivation layer is hafnium oxide, and the fourth passivation layer is silicon oxide.

[0017] As an implementation manner, the thicknesses of the first passivation layer, the second passivation layer, the third passivation layer, and the fourth passivation layer are all 10 - 500 nm.

[0018] As an implementation, the thickness of the bottom gate electrode is 20 to 200 nm.

[0019] As an implementation, the thickness of the source electrode and the drain electrode is 20 to 500 nm.

[0020] The second aspect of the present invention provides a method for fabricating compatible BEOL and hysteresis-free bipolar SnO TFTs.

[0021] A method for fabricating compatible BEOL and hysteresis-free bipolar SnO TFTs includes:

[0022] Deposit a metal electrode on a substrate, obtain the bottom gate electrode pattern of the desired TFTs and remove the excess metal and impurities to obtain the desired bottom gate electrode;

[0023] On the upper surface of the bottom gate electrode and the substrate, grow a first gate insulating layer and a second gate insulating layer by atomic layer deposition;

[0024] Grow a SnO thin film on the upper surface of the second gate insulating layer, anneal it immediately after deposition, and perform plasma fluorination treatment on the film after annealing to obtain a semiconductor channel layer;

[0025] Deposit metal electrodes at both ends of the upper surface of the semiconductor channel layer to form source electrodes and drain electrodes;

[0026] Deposit a first passivation layer, a second passivation layer, a third passivation layer, and a fourth passivation layer on the upper surfaces of the source electrode, the drain electrode, and the semiconductor channel layer in sequence to fabricate a thin film transistor;

[0027] Perform high-temperature annealing treatment on the fabricated thin film transistor to meet the process thermal budget requirements in BEOL.

[0028] As an implementation, control the quality of the first gate insulating layer and the second gate insulating layer by adjusting the film thickness, precursor purge time, and deposition temperature; when depositing the first gate insulating layer and the second gate insulating layer, the precursor purge time is 5 to 50 s, the deposition temperature is 100 to 300 °C; the thicknesses of the first gate insulating layer and the second gate insulating layer are both 2 to 50 nm.

[0029] As an implementation, use a plasma-enhanced chemical vapor deposition system and an atomic layer deposition system to deposit the first passivation layer, the second passivation layer, the third passivation layer, and the fourth passivation layer in sequence.

[0030] The beneficial effects of the present invention are:

[0031] (1) The gate insulating layer of the present invention has a stacked structure of hafnium oxide and aluminum oxide, where the aluminum oxide has a better contact interface with the SnO semiconductor layer, effectively suppressing the hysteresis phenomenon caused by the diffusion of tin elements in the semiconductor layer, and reducing the interface defect states through thermal annealing of the insulating layer, thereby improving the density of the thin film.

[0032] (2) The combined stacked structure of the passivation layer of the present invention can effectively reduce the adsorption of water and oxygen in the air by the back channel of the device, reduce the shift of the threshold voltage caused thereby, and improve the stability of the device.

[0033] (3) The fluorine plasma treatment in the present invention effectively passivates the oxygen vacancies in the SnO thin film, reduces defects, improves the hysteresis of the device, and improves stability;

[0034] (4) During the high-temperature annealing process of the device in the present invention, the bulk defects of stannous oxide are effectively reduced, resulting in a significant improvement in the hysteresis phenomenon. In addition, the high-temperature thermal annealing will cause the disproportionation reaction of SnO, which is also the reason for the device to change from P-type to bipolar.

[0035] (5) The bipolar SnO TFTs proposed by the present invention have no hysteresis behavior, laying a foundation for their subsequent applications in display, sensing, storage, and large-scale integrated logic, etc.

[0036] (6) The bipolar SnO TFTs proposed by the present invention have no hysteresis and at the same time have high hole mobility, low subthreshold swing, low off-state current, and high on / off current ratio, and all characteristic parameters are at a relatively high level.

[0037] (7) The bipolar SnO TFTs proposed by the present invention can withstand high temperatures (400 °C), the overall preparation process is compatible with BEOL, and the preparation cost is very low. The preparation method is simpler, easier to repeat, the thin film has good uniformity, and can be prepared on a large scale, greatly accelerating the progress of oxide semiconductors in practical applications.

[0038] (8) The preparation method of the bipolar SnO TFTs prepared by the present invention is simple, efficient, and easy to repeat, and is suitable for industrial large-scale production. This device has no hysteresis phenomenon, and its DC performance parameters are at a relatively high level in the same field, with high hole field-effect mobility (~1.5 cm 2 V -1 s -1 ), low subthreshold swing (0.18 V decade -1 ), low off-state current (1.3×10 - 12 A um -1 ), and high on / off current ratio (>10 4) Such SnO TFTs have good uniformity and can be prepared on a large scale. In addition, the entire process is compatible with BEOL, showing broad application prospects in large-scale integrated circuits.

[0039] Advantages of additional aspects of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings forming a part of this specification are used to provide a further understanding of the present invention. The schematic embodiments and descriptions thereof of the present invention are used to explain the present invention and do not constitute an improper limitation of the present invention.

[0041] Figure 1 Schematic structural diagram of the SnO TFT provided by an embodiment of the present invention;

[0042] Figure 2 Transfer characteristic diagram of the SnO TFT provided by an embodiment of the present invention;

[0043] Figure 3 Transfer characteristic diagram of the SnO TFT provided by an embodiment of the present invention under positive gate voltage sweep (V G : +3.3 to -3.3 V);

[0044] Figure 4 Transfer characteristic diagram of the SnO TFT provided by an embodiment of the present invention under reverse gate voltage sweep (V G : -3.3 to +3.3 V);

[0045] Figure 5 Output characteristic diagram of the SnO TFT provided by an embodiment of the present invention;

[0046] Figure 6 Transfer characteristic diagrams of the SnO active layer with and without fluorine plasma treatment in a comparative example of the two-layer passivation layer structure provided by the present invention;

[0047] Figure 7 Transfer characteristic diagram of a comparative example of the two-layer passivation layer structure provided by the present invention before high-temperature annealing;

[0048] Figure 8 Transfer characteristic diagram of a comparative example of the two-layer passivation layer structure provided by the present invention after high-temperature annealing;

[0049] Figure 9 Transfer characteristic diagram of a comparative example of the three-layer passivation layer structure provided by the present invention;

[0050] Figure 10 Transfer characteristic diagram of a comparative example of the four-layer passivation layer structure provided by the present invention.

[0051] Among them, 1. Substrate, 2. Bottom gate electrode, 3. First gate insulating layer, 4. Second gate insulating layer, 5. Semiconductor channel layer, 6. Source electrode, 7. Drain electrode, 8. First passivation layer, 9. Second passivation layer, 10. Third passivation layer, 11. Fourth passivation layer. Detailed implementation manners

[0052] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0053] It should be noted that the following detailed descriptions are all illustrative and are intended to provide further explanations of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs.

[0054] It should be noted that the terms used herein are only for describing specific implementation manners and are not intended to limit the exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should also be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0055] In the current rapidly developing situation of electronic technology, thin-film transistors (TFTs), as the core components in electronic devices, have continuously expanded their application fields, covering multiple key fields such as displays, storage, sensors, and various integrated circuits.

[0056] Regarding the sources of hysteresis phenomena, they are mainly in the following aspects: First, there are a large number of interface defects at the interface between the semiconductor channel layer and the gate insulating layer. When the gate voltage changes, due to the interface trap states capturing and releasing charges, the electrical properties of the device cannot change in time with the change of voltage, resulting in the generation of hysteresis phenomena; at the same time, defects existing in the gate insulating layer, such as oxygen vacancies, etc., will also adsorb and desorb charges. When the scanning direction of the gate voltage changes, the adsorbed and desorbed charges will affect the threshold voltage of the device, and thus hysteresis appears; in addition, from the perspective of the internal structure of the material, the oxide semiconductor material itself has a certain number of impurities and lattice defects, and these factors are very likely to form charge traps. When the gate voltage changes, charges undergo the processes of capture and release in these traps, resulting in the inability of the electrical properties of the device to respond to the change of voltage in time, and thus triggering hysteresis phenomena; furthermore, the atmospheric environment will inevitably affect the device and bring hysteresis phenomena. Especially for back-channel etching type devices, the adsorption and desorption of water and oxygen in the air on the back channel are important reasons for generating hysteresis.

[0057] In the prior art, research on SnO TFTs mainly focuses on improving performance such as mobility, on / off current ratio, and bias stability through thin-film preparation process optimization, element doping, interface engineering, and encapsulation passivation. However, there are few reports on the origin and improvement methods of hysteresis in SnO TFTs. The literature [T. Kim, H. Lee, S. E. Kim, et al. High Mobility p-Channel Tin Monoxide Thin-Film Transistors with Hysteresis-Free Like Behavior [J]. Applied Physics Letters, 2022, 121(14).] infers that defects in the SnO TFTs channel may be the main factor causing hysteresis and attempts to improve it through annealing and adding a passivation layer. In addition, the literature [Y. Jang, I. W. Yeu, J. S. Kim, et al. Reduction of the Hysteresis Voltage in Atomic-Layer-Deposited p-Type SnO Thin-Film Transistors by Adopting an Al2O3 Interfacial Layer [J]. Advanced Electronic Materials, 2019, 5(7).] proposes that hysteresis also originates from interface traps between the semiconductor layer and the gate insulating layer, and uses alumina as an interlayer between the gate dielectric and the semiconductor to reduce the hysteresis of the device. However, these reported studies on improving the hysteresis characteristics of SnO TFTs do not completely eliminate the hysteresis phenomenon. In addition, their overall processes do not involve compatibility issues with the back-end of line (BEOL) processes of integrated circuits.

[0058] According to Figure 1 , an embodiment of the present invention provides a bipolar SnO TFTs that is compatible with BEOL and has no hysteresis, including: a substrate 1, a bottom gate electrode 2, a stacked gate insulating structure, a semiconductor channel layer 5, a source electrode 6, a drain electrode 7, and a stacked passivation structure;

[0059] The bottom gate electrode 2 is disposed on the upper surface of the substrate 1;

[0060] The stacked gate insulating structure includes a first gate insulating layer 3 and a second gate insulating layer 4 arranged in sequence from bottom to top; the first gate insulating layer 3 is disposed on the upper surfaces of the bottom gate electrode 2 and the substrate 1;

[0061] The semiconductor channel layer 5 is disposed on the upper surface of the second gate insulating layer 4;

[0062] The source electrode 6 and the drain electrode 7 are respectively disposed at two ends of the upper surface of the semiconductor channel layer 5;

[0063] The stacked passivation structure includes a first passivation layer 8, a second passivation layer 9, a third passivation layer 10, and a fourth passivation layer 11 disposed in sequence from bottom to top; the first passivation layer 8 is disposed on the upper surfaces of the source electrode 6, the drain electrode 7, and the semiconductor channel layer 5.

[0064] In this embodiment, the substrate 1 can be a silicon substrate, a glass substrate, a flexible polyimide PI substrate, etc.

[0065] The thickness of the bottom gate electrode 2 is 20 - 200 nm. The bottom gate electrode 2 can be prepared from materials such as tungsten W, molybdenum Mo, copper Cu, indium tin oxide ITO, etc.

[0066] In an embodiment of the present invention, the first gate insulating layer 3 is a hafnium oxide thin film, and the second gate insulating layer 4 is an aluminum oxide thin film. Among them, aluminum oxide has a better contact interface with the SnO semiconductor layer, and can effectively inhibit the hysteresis phenomenon caused by the diffusion of tin elements in the semiconductor layer.

[0067] Among them, the thicknesses of the first gate insulating layer 3 and the second gate insulating layer 4 are both 2 - 50 nm.

[0068] In an embodiment of the present invention, the first passivation layer 8 is silicon nitride, the second passivation layer 9 is aluminum oxide, the third passivation layer 10 is hafnium oxide, and the fourth passivation layer 11 is silicon oxide. Among them, the thicknesses of the first passivation layer 8, the second passivation layer 9, the third passivation layer 10, and the fourth passivation layer 11 are all 10 - 500 nm.

[0069] The combined stacked structure of the passivation layer of the present invention can effectively reduce the adsorption of water and oxygen in the air by the back channel of the device, reduce the threshold voltage shift caused thereby, and improve the stability of the device.

[0070] In an embodiment of the invention, the thicknesses of the source electrode 6 and the drain electrode 7 are 20 - 500 nm. When preparing the source electrode 6 and the drain electrode 7, materials such as tungsten W, molybdenum Mo, titanium gold Ti / Au, etc. can be selected, and they can be prepared by radio frequency magnetron sputtering or electron beam evaporation.

[0071] The present invention provides a bipolar SnO TFTs with non - hysteretic behavior and its manufacturing method. Through the stacked design of the gate insulating layer and interface heat treatment, the plasma treatment of the SnO back channel, the stacked design of the device passivation layer, and the overall high - temperature annealing treatment of the device, SnO TFTs with non - hysteretic, high hole mobility, high on - off current ratio, and low sub - threshold swing are finally obtained. It is worth noting that the overall manufacturing process of the device is compatible with BEOL, which greatly improves the competitiveness of SnO TFTs in oxide semiconductors and broadens their application fields and prospects.

[0072] As Figure 1 shown, a method for fabricating BEOL-compatible and hysteresis-free bipolar SnO TFTs includes:

[0073] Step 1: Deposit a metal electrode on Substrate 1 to obtain the bottom gate electrode pattern of the desired thin film transistor and remove excess metal and impurities, resulting in the desired bottom gate electrode 2.

[0074] For example, deposit a metal electrode on Substrate 1 by radio frequency magnetron sputtering, then obtain the bottom gate electrode pattern of the desired thin film transistor through ultraviolet lithography and development, and use wet etching to remove the excess metal and then acetone to remove the photoresist residue, thereby obtaining the desired bottom gate electrode 2.

[0075] Among them, Substrate 1 can be a silicon substrate, a glass substrate, a flexible polyimide PI substrate, etc. The thickness of the bottom gate electrode 2 is 20 - 200 nm. The bottom gate electrode 2 can be prepared from materials such as tungsten W, molybdenum Mo, copper Cu, indium tin oxide ITO, etc.

[0076] Step 2: Grow a first gate insulating layer 3 and a second gate insulating layer 4 on the upper surface of the bottom gate electrode 2 and Substrate 1 by atomic layer deposition.

[0077] For example, grow the first gate insulating layer 3 and the second gate insulating layer 4 by atomic layer deposition.

[0078] In the specific implementation process, control the quality of the first gate insulating layer and the second gate insulating layer by adjusting the film thickness, precursor purge time, and deposition temperature, reduce interface state defects, thereby reducing the threshold voltage swing and hysteresis of subsequent devices, etc.

[0079] When depositing the first gate insulating layer 3 and the second gate insulating layer 4, control the precursor purge time to be 5 - 50 s and the deposition temperature to be 100 - 300 °C; the thicknesses of the first gate insulating layer and the second gate insulating layer are both 2 - 50 nm.

[0080] Among them, the first gate insulating layer 3 is a hafnium oxide thin film with a thickness of 2 - 50 nm; the second gate insulating layer 4 is an aluminum oxide thin film with a thickness of 2 - 50 nm.

[0081] The gate insulating layer is a stacked structure of hafnium oxide and aluminum oxide, and the interface of the dielectric layer is improved by thermal annealing, reducing interface defect states and enhancing the density of the thin film, etc.; the semiconductor channel layer is a SnO thin film treated with fluorine plasma, obtained by growing a SnO thin film by radio frequency magnetron sputtering and immediately annealing it, and then performing fluorine plasma treatment on it after annealing;

[0082] Step 3: Grow an SnO thin film on the upper surface of the second gate insulating layer 4, immediately anneal it after deposition, and then perform plasma fluorination treatment on the thin film to obtain a semiconductor channel layer.

[0083] For example, grow the SnO thin film by radio frequency magnetron sputtering.

[0084] In one or more embodiments, after growing the SnO thin film by radio frequency magnetron sputtering, immediately perform rapid thermal annealing on it. The gas atmosphere during annealing is a mixture of nitrogen and oxygen, control the proportion of oxygen between 10% and 30%, the annealing time is more than 10 minutes, and the annealing temperature is 180 - 250 °C to obtain a high-quality semiconductor thin film.

[0085] When annealing the SnO thin film, it can be carried out in a rapid thermal annealing equipment (RTA) or a tube furnace.

[0086] When performing fluorine plasma treatment on the semiconductor channel layer 5, it can be carried out in a plasma enhanced chemical vapor deposition system (PECVD) or an inductively coupled plasma etching system (ICP).

[0087] As an alternative embodiment, sulfur hexafluoride and argon, or tetrafluoromethane and argon, or trifluoromethane and argon can be used for fluorine plasma treatment. The gas flow rate is between 20 - 200 sccm, the flow rate ratio is controlled between 1:6 and 5:6, the power source power is set between 20 - 200 W, the reaction temperature is controlled between 10 - 60 °C, and the treatment time is controlled between 0 - 10 min.

[0088] Step 4: Deposit metal electrodes at both ends of the upper surface of the semiconductor channel layer 5 to form a source electrode 6 and a drain electrode 7.

[0089] For example, after ultraviolet lithography exposure and developing the electrode pattern, deposit the metal electrode by radio frequency magnetron sputtering and form the source electrode 6 and the drain electrode 7 through lift-off.

[0090] In other embodiments, it is also possible to first deposit the metal electrode by radio frequency magnetron sputtering, then through ultraviolet lithography and developing the pattern, and use wet etching to remove the excess metal, and form the source electrode 6 and the drain electrode 7 after removing the photoresist.

[0091] Among them, the thickness of the source electrode 6 and the drain electrode 7 is 20 - 500 nm.

[0092] When preparing the source electrode 6 and the drain electrode 7, materials such as tungsten W, molybdenum Mo, titanium gold Ti / Au, etc. can be selected and prepared by radio frequency magnetron sputtering or electron beam evaporation.

[0093] Step 5: Deposit a first passivation layer 8, a second passivation layer 9, a third passivation layer 10, and a fourth passivation layer 11 on the upper surfaces of the source electrode 6, the drain electrode 7, and the semiconductor channel layer 5 in sequence to complete the fabrication of SnO TFTs.

[0094] Specifically, use a plasma-enhanced chemical vapor deposition system and an atomic layer deposition system to deposit the first passivation layer 8, the second passivation layer 9, the third passivation layer 10, and the fourth passivation layer 11 in sequence.

[0095] The combined stacked structure of the passivation layers can effectively reduce the adsorption of water and oxygen in the air by the back channel of the device, thereby helping to improve the hysteresis phenomenon and enhance the stability of the device. Among them, the first passivation layer 8 is silicon nitride, the second passivation layer 9 is aluminum oxide, the third passivation layer 10 is hafnium oxide, and the fourth passivation layer 11 is silicon oxide. The thickness of each passivation layer is controlled between 10 and 500 nm.

[0096] Step 6: Perform a high-temperature annealing treatment on the fabricated thin-film transistor to meet the process thermal budget requirements in BEOL. For example, place the sample in an RTA, set the temperature to 350 - 400 °C, and the time to more than 30 min for rapid thermal annealing treatment to meet the process thermal budget requirements in BEOL.

[0097] Table 1 shows the various characteristic parameters of the SnO TFT provided by the present invention.

[0098] Table 1 Various Characteristic Parameters of SnO TFT

[0099] Performance Name Parameter Size Field-Effect Mobility (Hole) <![CDATA[1.5cm 2 V -1 s -1 > Subthreshold Swing <![CDATA[0.18V decade -1 > Threshold Voltage -0.625V On-State Current Density <![CDATA[1.8×10 -8 A um -1 > Off-State Current Density <![CDATA[1.3×10 -12 A um -1 > Switching Current Ratio <![CDATA[1.4×10 4 >

[0100] Figure 3 shows the transfer characteristic diagram of the SnO TFT provided by the embodiment of the present invention during the forward sweep (V G : +3.3 to -3.3 V); Figure 4 shows the transfer characteristic diagram of the SnO TFT provided by the embodiment of the present invention during the reverse sweep (V G : -3.3 to +3.3 V); Figure 5 shows the output characteristic diagram of the SnO TFT provided by the embodiment of the present invention. Figure 6 shows the transfer characteristic diagrams of the SnO active layer with and without fluorine plasma treatment. Figure 6 The structural supplement of the device is as follows: The passivation layer structure of the device is a double-layer structure. The silicon nitride layer in contact with SnO is below, and the silicon oxide layer is above, which is different from the 4-layer passivation layer structure involved in the present invention and is used as a comparative example. In addition, Figure 6 the gate insulating layer of the device is an aluminum oxide structure, which is different from the stacked gate insulating layer structure proposed by the present invention.

[0101] Figure 6It can be seen that after fluorine plasma treatment, the on-state current of the device increases and the off-state current decreases slightly, which leads to a decrease in the subthreshold swing of the device (from 0.54V decade -1 Down to 0.4V decade -1 ). The reduction of the subthreshold swing indicates the reduction of defect states in the SnO active layer, which will be beneficial to the improvement of device hysteresis. This is the first technical improvement of the hysteresis-free bipolar SnO provided by the present invention.

[0102] Figure 7 and Figure 8 It is the transfer characteristic diagram of the device before and after high temperature annealing. Figure 7 The device in Figure 6 The device in which the SnO active layer has been improved by fluorine plasma treatment is used as a comparative example for the next process improvement. Figure 7 The device in the middle has not been annealed at high temperature and shows obvious hysteresis; Figure 8 The hysteresis of the device in the figure is significantly reduced after high temperature annealing, indicating that high temperature annealing can significantly improve the hysteresis phenomenon. This is attributed to the migration and rearrangement of atoms, the repair of chemical bonds, the diffusion and removal of impurities, etc., which may occur in the SnO film during high temperature annealing, reducing the defect state in the film and thus improving the hysteresis of the device. In addition, the subthreshold swing is reduced after high temperature annealing (from 0.4V decade before annealing). -1 Reduced to 0.25V decade after annealing -1 ) can also prove the reduction of defect states. This is the second technical improvement of the hysteresis-free bipolar SnO provided by the present invention.

[0103] Figure 9 The devices in Figure 8 It shows less hysteresis. Figure 9 The device in the figure has a three-layer passivation layer structure. Figure 8 Based on the device, an aluminum oxide intercalation layer is added between the silicon nitride and silicon oxide layers, and the rest of the process steps are the same. The calculation results show that the hysteresis of the three-layer passivation layer device is 0.093V, which is less than Figure 8 The double passivation layer device has a voltage of 0.208 V. This proves that adding aluminum oxide as an intercalation layer can effectively prevent water and oxygen in the air from diffusing into the back channel.

[0104] Figure 10 The devices in Figure 9 It shows less hysteresis. Figure 10 The device in the figure has a 4-layer passivation layer structure. Figure 9 Based on the device, a hafnium oxide intercalation layer is added between the aluminum nitride and silicon oxide layers, and the rest of the process steps are the same. The calculation results show that the hysteresis of the 4-layer passivation layer device is 0.036V, which is less than Figure 80.093V for the device with a three-layer passivation layer. It is proved that the four-layer passivation layer stack structure formed by adding hafnium oxide has a better effect on preventing water and oxygen in the air from diffusing into the back channel. From Figure 8 , Figure 9 , Figure 10 The obtained four-layer passivation layer stack structure is the third technical improvement point of the non-hysteretic bipolar SnO provided by the present invention.

[0105] For Figures 6 to 10 devices, their gate insulating layer is a single aluminum oxide, while the gate insulating layer of the non-hysteretic bipolar SnO provided by the present invention is a stack structure of hafnium oxide and aluminum oxide. From Figure 10 the results of device optimization, the hysteresis phenomenon is already very small but not completely eliminated, especially manifested in the incomplete coincidence of the forward and reverse sweep curves under forward voltage. After replacing the aluminum oxide dielectric layer of the device in Figure 10 with a stack structure of hafnium oxide and aluminum oxide and performing thermal annealing treatment, the hysteresis phenomenon of the device is eliminated, as shown in Figure 2 , thus forming the final structure of the device provided by the present invention. The stack design of the gate insulating layer and the thermal annealing treatment reduce the interface defects between SnO and the dielectric layer and improve the hysteresis phenomenon, which is the fourth technical improvement point of the non-hysteretic bipolar SnO provided by the present invention.

[0106] The preparation method of the bipolar SnO TFTs of the present invention combines a variety of processing techniques, including: stack design of the gate insulating layer and interface heat treatment optimization, passivation treatment of the SnO back channel, stack design of the passivation layer, and high-temperature post-annealing treatment, and finally obtains non-hysteretic bipolar SnO TFTs. In addition, the SnO TFTs prepared by the present invention have high hole mobility, low subthreshold swing, high on / off current ratio, and the overall process flow is compatible with BEOL, greatly improving the competitiveness of SnO TFTs in oxide semiconductors and broadening their application fields and prospects.

[0107] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A BEOL-compatible and hysteresis-free bipolar SnO TFTs, characterized in that: include: Substrate, bottom gate electrode, stacked gate insulation structure, semiconductor channel layer, source electrode, drain electrode and stacked passivation structure; The bottom gate electrode is arranged on the upper surface of the substrate; The stacked gate insulation structure comprises a first gate insulation layer and a second gate insulation layer arranged in sequence from bottom to top; the first gate insulation layer is arranged on the upper surface of the bottom gate electrode and the substrate; The semiconductor channel layer is disposed on the upper surface of the second gate insulating layer; The source electrode and the drain electrode are respectively arranged at two ends of the upper surface of the semiconductor channel layer; The stacked passivation structure comprises a first passivation layer, a second passivation layer, a third passivation layer and a fourth passivation layer arranged in sequence from bottom to top; the first passivation layer is arranged on the upper surfaces of the source electrode, the drain electrode and the semiconductor channel layer.

2. The BEOL-compatible and hysteresis-free bipolar SnO TFTs according to claim 1, characterized in that: The first gate insulating layer is a hafnium oxide film, and the second gate insulating layer is an aluminum oxide film.

3. The BEOL-compatible and hysteresis-free bipolar SnO TFTs according to claim 1, characterized in that: The thickness of the first gate insulating layer and the second gate insulating layer are both 2-50 nm.

4. The BEOL-compatible and hysteresis-free bipolar SnO TFTs according to claim 1, characterized in that: The first passivation layer is silicon nitride, the second passivation layer is aluminum oxide, the third passivation layer is hafnium oxide, and the fourth passivation layer is silicon oxide.

5. The BEOL-compatible and hysteresis-free bipolar SnO TFTs according to claim 1, characterized in that: The thickness of the first passivation layer, the second passivation layer, the third passivation layer and the fourth passivation layer are all 10-500 nm.

6. The BEOL-compatible and hysteresis-free bipolar SnO TFTs according to claim 1, wherein: The thickness of the bottom gate electrode is 20-200 nm.

7. The BEOL-compatible and hysteresis-free bipolar SnO TFTs according to claim 1, wherein: The thickness of the source electrode and the drain electrode is 20-500 nm.

8. A method for preparing BEOL-compatible and hysteresis-free bipolar SnO TFTs according to any one of claims 1 to 7, characterized in that: include: Depositing a metal electrode on the substrate to obtain a bottom gate electrode pattern of a desired thin film transistor and removing excess metal and impurities to obtain a desired bottom gate electrode; On the bottom gate electrode and the upper surface of the substrate, a first gate insulating layer and a second gate insulating layer are grown by an atomic layer deposition method; Growing a SnO film on the upper surface of the second gate insulating layer, annealing it immediately after deposition, and then performing plasma fluorination treatment on the film after annealing to obtain a semiconductor channel layer; Depositing metal electrodes at both ends of the upper surface of the semiconductor channel layer to form a source electrode and a drain electrode; Depositing a first passivation layer, a second passivation layer, a third passivation layer and a fourth passivation layer on the upper surfaces of the source electrode, the drain electrode and the semiconductor channel layer in sequence to prepare TFTs; The fabricated TFTs are subjected to high temperature annealing to meet the process thermal budget requirements in BEOL.

9. The preparation method according to claim 8, characterized in that: The quality of the first gate insulating layer and the second gate insulating layer is controlled by regulating the film thickness, precursor purge time and deposition temperature; when depositing the first gate insulating layer and the second gate insulating layer, the precursor purge time is 5 to 50 seconds and the deposition temperature is 100 to 300° C.; the thickness of the first gate insulating layer and the second gate insulating layer are both 2 to 50 nm.

10. The preparation method according to claim 8, characterized in that: A plasma chemical vapor deposition system and an atomic layer deposition system are used to sequentially deposit a first passivation layer, a second passivation layer, a third passivation layer and a fourth passivation layer.

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