Formation method of semiconductor device

Abstract

The invention provides a method for forming a semiconductor device, which comprises the following steps: performing multiple times of film forming treatment to form a first stress layer on the surface of a source-drain doped region, the first stress layer comprising a plurality of sub-stress layers, and the sub-stress layers have tensile stress; the film forming treatment comprises the following steps: forming a sub stress layer on the source-drain doped region; and introducing passivation gas into the sub stress layer, wherein the passivation gas is used for increasing the bond length of at least part of chemical bonds in the sub stress layer. The first stress layer is formed through multiple times of film forming treatment, the coverage can be improved, and cracking can be prevented. Meanwhile, the tensile stress in the sub-stress layers can be increased by introducing passivation gas into the sub-stress layers, so that the migration speed of communication carriers is increased, and the performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device manufacturing, and particularly to a method for forming a semiconductor device. Background Art

[0002] The MOS (metal-oxide-semiconductor) transistor is one of the most important components in modern integrated circuits. The basic structure of the MOS transistor includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, and the gate structure includes: a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer; source / drain doping regions in the semiconductor substrate on both sides of the gate structure.

[0003] The working principle of the MOS transistor is: applying a voltage to the gate structure to generate a switching signal by adjusting the current in the channel at the bottom of the gate structure.

[0004] However, in the prior art, the performance of semiconductor devices composed of MOS transistors still needs to be improved. Summary of the Invention

[0005] To solve the above problems, the present invention proposes a method for forming a semiconductor device, which can improve the performance of the semiconductor device, such as enhancing the electron mobility of the transistor channel.

[0006] The technical solution of the present invention provides a method for forming a semiconductor device, which is characterized by including: providing a substrate, the substrate includes a device region, a gate structure is provided on the device region, and source / drain doping regions are respectively provided in the substrate of the device region on both sides of the gate structure; performing multiple film-forming processes to form a first stress layer on the surface of the source / drain doping regions, the first stress layer includes multiple sub-stress layers, and tensile stress exists in the sub-stress layers; the film-forming process includes: forming a sub-stress layer on the source / drain doping regions; introducing a passivation gas into the sub-stress layer, and the passivation gas is used to increase the bond length of at least part of the chemical bonds in the sub-stress layer.

[0007] Optionally, the thickness of the first stress layer is 30 nm to 50 nm; the thickness of the sub-stress layer is 40 Å to 60 Å; the number of times of the film-forming process is 5 to 10 times.

[0008] Optionally, the material of the first stress layer is one or more combinations of silicon nitride or silicon oxynitride.

[0009] Optionally, the process for forming the sub-stress layer includes: chemical vapor deposition, physical vapor deposition or atomic vapor deposition.

[0010] Optionally, the reactive gas for forming the sub-stress layer includes SIH4 and NH3; the process parameters for forming the sub-stress layer include: the flow rate of SIH4 is 45 sccm to 75 sccm; the flow rate of NH3 is 550 sccm to 750 sccm, the pressure is 4.5 torr to 7.5 torr; the temperature is 300 °C to 500 °C; the RF power is 240 W to 360 W.

[0011] Optionally, the passivation gas includes: nitrogen.

[0012] Optionally, the process parameters for introducing the passivation gas into the sub-stress layer include: the flow rate of the passivation gas is 5500 sccm to 8500 sccm; the RF power is 240 W to 360 W.

[0013] Optionally, the number of device regions is one or more; at least one first device region is included in the device regions, and the source-drain doped regions of the first device region are doped with N-type ions.

[0014] Optionally, a second device region is further included in the multiple device regions, and the source-drain doped regions of the second device region are doped with P-type ions.

[0015] Optionally, the material of the source-drain doped regions of the second device region is silicon germanium or germanium; the material of the substrate is polysilicon or single crystal silicon; and / or, the method further includes: removing the first stress layer of the second device region; after removing the first stress layer of the second device region, forming a second stress layer on the second device region, and the second stress layer has compressive stress.

[0016] Optionally, it further includes: removing the second stress layer of the first device region.

[0017] Optionally, it further includes: forming an interlayer dielectric layer on the first stress layer, and the material of the interlayer dielectric layer is different from that of the first stress layer; forming a through hole in the interlayer dielectric layer; removing a part of the first stress layer at the bottom of the through hole, forming a contact hole in the first stress layer, and retaining at least part of the first stress layer; forming plugs in the contact hole and the through hole.

[0018] Optionally, the step of forming a through hole in the interlayer dielectric layer includes: forming a sacrificial layer on the interlayer dielectric layer, and the sacrificial layer exposes part of the interlayer dielectric layer; etching the interlayer dielectric layer with the sacrificial layer as a mask and the first stress layer as a stop layer to remove part of the interlayer dielectric layer and form the through hole.

[0019] Optionally, the film forming process is also used to form the sub-stress layer on the gate structure.

[0020] The technical solution of the present application has the following beneficial effects:

[0021] In the method for forming a semiconductor device provided by the technical solution of the present application, the first stress layer is formed through multiple film-forming processes. Then, the thickness of the sub-stress layer formed by each film-forming process is relatively thin, with good coverage and not prone to cracking. At the same time, by introducing a passivation gas into the sub-stress layer, atoms of the passivation gas can replace the atoms of the chemical bonds with shorter bond lengths in the sub-stress layer, thereby increasing the tensile stress in the sub-stress layer, further improving the migration speed of communication carriers, and improving device performance.

[0022] Furthermore, removing the first stress layer in the second device region can reduce the influence of the first stress layer on the carrier migration rate in the channel of the second device region, and thus improve the performance of the PMOS device formed in the second device region. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention will be specifically described below with reference to the drawings and in combination with embodiments. The advantages and implementation manners of the present invention will become more obvious. Among them, the content shown in the drawings is only used to explain the present invention and does not constitute any limitation to the present invention in any sense. The drawings are only schematic and are not drawn strictly to scale. In the drawings:

[0024] Figures 1 to 2 is a schematic structural diagram of each step of the method for forming a semiconductor device provided by the prior art;

[0025] Figures 3 to 9 is a schematic structural diagram of each step of an embodiment of the method for forming a semiconductor device provided by the present invention;

[0026] Figures 10 to 13 is a schematic structural diagram of each step of another embodiment of the method for forming a semiconductor device provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] Figure 1 and Figure 2 is a schematic structural diagram of a method for forming a semiconductor device.

[0028] The forming method includes:

[0029] Please refer to Figure 1 , a semiconductor substrate 100 is provided, and a gate structure 101 is disposed on the semiconductor substrate 100, and source-drain doping regions 102 are disposed in the semiconductor substrate 100 on both sides of the gate structure 101;

[0030] Please refer to Figure 2 , a stop layer 110 is formed on the gate structure 101 and the source-drain doping regions 102; an interlayer dielectric layer 120 is formed on the stop layer 110;

[0031] Continue to refer toFigure 2 , a contact hole is formed in the interlayer dielectric layer 120, and the bottom of the contact hole exposes the source / drain doping region 102; a plug 121 is formed in the contact hole.

[0032] In the prior art, before forming the interlayer dielectric layer, the stop layer 110 is formed on the gate structure 101 and the source / drain doping region 102. During the formation process of the semiconductor device, only the stop layer 110 at the bottom of the contact hole is removed, and part of the stop layer 110 still remains in the device. The stop layer 110 has tensile stress, which can increase the migration rate of electrons in the channel and improve the corresponding speed of the semiconductor device.

[0033] In the prior art, a reaction gas is introduced into the substrate once to form a stop layer 110 with a thickness of 30 nm to 50 nm. The stop layer 110 formed in the corner region at the bottom of the gate structure has poor coverage and is prone to cracking, and the stress in the stop layer is small, so the improvement effect on the electron mobility is limited.

[0034] To solve the above technical problems, the technical solution of the present application provides a method for forming a semiconductor device, including: performing multiple film-forming processes to form a first stress layer on the surface of the source / drain doping region, the first stress layer includes multiple sub-stress layers, and the sub-stress layers have tensile stress; the film-forming process includes: forming a sub-stress layer on the source / drain doping region; introducing a passivation gas into the sub-stress layer, and the passivation gas is used to increase the bond length of at least part of the chemical bonds in the sub-stress layer. By forming the first stress layer through multiple film-forming processes, the coverage can be improved and cracking can be prevented. At the same time, by introducing the passivation gas into the sub-stress layer, the tensile stress in the sub-stress layer can be increased, thereby improving the migration speed of the carriers in the channel and improving the device performance.

[0035] Figure 3 is a schematic structural diagram of the first embodiment of the method for forming a semiconductor device of the present application.

[0036] Reference Figure 3 , to solve the problems of the prior art, the present application provides a method for forming a semiconductor device, including:

[0037] SP1, providing a substrate, the substrate includes a device region, a gate structure is disposed on the device region, and source / drain doping regions are respectively disposed in the substrate of the device region on both sides of the gate structure;

[0038] SP2, performing multiple film-forming processes to form a first stress layer on the source / drain doping region, the first stress layer includes multiple sub-stress layers, and the sub-stress layers have tensile stress; the film-forming process includes: forming a sub-stress layer on the source / drain doping region; introducing a passivation gas into the sub-stress layer, and the passivation gas is used to increase the bond length of at least part of the chemical bonds in the sub-stress layer.

[0039] Figures 4 to 9 It is a structural schematic diagram of each step of an embodiment of a method for forming a semiconductor device of the present application.

[0040] Refer to Figure 4 , execute SP1, provide a substrate 200, the substrate 200 includes a device region, a gate structure is provided on the device region, and source-drain doping regions 202 are respectively provided in the substrate 200 of the device region on both sides of the gate structure.

[0041] In this embodiment, the substrate 200 is polysilicon or single crystal silicon. In other embodiments, the material of the substrate 200 may also be silicon carbide.

[0042] In this embodiment, the number of the device regions is one or more; at least one first device region I is provided in the device region, and the material of the source-drain doping region 202 of the first device region I is an N-type semiconductor. A second device region II is also provided in the multiple device regions, and the source-drain doping region 202 of the second device region II is doped with P-type ions.

[0043] In this embodiment, the source-drain doping region 202 of the first device region I is doped with N-type ions, and the material of the first device region I is polysilicon or single crystal silicon. The material of the source-drain doping region 202 of the second device region II is polysilicon or single crystal silicon. In other embodiments, the material of the source-drain doping region 202 of the second device region II is silicon germanium or germanium.

[0044] In this embodiment, the gate structure includes: a gate 201 and a mask layer 204 located on the gate 201; by using the mask layer 204 as a mask, source-drain ions are doped into the substrate 200 to form the source-drain doping region 202. The doping ions of the first device region I are N-type ions; the doping ions of the second device region II are P-type ions.

[0045] In other embodiments, the step of forming the source-drain doping region 202 includes: forming grooves in the substrate 200 on both sides of the gate structure; forming the source-drain doping region 202 in the grooves. The material of the source-drain doping region 202 is different from that of the substrate 200. Specifically, the material of the source-drain doping region 202 of the first device region I is single crystal silicon or silicon carbide; the material of the source-drain doping region 202 of the second device region II is silicon germanium.

[0046] The material of the substrate 200 is polysilicon or single-crystalline silicon. The source-drain doping region 202 of the first device region I is made of silicon carbide. The lattice mismatch between the silicon carbide and the substrate 200 can form tensile stress in the channel of the first device region I, increasing the migration rate of the carriers in the channel of the first device region I. The source-drain doping region 202 of the second device region II is made of silicon-germanium, which can form compressive stress in the channel of the second device region II, increasing the migration rate of the carriers in the channel of the second device region II.

[0047] In this embodiment, an isolation structure 203 is further provided between the device regions. The isolation structure 203 can isolate different device regions, thereby avoiding crosstalk between the device regions.

[0048] Combined with reference Figures 5 to 7 , perform step SP2, perform multiple film-forming processes to form a first stress layer 210 on the source-drain doping region 202. The first stress layer 210 includes multiple sub-stress layers 211, and the sub-stress layer 211 has tensile stress; the film-forming process includes: forming a sub-stress layer 211 on the source-drain doping region 202; introducing a passivation gas into the sub-stress layer 211, and the passivation gas is used to increase the bond length of the chemical bonds in the sub-stress layer 211.

[0049] In the technical solution of the present application, the first stress layer 210 is formed by multiple film-forming processes. Then, the thickness of each sub-stress layer 211 formed by each film-forming process is relatively thin, with good coverage and not easy to crack. At the same time, by introducing a passivation gas into the sub-stress layer 211, the bond length of the chemical bond formed between the passivation gas and the sub-stress layer 211 can be increased, increasing the tensile stress in the sub-stress layer 211, thereby improving the migration speed of the carriers in the channel and improving the device performance. Specifically, in this embodiment, the sub-stress layer 211 is silicon nitride. However, during the reaction of SiH4 and NH3, the formed silicon nitride inevitably retains Si-H bonds. By introducing a passivation gas into the sub-stress layer 211, N atoms can replace the H atoms in the sub-stress layer 211, thereby forming Si-N bonds with longer bond lengths and increasing the tensile stress in the sub-stress layer 211.

[0050] Next, combined with Figures 5 to 7 The steps of the film-forming process will be described in detail.

[0051] Please refer to Figure 5 , form a sub-stress layer 211 on the source-drain doping region 202.

[0052] The sub-stress has high coverage, and the sub-stress layer 211 has tensile stress, which can improve the migration rate of the carriers in the channel of the first device region I.

[0053] In this embodiment, the sub-stress layer 211 also covers the gate structure.

[0054] The material of the sub-stress layer 211 is one or a combination of silicon nitride and silicon oxynitride. The material of the sub-stress layer 211 is different from the material of the gate 201 and different from the material of the source / drain doping region 202. Specifically, in this embodiment, the material of the sub-stress layer 211 is silicon nitride.

[0055] If the thickness of the sub-stress layer 211 is too small, the number of film-forming processes required to form the first stress layer 210 is large, which is likely to reduce the throughput of the semiconductor device; if the thickness of the sub-stress layer 211 is too large, the coverage of the sub-stress layer 211 formed is poor and it is likely to crack. Specifically, in this embodiment, the thickness of the sub-stress layer 211 is 40 Å to 60 Å.

[0056] The operation of forming the sub-stress layer 211 includes: chemical vapor deposition, physical vapor deposition or atomic vapor deposition.

[0057] The process parameters for forming the sub-stress layer 211 include: the reaction gas includes SIH 4 and NH 3 ; the flow rate of SIH 4 is 45 sccm to 75 sccm; the flow rate of NH 3 is 550 sccm to 750 sccm, the pressure is 4.5 torr to 7.5 torr; the temperature is 300 °C to 500 °C; the radio frequency power is 240 W to 360 W.

[0058] In this embodiment, the sub-stress layer 211 is formed on the entire substrate 200, including the first device region I and the second device region II. The sub-stress layer 211 is formed on the source / drain doping region 202, the gate structure and the isolation structure 203.

[0059] Please refer to Figure 6 , and a passivation gas is introduced into the sub-stress layer 211. The passivation gas is used to increase the bond length of at least some chemical bonds in the sub-stress layer 211.

[0060] The passivation gas can cause the atoms of the passivation gas to replace the atoms of the chemical bonds with shorter bond lengths in the sub-stress layer, thereby increasing the tensile stress in the sub-stress layer, and further improving the migration speed of the communication carriers and improving the device performance.

[0061] The passivation gas includes: nitrogen.

[0062] In this embodiment, the process parameters for introducing a passivation gas into the sub-stress layer 211 include: the flow rate of the passivation gas is 5500 sccm to 8500 sccm; the RF power is 240 W to 360 W.

[0063] Please refer to Figure 7 , and repeat the film-forming process multiple times to form multiple sub-stress layers 211 on the source-drain doped region 202 in sequence, thereby forming the first stress layer 210.

[0064] If the number of film-forming processes is too large, it is easy to reduce the throughput of the semiconductor device; if the number of sub-stress layers 211 is too small, the formed first stress layer 210 is relatively thin, which is not conducive to increasing the tensile stress in the first stress layer 210. Specifically, in this embodiment, the number of film-forming processes is 5 to 10 times, specifically 6 or 7 times.

[0065] Refer to Figure 8 , the forming method further includes: forming an interlayer dielectric layer 220 on the first stress layer 210, and the material of the interlayer dielectric layer 220 is different from that of the first stress layer 210.

[0066] In this embodiment, since the material of the interlayer dielectric layer 220 is different from that of the first stress layer 210, the first stress layer 210 can also be used as an etch stop layer for forming a through hole in the subsequent etching of the interlayer dielectric layer 220.

[0067] In this embodiment, the material of the first stress layer 210 is silicon nitride; the material of the interlayer dielectric is silicon oxide.

[0068] Please refer to Figure 9 , form a through hole in the interlayer dielectric layer 220; remove a part of the first stress layer 210 at the bottom of the through hole to form a contact hole in the first stress layer 210; form a plug 221 in the contact hole and the through hole.

[0069] In this embodiment, the step of forming a through hole in the interlayer dielectric layer 220 includes: forming a sacrificial layer on the interlayer dielectric layer 220, and the sacrificial layer exposes a part of the interlayer dielectric layer 220; using the sacrificial layer as a mask and using the first stress layer 210 as a stop layer to etch the interlayer dielectric layer 220 to remove a part of the interlayer dielectric layer 220, thereby forming the through hole.

[0070] Removing a part of the first stress layer 210 at the bottom of the through hole to form a contact hole in the first stress layer 210 includes: using the interlayer dielectric layer 220 as a mask to etch the first stress layer 210 until the source-drain doped region 202 is exposed.

[0071] In this embodiment, the plug 221 is only formed on a part of the source / drain doping region 202, and the via hole and the contact hole are also only formed on a part of the source / drain doping region 202; in other embodiments, the via hole and the contact hole may also be formed on the gate 201.

[0072] It should be noted that since the plug 221 is only formed on a part of the source / drain doping region 202, only a part of the first stress layer 210 is removed, and a part of the first stress layer 210 remains on the source / drain doping region 202 and the gate structure. The remaining first stress layer 210 can continue to provide a tensile stress for the channel and improve the carrier migration rate.

[0073] Figures 10 to 13 It is a schematic structural diagram of each step of another embodiment of the method for forming a semiconductor device of the present invention.

[0074] This embodiment and Figures 3 to 9 The same parts of the illustrated embodiment will not be elaborated here. The differences include:

[0075] After forming the first stress layer 210 and before forming the interlayer dielectric layer 220, it further includes: removing the first stress layer 210 in the second device region II; after removing the first stress layer 210 in the second device region II, a second stress layer 230 is formed on the second device region II. The following will be described in detail with reference to Figures 10 to 12 for details.

[0076] Refer to Figure 10 to remove the first stress layer 210 in the second device region II.

[0077] Since the second device region II is used to form a P-type transistor, applying a tensile stress to the channel in the second device region II will reduce the carrier migration rate in the channel of the second device region II. Removing the first stress layer 210 in the second device region II can prevent the influence of the tensile stress of the first stress layer 210 on the P-type transistor.

[0078] The process of removing the first stress layer 210 in the second device region II includes: one or both of dry etching and wet etching.

[0079] Refer to Figure 11 to form a second stress layer 230 on the second device region II after removing the first stress layer 210 in the second device region II.

[0080] The second stress layer 230 is made of a material different from that of the intermediate dielectric layer; the second stress layer 230 can be used as an etching stop layer for subsequently forming a via hole in the second device region II.

[0081] The material of the second stress layer 230 is one or a combination of silicon nitride and silicon oxynitride.

[0082] The second stress layer 230 can be formed by a single film forming process. Specifically, the process of forming the second stress layer 230 includes: plasma enhanced chemical vapor deposition technology with a dual-frequency radio frequency power supply.

[0083] The high-frequency radio frequency power supply is used to dissociate the reaction gas to form a reaction particle source, while the low-frequency power supply is used to give the charged groups a greater mean free path, which can usually produce a better bombardment effect, thereby making the thin film denser and forming a larger compressive stress. The process parameters for forming the first stress layer 210 include: the reaction gas includes SIH 4 and NH 3 .

[0084] The reaction gas also includes: one or a combination of hydrogen and heavy particles, and the heavy particles include argon or nitrogen.

[0085] Reference Figure 12 , remove the second stress layer 230 in the first device region I.

[0086] By removing the second stress layer 230 in the first device region I, the influence of the compressive stress in the second stress layer 230 on the channel carrier migration rate in the first device region I can be reduced, and the performance of the semiconductor device can be improved.

[0087] The process of removing the second stress layer 230 in the first device region I includes: one or a combination of wet etching and dry etching.

[0088] Reference Figure 13 , the method further includes: after forming a through hole in the intermediate dielectric layer in the second device region II, removing the second stress layer 230 at the bottom of the through hole.

[0089] In this embodiment, in the step of forming the through hole in the intermediate dielectric layer in the second device region II, the second stress layer 230 is used as an etching stop layer. After forming the through hole in the intermediate dielectric layer, remove the second stress layer 230 at the bottom of the through hole.

[0090] In this embodiment, the second stress layer 230 has the same material as the first stress layer 210. Removing the second stress layer 230 at the bottom of the through hole and the first stress layer 210 can be completed in the same process to simplify the process flow.

[0091] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for forming a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising a device region, the device region having a gate structure, and the device region substrate on both sides of the gate structure respectively having source and drain doping regions; Performing multiple film forming processes to form a first stress layer on the source-drain doped region, wherein the first stress layer includes multiple sub-stress layers, and the sub-stress layers have tensile stress; The film forming process comprises: forming a sub-stress layer on the source and drain doping regions; A passivation gas is introduced into the sub-stress layer, and the passivation gas is used to increase the bond length of at least part of the chemical bonds in the sub-stress layer.

2. The method for forming a semiconductor device according to claim 1, wherein: The thickness of the first stress layer is 30 nanometers to 50 nanometers; the thickness of the sub-stress layer is 40 angstroms to 60 angstroms; and the number of times of the film forming process is 5 to 10 times.

3. The method for forming a semiconductor device according to claim 1, wherein: The material of the first stress layer is one or more of silicon nitride and silicon oxynitride.

4. The method for forming a semiconductor device according to claim 1 or 3, characterized in that: The process of forming the sub-stress layer includes: chemical vapor deposition, physical vapor deposition or atomic vapor deposition.

5. The method for forming a semiconductor device according to claim 4, wherein: The reaction gas for forming the sub-stress layer includes SIH4 and NH3; the process parameters for forming the sub-stress layer include: The flow rate of SIH4 is 45 sccm to 75 sccm; the flow rate of NH3 is 550 sccm to 750 sccm, the pressure is 4.5 torr to 7.5 torr; the temperature is 300°C to 500°C; and the RF power is 240W to 360W.

6. The method for forming a semiconductor device according to claim 1, wherein: The passivation gas includes nitrogen.

7. The method for forming a semiconductor device according to claim 1, wherein: The process parameters for introducing the passivation gas into the sub-stress layer include: the flow rate of the passivation gas is 5500sccm to 8500sccm; and the radio frequency power is 240W to 360W.

8. The method for forming a semiconductor device according to claim 1, wherein: The number of the device regions is one or more; the device regions include at least one first device region, and the source and drain doping regions of the first device region are doped with N-type ions.

9. The method for forming a semiconductor device according to claim 8, wherein: The plurality of device regions further include a second device region, wherein source and drain doping regions of the second device region are doped with P-type ions.

10. The method for forming a semiconductor device according to claim 9, wherein: The material of the source and drain doping regions of the second device region is silicon germanium or germanium; the material of the substrate is polycrystalline silicon or single crystal silicon; and / or, The method further comprises: removing the first stress layer of the second device region; After removing the first stress layer in the second device region, a second stress layer is formed on the second device region, wherein the second stress layer has compressive stress.

11. The method for forming a semiconductor device according to any one of claim 10, wherein: Also includes: The second stress layer in the first device region is removed.

12. The method for forming a semiconductor device according to any one of claims 1 to 11, characterized in that: Also includes: forming an interlayer dielectric layer on the first stress layer, wherein the material of the interlayer dielectric layer is different from the material of the first stress layer; forming a through hole in the interlayer dielectric layer; A portion of the first stress layer at the bottom of the through hole is removed, a contact hole is formed in the first stress layer, and at least a portion of the first stress layer is retained; and a plug is formed in the contact hole and the through hole.

13. The method for forming a semiconductor device according to claim 12, wherein: The step of forming a through hole in the interlayer dielectric layer includes: forming a sacrificial layer on the interlayer dielectric layer, wherein the sacrificial layer exposes a portion of the interlayer dielectric layer; etching the interlayer dielectric layer using the sacrificial layer as a mask and the first stress layer as a stop layer to remove a portion of the interlayer dielectric layer to form the through hole.

14. The method for forming a semiconductor device according to claim 1, wherein: The film forming process is also used to form the sub-stress layer on the gate structure.

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