Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, the structure comprising: a substrate, the substrate comprising a first region and a second region adjacent to the first region; a fin standing on top of the substrate of the first region and the second region; a first gate structure on one side of the fin of the first region and covering sidewalls of the fin; a second gate structure on the other side of the fin of the first region and covering sidewalls of the fin, a top of the first gate structure being flush with a top of the second gate structure; and a third gate structure on top of the substrate of the second region and spanning part of the top and part of the sidewalls of the fin, a top of the third gate structure being flush with the tops of the first gate structure and the second gate structure. By controlling the voltage values of the first gate structure and the second gate structure to be different, the current value of the conductive channel in the first region is made different, and the adjustable range of the current value of the conductive channel is expanded.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] As semiconductor process technology advances, semiconductor process nodes continue to shrink, following Moore's Law. To adapt to this shrinking process node, the channel length of MOSFETs must be continuously shortened. However, as the channel length decreases, the distance between the source and drain also shortens, resulting in poorer gate control over the channel. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, to better adapt to the requirement of proportionally shrinking device dimensions, non-planar MOS transistors have emerged, such as gate-all-around (GAA) transistors or FinFETs. In FinFETs, the gate can control the ultra-thin body (fin) from at least both sides, providing stronger gate control over the channel compared to planar MOSFET devices, and effectively suppressing short-channel effects; moreover, FinFETs have better compatibility with existing integrated circuit manufacturing compared to other devices. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to further improve the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, the substrate including a first region and an adjacent second region; a fin protruding from the top of the substrate in the first and second regions; a first gate structure located on one side of the fin in the first region and covering the sidewall of the fin; a second gate structure located on the other side of the fin in the first region and covering the sidewall of the fin, the top of the first gate structure being flush with the top of the second gate structure; and a third gate structure located on the top of the substrate in the second region and spanning a portion of the top and a portion of the sidewall of the fin, the top of the third gate structure being flush with the tops of the first and second gate structures.

[0006] Optionally, the number of fins located in the first region may be one or more; when the number of fins in the first region is multiple, adjacent fins share a first gate structure; or, adjacent fins share a second gate structure, or, adjacent fins share a first gate structure and adjacent fins share a second gate structure.

[0007] Optionally, the semiconductor structure further includes: a hard mask layer located on top of the fin of the first region; the top of the hard mask layer is flush with the top of the first gate structure, the second gate structure, and the third gate structure.

[0008] Optionally, the material of the hard mask layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0009] Optionally, the thickness of the hard mask layer can be from 1 nanometer to 20 nanometers.

[0010] Optionally, the first gate structure includes a first work function layer having a first thickness, and the second gate structure includes a second work function layer having a second thickness.

[0011] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and an adjacent second region, wherein fins protrude from the top of the substrate in the first and second regions; in the first region, forming a first gate structure covering the sidewall of the fin on the top of the substrate on one side of the fin, and forming a second gate structure covering the sidewall of the fin on the top of the substrate on the other side of the fin, wherein the top of the first gate structure is flush with the top of the second gate structure; and in the second region, forming a third gate structure spanning the top of a portion of the fin and a portion of the sidewall on the top of the substrate, wherein the top of the third gate structure is flush with the top of the first and second gate structures.

[0012] Optionally, in the step of providing the substrate, the number of fins located in the first region is one or more; when the number of fins in the first region is multiple, in the step of forming the first gate structure and the second gate structure, adjacent fins share the same first gate structure; or, adjacent fins share the same second gate structure; or, adjacent fins share the same first gate structure and adjacent fins share the same second gate structure.

[0013] Optionally, in the step of providing the substrate, a hard mask layer is also formed on the top of the fin; before forming the first gate structure, the second gate structure and the third gate structure, the step further includes: removing the hard mask layer of the second region; in the step of forming the first gate structure and the second gate structure, the top of the hard mask layer of the first region is used as the stop position.

[0014] Optionally, the material of the hard mask layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0015] Optionally, the thickness of the hard mask layer can be from 1 nanometer to 20 nanometers.

[0016] Optionally, the step of removing the hard mask layer of the second region includes: forming a mask layer covering the fin on top of the substrate of the first region, with the mask layer exposing the hard mask layer of the second region; using the mask layer as a mask, performing patterning processing on the hard mask layer of the second region, and removing the hard mask layer of the second region; and removing the mask layer.

[0017] Optionally, the process for removing the hard mask layer in the second region includes dry etching.

[0018] Optionally, the first gate structure and the second gate structure in the first region are formed in the same step as the third gate structure in the second region.

[0019] Optionally, the steps of forming the first gate structure, the second gate structure, and the third gate structure include: forming a dummy gate structure spanning the fin on top of the substrate in the first and second regions; forming an interlayer dielectric layer on the substrate exposed by the dummy gate structure; removing the dummy gate structure and forming a first gate opening in the interlayer dielectric layer; forming a first gate material layer in the first gate opening; removing the first gate material layer on one side of the fin in the first region and forming a second gate opening in the remaining first gate material layer; forming a second gate material layer in the second gate opening; using the top of the fin as a stop position, planarizing the first gate material layer and the second gate material layer above the top of the fin, using the remaining second gate material layer in the first region as the first gate structure, the remaining first gate material layer in the first region as the second gate structure, and the remaining first gate material layer in the second region as the third gate structure.

[0020] Optionally, the process for removing the first gate material layer between adjacent fins in the first region includes a dry etching process.

[0021] Optionally, in the step of forming the first gate structure and the second gate structure, the first gate structure includes a first work function layer having a first thickness, and the second gate structure includes a second work function layer having a second thickness.

[0022] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0023] This invention provides a method for forming a semiconductor structure. In a first region, a first gate structure covering the sidewall of the fin is formed on the top of a substrate on one side of the fin, and a second gate structure covering the sidewall of the fin is formed on the top of a substrate on the other side of the fin. The tops of the first gate structure and the second gate structure are flush. In a second region, a third gate structure spanning the top of a portion of the fin and a portion of its sidewall is formed on the top of the substrate. The top of the third gate structure is flush with the tops of the first and second gate structures. That is, a first gate structure is formed on one side of the fin in the first region, and a second gate structure is formed on the other side of the fin. In other words, a dual-gate structure is formed in the first region to control conductivity. In the first region, by controlling the voltage values ​​of the first gate structure and the second gate structure to be different, the current values ​​of conductivity in the first region are different, thereby further expanding the adjustable range of the conductive channel current value in the first region, and thus improving the performance of the semiconductor structure. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the semiconductor structure corresponding to the present invention.

[0025] Figures 2 to 7 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0026] Currently, the gate structure surrounding the conductive channel is a single-gate structure. After applying a working voltage to the single-gate structure, the threshold turn-on voltage of the conductive channel is consistent, which means that the current value through the conductive channel is the same. This results in the adjustable range of the current value of the conductive channel in the semiconductor structure being too small, thus affecting the performance of the semiconductor structure.

[0027] To address the technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and an adjacent second region, wherein fins protrude from the top of the substrate in the first and second regions; in the first region, forming a first gate structure covering the sidewall of the fin on the top of the substrate on one side of the fin, and forming a second gate structure covering the sidewall of the fin on the top of the substrate on the other side of the fin, wherein the top of the first gate structure is flush with the top of the second gate structure; and in the second region, forming a third gate structure spanning the top of a portion of the fin and a portion of the sidewall on the top of the substrate, wherein the top of the third gate structure is flush with the top of the first and second gate structures.

[0028] This invention provides a method for forming a semiconductor structure. In a first region, a first gate structure covering the sidewall of the fin is formed on the top of a substrate on one side of the fin, and a second gate structure covering the sidewall of the fin is formed on the top of a substrate on the other side of the fin. The tops of the first gate structure and the second gate structure are flush. In a second region, a third gate structure spanning the top of a portion of the fin and a portion of its sidewall is formed on the top of the substrate. The top of the third gate structure is flush with the tops of the first and second gate structures. That is, a first gate structure is formed on one side of the fin in the first region, and a second gate structure is formed on the other side of the fin. In other words, a dual-gate structure is formed in the first region to control conductivity. In the first region, by controlling the voltage values ​​of the first gate structure and the second gate structure to be different, the current values ​​of conductivity in the first region are different, thereby further expanding the adjustable range of the conductive channel current value in the first region, and thus improving the performance of the semiconductor structure.

[0029] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] Figure 1 This is a schematic diagram of the semiconductor structure corresponding to the present invention.

[0031] The semiconductor structure includes: a substrate 200, which includes a first region 200A and an adjacent second region 200B; a fin 201, which protrudes from the top of the substrate 200 in the first region 200A and the second region 200B; a first gate structure 230, which is located on one side of the fin 201 in the first region 200A and covers the sidewall of the fin 201; a second gate structure 231, which is located on the other side of the fin 201 in the first region 200A and covers the sidewall of the fin 201, with the top of the first gate structure and the top of the second gate structure being flush; and a third gate structure 232, which is located on the top of the substrate 200 in the second region 200B and spans a portion of the top and a portion of the sidewall of the fin 201, with the top of the third gate structure 232 being flush with the top of the first gate structure 230 and the top of the second gate structure 231.

[0032] It should be noted that by providing a first gate structure 230 on one side of the fin 201 in the first region 200A and a second gate structure 231 on the other side of the fin 201 in the first region 200A, that is, a dual-gate structure is formed in the first region 200A to control the conduction. In the first region 200A, by controlling the voltage values ​​of the first gate structure 230 and the second gate structure 231 to be different, the current values ​​of conduction in the first region 200A are different, thereby further expanding the adjustable range of the conductive channel current value in the first region 200A, and thus improving the performance of the semiconductor structure.

[0033] Substrate 200 provides a process platform for the formation of semiconductor structures.

[0034] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate 200 may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth. The substrate 200 may also be other types of substrate 200 such as silicon-on-insulator substrate 200 or germanium-on-insulator substrate 200.

[0035] As an example, substrate 200 includes a first region 200A and an adjacent second region 200B, the first region 200A being used as a region for subsequently forming a dual-gate structure, and the second region 200B being used as a region for subsequently forming a single-gate structure.

[0036] Fin 201 is used to provide a conductive channel when the device is in operation.

[0037] In this embodiment, the material of the fin 201 is the same as the material of the substrate 200, and the material of the fin 201 is silicon.

[0038] In this embodiment, the number of fins 201 located in the first region 200A is one or more. As an example, Figure 1 The first region 200A shows two fins 201.

[0039] In this embodiment, the semiconductor structure further includes a hard mask layer 202, located on top of the fin 201.

[0040] Specifically, in the semiconductor structure formation process, the hard mask layer 202 is used as an etching mask for forming the fin 201. At the same time, during the formation of the first gate structure 230, the second gate structure 231, and the third gate structure 232, the top of the hard mask layer 202 can be used as a stop position to make the tops of the first gate structure 230, the second gate structure 231, and the third gate structure 232 flush, thereby improving the flatness of the top surfaces of the first gate structure 230, the second gate structure 231, and the third gate structure 232. Moreover, by controlling the thickness of the hard mask layer 202, the height of the first gate structure 230, the second gate structure 231, and the third gate structure 232 can be controlled, so that the height of the first gate structure 230, the second gate structure 231, and the third gate structure 232 reaches the target height.

[0041] In this embodiment, the material of the hard mask layer 202 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0042] Specifically, silicon oxide, silicon nitride, and silicon oxynitride are commonly used materials for the hard mask layer 202, which have the advantages of low process cost. At the same time, silicon oxide, silicon nitride, and silicon oxynitride have a high selectivity ratio (etching selectivity ratio and polishing selectivity ratio) with the materials selected for the fin 201, as well as with the materials selected for the first gate structure 230, the second gate structure 231, and the third gate structure 232. In the semiconductor structure formation process, the hard mask layer 202 can play the role of an etching mask, and the top of the hard mask layer 202 can serve as a stop position, reducing the probability of damage to other film layers (such as the fin 201), thereby improving the performance of the semiconductor structure.

[0043] It should be noted that the thickness of the hard mask layer 202 should not be too large or too small. If the thickness of the hard mask layer 202 is too small, during the semiconductor structure formation process, when using the hard mask layer 202 as a mask for patterning to form the fin 201, the protective effect of the hard mask layer 202 on the top of the fin 201 is easily reduced, increasing the probability of damage to the fin 201. Simultaneously, during the formation of the first gate structure 230, the second gate structure 231, and the third gate structure 232, if the thickness of the hard mask layer 202 is too small, the top of the hard mask layer 202 will not be able to act as a stop, causing damage to the first gate structure 230, the second gate structure 231, and the third gate structure 232. The top surface flatness of structures 231 and 232 is not high, causing the heights of the first gate structure 230, second gate structure 231, and third gate structure 232 to fall short of the target height, thus affecting the performance of the semiconductor structure. If the thickness of the hard mask layer 202 is too large, it increases the difficulty of removing the hard mask layer 202 in subsequent semiconductor fabrication processes. It also easily leads to excessively large heights of the first gate structure 230, second gate structure 231, and third gate structure 232, hindering further reduction in the overall height of the semiconductor structure. Therefore, in this embodiment, the thickness of the hard mask layer 202 is 1 nanometer to 20 nanometers.

[0044] In this embodiment, the top of the hard mask layer 202 is flush with the top of the first gate structure 230, the second gate structure 231, and the third gate structure 232.

[0045] Specifically, during the formation of the first gate structure 230, the second gate structure 231, and the third gate structure 232, the top of the hard mask layer 202 can be used as the stopping position to make the tops of the first gate structure 230, the second gate structure 231, and the third gate structure 232 flush, resulting in a high degree of flatness on the top surfaces of the first gate structure 230, the second gate structure 231, and the third gate structure 232. At the same time, the top of the third gate structure 232 is flush with the tops of the first gate structure 230 and the second gate structure 231, making the heights of the first gate structure 230, the second gate structure 231, and the third gate structure 232 consistent, thereby improving the uniformity of the height of the devices in the first region 200A and the height of the devices in the second region 200B.

[0046] In this embodiment, the semiconductor structure further includes an isolation structure 205 located on the substrate 200 exposed by the fin 201, and the isolation structure 205 covers part of the sidewall of the fin 201.

[0047] The isolation structure 205 is used to electrically isolate adjacent devices.

[0048] The isolation structure 205 is made of an insulating material, which can be silicon oxide, silicon nitride, or silicon oxynitride. As an example, the isolation structure 205 is made of silicon oxide.

[0049] The first gate structure 230 and the second gate structure 231 are used to control the opening and closing of the conductive channel when the semiconductor structure is working.

[0050] In this embodiment, when there are multiple fins 201 in the first region 200A, adjacent fins 201 share the first gate structure 230; or, adjacent fins 201 share the second gate structure 231, or, adjacent fins 201 share the first gate structure 230 and adjacent fins 201 share the second gate structure 231.

[0051] Specifically, by having adjacent fins 201 share the first gate structure 230 and the adjacent fins 201 share the second gate structure 231, the area occupied by the semiconductor structure can be reduced.

[0052] As an example, Figure 2 The first region 200A shows two fins 201. A first gate structure 230 is provided on the top of the substrate 200 between adjacent fins 201. A second gate structure 231 is formed on the top of the substrate 200 on the opposite side of the adjacent fins 201. The adjacent fins 201 share the first gate structure 230.

[0053] It should be noted that in the first region 200A, a first gate structure 230 is provided on one side of the fin 201, and a second gate structure 231 is provided on the other side of the fin 201. That is, a dual-gate structure is formed in the first region 200A to control the conduction. In the first region 200A, by controlling the voltage values ​​of the first gate structure 230 and the second gate structure 231 to be different, the current values ​​of conduction in the first region 200A are different, thereby further expanding the adjustable range of the conductive channel current value in the first region 200A, and thus improving the performance of the semiconductor structure.

[0054] It should also be noted that by making the top of the third gate structure 232 flush with the tops of the first gate structure 230 and the second gate structure 231, the top surfaces of the first gate structure 230, the second gate structure 231 and the third gate structure 232 have a high degree of flatness, which provides a better process foundation for subsequent semiconductor manufacturing processes (such as forming interconnect structures electrically connected to the gate structures). At the same time, by making the top of the third gate structure 232 flush with the tops of the first gate structure 230 and the second gate structure 231, the heights of the first gate structure 230, the second gate structure 231 and the third gate structure 232 are consistent, which improves the uniformity of the height of the devices in the first region 200A and the height of the devices in the second region 200B.

[0055] In the semiconductor structure formation process, the first gate structure 230 and the second gate structure 231 in the first region 200A and the third gate structure 232 in the second region 200B are formed in the same step.

[0056] Specifically, the first gate structure 230 and the second gate structure 231 in the first region 200A and the third gate structure 232 in the second region 200B are formed in the same step, which can reduce process steps, reduce process costs, and improve process efficiency. At the same time, forming the first gate structure 230, the second gate structure 231 and the third gate structure 232 in the same step means that the top of the hard mask layer 202 only needs to undergo one planarization process, which reduces the probability of the hard mask layer 202 being consumed excessively. This allows the height of the first gate structure 230, the second gate structure 231 and the third gate structure 232 to be as close as possible to the target height, thereby improving the performance of the semiconductor structure.

[0057] In this embodiment, the first gate structure 230 includes a first work function layer (not shown) with a first thickness, and the second gate structure 231 includes a second work function layer (not shown) with a second thickness.

[0058] Specifically, a first gate structure 230 is formed on one side of the fin 201 in the first region 200A, and a second gate structure 231 is formed on the other side of the fin 201. The first gate structure 230 includes a first work function layer with a first thickness, and the second gate structure 231 includes a second work function layer with a second thickness, so that the two sides of the same conductive channel have different threshold turn-on voltages, thereby facilitating the adjustment of the voltage of the semiconductor structure. An additional gain stage is introduced between the input and output to adjust the voltage gain characteristics. At the same time, it has a higher input impedance, which can better adapt to different signal sources, and in high-frequency applications, it has a higher frequency response and lower loss.

[0059] It should be noted that, as an example, in the semiconductor structure formation process, the second gate structure 231 in the first region 200A and the third gate structure 232 in the second region 200B are both formed from the same gate material layer. Therefore, the work function thickness of the second gate structure 231 in the first region 200A and the third gate structure 232 in the second region 200B is consistent, so that the threshold turn-on voltage of the third gate structure 232 is the same as the threshold turn-on voltage of the second gate structure 231.

[0060] In other embodiments, the second gate structure 231 and the third gate structure 232 may be formed in different steps, and the thickness of the work function of the second gate structure 231 and the thickness of the work function of the third gate structure 232 may be different.

[0061] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer (not shown), located on top of the substrate 200, and covering the sidewalls of the first gate structure 230, the sidewalls of the second gate structure 231, and the sidewalls of the third gate structure 232.

[0062] Interlayer dielectric layers are used for electrical isolation between adjacent devices.

[0063] The interlayer dielectric layer is made of an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the interlayer dielectric layer is made of silicon oxide.

[0064] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, wherein, Figures 2 to 7 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0065] refer to Figures 2 to 3 A substrate 100 is provided, which includes a first region 100A and a second region 100B adjacent thereto. Fins 101 protrude from the top of the substrate 100 in the first region 100A and the second region 100B.

[0066] Substrate 100 provides a process platform for subsequent semiconductor structure formation methods.

[0067] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0068] Fin 101 is used to provide a conductive channel when the device is in operation.

[0069] In this embodiment, the material of the fin 101 is the same as the material of the substrate 100, and the material of the fin 101 is silicon.

[0070] In this embodiment, the number of fins 101 located in the first region 100A is one or more. As an example, Figure 2 The first region 100A shows two fins 101.

[0071] As an example, substrate 100 includes a first region 100A and an adjacent second region 100B, the first region 100A being used as a region for subsequently forming a dual-gate structure, and the second region 100B being used as a region for subsequently forming a single-gate structure.

[0072] In this embodiment, a hard mask layer 102 is also formed on the top of the fin 101.

[0073] The hard mask layer 102 is used as an etching mask for forming the fin 101. At the same time, during the subsequent formation of the first gate structure, the second gate structure and the third gate structure, the top of the hard mask layer 102 can be used as the stop position to make the tops of the first gate structure, the second gate structure and the third gate structure flush, thereby improving the flatness of the top surface of the first gate structure, the second gate structure and the third gate structure. Moreover, by controlling the thickness of the hard mask layer 102, the height of the first gate structure, the second gate structure and the third gate structure can be controlled, so that the height of the first gate structure, the second gate structure and the third gate structure reaches the target height.

[0074] In this embodiment, the material of the hard mask layer 102 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0075] Specifically, silicon oxide, silicon nitride, and silicon oxynitride are commonly used materials for the hard mask layer 102, which have the advantages of low process cost. At the same time, silicon oxide, silicon nitride, and silicon oxynitride have a high selectivity ratio (etching selectivity ratio and polishing selectivity ratio) with the materials selected for the fin 101, as well as with the materials selected for the first gate structure, the second gate structure, and the third gate structure. This enables the hard mask layer 102 to function as an etching mask and allows the top of the hard mask layer 102 to serve as a stop position, reducing the probability of damage to other film layers (such as the fin 101) and thus improving the performance of the semiconductor structure.

[0076] It should be noted that the thickness of the hard mask layer 102 should not be too large or too small. If the thickness of the hard mask layer 102 is too small, during the patterning process of forming the fin 101 using the hard mask layer 102 as a mask, the protective effect of the hard mask layer 102 on the top of the fin 101 is easily reduced, increasing the probability of damage to the fin 101. At the same time, during the subsequent formation of the first gate structure, the second gate structure, and the third gate structure, because the thickness of the hard mask layer 102 is too small, the top of the hard mask layer 102 cannot play a stopping role, resulting in low flatness of the top surface of the first gate structure, the second gate structure, and the third gate structure, and the height of the first gate structure, the second gate structure, and the third gate structure not reaching the target height, thus affecting the performance of the semiconductor structure. If the thickness of the hard mask layer 102 is too large, the process difficulty of removing the hard mask layer 102 in the subsequent semiconductor structure processes is increased. At the same time, it is also easy for the height of the first gate structure, the second gate structure, and the third gate structure to be too large, which is not conducive to further reduction of the overall height of the semiconductor structure. Therefore, in this embodiment, the thickness of the hard mask layer 102 is 1 nanometer to 20 nanometers.

[0077] In this embodiment, the steps of forming the fin 101 and the hard mask layer 102 include: forming a fin material layer on top of the substrate 100; forming a hard mask material layer on top of the fin material layer; forming a patterned photoresist layer on top of the hard mask material layer; using the patterned photoresist layer as a mask to pattern the hard mask material layer, and using the remaining hard mask material layer as the hard mask layer 102; using the hard mask layer 102 as a mask to pattern the fin material layer, thereby forming the fin 101 protruding from the substrate 100.

[0078] As an example, the process of patterning the fin material layer using the hard mask layer 102 as a mask includes a dry etching process.

[0079] It should be noted that, in this embodiment, after forming the fin 101, the method for forming the semiconductor structure further includes: forming an isolation structure 105 on the substrate 100 of the fin 101, wherein the isolation structure 105 covers part of the sidewall of the fin 101.

[0080] The isolation structure 105 is used to electrically isolate adjacent devices.

[0081] The isolation structure 105 is made of an insulating material, which can be silicon oxide, silicon nitride, or silicon oxynitride. As an example, the isolation structure 105 is made of silicon oxide.

[0082] refer to Figure 4 Before the formation of the first gate structure, the second gate structure and the third gate structure, the process also includes: removing the hard mask layer 102 of the second region 100B.

[0083] Specifically, the hard mask layer 102 of the second region 100B is removed to expose the top of the fin 101 of the second region 100B. This facilitates the subsequent formation of a third gate structure in the second region 100B that covers part of the top and part of the sidewall of the fin 101. This allows both the top and sidewall of the fin 101 to serve as conductive channels, thereby improving the mobility and amount of charge carriers in the conductive communication.

[0084] In this embodiment, the step of removing the hard mask layer 102 of the second region 100B includes: forming a mask layer 108 covering the fin 101 on the top of the substrate 100 of the first region 100A, with the mask layer 108 exposing the hard mask layer 102 of the second region 100B; using the mask layer 108 as a mask, performing patterning processing on the hard mask layer 102 of the second region 100B, and removing the hard mask layer 102 of the second region 100B.

[0085] Specifically, the mask layer 108 protects the fin 101 and hard mask layer 102 in the first region 100A, reducing the probability that the process of removing the hard mask layer 102 in the second region 100B will damage the hard mask layer 102 in the first region 100A.

[0086] In this embodiment, the process for removing the hard mask layer 102 of the second region 100B includes a dry etching process.

[0087] Specifically, the dry etching process is an anisotropic dry etching process. Anisotropic dry etching process has the characteristics of anisotropic etching, and its longitudinal etching rate is much greater than its transverse etching rate. By using the dry etching process to remove the hard mask layer 102 of the second region 100B, the hard mask layer 102 in the second region 100B can be completely removed. At the same time, it also reduces the probability of damaging the sidewall of the fin 101 and improves the morphological quality of the sidewall in the second region 100B.

[0088] In this embodiment, the mask layer 108 includes an organic material layer (not shown), an anti-reflective coating (not shown) on the organic material layer, and a photoresist layer (not shown) on the anti-reflective coating.

[0089] The organic material layer is made of organic materials. In this embodiment, the organic material layer is spin-on carbon (SOC).

[0090] In other embodiments, the organic material layer may also be made of other organic materials, such as one or more of the following: ODL (organic dielectric layer), DUO (Deep UV Light Absorbing Oxide), and APF (Advanced Patterning Film).

[0091] Anti-reflective coating materials include BARC (bottom anti-reflective coating) materials. As an example, BARC material is Si-ARC (silicon-containing anti-reflective coating) material.

[0092] In other embodiments, the mask layer may also consist of only a photoresist layer.

[0093] It should be noted that after removing the hard mask layer 102 of the second region 100B, the process also includes removing the mask layer 108.

[0094] The process for removing the mask layer 108 includes wet etching or ashing.

[0095] refer to Figures 5 to 7 In the first region 100A, a first gate structure 130 covering the sidewall of the fin 101 is formed on the top of the substrate 100 on one side of the fin 101, and a second gate structure 131 covering the sidewall of the fin 101 is formed on the top of the substrate 100 on the other side of the fin 101, with the top of the second gate structure 131 being flush with the top of the second gate structure 131; in the second region 100B, a third gate structure 132 spanning a portion of the top and a portion of the sidewall of the fin 101 is formed on the top of the substrate 100, with the top of the third gate structure 132 being flush with the top of the first gate structure 130 and the top of the second gate structure 131.

[0096] It should be noted that in the first region 100A, a first gate structure 130 covering the sidewall of the fin 101 is formed on the top of the substrate 100 on one side of the fin 101, and a second gate structure 131 covering the sidewall of the fin 101 is formed on the top of the substrate 100 on the other side of the fin 101. The top of the second gate structure 131 is flush with the top of the second gate structure 131. That is, in the first region 100A, a first gate structure 130 is formed on one side of the fin 101, and a second gate structure 131 is formed on the other side of the fin 101. In other words, a dual-gate structure is formed in the first region 100A to control the conductivity. In the first region 100A, by controlling the voltage values ​​of the first gate structure 130 and the second gate structure 131 to be different, the current values ​​of the conductivity in the first region 100A are different, thereby further expanding the adjustable range of the conductive channel current value in the first region 100A, and thus improving the performance of the semiconductor structure.

[0097] It should also be noted that by making the top of the third gate structure 132 flush with the tops of the first gate structure 130 and the second gate structure 131, the top surfaces of the first gate structure 130, the second gate structure 131 and the third gate structure 132 have a high degree of flatness, which provides a better process foundation for subsequent semiconductor manufacturing processes (such as forming interconnect structures electrically connected to the gate structures). At the same time, by making the top of the third gate structure 132 flush with the tops of the first gate structure 130 and the second gate structure 131, the heights of the first gate structure 130, the second gate structure 131 and the third gate structure 132 are consistent, which improves the uniformity of the height of the devices in the first region 100A and the height of the devices in the second region 100B.

[0098] The first gate structure 130 and the second gate structure 131 are used to control the opening and closing of the conductive channel when the semiconductor structure is working.

[0099] In this embodiment, when there are multiple fins 101 in the first region 100A, in the step of forming the first gate structure and the second gate structure, adjacent fins 101 share the first gate structure 130; or, adjacent fins 101 share the second gate structure 131; or, adjacent fins 101 share the first gate structure 130 and adjacent fins 101 share the second gate structure 131.

[0100] Specifically, by having adjacent fins 101 share a first gate structure 130 and by having adjacent fins 101 share a second gate structure 131, the area occupied by the semiconductor structure can be reduced.

[0101] As an example, Figure 7The first region 100A shows two fins 101. A first gate structure 130 is formed on the top of the substrate 100 between adjacent fins 101. A second gate structure 131 is formed on the top of the substrate 100 on the opposite side of the adjacent fins 101. The adjacent fins 101 share the first gate structure 130.

[0102] In this embodiment, the first gate structure 130 and the second gate structure 131 in the first region 100A and the third gate structure 132 in the second region 100B are formed in the same step.

[0103] Specifically, the first gate structure 130 and the second gate structure 131 in the first region 100A and the third gate structure 132 in the second region 100B are formed in the same step, which can reduce process steps, reduce process costs, and improve process efficiency. At the same time, forming the first gate structure 130, the second gate structure 131 and the third gate structure 132 in the same step means that the top of the hard mask layer 102 only needs to undergo one planarization process, which reduces the probability of the hard mask layer 102 being consumed excessively. This allows the height of the first gate structure 130, the second gate structure 131 and the third gate structure 132 to be as close as possible to the target height, thereby improving the performance of the semiconductor structure.

[0104] In other embodiments, the first gate structure and the second gate structure in the first region and the third gate structure in the second region may be formed in different steps.

[0105] In this embodiment, in the steps of forming the first gate structure 130 and the second gate structure 131, the top of the hard mask layer 102 of the first region 100A is taken as the stop position.

[0106] Specifically, using the top of the hard mask layer 102 in the first region 100A as the stop position, the top of the third gate structure 132 is made flush with the tops of the first gate structure 130 and the second gate structure 131. This results in a high degree of flatness on the top surfaces of the first gate structure 130, the second gate structure 131, and the third gate structure 132, providing a better process foundation for subsequent semiconductor manufacturing processes (such as forming interconnect structures electrically connected to the gate structures). At the same time, the top of the third gate structure 132 is flush with the tops of the first gate structure 130 and the second gate structure 131, making the heights of the first gate structure 130, the second gate structure 131, and the third gate structure 132 consistent, thus improving the uniformity of the device heights in the first region 100A and the second region 100B.

[0107] In this embodiment, the steps of forming the first gate structure 130, the second gate structure 131, and the third gate structure 132 include: forming a dummy gate structure 110 spanning the fin 101 on the top of the substrate 100 of the first region 100A and the second region 100B; forming an interlayer dielectric layer (not shown) on the substrate 100 exposed by the dummy gate structure 110; removing the dummy gate structure 110 and forming a first gate opening (not shown) in the interlayer dielectric layer; forming a first gate material layer 121 in the first gate opening; removing the first gate material layer 121 on one side of the fin 101 in the first region 100A, and forming the remaining first gate material layer 130 in the third region 100A. A second gate opening (not shown) is formed in the gate material layer 121; a second gate material layer 120 is formed in the second gate opening; taking the top of the fin 101 as the stop position, the first gate material layer 121 and the second gate material layer 120 above the top of the fin 101 are planarized, the remaining second gate material layer 120 in the first region 100A is used as the first gate structure 130, the remaining first gate material layer 121 in the first region 100A is used as the second gate structure 131, and the remaining first gate material layer 121 in the second region 100B is used as the third gate structure 132.

[0108] Specifically, the pseudo-gate structure 110 provides spatial locations for forming the first gate structure 130, the second gate structure 131, and the third gate structure 132.

[0109] As an example, the material of the pseudo-gate structure 110 includes polycrystalline silicon.

[0110] Interlayer dielectric layers are used for electrical isolation between adjacent devices.

[0111] The interlayer dielectric layer is made of an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the interlayer dielectric layer is made of silicon oxide.

[0112] In this embodiment, the process of removing the first gate material layer 121 between adjacent fins 101 in the first region 100A includes a dry etching process.

[0113] Specifically, the dry etching process is an anisotropic dry etching process. Anisotropic dry etching has the characteristics of anisotropic etching, and its longitudinal etching rate is much greater than its lateral etching rate. By using the dry etching process to remove the first gate material layer 121 between adjacent fins 101 in the first region 100A, the morphology quality of the second gate opening sidewall can be improved, which is beneficial for the subsequent deposition of the first gate structure 130 in the second gate opening. This reduces the probability of voids appearing between the first gate structure 130 and the fin 101, thereby improving the performance of the semiconductor structure.

[0114] In this embodiment, in the steps of forming the first gate structure 130 and the second gate structure 131, the first gate structure 130 includes a first work function layer (not shown) with a first thickness, and the second gate structure 131 includes a second work function layer (not shown) with a second thickness.

[0115] Specifically, a first gate structure 130 is formed on one side of the fin 101 in the first region 100A, and a second gate structure 131 is formed on the other side of the fin 101. The first gate structure 130 includes a first work function layer with a first thickness, and the second gate structure 131 includes a second work function layer with a second thickness, so that the two sides of the same conductive channel have different threshold turn-on voltages, thereby facilitating the adjustment of the voltage of the semiconductor structure. An additional gain stage is introduced between the input and output to adjust the voltage gain characteristics. At the same time, it has a higher input impedance, which can better adapt to different signal sources, and in high-frequency applications, it has a higher frequency response and lower loss.

[0116] It should be noted that, as an example, the second gate structure 131 in the first region 100A and the third gate structure 132 in the second region 100B are both formed by the second gate material layer 120. Therefore, the work function thickness of the second gate structure 131 in the first region 100A and the third gate structure 132 in the second region 100B is consistent, so that the threshold turn-on voltage of the third gate structure 132 is the same as the threshold turn-on voltage of the second gate structure 131.

[0117] In other embodiments, the second gate structure and the third gate structure may be formed in different steps, and the thickness of the work function of the second gate structure and the thickness of the work function of the third gate structure may be different.

[0118] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, the substrate comprising a first region and a second region adjacent to it; The fins protrude from the top of the substrate in the first and second regions; A first gate structure is located on one side of the fin in the first region and covers the sidewall of the fin. The second gate structure is located on the other side of the fin in the first region and covers the sidewall of the fin. The top of the first gate structure is flush with the top of the second gate structure. The first gate structure includes a first work function layer with a first thickness, and the second gate structure includes a second work function layer with a second thickness, so that the two sides of the same conductive channel have different threshold turn-on voltages. A third gate structure is located on top of the substrate in the second region and spans a portion of the top and a portion of the sidewalls of the fin. The top of the third gate structure is flush with the tops of the first gate structure and the second gate structure.

2. The semiconductor structure as described in claim 1, characterized in that, The number of fins located in the first region is one or more; When there are multiple fins in the first region, adjacent fins share a first gate structure; or, adjacent fins share a second gate structure, or, adjacent fins share a first gate structure and adjacent fins share a second gate structure.

3. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a hard mask layer located on top of the fin in the first region; The top of the hard mask layer is flush with the top of the first gate structure, the second gate structure, and the third gate structure.

4. The semiconductor structure as described in claim 3, characterized in that, The material of the hard mask layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

5. The semiconductor structure as described in claim 3, characterized in that, The thickness of the hard mask layer is 1 nanometer to 20 nanometers.

6. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first region and an adjacent second region, wherein fins are protruding from the top of the substrate in the first and second regions; In the first region, a first gate structure covering the sidewall of the fin is formed on the top of the substrate on one side of the fin, and a second gate structure covering the sidewall of the fin is formed on the top of the substrate on the other side of the fin. The top of the first gate structure and the top of the second gate structure are flush. In the step of forming the first gate structure and the second gate structure, the first gate structure includes a first work function layer with a first thickness, and the second gate structure includes a second work function layer with a second thickness, so that the two sides of the same conductive channel have different threshold turn-on voltages. In the second region, a third gate structure is formed on the top of the substrate, spanning the top of the fin portion and a portion of the sidewalls, the top of the third gate structure being flush with the tops of the first gate structure and the second gate structure.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, In the step of providing the substrate, the number of fins located in the first region is one or more; When there are multiple fins in the first region, in the step of forming the first gate structure and the second gate structure, adjacent fins share the same first gate structure; or, adjacent fins share the same second gate structure; or, adjacent fins share the same first gate structure and adjacent fins share the same second gate structure.

8. The method for forming a semiconductor structure as described in claim 6, characterized in that, In the step of providing the substrate, a hard mask layer is also formed on the top of the fin; Before forming the first gate structure, the second gate structure and the third gate structure, the method further includes: removing the hard mask layer of the second region; In the step of forming the first gate structure and the second gate structure, the top of the hard mask layer of the first region is taken as the stop position.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The material of the hard mask layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, The thickness of the hard mask layer is 1 nanometer to 20 nanometers.

11. The method for forming a semiconductor structure as described in claim 8, characterized in that, The step of removing the hard mask layer of the second region includes: forming a mask layer covering the fin on top of the substrate of the first region, the mask layer exposing the hard mask layer of the second region; using the mask layer as a mask, performing patterning processing on the hard mask layer of the second region, removing the hard mask layer of the second region; and removing the mask layer.

12. The method for forming a semiconductor structure as described in claim 8, characterized in that, The process for removing the hard mask layer in the second region includes a dry etching process.

13. The method for forming a semiconductor structure as described in claim 6, characterized in that, The first gate structure and the second gate structure in the first region are formed in the same step as the third gate structure in the second region.

14. The method for forming a semiconductor structure as described in claim 6, characterized in that, The steps of forming the first gate structure, the second gate structure, and the third gate structure include: forming a dummy gate structure spanning the fin on top of the substrate of the first region and the second region; forming an interlayer dielectric layer on the substrate exposed by the dummy gate structure; removing the dummy gate structure and forming a first gate opening in the interlayer dielectric layer; forming a first gate material layer in the first gate opening; removing the first gate material layer on one side of the fin in the first region and forming a second gate opening in the remaining first gate material layer; forming a second gate material layer in the second gate opening; planarizing the first gate material layer and the second gate material layer above the top of the fin, using the top of the fin as a stop position; using the remaining second gate material layer in the first region as the first gate structure; using the remaining first gate material layer in the first region as the second gate structure; and using the remaining first gate material layer in the second region as the third gate structure.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The process for removing the first gate material layer between adjacent fins in the first region includes a dry etching process.

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