MOSFET optimization structure based on FinFET technology and preparation method thereof

Abstract

The invention relates to the technical field of MOS semiconductors, and discloses an MOSFET optimization structure based on the FinFET technology and a preparation method thereof.The MOSFET optimization structure comprises a plurality of MOS cells which are parallel to one another, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the interior of each semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P well layer and a P-layer, the profile of the section of the N substrate layer in each MOS cell is in a middle convex shape; a plurality of strip-shaped polycrystalline silicon are arranged in the P-layer on the left side in the single MOS cell, and the strip-shaped polycrystalline silicon is only in ohmic contact with the source electrode. The strip-shaped polycrystalline silicon on the left P-layer and the block-shaped polycrystalline silicon on the right side are only in ohmic contact with the source electrode, a low-resistance path is formed, parasitic resistance is reduced, the conduction current density is improved, and through the distribution design of the polycrystalline silicon, the electric field concentration in the device is reduced, the hot carrier effect is reduced, and the reliability is improved.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a MOSFET optimized structure based on FinFET technology and a preparation method thereof. Background Art

[0002] FinFET (Fin Field-Effect Transistor) is a three-dimensional transistor structure, whose core feature is to achieve multi-sided wrapping of the gate to the channel (usually three-sided or ring gate) through a vertical fin-shaped (Fin) semiconductor channel. Compared with traditional planar MOSFET, the optimization of FinFET is mainly reflected in: 1. Reducing drain-induced barrier lowering (DIBL) and subthreshold leakage current by enhancing the electrostatic control of the gate to the channel. 2. Increasing the on-current by connecting multiple fins in parallel or increasing the fin height (Hfin). 3. Steeper subthreshold swing (SS) and lower threshold voltage (Vth) fluctuations.

[0003] The existing patent discloses a high-reliability SIC-MOSFET terminal structure (publication number CN222190737U), which belongs to the field of semiconductor device technology. The high-reliability SIC-MOSFET terminal structure includes a source and a drain. The source is the input end of the MOSFET, which is used to supply current in the circuit, and the drain is the output end of the MOSFET, which is used to extract current. The FinFET structure proposed in the technology disclosed in the patent still increases the parasitic resistance due to excessive path resistance, which will further increase the hot carrier effect, causing the device to have exponential performance degradation at high temperatures. Summary of the invention

[0004] In order to solve the existing technical problems, the present invention provides a MOSFET optimized structure based on FinFET technology and a preparation method thereof, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, an optimized MOSFET structure based on FinFET technology, including a plurality of mutually parallel MOS cells, wherein the MOS cell includes a drain, a semiconductor epitaxial layer, a source, and a gate, wherein the semiconductor epitaxial layer includes an N substrate layer, an N drift layer, an N well layer, a P well layer, and a P-layer, and the cross-sectional profile of the N substrate layer in a single MOS cell is a convex shape in the middle; A plurality of strip-shaped polysilicon are provided in the P-layer on the left side inside a single MOS cell, and the strip-shaped polysilicon is only in ohmic contact with the source electrode; A block of polysilicon is disposed in the P-layer on the right side of a single MOS cell, and the block of polysilicon is only in ohmic contact with the source electrode.

[0006] Furthermore, a left high-resistance doping layer is provided in the P-layer on the left side inside a single MOS cell, and a right high-resistance doping layer is provided in the P-layer on the right side inside the single MOS cell.

[0007] Furthermore, both the left high-resistance doping layer and the right high-resistance doping layer are located at the junction between the source electrode and the P-layer.

[0008] Furthermore, a plurality of strip-shaped metals are further provided inside the bulk polycrystalline silicon, and the top of the strip-shaped metal is in contact with the source electrode.

[0009] Furthermore, a plurality of composite metals are further provided inside the N-well layer, and the top of the composite metal is in contact with the source electrode.

[0010] A preparation method for an optimized structure of a MOSFET based on FinFET technology specifically includes the following steps: S1. Inject phosphorus and arsenic elements into the top silicon layer with a thickness of 20 nm of the semiconductor epitaxial layer to form an active region; S2. Use EUV lithography and RIE etching to form an array of strip-shaped polycrystalline silicon and bulk polycrystalline silicon in the active region; S3. Continue to integrate a metal heat dissipation structure of strip-shaped metals and composite metals in the active region; S4. Achieve doping activation and strain layer protection through pulsed laser annealing; S5. Perform a performance improvement detection on the activated MOSFET structure.

[0011] Furthermore, in the step S1, the dose of phosphorus injection is , the energy during injection is 2 keV, and the dose of arsenic injection is , and the energy during injection is 5 keV.

[0012] Furthermore, in the step S5, the performance improvement of the MOSFET structure is judged according to the resistance change amount and the response speed of the MOSFET structure. Then, there is: In the formula, represents the performance coefficient of the MOSFET structure; represents an index used to control the sensitivity of the model formula, an empirical constant that determines the change rate of the performance coefficient; represents the resistance change amount of the MOSFET structure when rising from 25 °C to 100 °C, with the unit of mΩ; represents the proportion of the number of MOSFET structures used to detect the resistance change amount in the total sample number; represents the response speed of the MOSFET structure, with the unit of ns; The proportion of the number of MOSFET structures used to detect the response speed in the total number of samples.

[0013] The optimized MOSFET structure based on FinFET technology and its manufacturing method provided by the present invention achieve the following effects compared with the prior art: 1. In the present invention, the strip-shaped polysilicon on the left P-layer and the bulk polysilicon on the right are only in ohmic contact with the source electrode, forming a low-resistance path, reducing the parasitic resistance, increasing the on-state current density, and through the distribution design of the polysilicon, reducing the electric field concentration inside the device, reducing the hot carrier effect, and improving the reliability.

[0014] 2. In the present invention, the left and right high-resistance doping layers are located at the junction of the source electrode and the P-layer, adjusting the contact resistance and blocking the lateral diffusion of carriers, significantly reducing the leakage current, and the high-resistance layer disperses the thermal effect, reducing the performance degradation at high temperatures, and improving the stability of the device within a wide temperature range.

[0015] 3. In the present invention, the strip-shaped metal inside the bulk polysilicon is directly in contact with the source electrode, enhancing the local heat conduction ability, avoiding the formation of hot spots, improving the power tolerance, and the introduction of the metal structure optimizes the interface contact between the source electrode and the polysilicon, reducing the current transmission loss, and improving the switching speed. Moreover, the collaborative design of the strip-shaped metal and the polysilicon simplifies the process flow, while taking into account the electrical performance and heat dissipation requirements.

[0016] 4. In the present invention, the composite metal inside the N-well layer is directly connected to the source electrode, reducing the contact resistance between the N-well layer and the source electrode, improving the on-state efficiency, and the composite metal structure increases the mechanical strength of the device, reducing the stress damage during the manufacturing or packaging process, improving the yield, and the composite metal has both conductive and supporting functions, extending the device life while optimizing the electrical performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic structural diagram of the first embodiment in the present invention; Figure 2 It is a schematic structural diagram of the second embodiment in the present invention; Figure 3 It is a schematic structural diagram of the third embodiment in the present invention; Figure 4 It is a schematic structural diagram of the fourth embodiment in the present invention; Figure 5 It is the coefficient of performance c in the present invention affected by the empirical constant and the resistance change amount R.

[0018] In the figure: 1. drain; 2. source; 3. gate; 4. N substrate layer; 5. N drift layer; 6. N well layer; 7. P well layer; 8. P-layer; 9. strip polysilicon; 10. block polysilicon; 11. left high-resistance doped layer; 12. right high-resistance doped layer; 13. strip metal; 14. composite metal. DETAILED DESCRIPTION

[0019] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] like Figures 1-5 As shown, the preparation method of the optimized structure of MOSFET based on FinFET technology includes the following specific steps: Step 1: Phosphorus and arsenic are implanted on the top silicon layer of the semiconductor epitaxial layer with a thickness of 20 nm to form an active region; the dose of implanted phosphorus is The energy during injection is 2keV, and the dose of injected arsenic is The energy during injection is 5keV.

[0021] Step 2: EUV lithography and RIE etching are used to form an array of strip-shaped polysilicon 9 and block-shaped polysilicon 10 in the active area.

[0022] Step 3: Continue to integrate the metal heat dissipation structure of the strip metal 13 and the composite metal 14 in the active area.

[0023] Step 4: Realize doping activation and strain layer protection through pulsed laser annealing.

[0024] Step 5: Test the performance improvement of the activated MOSFET structure. The performance improvement of the MOSFET structure can be determined based on the resistance change and response speed of the MOSFET structure. Then: In the formula, represents the performance coefficient of the MOSFET structure; It represents the index used to control the sensitivity of the model formula and the empirical constant that determines the rate of change of the performance coefficient; It indicates the resistance change of the MOSFET structure from 25℃ to 100℃, in mΩ. Indicates the proportion of the number of MOSFET structures used to detect resistance changes in the total number of samples; Indicates the response speed of the MOSFET structure, in ns; Indicates the proportion of MOSFET structures used to detect response speed in the total number of samples.

[0025] Among them, the change in resistance of the MOSFET structure from 25°C to 100°C is taken as (mΩ), and the proportion of the number of MOSFET structures used to detect the change in resistance in the total number of samples is taken as . The response speed of the MOSFET structure is taken as (ns), and the proportion of the number of MOSFET structures used to detect the response speed in the total number of samples is taken as .

[0026] Among them, for the index used to control the sensitivity of the model formula, the empirical constant determining the change rate of the performance coefficient is taken as , then there is: It can be known from the above calculations that the performance coefficient of the device detected this time is ; if the performance coefficient of the traditional device detected is , then it means that the performance of the device is improved by 12.4%.

[0027] Example 1 As Figure 1 shown, according to one aspect of the present invention, there is provided an optimized MOSFET structure based on FinFET technology, including a plurality of juxtaposed MOS cells. The MOS cell includes a drain 1, a semiconductor epitaxial layer, a source 2, and a gate 3. The semiconductor epitaxial layer internally includes an N substrate layer 4, an N drift layer 5, an N well layer 6, a P well layer 7, and a P- layer 8. The cross-sectional profile of the N substrate layer 4 in a single MOS cell is convex in the middle; a plurality of strip-shaped polysilicons 9 are provided in the P- layer 8 on the left side inside a single MOS cell, and the strip-shaped polysilicons 9 are in ohmic contact with the source 2 only; a block-shaped polysilicon 10 is provided in the P- layer 8 on the right side inside a single MOS cell, and the block-shaped polysilicon 10 is in ohmic contact with the source 2 only. The middle convex cross-sectional profile of the N substrate layer 4 makes the gate wrap the channel more tightly, improves electrostatic control, effectively suppresses drain-induced barrier lowering (DIBL) and subthreshold leakage current, while the strip-shaped polysilicons 9 on the left side P- layer 8 and the block-shaped polysilicon 10 on the right side are in ohmic contact with the source only, forming a low-resistance path, reducing parasitic resistance, increasing the on-current density, and through the distribution design of the polysilicon, reducing the electric field concentration inside the device, reducing the hot carrier effect and improving reliability.

[0028] Example 2 As Figure 2As shown, a left high-resistance doping layer 11 is provided in the P-layer 8 on the left side inside a single MOS cell, and a right high-resistance doping layer 12 is provided in the P-layer 8 on the right side inside the single MOS cell. Both the left high-resistance doping layer 11 and the right high-resistance doping layer 12 are located at the junction between the source electrode 2 and the P-layer 8. The left and right high-resistance doping layers are located at the junction of the source electrode 2 and the P-layer 8, adjusting the contact resistance and blocking the lateral diffusion of carriers, significantly reducing the leakage current, and this high-resistance layer disperses the thermal effect, reduces the performance degradation at high temperatures, and improves the stability of the device within a wide temperature range.

[0029] Embodiment 3 As Figure 3 shown, a plurality of strip-shaped metals 13 are further provided inside the bulk polycrystalline silicon 10, wherein the top of the strip-shaped metal 13 is in contact with the source electrode 2. The strip-shaped metal 13 inside the bulk polycrystalline silicon 10 is directly in contact with the source electrode 2, enhancing the local heat conduction ability, avoiding the formation of hot spots, improving the power tolerance, and the introduction of this metal structure optimizes the interface contact between the source electrode 2 and the polycrystalline silicon, reducing the current transmission loss and increasing the switching speed. Moreover, the collaborative design of the strip-shaped metal 13 and the polycrystalline silicon simplifies the process flow while taking into account both the electrical performance and the heat dissipation requirements.

[0030] Embodiment 4 As Figure 4 shown, a plurality of composite metals 14 are further provided inside the N-well layer 6, wherein the top of the composite metal 14 is in contact with the source electrode 2. The composite metal 14 inside the N-well layer 6 is directly connected to the source electrode 2, reducing the contact resistance between the N-well layer 6 and the source electrode 2, improving the conduction efficiency, and the composite metal 14 structure increases the mechanical strength of the device, reduces the stress damage during the preparation or packaging process, improves the yield, and the composite metal 14 has both conductive and supporting functions, extending the device life while optimizing the electrical performance.

[0031] The above-described embodiments merely represent several implementation manners of the present invention, and their descriptions are relatively specific and detailed, but should not be construed as limiting the scope of the patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the appended claims.

Claims

1. A MOSFET optimized structure based on FinFET technology, comprising a plurality of mutually parallel MOS cells, wherein the MOS cells comprise a drain (1), a semiconductor epitaxial layer, a source (2), and a gate (3), wherein the semiconductor epitaxial layer comprises an N substrate layer (4), an N drift layer (5), an N well layer (6), a P well layer (7), and a P-layer (8), characterized in that: The cross-sectional profile of the N substrate layer (4) in a single MOS cell is convex in the middle; A plurality of strip-shaped polysilicon (9) are provided in the P-layer (8) on the left side inside a single MOS cell, and the strip-shaped polysilicon (9) is only in ohmic contact with the source electrode (2); A block of polysilicon (10) is provided in the P-layer (8) on the right side inside a single MOS cell, and the block of polysilicon (10) is only in ohmic contact with the source (2).

2. The MOSFET optimized structure based on FinFET technology according to claim 1, characterized in that: A left high-resistance doping layer (11) is provided in the P-layer (8) on the left side inside a single MOS cell, and a right high-resistance doping layer (12) is provided in the P-layer (8) on the right side inside a single MOS cell.

3. The MOSFET optimized structure based on FinFET technology according to claim 2, characterized in that: The left high-resistance doped layer (11) and the right high-resistance doped layer (12) are both located at the junction between the source electrode (2) and the P-layer (8).

4. The MOSFET optimized structure based on FinFET technology according to claim 1, characterized in that: A plurality of strip-shaped metals (13) are also provided inside the block-shaped polycrystalline silicon (10), wherein the top of the strip-shaped metals (13) is in contact with the source electrode (2).

5. The MOSFET optimized structure based on FinFET technology according to claim 1 or 2, characterized in that: A plurality of composite metals (14) are also provided inside the N-well layer (6), wherein the top of the composite metal (14) is in contact with the source electrode (2).

6. A method for preparing a MOSFET optimized structure based on FinFET technology, characterized in that: Applied to the structure described in any one of claims 1 to 5, the method for preparing the optimized structure of MOSFET based on FinFET technology comprises the following specific steps: S1, implanting phosphorus and arsenic elements into the top silicon layer of the semiconductor epitaxial layer with a thickness of 20nm to form an active region; S2, using EUV lithography and RIE etching to form an array of strip-shaped polycrystalline silicon (9) and block-shaped polycrystalline silicon (10) in the active area; S3, continuing to integrate a metal heat dissipation structure of a strip metal (13) and a composite metal (14) in the active area; S4, doping activation and strain layer protection through pulsed laser annealing; S5. Perform performance improvement test on the activated MOSFET structure.

7. The method for preparing the optimized structure of MOSFET based on FinFET technology according to claim 6, characterized in that: The dosage of phosphorus injected in step S1 is The energy during injection is 2keV, and the dose of injected arsenic is The energy during injection is 5keV.

8. The method for preparing the optimized structure of MOSFET based on FinFET technology according to claim 6, characterized in that: In step S5, the performance improvement of the MOSFET structure is determined based on the resistance change and response speed of the MOSFET structure. Then: In the formula, represents the performance coefficient of the MOSFET structure; It represents the index used to control the sensitivity of the model formula and the empirical constant that determines the rate of change of the performance coefficient; It indicates the resistance change of the MOSFET structure from 25℃ to 100℃, in mΩ. Indicates the proportion of MOSFET structures used to detect resistance changes in the total number of samples; Indicates the response speed of the MOSFET structure, in ns; Indicates the proportion of MOSFET structures used to detect response speed in the total number of samples.

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