Semiconductor die with resistive and / or diode connection between terminals of current sensing device and power transistor

Abstract

A semiconductor die includes: a semiconductor substrate; a power transistor formed in the semiconductor substrate; a current sensing device formed in the semiconductor substrate and occupying a smaller semiconductor substrate area than the power transistor; a first contact pad electrically connected to a first load terminal of the power transistor; a second contact pad electrically connected to a sensing terminal of the current sensing device, the second contact pad dedicated only to current sensing; and a resistive and / or diode connection between the sensing terminal of the current sensing device and the first load terminal of the power transistor. By providing an ESD discharge path to the first load terminal of the power transistor, the resistive and / or diode connection is individually designed for ESD (Electrostatic Discharge) protection of the current sensing device.

Description

BACKGROUND OF THE INVENTION

[0001] For semiconductor devices, the ESD (electrostatic discharge) durability test is a "charge injection" stress test, by which a certain amount of charge is forced into the electrical access points of the device. The level of charge injection is increased until irreversible damage is measured, either a drift in the electrical output or a catastrophic failure of the dielectric isolation within the device (e.g., gate oxide, interlayer dielectric, etc.). ESD durability is one of the specifications that define the SOA (safe operating area) of semiconductor devices.

[0002] In a power transistor chip (die), typical durability verification is performed according to the HBM (human body model) ESD specification, in which a 100 pF capacitor charged to a certain voltage is discharged through a 1.5 kΩ resistor onto the electrical contact of the chip. During each individual test, the remaining electrical contacts are either grounded or left floating. Under various possible stress combinations, the typical SOA specification requires at least 2 kV at the capacitor without causing electrical damage to the device.

[0003] ESD protection of power transistors before being assembled on a PCB is achieved only by monolithic integration solutions. For example, IGBT (insulated gate bipolar transistor) chips used in main inverter applications in electric vehicles are usually large chips, and thus the gate, emitter, and collector terminals easily meet the ESD specification through their associated capacitances. However, for more advanced inverter systems, IGBT chips with integrated current sensors are used. The current sensor is typically implemented as a small IGBT integrated within a larger main chip, and the area ratio can reach 1:10,000. The small size of the current sensor area (e.g., as low as 0.01 mm 2 ) makes the current sensor area potentially weak in terms of ESD durability, and typically the HBM specification for the current sensor area needs to be relaxed to below 2 kV. However, not all applications can tolerate this degradation in ESD durability.

[0004] Therefore, a solution is needed that improves the ESD durability of integrated current sensors in power transistor chips (dies) such as IGBTs. SUMMARY OF THE INVENTION

[0005] According to an embodiment of a semiconductor die, the semiconductor die includes: a semiconductor substrate; a power transistor formed in the semiconductor substrate; a current sensing device formed in the semiconductor substrate and occupying less semiconductor substrate area than the power transistor; a first contact pad electrically connected to a first load terminal of the power transistor; a second contact pad electrically connected to a sensing terminal of the current sensing device, wherein the second contact pad is dedicated solely to current sensing; and a resistive and / or diodic connection between the sensing terminal of the current sensing device and the first load terminal of the power transistor, wherein the resistive and / or diodic connection is designed separately for electrostatic discharge (ESD) protection of the current sensing device by providing an ESD discharge path to the first load terminal of the power transistor.

[0006] According to another embodiment of a semiconductor die, the semiconductor die includes: a semiconductor substrate; an insulated gate bipolar transistor (IGBT) formed in the semiconductor substrate; a current sensing device formed in the semiconductor substrate and occupying less semiconductor substrate area than the IGBT; an emitter contact pad electrically connected to an emitter terminal of the IGBT; a current sensing contact pad electrically connected to an emitter terminal of the current sensing device, wherein the current sensing contact pad is dedicated solely to current sensing; and a resistive and / or diodic connection between the emitter terminal of the current sensing device and the emitter terminal of the IGBT, wherein the resistive and / or diodic connection is designed separately for ESD protection of the current sensing device by providing an ESD discharge path to the emitter terminal of the IGBT.

[0007] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding like parts. Features of the various illustrated embodiments may be combined unless they are mutually exclusive. The embodiments are depicted in the drawings and detailed in the following description.

[0009] Figure 1 A schematic diagram of a semiconductor die having a resistive and / or diodic connection between a sensing terminal of a current sensing device and a load terminal of a power transistor, according to an embodiment, is illustrated.

[0010] Figure 2 A schematic diagram of a semiconductor die, according to another embodiment, is illustrated.

[0011] Figure 3 A schematic diagram of a semiconductor die, according to another embodiment, is illustrated.

[0012] Figure 4Illustrates a schematic diagram of a resistive and / or diode-connected according to another embodiment.

[0013] Figure 5 Illustrates a schematic diagram of a resistive and / or diode-connected according to another embodiment.

[0014] Figure 6 Illustrates a schematic diagram of a resistive and / or diode-connected according to another embodiment.

[0015] Figure 7 Illustrates a schematic diagram of an overcurrent detection circuit for detecting when the current mirrored by a current sensing device included in a semiconductor die exceeds a threshold limit.

[0016] Figure 8 Illustrates a top view of a semiconductor die in a region where a current sensing device is adjacent to a power transistor.

[0017] Figure 9 Illustrates a trench structure in a region where a current sensing device is adjacent to a power transistor along Figure 8 a cross-sectional view taken along line A-A' marked in

[0018] Figure 10 Illustrates a top view of a semiconductor die in a region where a current sensing device is adjacent to a power transistor according to another embodiment.

[0019] Figure 11 Illustrates a top view of a semiconductor die in a region where a current sensing device is adjacent to a power transistor according to another embodiment.

[0020] Figure 12A Illustrates a schematic diagram of a semiconductor die according to another embodiment, and Figure 12B illustrates a corresponding top view of a semiconductor die in a region where a current sensing device is adjacent to a power transistor.

[0021] Figure 13A Illustrates a schematic diagram of a semiconductor die according to another embodiment, and Figure 13B illustrates a corresponding top view of a semiconductor die in a region where a current sensing device is adjacent to a power transistor.

[0022] Figure 14A Illustrates a schematic diagram of a semiconductor die according to another embodiment, and Figure 14B illustrates a corresponding top view of a semiconductor die in a region where a current sensing device is adjacent to a power transistor.

[0023] Figure 15 Illustrates according to another embodiment Figure 14B the Zener configuration diode schematic shown. Detailed implementation manners

[0024] An improved ESD (electrostatic discharge) protection scheme for an integrated current sensing device included in a power transistor die (chip) such as an IGBT die is described herein. The current sensing device occupies a smaller area than the power transistor integrated in the same die, and thus has a smaller charge storage capacity in the event of an ESD occurring at the sensing terminal of the current sensing device. The ESD protection scheme described herein improves the ESD durability of the current sensing device by providing a resistive and / or diode-like connection between the sensing terminal of the current sensing device and the load terminal of the power transistor. The resistive and / or diode-like connection is designed separately for the ESD protection of the current sensing device.

[0025] During an ESD event, a short circuit event, or during conduction, high-frequency oscillations occur between the current sensing device and, for example, the main emitter portion of an IGBT. The resistive and / or diode-like connection acts as a short circuit at high frequencies, effectively shunting the oscillations to the main emitter portion of the IGBT. The main emitter portion of the IGBT has a significantly larger capacitance compared to the current sensing device, and thus has a larger charge storage capacity, and is therefore more robust in absorbing high-frequency oscillations without ESD failure and / or gate oxide breakdown / gate oxide reliability issues. The ESD protection scheme is described herein in the context of an IGBT power transistor, but the ESD protection scheme is equally applicable to other power transistor types such as power MOSFETs (metal oxide semiconductor field effect transistors), JFETs (junction gate field effect transistors), etc.

[0026] Next, an exemplary embodiment of the ESD protection scheme is described with reference to the accompanying drawings.

[0027] Figure 1 A schematic diagram of a semiconductor die 100 according to one embodiment is illustrated. The semiconductor die 100 includes a power transistor Q_main formed in a semiconductor substrate. Since Figure 1 is a schematic representation of the semiconductor die 100, the semiconductor substrate is not shown in Figure 1 . The semiconductor substrate may include one or more semiconductor materials for forming semiconductor devices such as power MOSFETs, IGBTs, JFETs, etc. For example, the semiconductor substrate may include silicon, silicon carbide (SiC), germanium (Ge), silicon germanium (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), etc. The semiconductor substrate may be a bulk semiconductor material or may include one or more epitaxial layers grown on a bulk semiconductor material.

[0028] The current sensing device 102 is formed in a semiconductor substrate and occupies less semiconductor substrate area than the power transistor Q_main. The current sensing device 102 is schematically illustrated as an auxiliary part of the power transistor Q_main in Figure 1 In physical form, the current sensing device 102 may have the same transistor cell structure as the power transistor Q_main, but the current sensing unit occupies less semiconductor substrate area than the power transistor unit. For example, the area ratio of the current sensing device 102 to the power transistor Q_main may be about 1:10000. However, this is just an example, and higher or lower area ratios are possible.

[0029] In each case, the semiconductor die 100 includes a first load terminal contact pad 'E' electrically connected to the first load terminal 'Em' of the power transistor Q_main and a second (current sensing) contact pad 'CS' electrically connected to the sensing terminal 'Es' of the current sensing device 102. In the case of an IGBT transistor, the first load terminal Em of the power transistor Q_main is the emitter terminal, and the sensing terminal Es of the current sensing device 102 is the emitter terminal. For a MOSFET, the first load terminal Em of the power transistor Q_main is the source terminal, and the sensing terminal Es of the current sensing device 102 is the source terminal.

[0030] As used herein, the term "contact pad" refers to an exposed metallized area of the semiconductor die 100 that is configured for external contact, e.g., by a probe of a test system or by an external electrical contact such as one or more bond wires, (one or more) metal strips, (one or more) metal clips, (one or more) solder balls, (one or more) copper pillars, etc. In other words, the contact pads of the semiconductor die 100 provide external electrical contact points for devices (such as the power transistor Q_main and the current sensing device 102) integrated in the semiconductor die 100.

[0031] The current sensing contact pad CS electrically connected to the sensing terminal Es of the current sensing device 102 is dedicated only to current sensing. That is, temperature sensing, if available at the semiconductor die 100, is achieved through a contact pad different from the current sensing contact pad CS electrically connected to the sensing terminal Es of the current sensing device 102. Thus, the current sensing contact pad CS is not a shared contact pad.

[0032] For example, as Figure 1 shown, a temperature sensing device 104 such as an anti-parallel diode may be integrated in the semiconductor die 100 together with the power transistor Q_main and the current sensing device 102. In Figure 1In [the circuit], two additional (temperature-sensing) contact pads 'Ta' and 'Tc' are electrically connected to corresponding terminals of the temperature-sensing device 104. The current-sensing device 102 is electrically and physically isolated from the temperature-sensing device 104, and the temperature-sensing contact pads Ta and Tc that are electrically connected to the terminals of the temperature-sensing device 104 are dedicated solely to temperature sensing.

[0033] Regardless of whether the semiconductor die 100 includes an integrated temperature-sensing device 104, the semiconductor die 100 has a resistive and / or diode-like connection 106 between the sensing terminal Es of the current-sensing device 102 and the first load terminal Em of the power transistor Q_main, where "diode-like" means belonging to or acting as a diode, and "resistive" means tending to or characterized by resistance. The resistive and / or diode-like connection 106 can be a purely resistive connection, a purely diode-like connection, or both a resistive connection and a diode-like connection.

[0034] By providing an ESD discharge path to the first load terminal Em of the power transistor Q_main that can be connected to AC ground, the resistive and / or diode-like connection 106 is designed specifically for ESD (electrostatic discharge) protection of the current-sensing device 102. The ESD discharge path enabled by the resistive and / or diode-like connection 106 is a controlled connection that is enabled during an ESD event at the sensing terminal Es of the current-sensing device 102.

[0035] As explained above, the current-sensing device 102 occupies less semiconductor substrate area than the power transistor Q_main. Therefore, in the event of an ESD, the current-sensing device 102 has a relatively lower charge storage capacity compared to the power transistor Q_main. The resistive and / or diode-like connection 106 protects the current-sensing device 102 by providing an ESD discharge path to the first load terminal Em of the power transistor Q_main.

[0036] In the case where both the current-sensing device 102 and the power transistor Q_main are IGBT devices, the main emitter portion of the power transistor Q_main has a significantly larger capacitance and thus a larger charge storage capacity compared to the emitter portion of the current-sensing device 102. By providing an ESD discharge path from the sensing terminal Es of the current-sensing device 102 to the emitter terminal Em of the power transistor Q_main via the resistive and / or diode-like connection 106, the ESD event is safely discharged into the main emitter portion of the power transistor Q_main.

[0037] The semiconductor die 100 has additional contact pads, such as an auxiliary contact pad “Ea” electrically connected to the first load terminal Em of the power transistor Q_main to implement, for example, Kelvin sensing, a contact pad “C” electrically connected to the second load terminal Cm of the power transistor Q_main, and a contact pad “G” electrically connected to the gate terminal Gm of both the power transistor Q_main and the current sensing device 102. In the case of an IGBT transistor, the second load terminal Cm of the power transistor Q_main is the collector terminal. For a MOSFET, the second load terminal Cm of the power transistor Q_main is the drain terminal. As Figure 1 indicated, the power transistor Q_main and the current sensing device 102 may share the gate connection and the second load terminal connection.

[0038] Figure 2 FIG. illustrates a schematic diagram of a semiconductor die 100 according to another embodiment. In Figure 2 this case, the temperature sensing device 104 and the auxiliary load terminal of the power transistor Q_main share the contact pad ‘Ea / Tc’. Doing so reduces the number of contact pads of the semiconductor die 100 by one. However, the current sensing contact pad CS electrically connected to the sensing terminal Es of the current sensing device 102 remains dedicated only to current sensing. Temperature sensing is still achieved through contact pads Ta, Ea / Tc different from the current sensing contact pad CS electrically connected to the sensing terminal Es of the current sensing device 102, ensuring that the current sensing contact pad CS is not a shared contact pad.

[0039] Figure 3 FIG. illustrates a schematic diagram of a semiconductor die 100 according to another embodiment. In Figure 3 this case, a resistive and / or diode-like connection 106 is implemented as a resistive (linear ohmic) connection with a resistance value ‘R’ such that the current leakage Ir between the sensing terminal Es of the current sensing device 102 and the first load terminal Em of the power transistor Q_main is at most one tenth of the current Is sensed by the current sensing device 102 in the on-state of the power transistor Q_main.

[0040] By selecting a resistance value R such that Is / Ir > 10, the ESD discharge path is activated under ESD stress conditions, and the sense terminal Es of the current sensing device 102 is coupled to the first load terminal Em of the power transistor Q_main to provide an additional charge storage reservoir, dissipate the ESD charge injection, and thus improve the ESD durability of the current sensing device 102 at the current sensing contact pad CS. In the off state of the power transistor Q_main, both the current sensing contact pad CS and the first load terminal contact pad E are grounded, and thus there is no leakage between the sense terminal Es of the current sensing device 102 and the first load terminal Em of the power transistor Q_main.

[0041] Figure 4 FIG. illustrates a schematic diagram of a resistive and / or diode-connected 106 according to another embodiment. In Figure 4 this, the resistive and / or diode-connected 106 is implemented as a diode (non-linear ohmic) connection that electrically isolates the sense terminal Es of the current sensing device 102 and the first load terminal Em of the power transistor Q_main for a voltage difference between the terminals Es and Em below the threshold, and electrically shorts the terminals Es and Em for a voltage difference between the terminals Es and Em above the threshold. If the diode connection is implemented using a polysilicon diode, for 1 diode, the threshold is: 0.7V at room temperature, and for Si, between 0.3 and 0.4V at 200 degrees Celsius.

[0042] In Figure 4 this, the diode connection includes a pair of diodes 200, 202, such as TVS (transient voltage suppression) diodes, which are coupled anode-to-anode between the sense terminal Es of the current sensing device 102 and the first load terminal Em of the power transistor Q_main to approximate a Zener diode, where the breakdown region defines the protection. Conversely, the TVS diodes 200, 202 can be coupled in a cathode-to-cathode configuration.

[0043] In any case, for small voltage differences, the TVS diodes 200, 202 provide isolation (“blocking effect”) between the current sensing contact pad CS of the semiconductor die 100 and the first load terminal contact pad E, but for high voltage pulses, such as those expected from ESD stress, short the current sensing contact pad CS (“shorting effect”) to the first load terminal contact pad E. When the potential at the current sensing contact pad CS of the semiconductor die 100 is high enough (positive or negative) relative to the first load contact pad E, one of the TVS diodes 200, 202 breaks down at a specific voltage. When the voltage pulse applied to the current sensing contact pad CS exceeds this breakdown voltage plus the pn junction voltages of the other TVS diodes 202, 200, the diode connection becomes a short circuit, dispersing the ESD charge injection and thus improving the ESD durability of the current sensing device 102 at the current sensing contact pad CS. The threshold separating the “blocking effect” from the “shorting effect” between the sensing terminal Es of the current sensing device 102 and the first load terminal Em of the power transistor Q_main is defined by the breakdown voltages of the diodes 200, 202, since in Figure 4 the illustrated embodiment the diodes 200, 202 face each other. More than two TVS diodes 200, 202 can be used to form the diode connection.

[0044] Figure 5 FIG. illustrates a schematic diagram of a resistive and / or diode connection 106 according to another embodiment. In Figure 5 it, the resistive and / or diode connection 106 is implemented as a diode connection formed by electrically connecting a single first diode 200 and a single second diode 202 back-to-back ( Figure 5 anode-to-anode in) between the sensing terminal Es of the current sensing device 102 and the first load terminal Em of the power transistor Q_main.

[0045] Figure 6 FIG. illustrates a schematic diagram of a resistive and / or diode connection 106 according to another embodiment. In Figure 6 it, the resistive and / or diode connection 106 is implemented as a diode connection formed by electrically connecting two or more first diodes 200 and two or more second diodes 202 in an anti-parallel manner between the sensing terminal Es of the current sensing device 102 and the first load terminal Em of the power transistor Q_main. In Figure 5 and 6In this case, the threshold for separating the "blocking effect" and the "short - circuit effect" between the sensing terminal Es of the current sensing device 102 and the first load terminal Em of the power transistor Q_main is defined by the forward voltage of the pn junctions of the diodes 200 and 202. In another embodiment, the resistive and / or diode - type connection 106 can be implemented using a single diode 200 and two or more anti - parallel diodes 202, or as two or more serially - connected diodes 200 and a single anti - parallel diode 202.

[0046] Figure 7 FIG. illustrates a schematic diagram of an over - current detection circuit 300 that is used to detect when the current mirrored by the current sensing device 102 included in the semiconductor die 100 exceeds a threshold limit. The over - current detection circuit 300 includes a sense resistor Rs, the voltage across which corresponds to the current sensed by the current sensing device 102 included in the semiconductor die 100. The over - current detection circuit 300 further includes a low - pass filter (LPF) 302 and a comparator 304, the comparator 304 having a reference voltage Vref and the output of the LPF 302 as inputs. When the output of the LPF 302 exceeds the reference voltage Vref, which indicates an over - current condition, the output of the comparator 304 is enabled or activated.

[0047] During normal operation, the voltage drop across the sense resistor Rs of the over - current detection circuit 300 is typically less than 1V, such that during normal operation, no difference exceeding 1V appears between the current sensing contact pad CS and the first load terminal contact pad E of the semiconductor die 100. Since the pn - junction forward voltage decreases with temperature, a sufficient number of pn junctions can be used to safely ensure at least 1V (e.g., up to 1.5V) isolation from, for example, - 40°C to 185°C. For a TVS diode, an appropriate breakdown voltage value can be designed such that a single TVS diode is sufficient across a voltage range covering the entire temperature range of interest.

[0048] Therefore, for Figures 4 to 6 the diode - type connection embodiment shown, isolation up to 1.5V should be sufficient to ensure isolation between the current sensing contact pad CS and the first load terminal contact pad E of the semiconductor die 100 only within the input dynamic range (e.g., 500mV to 1V) of the comparator 304. Even 1V isolation should be sufficient. The diode - type connection becomes short - circuited outside the input dynamic range of the comparator 304, dissipating ESD charge injection and thus improving the ESD durability of the current sensing device 102 at the current sensing contact pad CS.

[0049] Exemplary implementations of resistive and / or diode-like connections 106 included in semiconductor die 100 are described next. In some examples, the resistive and / or diode-like connection 106 is a purely resistive connection. In other examples, the resistive and / or diode-like connection 106 is a purely diode-like connection. In still other examples, the resistive and / or diode-like connection 106 is both a resistive connection and a diode-like connection. The examples of the resistive and / or diode-like connection 106 described below are explained in the context of an IGBT power transistor, but are equally applicable to other power transistor types, such as power MOSFETs, JFETs, etc.

[0050] Figure 8 A top view of semiconductor die 100 in a region where current sensing device 102 is adjacent to power transistor Q_main is illustrated. Current sensing contact pad CS and first load terminal contact pad E of semiconductor die 100 are visible Figure 8 therein, as contact pads CS, E are exposed metallization regions configured for external contact. An insulating layer 400, such as an interlayer dielectric or field oxide, is also shown Figure 8 therein, in the gap between contact pads CS, E. Figure 8 The lower portion of Figure 8 shows an enlarged plan view of semiconductor die 100 below contact pads CS, E and insulating layer 400. In one embodiment, current sensing device 102 is laterally interposed between a first portion 401 and a second portion 403 of power transistor Q_main such that current sensing device 102 is adjacent to the first portion 401 of power transistor Q_main on a first side of current sensing device 102 and is adjacent to the second portion 403 of power transistor Q_main on a second side of current sensing device 102 different from the first side. In

[0051] Furthermore, in Figure 8 a trench structure 402 laterally separates a first region 404 of semiconductor substrate 406 including power transistor Q_main from a second region 408 of semiconductor substrate 406 including current sensing device 102. Figure 9 A cross-sectional view along line A-A' marked in Figure 8 is illustrated.

[0052] The trench structure 402 can laterally surround the second region 408 of the semiconductor substrate 406 on one or more sides. The gate trench 410, which forms part of the transistor cell of the power transistor Q_main, can laterally branch from the trench structure 402 into the first region 404 of the semiconductor substrate 406, where one or more source or emitter trenches 411 are optionally staggered between the power transistor gate trenches 410. The gate trench 412, which forms part of the cell of the current sensing device 102, can laterally branch from the trench structure 402 into the second region 408 of the semiconductor substrate 406, where one or more source or emitter trenches 413 are optionally staggered between the sensing device gate trenches 412. The source or emitter trench 413 of the current sensing device 102 includes a contact 414 for electrical connection to the current sensing contact pad CS. The gate trenches 410, 412 include gate electrodes that are electrically insulated from the semiconductor substrate 406 and electrically connected to the contact pad G of the semiconductor die. The gate contact pad G and the gate electrodes are not visible in Figure 8 and 9 in.

[0053] The device cell also includes a contact 416 to an emitter region of the first conductivity type, which is formed in a body region 418 of a second conductivity type opposite to the first conductivity type. The emitter region is not visible in Figure 8 and Figure 9 in. The emitter regions of the power transistor cell together form the first load terminal Em of the power transistor Q_main, while the emitter regions of the sensing unit together form the sensing terminal Es of the current sensing device 102. The power transistor Q_main has more cells than the current sensing device 102 and thus has a larger emitter area (e.g., a power transistor to current sensing emitter area ratio of 10000:1), such that the emitter area of the power transistor Q_main has a larger charge storage capacity for ESD energy than the emitter area of the current sensing device 102.

[0054] For a power MOSFET or JFET cell, alternatively, the region of the first conductivity type formed in the body region 418 is the source region. A drift region 420 of the first conductivity type is provided below the body region 418, and a collector region 422 (or the drain region of the power MOSFET or JFET) is provided below the drift region 420. An optional region 423 of the first conductivity type can be implanted below the body region 418 as a type of barrier or carrier storage layer. The peak doping concentration of the optional barrier / carrier storage layer 423 is at least 10 times greater than the peak doping concentration of the drift region 420. The optional barrier / carrier storage layer 423 can be used to increase carrier confinement in the drift region 420.

[0055] For an n-channel device, the first conduction type is n-type and the second conduction type is p-type, while for a p-channel device, the first conduction type is p-type and the second conduction type is n-type. The gate electrode 414, emitter / source region, and body region 418 of the power transistor unit are not visible in Figure 8 because only the termination portion of the gate trench 410 of the power transistor unit is illustrated.

[0056] In Figure 8 and 9 the resistive and / or diode-like connection 106 includes a gap 424 in the trench structure 402 through which the sense terminal Es of the current sensing device 102 is electrically connected to the first load terminal Em of the power transistor Q_main. Figure 9 The semiconductor substrate 406 in the region of one of the gaps 424 in the trench structure 402 is illustrated. As Figure 9 shown, a body region 418 of the second conduction type is disposed in the gap 424 in the trench structure 402. A more heavily doped semiconductor material 426 of the second conduction type (e.g., p+ for an n-channel device or n+ for a p-channel device) and / or a more heavily doped semiconductor material 428 of the first conduction type (e.g., n+ for an n-channel device or p+ for a p-channel device) may also fill the gap 424 in the trench structure 402 above the body region 418 of the second conduction type.

[0057] If only the semiconductor material of the second conduction type fills the gap 424 in the trench structure 402, the resistive and / or diode-like connection 106 is a resistive connection formed by the body region 418 of the second conduction type. In one embodiment, the resistive connection formed by a portion of the body region 418 of the second conduction type that fills the gap 424 in the trench structure 402 has an equivalent resistance of approximately 400 ohms. The inventors have observed that the resistive connection formed by a portion of the body region 418 of the second conduction type that fills the gap 424 in the trench structure 402 has no negative impact on the current sensor function for overcurrent / short-circuit detection compared to a reference design in which there is no gap in the trench structure 402 between a first region 404 of the semiconductor substrate 406 including the power transistor Q_main and a second region 408 of the semiconductor substrate 406 including the current sensing device 102.

[0058] If the heavily doped semiconductor material 426 of the second conductivity type and the heavily doped semiconductor material 428 of the first conductivity type also fill the gap 424 in the trench structure 402, the resistive and / or diode connection 106 includes a resistive connection formed by the body region 418 of the second conductivity type in parallel with a diode connection formed by the junction of the heavily doped semiconductor material 426 of the second conductivity type and the heavily doped semiconductor material 428 of the first conductivity type. If the heavily doped p-type semiconductor material 426 of the second conductivity type is present at the surface, the heavily doped semiconductor material 428 of the first conductivity type can be formed. In this case, the heavily doped n-type semiconductor material 428 of the first conductivity type is provided to avoid too low a resistance between the current sensing contact pad CS and the first load terminal contact pad. In one embodiment, the number and size (e.g., length, width, depth, etc.) of the gaps 424 in the trench structure 402 are designed such that the current leakage Ir between the sensing terminal Es of the current sensing device 102 and the first load terminal Em of the power transistor Q_main is at most one-tenth of the current Is sensed by the current sensing device 102 in the on state of the power transistor Q_main.

[0059] Figure 10 A top view of the semiconductor die 100 in the region adjacent to the current sensing device 102 and the power transistor Q_main according to another embodiment is illustrated. In Figure 10 this, the outline of the first load terminal contact pad E of the semiconductor die 100 is illustrated using a bent solid line, and the outline of the current sensing contact pad CS is illustrated using a bent dashed line to provide an unobstructed view of the underlying components. Also in Figure 10 this, the resistive and / or diode connection 106 includes one or more doped polysilicon resistors 500 through which the sensing terminal Es of the current sensing device 102 is electrically connected to the first load terminal Em of the power transistor Q_main.

[0060] One or more first conductive vias 502 can electrically connect each doped polysilicon resistor 500 to the first load terminal contact pad E of the semiconductor die 100. One or more second conductive vias 504 can electrically connect each doped polysilicon resistor 500 to the current sensing contact pad CS of the semiconductor die 100.

[0061] Each doped polysilicon resistor 500 can be separated from the front main surface of the semiconductor substrate 406 by an insulating layer 400, and each doped polysilicon resistor 500 can span the region of the semiconductor substrate 406 that separates the power transistor Q_main from the current sensing device 102. For example, the interface or transition region of the semiconductor substrate 406 that separates the power transistor Q_main from the current sensing device 102 can includeFigure 8 the trench structure 402 shown, but without the gap 424. In this embodiment, each polysilicon resistor 500 is electrically connected to the sense terminal Es of the current sensing device 102 through one or more third conductive vias ( Figure 10 not visible in), which extend through the insulating layer 400 formed above the semiconductor substrate 102 and reach or enter the emitter region of the current sensing device unit. Each polysilicon resistor 500 is electrically connected to the first load terminal Em of the power transistor Q_main through one or more fourth conductive vias (also not visible in Figure 10 ), which extend through the insulating layer 400 formed above the semiconductor substrate 102 and reach or enter the emitter region of the power transistor device unit.

[0062] In Figure 10 , the resistive and / or diode-like connection 106 includes one or more first doped polysilicon resistors 500_1 and one or more second doped polysilicon resistors 500_2. The first doped polysilicon resistor 500_1 spans the first region 506 of the semiconductor substrate 406 that separates the current sensing device 102 from the first portion 508 of the power transistor Q_main. The second doped polysilicon resistor 500_2 spans the second region 510 of the semiconductor substrate 406 that separates the current sensing device 102 from the second portion 512 of the power transistor Q_main. Each first doped polysilicon resistor 500_1 is electrically connected to the first load terminal contact pad E of the semiconductor die 100 above the first portion 508 of the power transistor Q_main through a first conductive via 502_1, and is electrically connected to the current sensing contact pad CS of the semiconductor die 100 above the current sensing device 102 through a second conductive via 504_1. Each second doped polysilicon resistor 500_2 is electrically connected to the first load terminal contact pad E of the semiconductor die 100 above the second portion 512 of the power transistor Q_main through a first conductive via 502_2, and is electrically connected to the current sensing contact pad CS of the semiconductor die 100 above the current sensing device 102 through a second conductive via 504_2.

[0063] Figure 11 FIG. shows a top view of the semiconductor die 100 in the region adjacent to the current sensing device 102 and the power transistor Q_main according to another embodiment. In Figure 11 , the resistive and / or diode-like connection 106 includes one or more doped polysilicon resistors 600, and the sense terminal Es of the current sensing device 102 is electrically connected to the first load terminal Em of the power transistor Q_main through the polysilicon resistor. Different from the embodiment shown in Figure 10 , Figure 11One or more doped polysilicon resistors 600 are disposed in a trench 602 formed in a front major surface of a semiconductor substrate 106. The trench 602 extends laterally from a region 408 of the semiconductor substrate 406 including the current sensing device 102 into a region 404 of the semiconductor substrate 406 including the power transistor Q_main.

[0064] Each doped polysilicon resistor 600 is electrically connected at a first end of the trench 602 to a first load terminal contact pad E of the semiconductor die 100, e.g., via a first conductive via extending through an insulating layer 400 formed over the semiconductor substrate 102 ( Figure 11 not shown). Each doped polysilicon resistor 600 is electrically connected at a second end of the trench 602 opposite the first end to a current sensing contact pad CS of the semiconductor die 100, e.g., via a second conductive via extending through the insulating layer 400 formed over the semiconductor substrate 102 ( Figure 11 not shown).

[0065] In Figure 11 , the resistive and / or diode-like connection 106 includes a first doped polysilicon resistor 600_1 disposed in a first trench 602_1 formed in a front major surface of the semiconductor substrate 406 and extending laterally from a region of the semiconductor substrate 406 including a first portion 508 of the power transistor Q_main into a region of the semiconductor substrate 406 including the current sensing device 102. The resistive and / or diode-like connection 106 further includes a second doped polysilicon resistor 600_2 disposed in a second trench 602_2 formed in the front major surface of the semiconductor substrate 406 and extending laterally from a region of the semiconductor substrate 406 including a second portion 512 of the power transistor Q_main into a region of the semiconductor substrate 406 including the current sensing device 102. The first doped polysilicon resistor 600_1 is electrically connected to the first load terminal contact pad E of the semiconductor die 100 over the first portion 508 of the power transistor Q_main and is electrically connected to the current sensing contact pad CS of the semiconductor die 100 over the current sensing device 102. The second doped polysilicon resistor 600_2 is electrically connected to the first load terminal contact pad E of the semiconductor die 100 over the second portion 512 of the power transistor Q_main and is electrically connected to the current sensing contact pad CS of the semiconductor die 100 over the current sensing device 102.

[0066] Figure 12A FIG. illustrates a schematic diagram of a semiconductor die 100 according to another embodiment, and Figure 12B FIG. illustrates a corresponding top view of the semiconductor die 100 in a region where the current sensing device 102 abuts the power transistor Q_main. InFigure 12A and 12B In, the resistive and / or diode connection 106 includes a first diode 700 electrically connected between the sense terminal Es of the current sensing device 102 and the first load terminal Em of the power transistor Q_main, and a second diode 702 anti-parallel to the first diode 700. The diodes 700, 702 may be implemented as polysilicon diodes, for example, as Figure 12B shown. During the off state of the main power transistor Q_main, the diodes 700, 702 provide isolation between the current sensing contact pad CS and the first load terminal contact pad E of the semiconductor die 100 until a voltage imbalance of at least + / -0.65V. The isolation can be increased by using two or more diodes in series for Figure 12A each of the first diode 700 and the second diode 702 as shown.

[0067] In Figure 12B In, the resistive and / or diode connection 106 includes a first polysilicon pn diode 700_1 formed in a first polysilicon island 704_1, the first polysilicon island 704_1 being separated from the semiconductor substrate 406 by an insulating layer 400 and spanning a first region 506 of the semiconductor substrate 406 that separates the current sensing device 102 from a first portion 508 of the power transistor Q_main. A second polysilicon pn diode 702_1 anti-parallel to the first pn diode 700_1 is formed in a second polysilicon island 704_2, the second polysilicon island 704_2 being separated from the semiconductor substrate 406 by an insulating layer 400. The resistive and / or diode connection 106 further includes another first polysilicon pn diode 700_2 formed in a third polysilicon island 704_3, the third polysilicon island 704_3 being separated from the semiconductor substrate 406 by an insulating layer 400 and spanning a second region 510 of the semiconductor substrate 406 that separates the current sensing device 102 from a second portion 512 of the power transistor Q_main. A second polysilicon pn diode 702_2 anti-parallel to the first pn diode 700_2 is formed in a fourth polysilicon island 704_4, the fourth polysilicon island 704_4 being separated from the semiconductor substrate 406 by an insulating layer 400.

[0068] The anode (or cathode) of the first polysilicon pn diode 700_1 spanning the first region 506 of the semiconductor substrate 406 and the cathode (or anode) of the anti-parallel second polysilicon pn diode 702_1 are both electrically connected through the first conductive via 706_1 to the first load terminal contact pad E of the semiconductor die 100 above the first portion 508 of the power transistor Q_main. The cathode (or anode) of the first polysilicon pn diode 700_1 spanning the first region 506 of the semiconductor substrate 406 and the anode (or cathode) of the anti-parallel second polysilicon pn diode 702_1 are both electrically connected through the second conductive via 708_1 to the current sensing contact pad CS of the semiconductor die 100 above the current sensing device 102.

[0069] The cathode (or anode) of the first polysilicon pn diode 700_2 spanning the second region 510 of the semiconductor substrate 406 and the anode (or cathode) of the anti-parallel second polysilicon pn diode 702_2 are both electrically connected through the first conductive via 706_2 to the first load terminal contact pad E of the semiconductor die 100 above the second portion 512 of the power transistor Q_main. The anode (or cathode) of the first polysilicon pn diode 700_2 spanning the second region 510 of the semiconductor substrate 406 and the cathode (or anode) of the anti-parallel second polysilicon pn diode 702_2 are both electrically connected through the second conductive via 708_2 to the current sensing contact pad CS of the semiconductor die 100 above the current sensing device 102.

[0070] Figure 13A A schematic diagram of a semiconductor die 100 according to another embodiment is illustrated, and Figure 13B A corresponding top view of the semiconductor die 100 in the region where the current sensing device 102 is adjacent to the power transistor Q_main is illustrated. In Figure 13A and 13B the resistive and / or diode-like connection 106 includes at least two serially connected first diodes 800 electrically connected between the sensing terminal Es of the current sensing device 102 and the first load terminal Em of the power transistor Q_main, and at least two serially connected second diodes 802 anti-parallel to the at least two serially connected first diodes 800. During the off state of the main power transistor Q_main, the serially connected diodes 800, 802 provide isolation between the current sensing contact pad CS and the first load terminal contact pad E of the semiconductor die 100 until a voltage imbalance of at least + / -1.3V. The isolation can be increased by using more than two series diodes for Figure 13A each of the serially connected diodes 800, 802 shown.

[0071] In Figure 13BAmong them, at least two first diodes 800 connected in series are formed in a separate first polysilicon island 804, the first polysilicon island 804 is separated from the semiconductor substrate 406 by an insulating layer 400, and is connected in series electrically through a metallization structure 806 disposed above the first polysilicon island 804. At least two second diodes 802 connected in series are formed in a separate second polysilicon island 806, the second polysilicon island 806 is separated from the semiconductor substrate 406 by an insulating layer 400, and is connected in series electrically through a metallization structure 808 disposed above the second polysilicon island 806.

[0072] In Figure 13B Among them, the first 800_1 of at least two first diodes 800 connected in series formed in the first 804_1 of the first polysilicon island 804 and the first 802_1 of at least two second diodes 802 connected in series formed in the first 806_1 of the second polysilicon island 806 straddle a first region 506 of the semiconductor substrate 406, and this first region 506 separates the current sensing device 102 from the first part 508 of the power transistor Q_main. The second 800_2 of at least two first diodes 800 connected in series formed in the second 804_2 of the first polysilicon island 804 is connected in series with the first 800_1 of at least two first diodes 800 through a first metallization structure 806, and the second 802_2 of at least two second diodes 802 connected in series formed in the second 806_2 of the second polysilicon island 806 is connected in series with the first 802_1 of at least two second diodes 802 through a second metallization structure 808.

[0073] The third 800_3 of at least two serially-connected first diodes 800 formed in the third 804_3 of the first polysilicon island 804 and the third 802_3 of at least two serially-connected second diodes 802 formed in the third 806_3 of the second polysilicon island 806 span a second region 510 of the semiconductor substrate 406, which separates the current sensing device 102 from the second part 512 of the power transistor Q_main. The fourth 800_4 of at least two serially-connected first diodes 800 formed in the fourth 804_4 of the first polysilicon island 804 is serially connected to the third 800_3 of at least two serially-connected first diodes 800 through a third metallization structure 810, and the fourth 802_4 of at least two serially-connected second diodes 802 formed in the fourth 806_4 of the second polysilicon island 806 is serially connected to the third 802_3 of at least two serially-connected second diodes 802 through a fourth metallization structure 812. Electrical connections between the diodes 800, 802 and the overlying metal structures E, CS, 806, 808, 810, 812 are formed by corresponding conductive vias 814. In Figure 13B only the outlines of the first load terminal contact pad E, the current sensing contact pad CS of the semiconductor die 100, and the metallization structures 806, 808, 810, 812 interconnecting the diodes 800, 802 are illustrated to provide an unobstructed view of the underlying components.

[0074] Figure 14A A schematic diagram of a semiconductor die 100 according to another embodiment is illustrated, and Figure 14B a corresponding top view of the semiconductor die 100 in the region where the current sensing device 102 is adjacent to the power transistor Q_main is illustrated. In Figure 14A and 14B the resistive and / or diode-like connection 106 includes two or more diodes 900, 902, which are electrically connected in a Zener configuration between the sensing terminal Es of the current sensing device 102 and the first load terminal Em of the power transistor Q_main. The diodes 900, 902 can be implemented as polysilicon diodes, for example, as Figure 14B shown. During the off state of the main power transistor Q_main, the Zener-configured diodes 900, 902 provide isolation greater than + / - 0.65V (e.g., for a single diode implementation at room temperature) between the current sensing contact pad CS and the first load terminal contact pad E of the semiconductor die 100. The Zener isolation comes from reverse breakdown. Thus, the isolation value does not necessarily have to be a multiple of + / - 0.65V (at room temperature), but the breakdown location can be designed at other voltages.

[0075] In Figure 14BIn [the figure], diodes 900, 902 electrically connected in Zener configuration are implemented as two (2) first polysilicon pnp (or npn) diodes 904_1, 904_2 that span a first region 506 of semiconductor substrate 406, which separates current sensing device 102 from a first portion 508 of power transistor Q_main. Two (2) second polysilicon pnp (or npn) diodes 906_1, 906_2 span a second region 510 of semiconductor substrate 406, which separates current sensing device 102 from a second portion 512 of power transistor Q_main. Each pnp (or npn) diode is formed in a respective polysilicon island 908, which is separated from semiconductor substrate 406 by insulating layer 400. Electrical connections between diodes 900, 902 and overlying metal structures E, CS are formed by respective conductive vias 910.

[0076] Figure 15 illustrates according to another embodiment Figure 14B a schematic diagram of one of the diodes 900, 902 in the Zener configuration shown. In Figure 15 [the figure], each half of the diodes 900, 902 in Zener configuration includes two series-connected pn diodes, where the innermost two pn diodes share a common cathode to implement the Zener configuration. The diodes 900, 902 in Zener configuration may be formed in a polysilicon island 1000, which is separated from semiconductor substrate 406 by insulating layer 400.

[0077] Although the present disclosure is not limited thereto, the following numbered examples illustrate one or more aspects of the present disclosure.

[0078] Example 1. A semiconductor die, comprising: a semiconductor substrate; a power transistor formed in the semiconductor substrate; a current sensing device formed in the semiconductor substrate and occupying less semiconductor substrate area than the power transistor; a first contact pad electrically connected to a first load terminal of the power transistor; a second contact pad electrically connected to a sensing terminal of the current sensing device, where the second contact pad is dedicated solely to current sensing; and a resistive and / or diode-like connection between the sensing terminal of the current sensing device and the first load terminal of the power transistor, where the resistive and / or diode-like connection is designed separately for electrostatic discharge (ESD) protection of the current sensing device by providing an ESD discharge path to the first load terminal of the power transistor.

[0079] Example 2. The semiconductor die according to Example 1, further comprising: a temperature sensing device; and a third contact pad electrically connected to a terminal of the temperature sensing device, where the current sensing device is electrically and physically isolated from the temperature sensing device, and where the third contact pad is dedicated solely to temperature sensing.

[0080] Example 3. The semiconductor die according to Example 1 or 2, wherein the resistive and / or diode-like connection comprises a resistive connection having a resistance value such that the current leakage between the sense terminal of the current sensing device and the first load terminal of the power transistor is at most one tenth of the current sensed by the current sensing device in the on state of the power transistor.

[0081] Example 4. The semiconductor die according to any one of Examples 1 to 3, wherein the resistive and / or diode-like connection comprises a diode-like connection that electrically isolates the terminals for a voltage difference between the terminals below a threshold and electrically shorts the terminals for a voltage difference between the terminals above a threshold.

[0082] Example 5. The semiconductor die according to any one of Examples 1 to 4, wherein a trench structure laterally separates a first region of the semiconductor substrate including the power transistor from a second region of the semiconductor substrate including the current sensing device, and wherein the resistive and / or diode-like connection comprises a plurality of gaps in the trench structure, and the sense terminal of the current sensing device is electrically connected to the first load terminal of the power transistor through the gaps.

[0083] Example 6. The semiconductor die according to Example 5, wherein the gaps in the trench structure are filled with p-type semiconductor material and / or n-type semiconductor material.

[0084] Example 7. The semiconductor die according to Example 6, wherein the power transistor is an IGBT (Insulated Gate Bipolar Transistor), wherein the current sensing device is an IGBT, wherein the first load terminal of the power transistor is the emitter terminal, wherein the sense terminal of the current sensing device is the emitter terminal, and wherein the emitter terminals of the power transistor and the current sensing device are electrically connected to each other through the p-type semiconductor material and / or n-type semiconductor material filling the gaps in the trench structure.

[0085] Example 8. The semiconductor die according to any one of Examples 5 to 7, wherein the number and size of the gaps in the trench structure are designed such that the current leakage between the sense terminal of the current sensing device and the first load terminal of the power transistor is at most one tenth of the current sensed by the current sensing device in the on state of the power transistor.

[0086] Example 9. The semiconductor die according to any one of Examples 1 to 8, wherein the resistive and / or diode-like connection comprises: one or more doped polysilicon resistors, and the sense terminal of the current sensing device is electrically connected to the first load terminal of the power transistor through the doped polysilicon resistors.

[0087] Example 10. The semiconductor die according to Example 9, wherein one or more first conductive vias electrically connect one or more doped polysilicon resistors to a first contact pad, and wherein one or more second conductive vias electrically connect one or more doped polysilicon resistors to a second contact pad.

[0088] Example 11. The semiconductor die according to Example 9 or 10, wherein the one or more doped polysilicon resistors are separated from a first major surface of the semiconductor substrate by an insulating layer, and wherein each of the one or more doped polysilicon resistors spans a region of the semiconductor substrate that separates the power transistor from the current sensing device.

[0089] Example 12. The semiconductor die according to Example 9, wherein one or more doped polysilicon resistors are disposed in a plurality of trenches formed in a first major surface of the semiconductor substrate, wherein the plurality of trenches extend laterally from a first region of the semiconductor substrate including the current sensing device into a second region of the semiconductor substrate including the power transistor, wherein the one or more doped polysilicon resistors are electrically connected to a first contact pad at a first end of the plurality of trenches, and wherein the one or more doped polysilicon resistors are electrically connected to a second contact pad at a second end of the plurality of trenches opposite the first end.

[0090] Example 13. The semiconductor die according to any one of Examples 1 to 12, wherein the current sensing device is laterally interposed between a first portion of the power transistor and a second portion of the power transistor, such that the current sensing device abuts the first portion of the power transistor on a first side of the current sensing device and abuts the second portion of the power transistor on a second side of the current sensing device different from the first side.

[0091] Example 14. The semiconductor die according to Example 13, wherein: the resistive and / or diode-like connection includes one or more first doped polysilicon resistors that span a first region of the semiconductor substrate that separates the current sensing device from the first portion of the power transistor; the resistive and / or diode-like connection further includes one or more second doped polysilicon resistors that span a second region of the semiconductor substrate that separates the current sensing device from the second portion of the power transistor; each of the one or more first doped polysilicon resistors is electrically connected to a first contact pad above the first portion of the power transistor and a second contact pad above the current sensing device; and each of the one or more second doped polysilicon resistors is electrically connected to a first contact pad above the second portion of the power transistor and a second contact pad above the current sensing device.

[0092] Example 15. The semiconductor die according to Example 13, wherein: the resistive and / or diode connection includes a first doped polysilicon resistor disposed in a plurality of first trenches formed in a first major surface of the semiconductor substrate, the plurality of first trenches extending laterally from a region of the semiconductor substrate including a first portion of the power transistor into a region of the semiconductor substrate including the current sensing device; the resistive and / or diode connection further includes a second doped polysilicon resistor disposed in a plurality of second trenches formed in the first major surface of the semiconductor substrate, and extending laterally from a region of the semiconductor substrate including a second portion of the power transistor into a region of the semiconductor substrate including the current sensing device; the first doped polysilicon resistor is electrically connected to a first contact pad above the first portion of the power transistor and a second contact pad above the current sensing device; and the second doped polysilicon resistor is electrically connected to the first contact pad above the second portion of the power transistor and the second contact pad above the current sensing device.

[0093] Example 16. The semiconductor die according to any one of Examples 1 to 15, wherein the resistive and / or diode connection includes: one or more first diodes electrically connected between a sensing terminal of the current sensing device and a first load terminal of the power transistor; and one or more second diodes anti-parallel to the one or more first diodes.

[0094] Example 17. The semiconductor die according to Example 16, wherein at least two serially connected first diodes are electrically connected between a sensing terminal of the current sensing device and a first load terminal of the power transistor, and wherein at least two serially connected second diodes are anti-parallel to the at least two serially connected first diodes.

[0095] Example 18. The semiconductor die according to Example 17, wherein the at least two serially connected first diodes are formed in a separate first polysilicon island separated from the semiconductor substrate by an insulating layer, wherein the at least two serially connected first diodes are serially electrically connected through a metallization structure disposed above the first polysilicon island, wherein the at least two serially connected second diodes are formed in a separate second polysilicon island separated from the semiconductor substrate by an insulating layer, and wherein the at least two serially connected second diodes are serially electrically connected through a metallization structure disposed above the second polysilicon island.

[0096] Example 19. The semiconductor die according to any one of Examples 1 to 18, wherein the resistive and / or diode connection includes: two or more diodes electrically connected in a Zener configuration between a sensing terminal of the current sensing device and a first load terminal of the power transistor.

[0097] Example 20. The semiconductor die according to any one of Examples 1 to 19, wherein the resistive and / or diode-like connection includes a diode-like connection in parallel with the resistive connection.

[0098] Example 21. A semiconductor die, comprising: a semiconductor substrate; an IGBT (insulated gate bipolar transistor) formed in the semiconductor substrate; a current sensing device formed in the semiconductor substrate and occupying less semiconductor substrate area than the IGBT; an emitter contact pad electrically connected to the emitter terminal of the IGBT; a current sensing contact pad electrically connected to the emitter terminal of the current sensing device, wherein the current sensing contact pad is dedicated only to current sensing; and a resistive and / or diode-like connection between the emitter terminal of the current sensing device and the emitter terminal of the IGBT, wherein the resistive and / or diode-like connection is designed separately for ESD (electrostatic discharge) protection of the current sensing device by providing an ESD discharge path to the emitter terminal of the IGBT.

[0099] Terms such as "first", "second", etc. are used to describe various elements, regions, sections, etc. And are not intended to be limiting. Throughout the specification, like terms refer to like elements.

[0100] As used herein, the terms "having", "containing", "including", "comprising", etc. are open terms indicating the presence of the element or feature, but not excluding additional elements or features. The articles "a", "an", and "the" are intended to include both the plural and the singular, unless the context clearly indicates otherwise.

[0101] Unless otherwise expressly stated, the expression "and / or" should be interpreted to include all possible conjunctive and disjunctive combinations. For example, the expression "A and / or B" should be interpreted to mean only A, only B, or both A and B. The expression "at least one of" should be interpreted in the same manner as "and / or", unless otherwise expressly stated. For example, the expression "at least one of A and B" should be interpreted to mean only A, only B, or both A and B.

[0102] It should be understood that, unless otherwise specifically stated, the features of the various embodiments described herein can be combined with each other.

[0103] Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that various alternative and / or equivalent implementations can be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Accordingly, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor die, comprising: Semiconductor substrate; A power transistor formed in a semiconductor substrate; a current sensing device formed in a semiconductor substrate and occupying less semiconductor substrate area than a power transistor; a first contact pad electrically connected to a first load terminal of the power transistor; a second contact pad electrically connected to a sense terminal of the current sensing device, wherein the second contact pad is dedicated only to current sensing; and a resistive and / or diode-like connection between a sensing terminal of the current sensing device and a first load terminal of the power transistor, The resistive and / or diode-like connection is designed solely for ESD (electrostatic discharge) protection of the current sensing device by providing an ESD discharge path to the first load terminal of the power transistor.

2. The semiconductor die of claim 1 , further comprising: Temperature sensing devices; and a third contact pad electrically connected to a terminal of the temperature sensing device, The current sensing device is electrically and physically isolated from the temperature sensing device. The third contact pad is only used for temperature sensing.

3. The semiconductor die of claim 1 , wherein the resistive and / or diode-like connection comprises a resistive connection having a resistance value such that a current leakage between a sensing terminal of the current sensing device and a first load terminal of the power transistor is at most one tenth of a current sensed by the current sensing device in an on-state of the power transistor.

4. The semiconductor die of claim 1 , wherein the resistive and / or diode-like connection comprises a diode-like connection that electrically isolates the terminals for a voltage difference between the terminals below a threshold and electrically shorts the terminals for a voltage difference between the terminals above a threshold.

5. The semiconductor die of claim 1 , wherein a trench structure laterally separates a first region of the semiconductor substrate comprising the power transistor from a second region of the semiconductor substrate comprising the current sensing device, and wherein the resistive and / or diode-like connections comprise a plurality of gaps in the trench structure through which a sensing terminal of the current sensing device is electrically connected to the first load terminal of the power transistor. 6 . The semiconductor die of claim 5 , wherein p-type semiconductor material and / or n-type semiconductor material fills gaps in the trench structure.

7. A semiconductor die according to claim 6, wherein the power transistor is an IGBT (Insulated Gate Bipolar Transistor), wherein the current sensing device is an IGBT, wherein the first load terminal of the power transistor is an emitter terminal, wherein the sensing terminal of the current sensing device is an emitter terminal, and wherein the emitter terminal of the power transistor and the emitter terminal of the current sensing device are electrically connected to each other through a p-type semiconductor material and / or an n-type semiconductor material filling a gap in the trench structure.

8. The semiconductor die of claim 5 , wherein the number and size of the gaps in the trench structure are designed so that a current leakage between a sensing terminal of the current sensing device and a first load terminal of the power transistor is at most one tenth of a current sensed by the current sensing device in an on-state of the power transistor.

9. The semiconductor die of claim 1 , wherein the resistive and / or diode-like connections include: One or more doped polysilicon resistors through which a sense terminal of the current sensing device is electrically connected to the first load terminal of the power transistor.

10. The semiconductor die of claim 9, wherein the one or more first conductive vias electrically connect the one or more doped polysilicon resistors to the first contact pad, and wherein the one or more second conductive vias electrically connect the one or more doped polysilicon resistors to the second contact pad.

11. The semiconductor die of claim 9, wherein the one or more doped polysilicon resistors are separated from the first major surface of the semiconductor substrate by an insulating layer, and wherein each of the one or more doped polysilicon resistors spans a region of the semiconductor substrate that separates the power transistor from the current sensing device.

12. The semiconductor die of claim 9 , wherein the one or more doped polysilicon resistors are disposed in a plurality of grooves formed in a first main surface of a semiconductor substrate, wherein the plurality of grooves extend laterally from a first region of the semiconductor substrate including a current sensing device to a second region of the semiconductor substrate including a power transistor, wherein the one or more doped polysilicon resistors are electrically connected to a first contact pad at a first end of the plurality of grooves, and wherein the one or more doped polysilicon resistors are electrically connected to a second contact pad at a second end of the plurality of grooves opposite to the first end.

13. The semiconductor die of claim 1 , wherein the current sensing device is laterally interposed between a first portion of the power transistor and a second portion of the power transistor such that the current sensing device abuts the first portion of the power transistor on a first side of the current sensing device and abuts the second portion of the power transistor on a second side of the current sensing device that is different from the first side.

14. The semiconductor die of claim 13, wherein: The resistive and / or diode-like connection includes one or more first doped polysilicon resistors across a first region of the semiconductor substrate, the first region separating the current sensing device from a first portion of the power transistor; The resistive and / or diode-type connection further includes one or more second doped polysilicon resistors across a second region of the semiconductor substrate, the second region separating the current sensing device from a second portion of the power transistor; each of the one or more first doped polysilicon resistors is electrically connected to a first contact pad over the first portion of the power transistor and a second contact pad over the current sensing device; and Each of the one or more second doped polysilicon resistors is electrically connected to a first contact pad over the second portion of the power transistor and a second contact pad over the current sensing device.

15. The semiconductor die of claim 13, wherein: The resistive and / or diode-like connection comprises a first doped polysilicon resistor disposed in a plurality of first trenches formed in a first main surface of the semiconductor substrate and extending laterally from a region of the semiconductor substrate comprising a first portion of the power transistor into a region of the semiconductor substrate comprising the current sensing device; The resistive and / or diode-type connection further comprises a second doped polysilicon resistor disposed in a plurality of second trenches formed in the first main surface of the semiconductor substrate and extending laterally from a region of the semiconductor substrate including the second portion of the power transistor into a region of the semiconductor substrate including the current sensing device; a first doped polysilicon resistor electrically connected to a first contact pad over the first portion of the power transistor and a second contact pad over the current sensing device; and The second doped polysilicon resistor is electrically connected to a first contact pad over the second portion of the power transistor and a second contact pad over the current sensing device.

16. The semiconductor die of claim 1, wherein the resistive and / or diode-like connections include: one or more first diodes electrically connected between a sense terminal of the current sensing device and a first load terminal of the power transistor; and One or more second diodes are connected in anti-parallel with the one or more first diodes.

17. The semiconductor die of claim 16, wherein at least two first diodes connected in series are electrically connected between a sensing terminal of the current sensing device and a first load terminal of the power transistor, and wherein at least two second diodes connected in series are anti-parallel to the at least two first diodes connected in series.

18. A semiconductor die according to claim 17, wherein the at least two first diodes connected in series are formed in separate first polysilicon islands separated from the semiconductor substrate by an insulating layer, wherein the at least two first diodes connected in series are electrically connected in series via a metallization structure disposed above the first polysilicon islands, wherein the at least two second diodes connected in series are formed in separate second polysilicon islands separated from the semiconductor substrate by an insulating layer, and wherein the at least two second diodes connected in series are electrically connected in series via a metallization structure disposed above the second polysilicon islands.

19. The semiconductor die of claim 1 , wherein the resistive and / or diode-like connections include: Two or more diodes are electrically connected in a Zener configuration between a sense terminal of the current sensing device and a first load terminal of the power transistor.

20. The semiconductor die of claim 1, wherein the resistive and / or diode-like connection comprises a diode-like connection in parallel with a resistive connection.

21. A semiconductor die, comprising: Semiconductor substrate; IGBT (Insulated Gate Bipolar Transistor) formed in a semiconductor substrate; A current sensing device is formed in a semiconductor substrate and occupies less semiconductor substrate area than an IGBT; An emitter contact pad electrically connected to an emitter terminal of the IGBT; a current sensing contact pad electrically connected to an emitter terminal of the current sensing device, wherein the current sensing contact pad is dedicated only to current sensing; and a resistive and / or diode-like connection between the emitter terminal of the current sensing device and the emitter terminal of the IGBT, The resistive and / or diode-like connections are designed solely for ESD (electrostatic discharge) protection of the current sensing device by providing an ESD discharge path to the emitter terminal of the IGBT.

Images