Back contact cell, photovoltaic module and preparation method thereof

Abstract

The invention discloses a back contact battery and a preparation method thereof. The back contact cell comprises a semiconductor substrate, the back surface of the semiconductor substrate is provided with at least one first area and at least one second area which are alternately distributed, and the adjacent first area and second area are separated by a third area; the first doped semiconductor layer is at least positioned on the semiconductor substrate in the first region; the first doped semiconductor layer is at least located on the semiconductor substrate in the first region, the second doped semiconductor layer is at least located on the semiconductor substrate in the second region, the conduction type of the first doped semiconductor layer is opposite to that of the second doped semiconductor layer, and the position, adjacent to the first region, of the third region is provided with a first boundary region; the position, adjacent to the second area, of the third area is provided with a second boundary area, and the first boundary area and / or the second boundary area are / is provided with one or more pits. According to the scheme, the light trapping effect of the back contact cell can be improved, so that the photoelectric conversion efficiency is further improved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaics, and particularly to a back contact battery, a photovoltaic module and a preparation method thereof. Background Art

[0002] Photovoltaic solar cells are one of the mainstream clean and renewable energy sources at present. Continuously improving the photoelectric conversion efficiency of photovoltaic solar cells and reducing the cost per kilowatt-hour are the goals of research and industrial manufacturing in this field. The interdigitated back contact (IBC) battery is a typical high-efficiency battery structure. Continuously optimizing the structural design of the back contact battery and improving the photoelectric conversion efficiency are the hot research directions in the industry in recent years.

[0003] Since the grid lines of the back contact battery are all concentrated on the back, there has always been an inherent shortcoming in the photoelectric conversion efficiency of the back. It is necessary to continuously optimize the light absorption rate and utilization rate of the back, and at the same time consider the passivation effect of the back, so as to improve the photoelectric conversion efficiency of the back and further amplify the advantages of the back contact battery. How to further achieve the above optimization effect requires continuous exploration and experimentation. In the prior art, the back structure of the IBC battery is mainly divided into a P region, an N region and an isolation region (Gap region). The two edges of the Gap region are usually flat in morphology. For a flat morphology, it is beneficial for passivation, but the reflectivity of the back light will be high.

[0004] Therefore, a solution to at least one of the above problems is needed. Summary of the Invention

[0005] The purpose of the present application is to provide a back contact battery, a photovoltaic module and a preparation method thereof, so as to improve the light absorption rate and utilization rate of the back contact battery by making the first boundary region at the position where the third region is adjacent to the first region and the second boundary region at the position where the third region is adjacent to the second region have one or more pits, thereby improving the photoelectric conversion efficiency.

[0006] To achieve the above object, in a first aspect, the present application provides a back-contact battery, comprising: a semiconductor substrate having a back surface, on which at least one first region and at least one second region are alternately distributed, and adjacent first and second regions are separated by a third region; a first doped semiconductor layer disposed at least on the semiconductor substrate of the first region; and a second doped semiconductor layer disposed at least on the semiconductor substrate of the second region, the first doped semiconductor layer and the second doped semiconductor layer having opposite conduction types, wherein a first boundary region is provided at a position where the third region is adjacent to the first region, and a second boundary region is provided at a position where the third region is adjacent to the second region, and one or more pits are provided in the first boundary region and / or the second boundary region.

[0007] In the case of adopting the above technical solution, firstly, the third region on the back surface of the semiconductor substrate can isolate the first doped semiconductor layer and the second doped semiconductor layer, reducing the carrier recombination rate at the lateral junction of the first doped semiconductor layer and the second doped semiconductor layer, which is beneficial to improving the photoelectric conversion efficiency of the back-contact battery. Secondly, one or more pits are provided in the first boundary region at the position where the third region is adjacent to the first region and / or the second boundary region at the position where the third region is adjacent to the second region. The presence of the pits can improve the light trapping effect of the back-contact battery, enhance the light absorption rate and utilization rate of the back-contact battery, and thus improve the photoelectric conversion efficiency.

[0008] As a possible implementation, the pits include closed pits and / or non-closed pits. The side of the closed pit is surrounded by the semiconductor substrate to form a closed structure, and the side of the non-closed pit is partially surrounded by the semiconductor substrate to form a non-closed structure.

[0009] In the case of adopting the above technical solution, there can be various situations of the pits. For example, the closed pits and the non-closed pits can be used alone or in combination. For example, in some cases, a boundary region has only one type of closed pits or non-closed pits; in some cases, a boundary region includes both closed pits and non-closed pits; in some cases, a boundary region has only closed pits, and another boundary region adjacent to the same third region as this boundary region has only non-closed pits; in some cases, a boundary region includes both closed pits and non-closed pits, and another boundary region adjacent to the same third region as this boundary region has only non-closed pits; in some cases, a boundary region includes both closed pits and non-closed pits, and another boundary region adjacent to the same third region as this boundary region includes both closed pits and non-closed pits; and so on. Whether the pits are closed and the opening direction of the pits will both change the path of light, thus ultimately affecting the light trapping effect. By combining different types of pits or combining different opening directions of different pits, the light trapping effect of the back contact battery can be improved, the light absorption rate and utilization rate of the back contact battery can be increased, and thus the photoelectric conversion efficiency can be improved.

[0010] As a possible implementation manner, the semiconductor substrate around the side of the closed pit and / or the non-closed pit has a rib.

[0011] In the case of adopting the above technical solution, due to the existence of the rib in the pit, the number of reflections and the absorption rate of light in the pit can be increased, and the direct reflection of light from the side of the pit can be avoided, so that the light trapping effect of the back contact battery can be improved, the light absorption rate and utilization rate of the back contact battery can be increased, and thus the photoelectric conversion efficiency can be improved.

[0012] As a possible implementation manner, the ribs of at least one of the closed pits are butted to form at least one butting seam, and / or the ribs of at least one of the non-closed pits are butted to form at least one butting seam.

[0013] In the case of adopting the above technical solution, since the ribs of the pits are butted to form at least one butting seam, the larger the number of the butting seams, the more uneven the inner surface of the pit indicates, the number of reflections and the absorption rate of light in the pit can be increased, and the direct reflection of light from the side of the pit can be avoided, so that the light trapping effect of the back contact battery can be improved, the light absorption rate and utilization rate of the back contact battery can be increased, and thus the photoelectric conversion efficiency can be improved.

[0014] As a possible implementation manner, the first boundary region has at least the closed pits; and / or the second boundary region has at least the non-closed pits.

[0015] In the case of adopting the above technical solution, at least the closed pits in the first boundary region and at least the non-closed pits in the second boundary region can be used alone or in combination to improve the light trapping effect of the back contact battery in different opening directions of the pits, enhance the light absorption rate and utilization rate of the back contact battery, and thus improve the photoelectric conversion efficiency.

[0016] As a possible implementation, one or both of the first boundary region and the second boundary region have the closed pits and the non-closed pits.

[0017] In the case of adopting the above technical solution, at least the closed pits and non-closed pits in the first boundary region and at least the closed pits and non-closed pits in the second boundary region can be used alone or in combination to improve the light trapping effect of the back contact battery in different opening directions of the pits, enhance the light absorption rate and utilization rate of the back contact battery, and thus improve the photoelectric conversion efficiency.

[0018] As a possible implementation, the number of the closed pits in the first boundary region is more than the number of the closed pits in the second boundary region; and / or the number of the non-closed pits in the second boundary region is more than the number of the non-closed pits in the first boundary region.

[0019] In the case of adopting the above technical solution, by making the number of the closed pits in the first boundary region more than the number of the closed pits in the second boundary region, and / or making the number of the non-closed pits in the second boundary region more than the number of the non-closed pits in the first boundary region, for example, when the first region is a P region and the second region is an N region, the light trapping effect of the back contact battery can be improved, the light absorption rate and utilization rate of the back contact battery can be enhanced, and thus the photoelectric conversion efficiency can be improved.

[0020] As a possible implementation, at least part of the pits have extended eaves of the corresponding doped semiconductor layer above them, and / or at least part of the vicinity of the top of the pits has exposed parts not covered by the corresponding doped semiconductor layer.

[0021] In the case of adopting the above technical solution, the eaves can reflect the light reaching them to the pits below, the pits in another boundary region or the semiconductor substrate to increase the light absorption rate and utilization rate, while the exposed parts can directly increase the light absorption rate and utilization rate of the semiconductor substrate. By means of different combinations of the eaves, the exposed parts and the pits, the light trapping effect of the back contact battery can be improved, the light absorption rate and utilization rate of the back contact battery can be enhanced, and thus the photoelectric conversion efficiency can be improved.

[0022] As a possible implementation, an extended brim portion of a first doped semiconductor layer is disposed above at least a part of the pits in the first boundary region, and / or an exposed portion not covered by a second doped semiconductor layer is disposed near the top of at least a part of the pits in the second boundary region.

[0023] In the case of adopting the above technical solution, the brim portion of the first boundary region can reflect the incident light to the pits below, the pits in the second boundary region or the semiconductor substrate to increase the light absorption rate and utilization rate. The exposed portion of the second boundary region can directly increase the light absorption rate and utilization rate of the semiconductor substrate. By means of different combinations of the brim portion, the exposed portion and the pits, the light trapping effect of the back contact battery can be improved, the light absorption rate and utilization rate of the back contact battery can be enhanced, and thus the photoelectric conversion efficiency can be increased.

[0024] As a possible implementation, the thickness of the semiconductor substrate in the first region is greater than the thickness of the semiconductor substrate in the second region.

[0025] In the case of adopting the above technical solution, due to the thickness difference between the semiconductor substrate in the first region and the semiconductor substrate in the second region, the light reaching the pits in the first boundary region or the pits in the second boundary region may be reflected to the pits in the other boundary region or the semiconductor substrate, rather than being directly reflected away from the third region, which can improve the light trapping effect of the back contact battery, enhance the light absorption rate and utilization rate of the back contact battery, and thus increase the photoelectric conversion efficiency.

[0026] As a possible implementation, the first doped semiconductor layer has an extension portion, and / or the second doped semiconductor layer has an extension portion. At least one of the first doped semiconductor layer and the second doped semiconductor layer is overlapped with the other doped semiconductor layer through its extension portion. The first boundary region further includes a first position adjacent to the extension portion in the third region, or the second boundary region further includes a second position adjacent to the extension portion in the third region.

[0027] In the case of adopting the above technical solution, the first doped semiconductor and the second doped semiconductor with opposite conduction types are locally electrically connected through the extension portion. With little influence on the working efficiency of the back contact battery in the forward voltage region, the risk of hot spots of the back contact battery can be reduced to a certain extent, the anti-hot spot effect can be achieved, and the anti-burning ability of the back contact battery can be enhanced.

[0028] As a possible implementation, the total number of closed pits at at least one corner of the first position or the second position is not less than the total number of non-closed pits at the at least one corner.

[0029] In the case of adopting the above technical solution, while achieving the anti-hot spot effect, by setting an appropriate number of closed pits or non-closed pits at the first position or the second position, the light trapping effect of the back contact battery can also be improved, the light absorption rate and utilization rate of the back contact battery can be enhanced, and thus the photoelectric conversion efficiency can be improved.

[0030] As a possible implementation manner, the first boundary region includes a first sub-boundary region within 50 μm extending from the edge of the first region away from the third region towards the first region, the second boundary region includes a second sub-boundary region within 50 μm extending from the edge of the second region away from the third region towards the second region, and one or more of the pits are provided in the first sub-boundary region and / or the second sub-boundary region.

[0031] In the case of adopting the above technical solution, since the positions of the first boundary region, the second boundary region and the pits within the corresponding boundary regions are not limited to the side walls of the semiconductor substrate, the existence range of the pits is expanded, the light trapping effect of the back contact battery can be improved, the light absorption rate and utilization rate of the back contact battery can be enhanced, and thus the photoelectric conversion efficiency can be improved.

[0032] As a possible implementation manner, the side walls of the semiconductor substrate in the first boundary region and / or the second boundary region have a wavy undulating structure in a direction perpendicular to the extending direction of the third region, the closed pits are located at the protruding positions of the undulating structure, or the non-closed pits are located at the recessed positions of the undulating structure.

[0033] In the case of adopting the above technical solution, different combinations of the undulating structure of the side walls of the semiconductor substrate and the pits can further improve the light trapping effect of the side walls, enhance the light absorption rate and utilization rate of the back contact battery, and thus improve the photoelectric conversion efficiency.

[0034] As a possible implementation manner, in the first sub-boundary region and / or the second sub-boundary region, the pits in the first sub-boundary region and the second sub-boundary region closer to the third region have a larger diameter than the pits in the first sub-boundary region and the second sub-boundary region farther from the third region.

[0035] In the case of adopting the above technical solution, by making the pits at different positions have different diameters, the adverse effects of the pits on the first region or the second region can be reduced, and at the same time, the light trapping effect of the back contact battery can be improved, the light absorption rate and utilization rate of the back contact battery can be enhanced, and thus the photoelectric conversion efficiency can be improved.

[0036] As a possible implementation, the first doped semiconductor layer is a P-type doped semiconductor layer and the second doped semiconductor layer is an N-type doped semiconductor layer.

[0037] In the case of adopting the above technical solution, by appropriately setting the first region and the second region and the conduction types of the corresponding doped semiconductor layers, the light trapping effect of the back contact battery can be further improved compared with other conduction type settings, and the light absorption rate and utilization rate of the back contact battery can be increased, thereby improving the photoelectric conversion efficiency.

[0038] In a second aspect, the present application provides a method for manufacturing a back contact battery, which is characterized by comprising:

[0039] Providing a semiconductor substrate having a back surface, on which at least one first region and at least one second region are alternately distributed, and adjacent first regions and second regions are separated by a third region;

[0040] Forming a first doped semiconductor layer on the semiconductor substrate in the first region; and

[0041] Forming a second doped semiconductor layer on the semiconductor substrate in the second region, the first doped semiconductor layer and the second doped semiconductor layer having opposite conduction types; and

[0042] Wherein a first boundary region is provided at a position where the third region is adjacent to the first region, and a second boundary region is provided at a position where the third region is adjacent to the second region, and the first boundary region and / or the second boundary region have one or more pits.

[0043] As a possible implementation, after providing the semiconductor substrate and before forming the second doped semiconductor layer, the manufacturing method comprises:

[0044] Forming the first doped semiconductor layer provided as a whole layer on the back surface of the semiconductor substrate;

[0045] Forming a first mask layer on a portion of the first doped semiconductor layer corresponding to the first region;

[0046] Under the masking action of the first mask layer, selectively removing portions of the first doped semiconductor layer located on the third region and the second region; and

[0047] Making the thickness of the semiconductor substrate in the first region greater than the thickness of the semiconductor substrate in the third region and the second region.

[0048] As a possible implementation, after making the thickness of the semiconductor substrate in the first region greater than the thicknesses of the semiconductor substrates in the third region and the second region, the manufacturing method includes:

[0049] Depositing the second doped semiconductor layer on the first doped semiconductor layer, the third region, and the second region;

[0050] Forming a second mask layer on the portion of the second doped semiconductor layer corresponding to the second region;

[0051] Under the masking effect of the second mask layer, selectively removing the portions of the second doped semiconductor layer corresponding to the first region and the third region; and

[0052] Making the thickness of the semiconductor substrate in the second region greater than the thickness of the semiconductor substrate in the third region.

[0053] As a possible implementation, forming the first mask layer includes:

[0054] Forming a first doped glass layer with a whole-layer setting on the first doped semiconductor layer;

[0055] Using a laser etching process to perform heat treatment on the portions of the first doped glass layer corresponding to the third region and the second region, so that the non-heat-treated portion of the first doped glass layer forms the first mask layer;

[0056] Removing the heat-treated portion of the first doped glass layer.

[0057] In a third aspect, the present application provides a photovoltaic module, including: a battery string, which is formed by electrically connecting a plurality of back-contact batteries according to the first aspect; and a packaging layer, which covers the surface of the battery string.

[0058] For the beneficial effects of the second and third aspects and their various implementations in the present application, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementations, which will not be elaborated here. Description of the Drawings

[0059] The drawings described herein are used to provide a further understanding of the present application, and constitute a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0060] Figure 1 It is a cross-sectional schematic view showing the back side of a back-contact battery in the related art;

[0061] Figure 2Schematic longitudinal sectional view of the structure of a back-contact battery according to an embodiment of the present application;

[0062] Figures 3A - 3C Top view schematic of a partial structure of a back-contact battery including an extension portion according to multiple embodiments of the present application; Figure 3D Electron microscope image of a partial structure of a back-contact battery including an extension portion according to an embodiment of the present application;

[0063] Figure 4 Electron microscope image of a partial structure of a back-contact battery according to an embodiment of the present application;

[0064] Figure 5 Electron microscope image of a partial structure of a back-contact battery according to an embodiment of the present application;

[0065] Figure 6 Electron microscope image of a partial structure of a back-contact battery according to an embodiment of the present application;

[0066] Figure 7 Electron microscope image of a partial structure of a back-contact battery according to an embodiment of the present application;

[0067] Figure 8A and Figure 8B Schematic longitudinal sectional view of a partial structure of a back-contact battery including a brim portion according to an embodiment of the present application. Detailed implementation manners

[0068] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present application. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present application.

[0069] Various schematic structural views according to embodiments of the present application are shown in the accompanying drawings. These figures are not drawn to scale, where for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0070] In the context of the present application, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component between them. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component. To make the technical problems, technical solutions, and beneficial effects to be solved by the present invention clearer and more understandable, the following further details the present application in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present application.

[0071] In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first", "second", "third" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0072] Currently, solar cells are being used more and more widely as a new energy alternative. Among them, a photovoltaic solar cell is a device that converts the light energy of the sun into electrical energy. Specifically, a solar cell utilizes the photovoltaic effect to generate carriers, and then uses electrodes to extract the carriers, thereby facilitating the effective utilization of electrical energy.

[0073] Among them, when both the positive and negative electrodes included in the solar cell are located on the back surface of the solar cell, the solar cell is a back-contact cell. The front surface of the back-contact cell can be used as the light-receiving surface for receiving incident light, and the back surface can be used as the backlight surface. Since there is no influence of metal electrode shielding on the back surface of the back-contact cell, compared with a solar cell with shielding on the front surface, the back-contact cell has a higher short-circuit current and photoelectric conversion efficiency. Specifically, as Figure 1 shown, an existing back-contact cell generally includes a semiconductor substrate 11, and a first doped semiconductor layer 12 located in a first region and a second doped semiconductor layer 13 located in a second region that are alternately and spaced apart on the back side of the semiconductor substrate 11. The first doped semiconductor layer 12 and the second doped semiconductor layer 13 have opposite conduction types.

[0074] In the actual preparation process, a whole layer of the first doped semiconductor layer is usually formed on the back side; and the first doped semiconductor layer is selectively etched to retain only the first doped semiconductor layer located on a partial region of the back surface. Then, a second doped semiconductor layer is formed on the first doped semiconductor layer and the part exposed by etching the first doped semiconductor layer, and the second doped semiconductor layer is selectively etched so that the first doped semiconductor layer and the second doped semiconductor layer are alternately and spaced apart on the back surface of the semiconductor substrate.

[0075] However, as Figure 1 shown, the conduction types of the first doped semiconductor layer 12 and the second doped semiconductor layer 13 are opposite. In order to prevent the first doped semiconductor layer 12 and the second doped semiconductor layer 13 from conducting and causing a short circuit, existing manufacturing methods will form a third region 16 with a certain width between them through methods such as laser etching and wet chemical etching to separate the first doped semiconductor layer 12 in the first region and the second doped semiconductor layer 13 in the second region.

[0076] The edge regions of the third region adjacent to the first region and the edge regions of the third region adjacent to the second region are usually flat in topography. For a flat topography, although it is beneficial for passivation, the reflectivity of the backlight is relatively high, which is not conducive to the absorption of the backlight.

[0077] To solve the above technical problems, in a first aspect, the present application provides a back-contact battery. As Figure 2 shown, the back-contact battery provided by an embodiment of the present application includes: a semiconductor substrate 11, a first doped semiconductor layer 12, and a second doped semiconductor layer 13. The semiconductor substrate 11 has a front surface and a back surface. At least one first region 14 and at least one second region 15 are alternately distributed on the back surface, and the adjacent first region 14 and second region 15 are separated by a third region 16. The conduction types of the first doped semiconductor layer 12 and the second doped semiconductor layer 13 are opposite. In some embodiments, the first doped semiconductor layer 12 is one of an N-type doped semiconductor layer or a P-type doped semiconductor layer; the second doped semiconductor layer 13 is the other of an N-type doped semiconductor layer or a P-type doped semiconductor layer. The third region 16 separates the first doped semiconductor layer 12 and the second doped semiconductor layer 13, which can reduce the carrier recombination rate at the lateral junction of the first doped semiconductor layer 12 and the second doped semiconductor layer 13, and is beneficial to improving the photoelectric conversion efficiency of the back-contact battery. The semiconductor substrate 11 can be a silicon substrate, for example, an N-type silicon substrate or a P-type silicon substrate.

[0078] The surface of the third region 16 can be a polished topography or a textured surface topography. In the case of a polished topography, the surface of the third region 16 is relatively flat. Based on this, when the back-contact battery further includes a surface passivation layer, compared with the textured surface topography, the thickness of the part of the surface passivation layer formed on the third region 16 with a polished surface topography is greater, which can improve the passivation effect of the surface passivation layer on the third region 16, reduce the carrier recombination rate on the surface of the third region 16, and is beneficial to improving the photoelectric conversion efficiency of the back-contact battery.

[0079] The first doped semiconductor layer 12 is at least located on the semiconductor substrate 11 in the first region 14, and the second doped semiconductor layer 13 is at least located on the semiconductor substrate 11 in the second region 15. As used herein, "at least located" means that the first doped semiconductor layer 12 is located in the first region 14, but there may be a brim portion extending from the first region 14 to the adjacent third region 16, or the second doped semiconductor layer 13 is located in the second region 15, but there may be a brim portion extending from the second region 15 to the adjacent third region 16, as will be described in detail below.

[0080] The position where the third region 16 is adjacent to the first region 14 has a first boundary region, and the position where the third region 16 is adjacent to the second region 15 has a second boundary region. In some embodiments, the first boundary region may have one or more pits 20. In some embodiments, the second boundary region may have one or more pits 20. In some embodiments, both the first boundary region and the second boundary region have one or more pits 20. As used herein, the "first boundary region" includes the semiconductor substrate at the junction of the third region 16 and the first region 14 and the region within a certain distance (e.g., 50 μm) extending from the edge of the first region 14 away from the third region 16 into the first region 14, where the region within a certain distance extending from the edge of the first region 14 away from the third region 16 into the first region 14 can be referred to as the first sub-boundary region; similarly, the "second boundary region" includes the semiconductor substrate at the junction of the third region 16 and the second region 15 and the region within a certain distance (e.g., 50 μm) extending from the edge of the second region 15 away from the third region 16 into the second region 15, where the region within a certain distance extending from the edge of the second region 15 away from the third region 16 into the second region 15 can be referred to as the second sub-boundary region. Figure 2 The pits 20 located in the first sub-boundary region are shown, but the positions of the pits are not limited to this position. Below will be combined with Figures 3A - 3D and Figures 4 - 7 The positions of the pits will be described in more detail. The first boundary region at the position where the third region is adjacent to the first region and / or the second boundary region at the position where the third region is adjacent to the second region have one or more pits. The pits existing on the sidewalls of the semiconductor substrate in the corresponding boundary regions and the semiconductor substrate in the corresponding sub-boundary regions can improve the light trapping effect of the back contact battery, enhance the light absorption rate and utilization rate of the back contact battery, and thus improve the photoelectric conversion efficiency.

[0081] As Figures 4 to 7 shown, the pits may include closed pits and / or non-closed pits. The sides of the closed pits are surrounded by the semiconductor substrate to form a closed structure (e.g., as Figure 4 , Figure 6 and Figure 7as shown), rather than the side of the closed pit being partially surrounded by the semiconductor substrate to form an unclosed structure (e.g., as shown in Figure 4 , Figure 5 and Figure 7 ). It should be noted that in this article, a "closed pit" has an open top and closed sides and bottom, while an "unclosed pit" has an open top and open sides and bottom. "Closed" and "unclosed" are only used to indicate whether the sides and bottom of the pit form a closed structure. The top of the pit refers to the part farther from the semiconductor substrate relative to the thickness direction of the semiconductor substrate. In addition, the "sides of the closed pit" are all surrounded by the semiconductor substrate, while the "sides of the unclosed pit" are surrounded by the semiconductor substrate, and the other part of the unclosed pit that is not surrounded by the semiconductor substrate is the open part. Whether the pit is closed and the opening direction of the pit will both change the path of light, thus ultimately affecting the light trapping effect. By combining different types of pits or different opening directions of different pits (the opening direction can include the direction of the top opening part of the closed pit and the unclosed pit and the opening direction of the unclosed part of the side of the unclosed pit), the light trapping effect of the back contact battery can be improved, the light absorption rate and utilization rate of the back contact battery can be increased, and thus the photoelectric conversion efficiency can be improved. The semiconductor substrate surrounding the sides of the closed pit and / or the unclosed pit has ridges 21 (as shown in Figures 5 - 7 ). Due to the presence of the ridges 21 in the pit, the number of reflections and the absorption rate of light in the pit can be increased, and the side of the pit can be prevented from directly reflecting the light away from the pit, which can improve the light trapping effect of the back contact battery, increase the light absorption rate and utilization rate of the back contact battery, and thus improve the photoelectric conversion efficiency. The ridges 21 of at least one closed pit are docked to form at least one docking seam 22 (as shown in Figure 6 ), and / or the ridges of at least one unclosed pit are docked to form at least one docking seam 22 (as shown in Figure 5 and Figure 7 ). Since the ridges of the pit are docked to form at least one docking seam, the larger the number of docking seams, the more uneven the inner surface of the pit, which can increase the number of reflections and the absorption rate of light in the pit, prevent the side of the pit from directly reflecting the light away from the pit, improve the light trapping effect of the back contact battery, increase the light absorption rate and utilization rate of the back contact battery, and thus improve the photoelectric conversion efficiency.

[0082] From Figure 4 , Figure 6 and Figure 7It can be seen that the top opening part of the closed pit has a certain diameter. As the diameter increases, the number of docking seams formed by the docking of the ridges of the closed pit will correspondingly increase. For example, in some embodiments, when the arc at the top of the non-closed pit is greater than 120 degrees, at least one docking seam is formed by the docking of the ridges; the number of docking seams formed by the docking of the ridges of the closed pit can be, for example, 1-8 or 1-6. Similar to the closed pit, the diameter of the non-closed pit can be defined relative to the approximate circle corresponding to the arc at the top of the non-closed pit. In one embodiment, when the diameters are equal, the number of docking seams formed by the docking of the ridges of the closed pit can be greater than the number of docking seams formed by the docking of the ridges of the non-closed pit. As for the diameter of the pit, it can be set according to actual needs and will not be specifically limited here. For example, the diameter of the pit can be not less than 2 μm, so as to improve the light trapping effect of the back contact battery, increase the light absorption rate and utilization rate of the back contact battery, and thus improve the photoelectric conversion efficiency.

[0083] The closed pits and non-closed pits can exist in various combinations in the first boundary region and the second boundary region. In some embodiments, the first boundary region only has closed pits. In some embodiments, the first boundary region has both closed pits and non-closed pits. In some embodiments, the second boundary region only has non-closed pits. In some embodiments, the second boundary region has both closed pits and non-closed pits. The closed pits and non-closed pits in the first boundary region and the closed pits and non-closed pits in the second boundary region can be individual or combined to improve the light trapping effect of the back contact battery in different opening directions of the pits, increase the light absorption rate and utilization rate of the back contact battery, and thus improve the photoelectric conversion efficiency. In some embodiments, the number of closed pits in the first boundary region is more than the number of closed pits in the second boundary region. In some embodiments, the number of non-closed pits in the second boundary region is more than the number of non-closed pits in the first boundary region. By making the number of closed pits in the first boundary region more than the number of closed pits in the second boundary region, and / or making the number of non-closed pits in the second boundary region more than the number of non-closed pits in the first boundary region, for example, when the first region is a P region and the second region is an N region, the light trapping effect of the back contact battery can be improved, the light absorption rate and utilization rate of the back contact battery can be increased, and thus the photoelectric conversion efficiency can be improved.

[0084] In the actual preparation process, the corresponding doped semiconductor layer can have an extended brim portion 23 (such as Figure 8A and Figure 8BAs shown). Above some of the pits, there may be an extended brim portion 23, which is a portion extended from the corresponding doped semiconductor layer and is suspended. In some embodiments, the brim portion 23 is not adjacent to the plane where the top of the underlying pit is located, and has a certain height relative to the plane where the top of the underlying pit is located (such as Figure 8A shown as H in). This height can be set according to actual requirements and will not be specifically limited here. For example, this height can be 0.2 μm - 2 μm. In some other embodiments, the brim portion 23 is adjacent to the plane where the top of the underlying pit is located, as Figure 8B shown. Figure 8A The brim portion in is referred to as having a first brim portion structure, Figure 8B The brim portion in is referred to as having a second brim portion structure. The brim portion 23 having the first brim portion structure can exist above part or all of the edges of the top of the pit. The first brim portion structure and the second brim portion structure can exist alone or in any combination above part or all of the edges of the top of a closed pit or an open pit. For example, in the case where the brim portion 23 having the first brim portion structure exists above part of the edges of the top of the pit, there may be no brim portion above the remaining edges of the top of the pit, or there may be a brim portion 23 having the second brim portion structure. Or, the brim portion 23 having the second brim portion structure can exist above part or all of the edges of the top of the pit. Additionally, in the case where the brim portion 23 having the second brim portion structure exists above part of the edges of the top of the pit, there may be no brim portion above the remaining edges of the top of the pit, or there may be a brim portion 23 having the first brim portion structure. Furthermore, during the actual manufacturing process, the corresponding doped semiconductor layer can partially cover the semiconductor substrate 11, such that the surface of the semiconductor substrate 11 has an exposed portion 24 (as Figures 4 - 6As shown). There may also be an exposed portion 24 near the top of some of the pits that is not covered by the doped semiconductor layer. This exposed portion is the part of the surface of the semiconductor substrate 11 where the doped semiconductor layer does not extend to the edge of the top of the pit. The exposed portion between the edge of the top of some of the pits and the edge of the doped semiconductor layer causes there to be a certain distance between the edge of the doped semiconductor layer near the pit and the edge of the top of the pit. This distance can be set according to actual requirements and is not specifically limited here. For example, this distance can be 0.2 μm - 5 μm. The exposed portion 24 can exist near all the edges of the top of the pit, or can only exist near some of the edges of the top of the pit. The brim portion and the exposed portion can exist in various combinations above and near the top of the closed pits and above and near the top of the non-closed pits. In some embodiments, there is a brim portion above some of the pits in the first boundary region. In some embodiments, there is a brim portion above some of the pits in the first boundary region, while there is an exposed portion near the top of some other pits. In some embodiments, there is an exposed portion near the top of some of the pits in the second boundary region. In some embodiments, there is an exposed portion near the top of some of the pits in the second boundary region, while there is a brim portion above some other pits. For example, in the case where the first region is a P region and the second region is an N region, it is more likely that there is a brim portion above some of the pits in the first boundary region, while there is an exposed portion near the top of some of the pits in the second boundary region. The brim portion can reflect the light reaching it to the pits below, the pits in the other boundary region, or the semiconductor substrate to increase the light absorption rate and utilization rate, while the exposed portion can directly increase the light absorption rate and utilization rate of the semiconductor substrate. By means of different combinations of the brim portion, the exposed portion, and the pits, the light trapping effect of the back contact battery can be improved, the light absorption rate and utilization rate of the back contact battery can be enhanced, and thus the photoelectric conversion efficiency can be improved.

[0085] During the actual preparation process, the thickness of the semiconductor substrate in the first region may be greater than the thickness of the semiconductor substrate in the second region. As used herein, the term "thickness" means the extension range of the semiconductor substrate in the vertical direction relative to the back surface of the back contact battery. In this case, due to the thickness difference between the semiconductor substrate in the first region and the semiconductor substrate in the second region, the light reaching the pits in the first boundary region or the light reaching the pits in the second boundary region may be reflected to the pits in the other boundary region or the semiconductor substrate, rather than being directly reflected away from the third region, which can improve the light trapping effect of the back contact battery, enhance the light absorption rate and utilization rate of the back contact battery, and thus improve the photoelectric conversion efficiency.

[0086] In addition, as Figure 3A and Figure 3BAs shown, one of the first doped semiconductor layer 12 or the second doped semiconductor layer 13 may have an extension portion 27 and may lap onto the other of the first doped semiconductor layer 12 or the second doped semiconductor layer 13 through its extension portion 27. In Figure 3A , the first doped semiconductor layer 12 has an extension portion 27, which has the same conductivity type as the first doped semiconductor layer. In Figure 3B , the second doped semiconductor layer 13 has an extension portion 27, which has the same conductivity type as the second doped semiconductor layer. Additionally, both the first doped semiconductor layer 12 and the second doped semiconductor layer 13 may have an extension portion 27 and dock or lap at a third region through their respective extension portions (as Figure 3C shown). The above extension portions may have the same conductivity type as the first doped semiconductor layer 12 and the second doped semiconductor layer 13 respectively, such that the first doped semiconductor layer 12 and the second doped semiconductor layer 13 form a local electrical connection. In this article, although an extension portion is described as an extension portion of a specific doped semiconductor layer, the conductivity type of this extension portion does not necessarily have to be the same as the conductivity type of this specific doped semiconductor layer, but may be the same as the conductivity type of either the first doped semiconductor layer or the second doped semiconductor layer, as long as the conductivity type of this extension portion and the combination of the conductivity types of the first doped semiconductor layer, the second doped semiconductor layer, and possibly another extension portion form a local electrical connection between the first doped semiconductor layer 12 and the second doped semiconductor layer 13. Furthermore, Figures 3A - 3C one or more of the different types of extension portions shown in may be present such that several same-type or different-type local electrical connections are formed between the first doped semiconductor layer 12 and the second doped semiconductor layer 13. By locally electrically connecting the first doped semiconductor 12 and the second doped semiconductor 13 with opposite conductivity types, the risk of hot spots in the back-contact battery can be reduced to a certain extent with less impact on the operating efficiency of the back-contact battery in the forward voltage region, the anti-hot spot effect can be achieved, and the anti-burnout ability of the back-contact battery can be improved.

[0087] In some embodiments, the first boundary region may further include a first position adjacent to the extension portion in the third region 16, or the second boundary region may further include a second position adjacent to the extension portion in the third region 16. The first position (including for example at least one of its corners) and / or the second position (including for example at least one of its corners) may have one or more pits, as Figures 3A - 3C shown. Additionally, in Figures 3A - 3C , although the presence of pits is shown by circles at various positions, this is only an example, and the positions and numbers of the pits may be different from those shown. Figures 3A - 3CThe circles shown in the figure can represent either closed pits or non-closed pits. For example, there can be more pits, fewer pits, different types of pits, etc. in the first boundary region and the second boundary region (such as on the sidewalls of the semiconductor substrate in the first boundary region, the sidewalls of the semiconductor substrate in the second boundary region, various positions of the extension, etc.). In one embodiment, the total number of closed pits at at least one corner of the first position or the second position is not less than the total number of non-closed pits at the at least one corner. In this case, while achieving the anti-thermal spot effect, by setting an appropriate number of closed pits or non-closed pits at the first position or the second position, the light trapping effect of the back contact cell can also be improved, the light absorption rate and utilization rate of the back contact cell can be enhanced, thereby improving the photoelectric conversion efficiency.

[0088] Figure 3D It is an electron micrograph of a partial structure of a back contact cell including an extension according to an embodiment of the present application. Figure 3D The scheme shown in the figure includes in reference Figures 3A - 3C the scheme described. Reference can be made to the description of Figures 3A - 3C to understand Figure 3D the scheme. It should be noted that Figure 3D both sides of the extension 27 shown in the figure can have different pit types, pit numbers, and undulating structures. For example, Figure 3D the sidewall on the left side of the extension 27 shown in the figure can have a greater number of pits and a more severe undulating degree compared to the sidewall on the right side. For example, the degree of indentation and protrusion of the undulating structure is more obvious. Figure 3D The pit types, pit numbers, and undulating structures on both sides of the extension shown in the figure are only for illustrative purposes, and various other situations can exist. For example, in some embodiments, the sidewall on the right side of the extension can have a greater number of pits and a more severe undulating degree, a greater number of pits and a similar undulating degree, approximately the same number of pits and a similar undulating degree, etc. compared to the sidewall on the left side. In this case, while achieving the anti-thermal spot effect, by setting an appropriate number of closed pits or non-closed pits on both sides of the extension, the light trapping effect of the back contact cell can also be improved, the light absorption rate and utilization rate of the back contact cell can be enhanced, thereby improving the photoelectric conversion efficiency. Regarding the undulating structure, a more detailed description is given below with reference to Figure 4 this.

[0089] In some embodiments, as Figure 4As shown, the sidewalls of the semiconductor substrate in the first boundary region and / or the second boundary region may have a wavy undulating structure in a direction perpendicular to the extending direction of the third region 16. The closed pits may be located at the protruding positions 25 of the undulating structure, or the non-closed pits may be located at the recessed positions 26 of the undulating structure. As described above, the first region 14 and the second region 15 are alternately distributed, and the extending direction of the third region 16 is parallel to the extending directions of the first region 14 and the second region 15 (e.g., Figure 4 the up-and-down direction parallel to the paper plane shown in Figure 2 ). In comparison, referring to the cross-sectional view of Figures 3A - 3C , the direction perpendicular to the paper plane of the third region 16 may be regarded as the extending direction of the third region 16. In addition, in Figure 4 , although the top views of the sidewalls of the semiconductor substrate in the first boundary region and the second boundary region are shown as straight lines, this is only an example. The sidewalls of the semiconductor substrate in the first boundary region and the second boundary region may have a wavy undulating structure in a direction perpendicular to the extending direction of the third region 16. The closed pits may be located at the protruding positions 25 of the undulating structure, or the non-closed pits may be located at the recessed positions 26 of the undulating structure, as shown in Figure 4 . Different combinations of the undulating structure and pits of the sidewalls of the semiconductor substrate can further improve the light trapping effect of the sidewalls, enhance the light absorption rate and utilization rate of the back contact battery, and thus improve the photoelectric conversion efficiency. As for the spacing between the pits, it can be set according to actual needs and is not specifically limited here. For example, the spacing between the pits can be 10 μm - 500 μm. In some embodiments, the spacing between the pits can be changed by adjusting the laser spot.

[0090] In some embodiments, in the first sub-boundary region and / or the second sub-boundary region, compared with the pits in the first sub-boundary region and the second sub-boundary region far from the third region 16, the pits in the first sub-boundary region and the second sub-boundary region closer to the third region 16 have a larger diameter. By making the pits at different positions have different diameters, the adverse effects of the pits on the first region or the second region can be reduced, and at the same time, the light trapping effect of the back contact battery can be improved, the light absorption rate and utilization rate of the back contact battery can be enhanced, and thus the photoelectric conversion efficiency can be improved.

[0091] In the actual application process, as shown in Figure 2 , the front surface of the semiconductor substrate 11 may be a flat surface; or, the front surface of the semiconductor substrate may also be a textured surface.

[0092] As shown in Figure 2As shown, the first doped semiconductor layer 12 is formed on the first region 14. Therefore, the range of the first region 14 on the back side of the semiconductor substrate 11 can be determined according to the requirements for the formation range of the first doped semiconductor layer 12 in actual application scenarios. Secondly, the second doped semiconductor layer 13 is formed on the second region 15. Therefore, the range of the second region 15 on the back side of the semiconductor substrate 11 can be determined according to the requirements for the formation range of the second doped semiconductor layer 13 in actual application scenarios. As for the third region 16, as described above, the third region 16 can isolate the first doped semiconductor layer 12 and the second doped semiconductor layer 13 with opposite conduction types and suppress leakage current. Therefore, the range of the third region 16 on the back side can be determined according to the requirements for the anti-leakage distance between the first doped semiconductor layer 12 and the second doped semiconductor layer 13 in actual application scenarios.

[0093] For the above-mentioned first doped semiconductor layer and second doped semiconductor layer, in terms of materials, the materials of the above-mentioned first doped semiconductor layer or second doped semiconductor layer can be semiconductor materials such as silicon, silicon-germanium, germanium, or gallium arsenide. In terms of the arrangement form of substances, the crystal phase of the first doped semiconductor layer or second doped semiconductor layer can be amorphous, microcrystalline, nanocrystalline, single crystal, or polycrystalline, etc. In terms of the conduction type, the conduction type of the first doped semiconductor layer or second doped semiconductor layer can be opposite to that of the semiconductor substrate, or the same as that of the semiconductor substrate, as long as the conduction types of the first doped semiconductor layer and the second doped semiconductor layer are opposite. As for the thicknesses of the first doped semiconductor layer and the second doped semiconductor layer, they can be set according to actual needs and are not specifically limited here. For example, the thickness of the first doped semiconductor layer or second doped semiconductor layer can be 100 nm - 600 nm.

[0094] In the actual application process, the first doped semiconductor layer can be directly formed on the first region 14 of the semiconductor substrate. Or, as Figure 2 shown, the back contact battery further includes a first passivation layer 18 located between the first region 14 of the semiconductor substrate 11 and the first doped semiconductor layer 12. In this case, the first passivation layer 18 and the first doped semiconductor layer 12 can form a selective contact structure to chemically passivate the first region 14 on the back side of the semiconductor substrate 11 and selectively collect carriers of the corresponding conduction type, reduce the carrier recombination rate on the back side, and facilitate improving the photoelectric conversion efficiency of the back contact battery.

[0095] The material of the first passivation layer can be determined according to the material of the first doped semiconductor layer and the type of the selective contact structure formed by the first passivation layer and the first doped semiconductor layer in actual application scenarios, and is not specifically limited here.

[0096] For example, when the selective contact structure formed by the first passivation layer and the first doped semiconductor layer is a tunneling passivation contact structure, the first doped semiconductor layer is a doped polysilicon layer, and the first passivation layer is a tunneling passivation layer. The material of the tunneling passivation layer may include materials such as silicon oxide, aluminum oxide, or titanium oxide.

[0097] For another example, when the selective contact structure formed by the first passivation layer and the first doped semiconductor layer is a heterojunction contact structure, the first doped semiconductor layer is a doped amorphous silicon layer and / or a doped microcrystalline silicon layer, and the first passivation layer is an intrinsic amorphous silicon layer and / or an intrinsic microcrystalline silicon layer.

[0098] As for the thickness of the first passivation layer, it can be set according to actual requirements and will not be specifically limited here. For example, the thickness of the first passivation layer can be 0.5 nm - 10 nm.

[0099] The second doped semiconductor layer can be directly formed on the second region of the semiconductor substrate. Or, as Figure 2 shown, the back contact battery further includes a second passivation layer 19 located between the second region 15 of the semiconductor substrate 11 and the second doped semiconductor layer 13. In this case, the second passivation layer 19 and the second doped semiconductor layer 13 can form a selective contact structure to chemically passivate the second region 15 on the back surface of the semiconductor substrate 11 and selectively collect carriers of the corresponding conductivity type, reducing the carrier recombination rate on the back side and facilitating the improvement of the photoelectric conversion efficiency of the back contact battery.

[0100] The material and thickness of the second passivation layer can refer to the material and thickness of the first passivation layer described above and will not be elaborated here.

[0101] As a possible implementation, as Figure 2 shown, the above back contact battery may further include a surface passivation layer 17 covering the first doped semiconductor layer 12, the second doped semiconductor layer 13, and the third region 16. In this case, the surface passivation layer 17 can passivate the back side of the back contact battery and reduce the carrier recombination rate on the back side.

[0102] Specifically, the material of the above surface passivation layer can be any insulating material with a passivation effect such as silicon oxide, aluminum oxide, or silicon nitride. As for the thickness of the surface passivation layer, it can be determined according to the actual application scenario and will not be specifically limited here.

[0103] In a second aspect, the present application provides a method for manufacturing a back contact battery. The method for manufacturing the back contact battery may include the following steps:

[0104] First, a semiconductor substrate 11 is provided; the semiconductor substrate 11 has a back surface, and at least one first region 14 and at least one second region 15 are alternately distributed on the back surface, and the adjacent first region 14 and second region 15 are spaced by a third region 16. The thickness of the semiconductor substrate can be 50 μm - 500 μm; the semiconductor substrate 11 can be processed by wire saw cutting and surface chemical polishing to make the surface smooth and flat.

[0105] Next, a first doped semiconductor layer 12 is formed on the semiconductor substrate 11 in the first region 14.

[0106] In the actual preparation process, after providing the semiconductor substrate 11 and before forming the second doped semiconductor layer 13, a first doped semiconductor layer 12 provided as a whole layer can be formed on the back surface of the semiconductor substrate 11. A first mask layer is formed on the part of the first doped semiconductor layer 12 corresponding to the first region 14. Under the masking effect of the first mask layer, the parts of the first doped semiconductor layer 12 located on the third region 16 and the second region 15 are selectively removed, and the thickness of the semiconductor substrate 11 in the first region 14 is made greater than the thickness of the semiconductor substrate 11 in the third region 16 and the second region 15. As for the thickness of the semiconductor substrates in the first region 14, the second region 15, and the third region 16, it can be determined according to the actual application scenario and is not specifically limited here. For example, the thickness of the semiconductor substrates in the first region 14, the second region 15, and the third region 16 is such that the depth of the third region 16 relative to the lower one of the thicknesses of the semiconductor substrates in the first region 14 and the second region 15 is 1 μm - 10 μm.

[0107] The material of the first mask layer can be any material with a masking effect and is not specifically limited here. The formation process and specific formation process of the doped semiconductor layer and the first mask layer can be determined according to the specific materials of the first doped semiconductor layer and the first mask layer.

[0108] Exemplarily, in the case where the material of the first doped semiconductor layer includes silicon, forming the first mask layer may include the following steps: forming a first intrinsic semiconductor layer provided as a whole layer on the back surface of the semiconductor substrate. Next, doping treatment is performed on the first intrinsic semiconductor layer to make the first intrinsic semiconductor layer form a first doped semiconductor layer, and a first doped silicon glass layer provided as a whole layer is formed on the first doped semiconductor layer. Then, using a laser etching process, heat treatment is performed on the parts of the first doped silicon glass layer corresponding to the third region and the second region, so that the unheated part of the first doped silicon glass layer forms the first mask layer. Then, the heated part of the first doped silicon glass layer is removed.

[0109] Specifically, the material of the first doped semiconductor layer including silicon may mean that the material of the first doped semiconductor layer only includes silicon; or it may also mean that the material of the first doped semiconductor layer includes both silicon and other semiconductor materials such as silicon germanium. Secondly, in the actual preparation process, processes such as chemical vapor deposition can be used to form the first intrinsic semiconductor layer disposed as a whole layer on the back side. Next, processes such as diffusion can be used to dope the first intrinsic semiconductor layer. After the above doping treatment, not only can the first doped semiconductor layer be obtained, but also a first doped silicon glass layer disposed as a whole layer can be formed on the first doped semiconductor layer. Then, a laser etching process is used to perform heat treatment on a part of the first doped silicon glass layer. At this time, the density of the part of the first doped silicon glass layer that is laser-treated becomes poor and it is easily removed. While the density of the part of the first doped silicon glass layer that is not laser-treated is relatively high and it is not easily removed, so that after heat treatment, different parts of the first doped silicon glass layer have different etching selectivity ratios, obtaining a first mask layer for patterning the first doped semiconductor layer, without the need to additionally form other mask materials and other mask deposition processes to obtain the first mask layer, which is beneficial to reducing the manufacturing cost of the back contact battery and simplifying the preparation process of the back contact battery. As for the specific conditions of the laser etching process, they can be set according to the actual application scenario and are not specifically limited here. The pits can be formed during the process of using the laser etching process to perform heat treatment on a part of the first doped silicon glass layer.

[0110] Of course, in the case where the material of the first doped semiconductor layer includes silicon, or the material of the first doped semiconductor layer does not include silicon, processes such as chemical vapor deposition and doping can also be used to form the first doped semiconductor layer disposed as a whole layer on the back side. Then, processes such as chemical vapor deposition and etching can be used to form a first mask layer made of other materials with a masking effect such as silicon nitride.

[0111] In addition, after forming the first mask layer, wet chemical and other processes can be used to selectively remove the parts of the first doped semiconductor layer located in the third region and the second region under the masking effect of the first mask layer; and make the thickness of the semiconductor substrate in the first region greater than the thicknesses of the semiconductor substrates in the third region and the second region. By using wet chemical and other processes to selectively remove the parts of the first doped semiconductor layer located in the third region and the second region under the masking effect of the first mask layer, a groove structure recessed into the semiconductor substrate relative to the first region can be formed in the third region and the second region, and the end of the first doped semiconductor layer adjacent to the third region can be suspended to form a capping portion. There is a plane disposed in the side wall of the groove structure in a horizontal direction relative to the back surface of the back contact battery, and this plane may include pits. As described above, the capping portion has a certain height relative to the plane where the top of the lower pit is located.

[0112] In the actual preparation process, processes such as wet chemical processes are adopted, and under the masking effect of the mask layer, a groove structure recessed relative to the first region is formed on the third region and the second region, which can prevent the high-temperature laser from damaging the semiconductor substrate and is beneficial to improving the yield of the back-contact battery. In addition, when the groove structure is formed by a wet chemical process, since the etching method of the wet chemical solution on the semiconductor substrate is generally isotropic etching, it is beneficial to increase the length of the end portion suspended in the first doped semiconductor layer.

[0113] Specifically, the process conditions for selectively etching the first doped semiconductor layer can be determined according to the etching process adopted, the material of the first doped semiconductor layer, and the thickness of the semiconductor substrate in the third region and the thickness of the semiconductor substrate in the second region after this operation, etc., and no specific limitation is made here.

[0114] It should be noted that when the prepared back-contact battery further includes a first passivation layer located between the first region and the first doped semiconductor layer, after providing the semiconductor substrate and before forming the first doped semiconductor layer on the first region, the preparation method of the back-contact battery further includes the following steps: adopting deposition and etching processes to first form a first passivation layer on the semiconductor substrate in the first region.

[0115] Alternatively, after providing the semiconductor substrate 11, a first passivation layer 18 provided as a whole layer on the back side can be formed by processes such as chemical vapor deposition. Then, after forming the first mask layer and selectively etching the first doped semiconductor layer 12 under the masking effect of the first mask layer, the first passivation layer 18 is selectively etched. In this case, there is no need to additionally form a corresponding mask layer for forming the first passivation layer 18, simplifying the preparation process of the back-contact battery.

[0116] Next, after making the thickness of the semiconductor substrate 11 in the first region 14 greater than the thicknesses of the semiconductor substrates 11 in the third region 16 and the second region 15, a second doped semiconductor layer 13 is formed on the second region 15; and making the thickness of the semiconductor substrate 11 in the second region 15 greater than the thickness of the semiconductor substrate 11 in the third region 16.

[0117] In the actual preparation process, after making the thickness of the semiconductor substrate 11 in the first region 14 greater than the thicknesses of the semiconductor substrates 11 in the third region 16 and the second region 15, deposit the second doped semiconductor layer 13 on the first doped semiconductor layer 12, the third region 16, and the second region 15; and form a second mask layer on the portion of the second doped semiconductor layer 13 corresponding to the second region 15. Next, under the masking effect of the second mask layer, selectively remove the portions of the second doped semiconductor layer 13 corresponding to the first region 14 and the third region 16; and make the thickness of the semiconductor substrate 11 in the second region 15 greater than the thickness of the semiconductor substrate 11 in the third region 16.

[0118] Exemplarily, when the material of the second doped semiconductor layer 13 includes silicon, depositing the second doped semiconductor layer 13 on the first doped semiconductor layer 12, the third region 16, and the second region 15; and forming the second mask layer on the portion of the second doped semiconductor layer 13 corresponding to the second region 15 may include the following steps: deposit a second intrinsic semiconductor layer on the first doped semiconductor layer 12, the third region 16, and the second region 15. Next, perform a doping process on the second intrinsic semiconductor layer to make the second intrinsic semiconductor layer form the second doped semiconductor layer 13, and form a second doped silicon glass layer provided as a whole layer on the second doped semiconductor layer 13. Then, use a laser etching process to perform a heat treatment on the portions of the second doped silicon glass layer corresponding to the first region 14 and the third region 16, so that the portion of the second doped silicon glass layer corresponding to the second region 15 forms the second mask layer. Then, remove the heat-treated portion of the second doped silicon glass layer.

[0119] Specifically, that the material of the second doped semiconductor layer includes silicon may mean that the material of the second doped semiconductor layer only includes silicon; or it may also mean that the material of the second doped semiconductor layer includes both silicon and other semiconductor materials such as germanium silicon. Secondly, in the actual preparation process, processes such as chemical vapor deposition can be used to form the second intrinsic semiconductor layer provided as a whole layer on the back side. Next, processes such as diffusion can be used to dope the second intrinsic semiconductor layer. After the above doping treatment, not only can the second doped semiconductor layer be obtained, but also a second doped silicon glass layer provided as a whole layer can be formed on the second doped semiconductor layer. Then, a laser etching process is used to perform heat treatment on the portions of the second doped silicon glass layer corresponding to the first region and the third region. At this time, the density of the portion of the second doped silicon glass layer treated by the laser becomes poor and it is easily removed. The portion of the second doped silicon glass layer corresponding to the second region is not treated by the laser. At this time, the density of the portion of the second doped silicon glass layer corresponding to the second region is relatively high and it is not easily removed. Thus, after the heat treatment, different parts of the second doped silicon glass layer have different etching selectivity ratios, and a second mask layer for patterning the second doped semiconductor layer is obtained, without the need to additionally form other mask materials and other mask deposition processes to obtain the second mask layer, which is beneficial to reducing the preparation cost of the back contact battery and simplifying the preparation process of the back contact battery. The pits can be formed during the process of using the laser etching process to perform heat treatment on a part of the second doped silicon glass layer.

[0120] Of course, in the case where the material of the second doped semiconductor layer includes silicon or the material of the second doped semiconductor layer does not include silicon, processes such as chemical vapor deposition and doping can also be used to form the second doped semiconductor layer provided as a whole layer on the back side. Then, processes such as chemical vapor deposition and etching can be used to form a second mask layer made of other materials with a masking effect such as silicon nitride.

[0121] In addition, after the second mask layer is formed, wet chemical processes or the like can be used to selectively remove the portions of the second doped semiconductor layer located on the third region and the first doped semiconductor layer under the masking effect of the second mask layer; and the thickness of the semiconductor substrate in the second region is made greater than the thickness of the semiconductor substrate in the third region. By using wet chemical processes or the like to selectively remove the portions of the second doped semiconductor layer located on the third region and the first doped semiconductor layer under the masking effect of the second mask layer, a groove structure recessed into the semiconductor substrate can be formed in the third region relative to the first region and the second region, and an exposed portion can exist in the second boundary region, where the exposed portion is the part where the second doped semiconductor layer does not extend to the edge of the sidewall of the semiconductor substrate or the edge of the top of the pit. As described above, the exposed portion between the edge of the top of the pit and the edge of the second doped semiconductor layer makes the edge of the second doped semiconductor layer close to the pit have a certain distance from the edge of the top of the pit.

[0122] In the actual preparation process, by using wet chemical processes or the like and under the masking effect of the mask layer, a groove structure recessed into the semiconductor substrate can be formed in the third region relative to the first region and the second region, which can prevent the semiconductor substrate from being damaged by high-temperature laser and is beneficial to improving the yield of the back-contact battery.

[0123] Specifically, the process conditions for selectively etching the second doped semiconductor layer can be determined according to the etching process used, the material of the second doped semiconductor layer, the thickness of the semiconductor substrate in the third region, etc., and no specific limitation is made here.

[0124] It should be noted that when the prepared back-contact battery further includes a second passivation layer located between the second region and the second doped semiconductor layer, after making the thickness of the semiconductor substrate in the first region 14 greater than the thicknesses of the semiconductor substrates in the third region 16 and the second region 15, and before forming the second doped semiconductor layer 13 on the second region 15, the preparation method of the back-contact battery further includes the following steps: using deposition and etching processes to first form the second passivation layer on the second region 15.

[0125] Alternatively, after making the thickness of the semiconductor substrate in the first region 14 greater than the thicknesses of the semiconductor substrates in the third region 16 and the second region 15, and before forming the second doped semiconductor layer 13 on the second region 15, chemical vapor deposition or the like can be used to deposit the second passivation layer 19 on the first doped semiconductor layer 12, the second region 15, and the third region 16. Then, after the second mask layer is formed and the second doped semiconductor layer 13 is selectively etched under the masking effect of the second mask layer, the second passivation layer 19 is selectively etched. In this case, there is no need to additionally form a corresponding mask layer for forming the second passivation layer 19, which simplifies the preparation process of the back-contact battery.

[0126] In addition, in the case where the prepared back-contact battery further includes a surface passivation layer covering the first doped semiconductor layer 12, the second doped semiconductor layer 13, and the third region 16, after making the thickness of the semiconductor substrate 11 in the second region 15 greater than the thickness of the semiconductor substrate 11 in the third region 16, processes such as chemical vapor deposition can be used to form a surface passivation layer 17 covering the first doped semiconductor layer 12, the second doped semiconductor layer 13, and the third region 16.

[0127] In a third aspect, the present application provides a photovoltaic module, including: a battery string formed by electrically connecting a plurality of back-contact batteries according to the first aspect; and a packaging layer covering the surface of the battery string.

[0128] For various deformation schemes and beneficial effects of the second and third aspects of the present application and their various implementation manners, reference can be made to the first aspect and its various implementation manners, which will not be elaborated herein.

[0129] In the above description, technical details such as the layout and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the required shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. In addition, although the above embodiments are described separately, this does not mean that the measures in each embodiment cannot be used in combination advantageously.

[0130] The embodiments of the present application have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present application. The scope of the present application is defined by the appended claims and their equivalents. Without departing from the scope of the present application, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present application. Unless there are technical obstacles or contradictions, the various technical features disclosed in the present application can be freely combined to form additional embodiments, and these additional embodiments are all within the protection scope of the present application.

Claims

1. A back contact battery, characterized in that: include: A semiconductor substrate, wherein the semiconductor substrate has a back surface, wherein the back surface is provided with at least one first region and at least one second region that are alternately distributed, and adjacent first regions and second regions are separated by a third region; A first doped semiconductor layer, wherein the first doped semiconductor layer is at least located on the semiconductor substrate in the first region; as well as a second doped semiconductor layer, the second doped semiconductor layer is at least located on the semiconductor substrate in the second region, and the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types, The third region has a first boundary region at a position adjacent to the first region, the third region has a second boundary region at a position adjacent to the second region, and the first boundary region and / or the second boundary region has one or more pits.

2. The back contact cell according to claim 1, characterized in that: The pit includes a closed pit and / or a non-closed pit, wherein the side of the closed pit is surrounded by the semiconductor substrate to form a closed structure, and the side of the non-closed pit is partially surrounded by the semiconductor substrate to form a non-closed structure.

3. The back contact battery according to claim 2, characterized in that: The semiconductor substrate has prisms around the side portions forming the closed pit and / or the non-closed pit.

4. The back contact cell according to claim 3, characterized in that: The prisms of at least one of the closed recesses are butted together to form at least one butt seam, and / or the prisms of at least one of the non-closed recesses are butt-jointed together to form at least one butt seam.

5. The back contact cell according to any one of claims 2 to 4, characterized in that: The first boundary area at least has the closed pit; and / or the second boundary area at least has the non-closed pit.

6. The back contact cell according to claim 5, characterized in that: One or both of the first boundary region and the second boundary region have the closed pits and the non-closed pits.

7. The back contact cell according to any one of claims 2 to 4, characterized in that: The number of closed pits in the first border area is greater than the number of closed pits in the second border area; and / or The number of non-closed pits in the second border area is greater than the number of non-closed pits in the first border area.

8. The back contact cell according to claim 1, characterized in that: At least part of the pit has an extended brim portion of the corresponding doped semiconductor layer above it, and / or at least part of the pit has an exposed portion not covered by the corresponding doped semiconductor layer near the top.

9. The back contact battery according to claim 8, characterized in that An extended brim portion of the first doped semiconductor layer is provided above at least part of the pits in the first boundary region, and / or an exposed portion not covered by the second doped semiconductor layer is provided near the top of at least part of the pits in the second boundary region.

10. The back contact cell according to claim 9, characterized in that: The thickness of the semiconductor substrate in the first region is greater than the thickness of the semiconductor substrate in the second region.

11. The back contact cell according to any one of claims 2 to 4, characterized in that: The first doped semiconductor layer has an extension portion, and / or the second doped semiconductor layer has an extension portion, at least one of the first doped semiconductor layer and the second doped semiconductor layer is overlapped to the other doped semiconductor layer of the first doped semiconductor layer and the second doped semiconductor layer through its extension portion, and the first boundary region further includes a first position where the third region is adjacent to the extension portion, or the second boundary region further includes a second position where the third region is adjacent to the extension portion.

12. The back contact cell according to claim 11, characterized in that: The total number of closed pits at at least one corner of the first position or the second position is not less than the total number of non-closed pits at the at least one corner.

13. The back contact cell according to any one of claims 2 to 4, characterized in that: The first boundary region includes a first sub-border region within 50 μm extending from the edge of the first region away from the third region toward the first region, the second boundary region includes a second sub-border region within 50 μm extending from the edge of the second region away from the third region toward the second region, and the first sub-border region and / or the second sub-border region have one or more pits.

14. The back contact cell according to any one of claims 2 to 4, characterized in that: The side walls of the semiconductor substrate in the first boundary region and / or the second boundary region present a wavy undulating structure in a direction perpendicular to the extension direction of the third region, and the closed pit is located at a protruding position of the undulating structure, or the non-closed pit is located at a recessed position of the undulating structure.

15. The back contact cell according to claim 13, characterized in that: In the first sub-boundary region and / or the second sub-boundary region, pits in the first sub-boundary region and the second sub-boundary region closer to the third region have a larger diameter than pits in the first sub-boundary region and the second sub-boundary region far away from the third region.

16. A method for preparing a back contact battery, characterized in that: include: Providing a semiconductor substrate, the semiconductor substrate having a back surface, the back surface being provided with at least one first region and at least one second region that are alternately distributed, and adjacent first regions and second regions are spaced apart by a third region; forming a first doped semiconductor layer on the semiconductor substrate in the first region; as well as forming a second doped semiconductor layer on the semiconductor substrate in the second region, wherein the first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity types; and The third region has a first boundary region at a position adjacent to the first region, the third region has a second boundary region at a position adjacent to the second region, and the first boundary region and / or the second boundary region has one or more pits.

17. The preparation method according to claim 16, characterized in that: The pit includes a closed pit and / or a non-closed pit, wherein the side of the closed pit is surrounded by the semiconductor substrate to form a closed structure, and the side of the non-closed pit is partially surrounded by the semiconductor substrate to form a non-closed structure.

18. The preparation method according to claim 17, characterized in that: The semiconductor substrate has prisms around the side portions forming the closed pit and / or the non-closed pit.

19. The preparation method according to claim 18, characterized in that: The first boundary area at least has the closed pit; and / or the second boundary area at least has the non-closed pit.

20. A photovoltaic module, characterized in that: include: A battery string, the battery string being formed by electrically connecting a plurality of back-contact batteries according to any one of claims 1 to 15; as well as A packaging layer covers a surface of the battery string.

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