Back contact battery and photovoltaic module

Abstract

The invention discloses a back contact cell and a photovoltaic module, relates to the technical field of photovoltaic, and aims to enable one side, deviating from a semiconductor substrate, of a second passivation layer to have a relatively high light trapping effect and enable a first passivation layer to have a relatively high passivation effect on an isolation region. The back contact cell includes a semiconductor substrate, a first doped semiconductor portion, a second doped semiconductor portion, a first passivation layer, and a second passivation layer. The first passivation layer covers the first doped semiconductor portion, the second doped semiconductor portion and the isolation region. In one side of the first passivation layer away from the semiconductor substrate, the surface of the part corresponding to the isolation region is a first region surface. The second passivation layer covers the second surface. Wherein the surface of the first area is provided with a suede area and a plurality of plane areas formed by surrounding of different pyramid-like structures included in the suede area. The surface of the side, away from the semiconductor substrate, of the second passivation layer is a suede, and the adjacent pyramid-like structures in the side, away from the semiconductor substrate, of the second passivation layer make contact with each other.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and particularly to a back-contact battery and a photovoltaic module. Background Art

[0002] A back-contact battery refers to a solar cell in which the light-facing surface of the cell has no electrodes, and the positive and negative electrodes are both disposed on the backlight side of the cell, thereby reducing the shielding of the electrodes on the cell and increasing the short-circuit current of the cell, improving the energy conversion efficiency of the cell. Moreover, on the back side of the back-contact battery, an isolation region is provided for isolating the first doped semiconductor portion and the second doped semiconductor portion with opposite conduction types and isolating the first doped semiconductor portion and the second doped semiconductor portion from the cell side boundary, for reducing the leakage risk and reducing the carrier recombination rate.

[0003] However, in the existing back-contact battery on the back side, the passivation effect of the first passivation layer on the isolation region is poor, which is not conducive to reducing the number of surface defects at the isolation region, resulting in poor working performance of the back-contact battery. Summary of the Invention

[0004] The purpose of the present invention is to provide a back-contact battery and a photovoltaic module, which, while having a high light-trapping effect on the side of the second passivation layer facing away from the semiconductor substrate, enable the first passivation layer to have a high passivation effect on the isolation region, reduce the number of surface defects at the isolation region, and are conducive to improving the working performance of the back-contact battery.

[0005] To achieve the above purpose, in a first aspect, the present invention provides a back-contact battery, which includes: a semiconductor substrate, a first doped semiconductor portion, a second doped semiconductor portion, a first passivation layer, and a second passivation layer. The semiconductor substrate includes opposite first and second surfaces. The first surface includes a first region, a second region, and an isolation region. The first region and the second region are alternately and spaced apart. The first surface has a boundary, and the isolation region is located between the first region and the second region and between the boundary and the outermost first region and the outermost second region respectively. The first doped semiconductor portion is disposed in or on the first region. The second doped semiconductor portion is disposed in or on the second region. The second doped semiconductor portion and the first doped semiconductor portion have opposite conduction types. The first passivation layer covers the first doped semiconductor portion, the second doped semiconductor portion, and the isolation region. On the side of the first passivation layer facing away from the semiconductor substrate, the surface of the portion corresponding to the isolation region is the first region surface. The second passivation layer covers the second surface. Wherein, the first region surface has a textured area and a plurality of planar areas surrounded by different pyramid-like structures included in the textured area. The surface of the side of the second passivation layer facing away from the semiconductor substrate is textured, and adjacent pyramid-like structures in the second passivation layer on the side facing away from the semiconductor substrate are in contact with each other.

[0006] In the case of adopting the above technical solution, in the back-contact battery provided by the present invention, a first doped semiconductor portion and a second doped semiconductor portion are provided on one side of the first surface of the semiconductor substrate. Based on this, it can be understood that the first surface of the semiconductor substrate corresponds to the back surface of the back-contact battery, and the second surface of the semiconductor substrate corresponds to the front surface of the back-contact battery. In this case, the second passivation layer included in the back-contact battery covers the second surface, and the surface on the side of the second passivation layer facing away from the semiconductor substrate is a matte surface. The adjacent pyramid-like structures within the second passivation layer on the side facing away from the semiconductor substrate are in contact with each other. At this time, the distribution density of the pyramid-like structures within the second passivation layer on the side facing away from the semiconductor substrate is relatively large, which is conducive to increasing the specific surface area of the second passivation layer on the side facing away from the semiconductor substrate, so that the second passivation layer on the side facing away from the semiconductor substrate has a good light-trapping effect, and the front side of the back-contact battery has a high light utilization rate.

[0007] In addition, the back-contact battery further includes a first passivation layer provided on the first doped semiconductor portion, the second doped semiconductor portion, and the isolation region. In the side of the first passivation layer facing away from the semiconductor substrate, the surface of the first region corresponding to the isolation region not only has a matte surface area, so that the surface of the first region has a certain light-trapping effect, but also the surface of the first region has a plurality of planar regions surrounded by different pyramid-like structures included in the matte surface area. The planar regions are flatter than the matte surface area, so that the surface of the first region has a lower surface roughness compared to the surface of the second passivation layer on the side facing away from the semiconductor substrate. In the actual manufacturing process, the first passivation layer is usually formed on the first doped semiconductor portion, the second doped semiconductor portion, and the isolation region by a deposition process. The surface morphology of the first region of the first passivation layer can reflect the surface morphology of the isolation region of the semiconductor substrate to a certain extent. Therefore, when the surface of the first region has a relatively small roughness due to the presence of planar regions, the surface roughness of the isolation region is also relatively small, which is beneficial to improving the formation quality and passivation effect of the first passivation layer on the isolation region, reducing the number of surface defects at the isolation region, and improving the working performance of the back-contact battery.

[0008] As a possible implementation solution, among all the pyramid-like structures on the surface of the second passivation layer on the side facing away from the semiconductor substrate and the surface of the first region, at least the pyramid-like structures with four side ridges distributed diagonally are complete pyramid-like structures, and the remaining pyramid-like structures are incomplete pyramid-like structures. Moreover, the proportion of the number of complete pyramid-like structures in all the pyramid-like structures per unit area on the side of the second passivation layer facing away from the semiconductor substrate is greater than the proportion of the number of complete pyramid-like structures in all the pyramid-like structures per unit area on the surface of the first region.

[0009] When the above technical solution is adopted, the number of complete pyramid-like structures per unit area on the surface of the first region is relatively small, so that the number of top corner undulating microstructures of incomplete pyramid-like structures on the surface of the first region is greater, which is beneficial to improving the light trapping effect of the surface of the first region and improving the double-sidedness rate of the back contact battery.

[0010] As a possible implementation scheme, in the velvet area included in the first region surface, at least one side of the pyramid-like structure has a sheet-like protrusion. Along the extension direction of the side of the pyramid-like structure, the cross-section of the sheet-like protrusion is in a triangular shape.

[0011] In the case of adopting the above technical solution, in addition to the pyramid-like structure, at least one pyramid-like structure in the velvet area included in the surface of the first region has a sheet-like protrusion on its side. The sheet-like protrusion can superimpose its own undulation on the pyramid-like structure that originally has an undulating morphology, and the cross-sectional shape of the sheet-like protrusion is a triangular shape. Compared with a hemispherical or other smooth morphology, the triangular shape has a certain sharp microstructure, which is conducive to further increasing the roughness of the surface of the first region, improving the light trapping effect of the surface of the first region, and further facilitating the improvement of the bifaciality of the back contact battery.

[0012] As a possible implementation scheme, the top angle of at least one pyramid-like structure on the surface of the first region is greater than the top angle of the pyramid-like structure on the side of the second passivation layer facing away from the semiconductor substrate.

[0013] When the above technical solution is adopted, compared with the pyramid-like structure of the second passivation layer on the side away from the semiconductor substrate, at least one pyramid-like structure on the surface of the first area has a relatively large apex angle. At this time, the top of at least one pyramid-like structure on the surface of the first area is less sharp, which is correspondingly beneficial to making the surface undulations of the isolation area less sharp, thereby reducing the stress of the first passivation layer at the undulations of the isolation area, reducing the risk of damage to the first passivation layer in the isolation area, and further improving the passivation effect of the first passivation layer on the isolation area.

[0014] As a possible implementation scheme, a one-dimensional size of at least one pyramid-like structure on the surface of the first region is larger than a one-dimensional size of a pyramid-like structure on a side of the second passivation layer facing away from the semiconductor substrate.

[0015] In the case of adopting the above technical solution, compared with the pyramid-like structure on the side of the second passivation layer away from the semiconductor substrate, at least one pyramid-like structure on the surface of the first region has a relatively large one-dimensional size, which is beneficial to reducing the distribution quantity of the pyramid-like structures on the surface of the first region, reducing the undulation density on the surface of the first region, correspondingly beneficial to making the undulation density on the surface of the isolation region relatively low, thereby reducing the stress at the undulations of the first passivation layer in the isolation region and reducing the breakage risk of the first passivation layer on the isolation region, and further improving the passivation effect of the first passivation layer on the isolation region.

[0016] As a possible implementation solution, the first doped semiconductor part is an emitter doping part. The surface of the isolation region includes a first sub-surface between the boundary and the outermost first region, and a second sub-surface between the boundary and the outermost second region. In the surface of the first passivation layer on the side away from the semiconductor substrate, the region surface corresponding to the first sub-surface (close to the emitter doping part) is the first sub-region surface, and the region surface corresponding to the second sub-surface is the second sub-region surface. The first sub-region surface and the second sub-region surface have pyramid-like structures. Among them, the one-dimensional size of the pyramid-like structure in the first sub-region surface is larger than the one-dimensional size of the pyramid-like structure in the second sub-region surface; and / or, the uniformity of the one-dimensional size of the pyramid-like structure in the first sub-region surface is greater than the uniformity of the one-dimensional size of the pyramid-like structure in the second sub-region surface; and / or, the apex angle of the pyramid-like structure in the first sub-region surface is smaller than the apex angle of the pyramid-like structure in the second sub-region surface.

[0017] In the case of adopting the above technical solution, in the surface of the first passivation layer on the side away from the semiconductor substrate, at least one of the one-dimensional size, the uniformity of the one-dimensional size, and the apex angle of the pyramid-like structure on the first sub-region surface corresponding to the first sub-surface (close to the emitter doping part) is larger than that of the pyramid-like structure on the second sub-region surface, which is beneficial to increasing the undulation degree and surface roughness of the first sub-region surface, beneficial to improving the light trapping effect of the first sub-region surface, and beneficial to making more light refract into the first doped semiconductor part adjacent to the first sub-region surface, thereby improving the bifaciality of the back contact battery. At the same time, the first doped semiconductor part is an emitter doping part. Since the emitter doping part is used to provide the injection and separation of electron-hole pairs, when more light is incident on the emitter doping part, it is beneficial to excite more photo-generated carriers, and thus beneficial to improving the conversion efficiency of the back contact battery. And the second sub-region surface corresponding to the second sub-surface has a relatively low surface roughness. Correspondingly, the second sub-surface also has a relatively low surface roughness, which is beneficial to improving the deposition quality and passivation effect of the first passivation layer on the second sub-surface.

[0018] As a possible implementation, the isolation region surface includes a first sub-surface located between the boundary and the outermost first region, a second sub-surface located between the boundary and the outermost second region, and a third sub-surface located between the first region and the second region. Moreover, in the surface on the side of the first passivation layer away from the semiconductor substrate, the regional surface corresponding to the first sub-surface is the first sub-regional surface, the regional surface corresponding to the second sub-surface is the second sub-regional surface, and the regional surface corresponding to the third sub-surface is the third sub-regional surface. The second sub-regional surface and the third sub-regional surface have a quasi-pyramid structure. When the conductivity type of the second doped semiconductor portion is the same as that of the semiconductor substrate, the one-dimensional size of the quasi-pyramid structure of the second sub-regional surface is smaller than the one-dimensional size of the quasi-pyramid structure of the third sub-regional surface, and / or the apex fillet curvature of the quasi-pyramid structure of the second sub-regional surface is greater than the apex fillet curvature of the quasi-pyramid structure of the third sub-regional surface.

[0019] In the case of adopting the above technical solution, the part of the isolation region located between the first region and the second region is mainly used to isolate the first doped semiconductor portion and the second doped semiconductor portion with opposite conductivity types, reducing the leakage between the two. Therefore, when the third sub-regional surface corresponding to the third sub-surface in the surface on the side of the first passivation layer away from the semiconductor substrate has a relatively large one-dimensional size and a small apex fillet curvature, the third sub-regional surface has a relatively large surface roughness, and correspondingly, the third sub-surface also has a large undulating topography, so that the etching degree of the isolation region in the region corresponding to the third sub-surface is relatively high, which is conducive to further reducing the leakage risk between the first doped semiconductor portion and the second doped semiconductor portion. In addition, the second sub-regional surface has a small quasi-pyramid structure and a large apex fillet curvature of the quasi-pyramid structure, which is conducive to making the second sub-regional surface and the second sub-surface have a low surface roughness, improving the passivation effect of the first passivation layer on the second sub-surface, and reducing the number of defects on the second sub-surface.

[0020] As a possible implementation, the first surface is quasi-rectangular. Along the extension direction parallel to the long side of the quasi-rectangle, the widths of the parts of the first sub-regional surface and the second sub-regional surface adjacent to one short side in the quasi-rectangle are greater than the widths of the parts of the first sub-regional surface and the second sub-regional surface adjacent to the other short side in the quasi-rectangle.

[0021] In the case of adopting the above technical solution, when the widths of the parts of the first sub-region surface and the second sub-region surface adjacent to a short side of the quasi-rectangle are greater than the widths of the parts of the first sub-region surface and the second sub-region surface adjacent to the other short side of the quasi-rectangle respectively, it indicates that along the extension direction parallel to the long side of the quasi-rectangle, the etching amounts of the first doped semiconductor part and the second doped semiconductor part at the two short sides are different. The difference in the etching amount is because when using equipment such as chain cleaning to remove the circumferential plating on the second surface of the semiconductor substrate, due to the influence of liquid turning, the amount of liquid turning at the front end along the traveling direction is relatively large, and thus the etching amounts of the first doped semiconductor part and the second doped semiconductor part at the short sides corresponding to the etching front end are relatively large. It can be seen that the extension direction of the long side of the quasi-rectangle is consistent with the etching traveling direction, which can reduce the degree of influence on the etching accuracy caused by factors such as structural jitter during the etching process, improve the etching stability and etching accuracy, and thus is beneficial to improving the yield of the back-contact battery.

[0022] As a possible implementation solution, along the extension direction parallel to the long side, the widths of the parts of the first sub-region surface and the second sub-region surface adjacent to a short side of the quasi-rectangle are greater than or equal to 10 μm and less than or equal to 50 μm; and / or, the widths of the parts of the first sub-region surface and the second sub-region surface adjacent to the other short side of the quasi-rectangle are greater than or equal to 3 μm and less than or equal to 10 μm. In this case, while ensuring that the circumferential plating on the second surface of the semiconductor substrate can be completely removed through the etching operation, a certain distance can be maintained between the boundaries of the parts of the first doped semiconductor part and the second doped semiconductor part at the edge and the first surface, which is beneficial to reducing the leakage risk. In addition, it can also prevent the influence on the area ratio of the first doped semiconductor part and the second doped semiconductor part on the first surface due to the excessive above-mentioned widths, which is beneficial to the first doped semiconductor part and the second doped semiconductor part having a high carrier collection ability and field passivation effect.

[0023] As a possible implementation solution, the side line of the second doped semiconductor part at at least one corner close to the first surface has a wavy concave-convex alternating structure. In this case, there is no need to strictly control the manufacturing accuracy to obtain a straight side line, which is beneficial to reducing the manufacturing process difficulty. In addition, there are convex parts along the direction close to the corner in the side line of the second doped semiconductor part at at least one corner close to the first surface, which can increase the area ratio of the second doped semiconductor part on one side of the first surface, and is beneficial to the second doped semiconductor part having a high carrier collection ability and field passivation effect.

[0024] As a possible implementation solution, both the first region and the second region include strip regions and connection regions. The strip regions included in the first region and the strip regions included in the second region both extend in a first direction and are alternately and spaced apart in a second direction. The first direction is different from the second direction. The connection regions included in the first region and the connection regions included in the second region both extend in the second direction and are alternately and spaced apart in the first direction. The connection regions included in the first region are connected to at least part of the strip regions included in the first region, and the connection regions included in the second region are connected to at least part of the strip regions included in the second region. The strip regions included in the first region are disconnected at the intersection with the connection regions included in the second region, and the strip regions included in the second region are disconnected at the intersection with the connection regions included in the first region. The first surface has a chamfer, and the first region has an extension at the chamfer. The extension extends in the second direction and is spaced apart from the strip regions included in the second region in the first direction. In the first doped semiconductor portion, the edge line of the portion near the chamfer has a first undulating morphology, and the edge line of the portion near the contour line continuous with the chamfer has a second undulating morphology. Wherein, along the direction from the edge to the center of the first surface, the undulating height of the first undulating morphology is greater than the undulating height of the second undulating morphology, and / or the width of the convex portion in the first undulating morphology is less than the width of the convex portion in the second undulating morphology.

[0025] In the case of adopting the above technical solution, there is no need to strictly control the manufacturing precision in order to obtain a straight edge line, which is beneficial to reducing the difficulty of the manufacturing process. In addition, due to the influence of factors such as cutting, there are more surface defects at the chamfer of the first surface. Therefore, when the undulating height of the first undulating morphology near the chamfer is greater than the undulating height of the second undulating morphology near the contour line continuous with the chamfer, the distance between the concave portion of the first doped semiconductor portion at the chamfer and the chamfer boundary is greater, which is beneficial to reducing the leakage risk. And when the width of the convex portion in the first undulating morphology is less than the width of the convex portion in the second undulating morphology, the setting density of the concave portion in the first undulating morphology is greater, which can also reduce the leakage risk.

[0026] As a possible implementation solution, the undulating height of the first undulating morphology is greater than or equal to 3 μm and less than or equal to 10 μm; and / or the width of the convex portion in the first undulating morphology is greater than or equal to 15 μm and less than or equal to 40 μm. In this case, while further reducing the leakage risk, the first doped semiconductor portion has a larger area ratio on one side of the first surface, which is beneficial to improving the carrier collection ability and field passivation effect of the first doped semiconductor portion.

[0027] In a second aspect, the present invention provides a photovoltaic module, and the photovoltaic module includes the back contact battery provided by the first aspect and its various implementation manners.

[0028] For the beneficial effects of the second aspect and its various implementation manners in the present invention, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementation manners, and details are not described herein again. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The drawings described herein are used to provide a further understanding of the present invention, and constitute a part of the present invention. The schematic embodiments and descriptions thereof of the present invention are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0030] Figure 1 is a longitudinal sectional schematic view of the first structure of the back contact battery provided by an embodiment of the present invention;

[0031] Figure 2 is an SEM image of a partial area on the side of the second passivation layer facing away from the semiconductor substrate in the back contact battery provided by an embodiment of the present invention;

[0032] Figure 3 is an SEM image of the surface of a partial first area in the back contact battery provided by an embodiment of the present invention;

[0033] Figure 4 is an SEM image of the surface of a partial first sub-area in the back contact battery provided by an embodiment of the present invention;

[0034] Figure 5 is an SEM image of the surface of a partial second sub-area in the back contact battery provided by an embodiment of the present invention;

[0035] Figure 6 is a schematic diagram showing the distribution relationship between the first area and the second area in the back contact battery provided by an embodiment of the present invention Figure 1 ;

[0036] Figure 7 is a schematic diagram showing the distribution relationship between the first area and the second area in the back contact battery provided by an embodiment of the present invention Figure 2 ;

[0037] Figure 8 is a schematic diagram showing the distribution relationship between the first area and the second area in the back contact battery provided by an embodiment of the present invention Figure 3 ;

[0038] Figure 9 is a longitudinal sectional schematic view of the second structure of the back contact battery provided by an embodiment of the present invention;

[0039] Figure 10 is a longitudinal sectional schematic view of the third structure of the back contact battery provided by an embodiment of the present invention;

[0040] Figure 11 is a longitudinal sectional schematic view of the fourth structure of the back contact battery provided by an embodiment of the present invention;

[0041] Figure 12 It is a longitudinal sectional view schematic diagram of the fifth structure of the back-contact battery provided by the embodiment of the present invention;

[0042] Figure 13 It is a schematic diagram of the distribution relationship between a part of the first doped semiconductor part and a part of the second doped semiconductor part in the back-contact battery provided by the embodiment of the present invention;

[0043] Figure 14 It is a schematic diagram of the distribution of a part of the second doped semiconductor part in the back-contact battery provided by the embodiment of the present invention;

[0044] Figure 15 It is a longitudinal sectional view schematic diagram of the sixth structure of the back-contact battery provided by the embodiment of the present invention;

[0045] Figure 16 It is a longitudinal sectional view schematic diagram of the seventh structure of the back-contact battery provided by the embodiment of the present invention;

[0046] Figure 17 It is a longitudinal sectional view schematic diagram of the eighth structure of the back-contact battery provided by the embodiment of the present invention.

[0047] Reference numerals: 11 is a semiconductor substrate, 12 is a first region, 13 is a second region, 14 is an isolation region, 15 is a first doped semiconductor part, 16 is a second doped semiconductor part, 17 is a first passivation layer, 18 is a second passivation layer, 19 is the surface of the first region, 20 is a matte area, 21 is a planar area, 22 is a complete pseudo-pyramid structure, 23 is an incomplete pseudo-pyramid structure, 24 is a sheet-like protrusion, 25 is a first sub-surface, 26 is a second sub-surface, 27 is a third sub-surface, 28 is the surface of the first sub-region, 29 is the surface of the second sub-region, 30 is the surface of the third sub-region, 31 is a strip area, 32 is a connection area, 33 is an extension part, 34 is a first surface passivation layer, 35 is a first antireflection layer, 36 is a first transparent conductive layer, 37 is a second surface passivation layer, 38 is a second antireflection layer, 39 is a first interface passivation layer, 40 is a second interface passivation layer. Detailed implementation manners

[0048] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present invention.

[0049] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, where in order to express more clearly, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0050] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element can be "under" the other layer / element. In order to make the technical problems to be solved, technical solutions, and beneficial effects of the present invention more clearly understood, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0051] Furthermore, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, the meaning of "a plurality" is two or more, unless otherwise specifically defined. The meaning of "several" is one or more, unless otherwise specifically defined.

[0052] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0053] A solar cell is a device that can convert the light energy of the sun into electrical energy. Specifically, when the solar cell is in a working state, sunlight shines on the semiconductor p-n junction of the solar cell, forming new hole-electron pairs. Under the action of the built-in electric field in the p-n junction, the photo-generated holes flow to the p region, and the photo-generated electrons flow to the n region. After connecting the circuit, an electric current can be generated. Among them, a back-contact cell is a solar cell in which both the positive electrode and the negative electrode are located on the back surface of the cell. Compared with a double-sided contact solar cell, the front surface of this back-contact cell has no metal electrode obstruction, so that the light-facing side of the back-contact cell has a higher light utilization rate. Therefore, the back-contact cell has a higher short-circuit current and photoelectric conversion efficiency, and is one of the technical directions for realizing high-efficiency crystalline silicon cells at present.

[0054] Specifically, the back-contact cell generally includes a semiconductor substrate, a first doped semiconductor portion, a second doped semiconductor portion, and a first passivation layer. Among them, the first doped semiconductor portion and the second doped semiconductor portion are alternately and spaced apart on one side of the semiconductor substrate corresponding to the back surface of the cell. Moreover, the back-contact cell has isolation regions between the first doped semiconductor portion and the second doped semiconductor portion with opposite conduction types, and between the side boundaries of the first doped semiconductor portion and the second doped semiconductor portion and the semiconductor substrate, for reducing the leakage risk and reducing the carrier recombination rate. The first passivation layer covers the sides of the first doped semiconductor portion and the second doped semiconductor portion facing away from the semiconductor substrate, and covers the isolation regions, for reducing the number of defects on the contact surface and reducing the carrier recombination rate.

[0055] In addition, in order to improve the light utilization rate of the back-contact cell, texturing is usually performed on the light-facing side of the cell and the isolation regions to improve the light trapping effect in these two regions. And, in the actual manufacturing process, in order to improve the manufacturing efficiency of the back-contact cell, the texturing operations on the light-facing side of the cell and on the isolation regions are carried out simultaneously, which results in a larger specific surface area and a higher surface roughness in the isolation regions, making the passivation effect of the first passivation layer on the isolation regions poor, not conducive to reducing the number of surface defects in the isolation regions, and resulting in poor working performance of the back-contact cell.

[0056] To solve the above technical problems, on the one hand, an embodiment of the present invention provides a back-contact cell. As Figures 1 to 5As shown in the figure, the back contact battery provided by the embodiment of the present invention includes: a semiconductor substrate 11, a first doped semiconductor portion 15, a second doped semiconductor portion 16, a first passivation layer 17, and a second passivation layer 18. The semiconductor substrate 11 includes opposite first and second surfaces. The first surface includes a first region 12, a second region 13, and an isolation region 14. The first region 12 and the second region 13 are alternately and spaced apart. The first surface has a boundary, and the isolation region 14 is located between the first region 12 and the second region 13, and between the boundary and the outermost first region 12 and the outermost second region 13 respectively. The first doped semiconductor portion 15 is disposed within or on the first region 12. The second doped semiconductor portion 16 is disposed within or on the second region 13. The second doped semiconductor portion 16 and the first doped semiconductor portion 15 have opposite conductivity types. The first passivation layer 17 covers the first doped semiconductor portion 15, the second doped semiconductor portion 16, and the isolation region 14. On the side of the first passivation layer 17 facing away from the semiconductor substrate 11, the surface of the portion corresponding to the isolation region 14 is the first region surface 19. The second passivation layer 18 covers the second surface. Wherein, the first region surface 19 has a matte area 20 and a plurality of planar areas 21 surrounded by different pyramid-like structures included in the matte area 20. The surface of the side of the second passivation layer 18 facing away from the semiconductor substrate 11 is matte, and adjacent pyramid-like structures within the side of the second passivation layer 18 facing away from the semiconductor substrate 11 are in contact with each other.

[0057] In the case of adopting the above technical solution, as Figures 1 to 5 shown, in the back contact battery provided by the embodiment of the present invention, a first doped semiconductor portion 15 and a second doped semiconductor portion 16 are disposed on one side of the first surface of the semiconductor substrate 11. Based on this, it can be understood that the first surface of the semiconductor substrate 11 corresponds to the back surface of the back contact battery, and the second surface of the semiconductor substrate 11 corresponds to the front surface of the back contact battery. In this case, the second passivation layer 18 included in the back contact battery covers the second surface, and the surface of the side of the second passivation layer 18 facing away from the semiconductor substrate 11 is matte, and adjacent pyramid-like structures within the side of the second passivation layer 18 facing away from the semiconductor substrate 11 are in contact with each other. At this time, the distribution density of the pyramid-like structures within the side of the second passivation layer 18 facing away from the semiconductor substrate 11 is relatively large, which is conducive to increasing the specific surface area of the side of the second passivation layer 18 facing away from the semiconductor substrate 11, so that the side of the second passivation layer 18 facing away from the semiconductor substrate 11 has a good light trapping effect, and the front side of the back contact battery has a high light utilization rate. In addition, as Figures 1 to 5As shown, the back-contact battery further includes a first passivation layer 17 disposed on the first doped semiconductor portion 15, the second doped semiconductor portion 16, and the isolation region 14. On the side of the first passivation layer 17 facing away from the semiconductor substrate 11, the first region surface 19 corresponding to the isolation region 14 not only has a textured region 20, so that the first region surface 19 has a certain light-trapping effect, but also the first region surface 19 further has a plurality of planar regions 21 surrounded by different pyramid-like structures included in the textured region 20. The planar regions 21 are flatter than the textured region 20, such that the first region surface 19 has a lower surface roughness relative to the surface of the second passivation layer 18 on the side facing away from the semiconductor substrate 11. In the actual manufacturing process, the first passivation layer 17 is usually formed on the first doped semiconductor portion 15, the second doped semiconductor portion 16, and the isolation region 14 by a deposition process. The topography of the first region surface 19 of the first passivation layer 17 can to a certain extent reflect the surface topography of the isolation region 14 of the semiconductor substrate 11. Therefore, when the first region surface 19 has planar regions 21 and its own roughness is relatively small, the surface roughness of the isolation region 14 is also relatively small, which is beneficial to improving the formation quality and passivation effect of the first passivation layer 17 on the isolation region 14, reducing the number of surface defects at the isolation region 14, and is beneficial to improving the working performance of the back-contact battery.

[0058] In the actual application process, the embodiments of the present invention do not make specific limitations on the material and conductivity type of the semiconductor substrate. Exemplarily, the above semiconductor substrate may be a silicon substrate. Alternatively, the above semiconductor substrate may also be a substrate of any semiconductor material such as a germanium-silicon substrate, a germanium substrate, or a gallium arsenide substrate. Secondly, the semiconductor substrate may be a P-type semiconductor substrate, an N-type semiconductor substrate, or an intrinsic semiconductor substrate.

[0059] Secondly, the above semiconductor substrate includes opposite first and second surfaces. The first surface of the semiconductor substrate corresponds to the back surface of the back-contact battery, and the second surface of the semiconductor substrate corresponds to the front surface of the back-contact battery. Among them, the distribution of the first region, the second region, and the isolation region on the first surface can be determined according to the distribution of the first doped semiconductor portion and the second doped semiconductor portion formed on one side of the first surface. Specifically, since the first doped semiconductor portion included in the back-contact battery is disposed in or on the first region, the distribution range of the first region on the first surface can be determined according to the distribution requirements of the first doped semiconductor portion in the actual application scenario. Since the second doped semiconductor portion included in the back-contact battery is disposed in or on the second region of the first surface, the distribution range of the second region on the first surface can be determined according to the distribution requirements of the second doped semiconductor portion on one side of the first surface of the semiconductor substrate. As for the isolation region, after the ranges of the first region and the second region are determined, the range of the isolation region in the first surface is also determined.

[0060] It can be understood that in the first surface of the semiconductor substrate, one of the first region and the second region roughly corresponds to the emitter region, and the other roughly corresponds to the back field region. Among them, one of the first region and the second region corresponds to the P region, and the other corresponds to the N region, and the isolation region is the other region in the first surface except the P region and the N region.

[0061] As for the shapes of the first region, the second region and the isolation region, they can be determined according to the actual application scenarios and are not specifically limited here. For example: as Figure 6 shown, the first region 12 and the second region 13 can be alternately distributed at intervals in a strip shape. Another example: as Figure 7 and Figure 8 shown, at least some regions of the first region 12 and the second region 13 can also be alternately distributed at intervals in an interdigitated shape.

[0062] As for the specific surface topography of the second surface of the semiconductor substrate, it can be understood that the second passivation layer is formed on the second surface by a deposition process. The surface undulation topography on the side of the second passivation layer facing away from the semiconductor substrate can, to a certain extent, reflect the surface undulation topography of the second surface of the semiconductor substrate. Therefore, the surface topography of the second surface can refer to the surface topography of the side of the second passivation layer facing away from the semiconductor substrate. In some examples, as Figure 1 shown, since the surface of the side of the second passivation layer 18 facing away from the semiconductor substrate 11 is a matte surface, and the adjacent pyramid-like structures inside the side of the second passivation layer 18 facing away from the semiconductor substrate 11 are in contact with each other, the second surface of the semiconductor substrate 11 is a matte surface, and the adjacent pyramid-like structures inside the second surface are in contact with each other. As for the specific topography, one-dimensional size and distribution of the pyramid-like structures in the second surface, etc., reference can be made to the specific topography, one-dimensional size and distribution of the pyramid-like structures on the side of the second passivation layer 18 facing away from the semiconductor substrate 11 in the following text, and details are not elaborated here.

[0063] Regarding the specific topography of the first surface of the semiconductor substrate, as described above, the surface undulation topography on the side of the first passivation layer facing away from the semiconductor substrate can, to a certain extent, reflect the surface undulation topography of the first surface of the semiconductor substrate. Therefore, the surface topography of the first doped semiconductor portion and the second doped semiconductor portion on the side facing away from the semiconductor substrate, as well as the surface topography of the isolation region in the first surface, can refer to the surface topography of the first passivation layer on the side facing away from the semiconductor substrate. In some examples, the surface of the first region corresponding to the isolation region on the side of the first passivation layer facing away from the semiconductor substrate has a matte region and a plurality of planar regions surrounded by different pyramid-like structures included in the matte region. Therefore, on the first surface of the semiconductor substrate, the surface of the isolation region has a matte region and a plurality of planar regions surrounded by different pyramid-like structures included in the matte region, so as to improve the passivation effect of the first passivation layer on the isolation region and reduce the carrier recombination rate at the isolation region. Among them, information such as the range and distribution of the matte region and the planar region of the isolation region, as well as the one-dimensional size, topography, and distribution of the pyramid-like structures in the matte region, can refer to the information such as the range and distribution of the matte region and the planar region of the first region surface in the following text, as well as the one-dimensional size, topography, and distribution of the pyramid-like structures in the matte region. For example, the planar region can include a planar structure, a regular or irregular tower base structure, etc., as long as it is flatter and has a lower roughness than the matte region.

[0064] In addition, for the isolation region, as Figure 1 shown, the surface of the isolation region includes a first sub-surface 25 located between the boundary and the outermost first region 12, a second sub-surface 26 located between the boundary and the outermost second region 13, and a third sub-surface 27 located between the first region 12 and the second region 13. Correspondingly, in the surface of the first passivation layer 17 on the side facing away from the semiconductor substrate 11, the regional surface corresponding to the first sub-surface 25 is the first sub-regional surface 28, the regional surface corresponding to the second sub-surface 26 is the second sub-regional surface 29, and the regional surface corresponding to the third sub-surface 27 is the third sub-regional surface 30. Among them, the surface topography of the first sub-surface 25, the second sub-surface 26, and the third sub-surface 27 of the isolation region 14 can respectively refer to the surface topography of the first sub-regional surface 28, the second sub-regional surface 29, and the third sub-regional surface 30 in the following text of the side of the first passivation layer 17 facing away from the semiconductor substrate 11, which will not be elaborated here.

[0065] For the above-mentioned first doped semiconductor portion and second doped semiconductor portion, in terms of the conduction type, the embodiments of the present invention do not specifically limit the conduction types of the first doped semiconductor portion and the second doped semiconductor portion, as long as the conduction types of the first doped semiconductor portion and the second doped semiconductor portion are opposite. Specifically, the conduction type of the first doped semiconductor portion may be N-type, and the conduction type of the second doped semiconductor portion is P-type. Or, the conduction type of the first doped semiconductor portion may also be P-type, and the conduction type of the second doped semiconductor portion is N-type.

[0066] In terms of the formation position, as Figure 1 , Figures 9 to 11 shown, the first doped semiconductor portion 15 may be a doped region disposed in the first region 12, or may be a doped semiconductor layer formed on the first region 12. Secondly, the second doped semiconductor portion 16 may be a doped region disposed in the second region 13, or may be a doped semiconductor layer formed on the second region 13.

[0067] Both the first doped semiconductor portion and the second doped semiconductor portion may be doped regions formed within the semiconductor substrate; or they may both be doped semiconductor layers formed on the semiconductor substrate; or one of the first doped semiconductor portion and the second doped semiconductor portion may be a doped region and the other may be a doped semiconductor layer.

[0068] Wherein, when the first doped semiconductor portion and / or the second doped semiconductor portion is a doped semiconductor layer, the material of the doped semiconductor layer may include any one of semiconductor materials such as silicon, silicon germanium, germanium, or gallium arsenide. In terms of the arrangement form of the substance, the crystal phase of the doped semiconductor layer may be amorphous, microcrystalline, nanocrystalline, single crystal, or polycrystalline, etc.

[0069] When both the first doped semiconductor portion and the second doped semiconductor portion are doped semiconductor layers, the materials of the first doped semiconductor portion and the second doped semiconductor portion may be the same or different.

[0070] For example: The materials of the first doped semiconductor portion and the second doped semiconductor portion may both be polysilicon or amorphous silicon.

[0071] Another example: The material of one of the first doped semiconductor portion and the second doped semiconductor portion includes polysilicon, and the material of the other includes amorphous silicon.

[0072] Secondly, as Figure 1 shown, when the first doped semiconductor portion 15 is a doped semiconductor layer, the first doped semiconductor portion 15 may be directly disposed on the first region 12. Or, as Figure 12As shown, the above-mentioned back-contact battery may further include a first interface passivation layer 39 located between the first doped semiconductor portion 15 and the semiconductor substrate 11. In this case, the passivation contact structure composed of the first interface passivation layer 39 and the first doped semiconductor portion 15 has an excellent interface passivation effect, can achieve selective carrier collection, reduce the carrier recombination rate in the first region 12 of the first surface of the semiconductor substrate 11, and further improve the photoelectric conversion efficiency of the back-contact battery. The material and thickness of the first interface passivation layer 39 can be set according to the material of the first doped semiconductor portion 15 and actual requirements, and no specific limitation is made here. For example, when the material of the first doped semiconductor portion is doped polysilicon, the first interface passivation layer is a tunneling oxide layer. Another example is that when the material of the first doped semiconductor portion includes at least one of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the first interface passivation layer is an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, an intrinsic nanocrystalline silicon layer, or a mixed layer of the above three.

[0073] Regarding the second doped semiconductor portion, as Figure 1 shown, when the second doped semiconductor portion 16 is a doped semiconductor layer, the above-mentioned second doped semiconductor portion 16 can be directly disposed on the second region 13. Or, as Figure 12 shown, the above-mentioned back-contact battery may further include a second interface passivation layer 40, and the second interface passivation layer 40 is located between the semiconductor substrate 11 and the second doped semiconductor portion 16. In this case, the passivation contact structure composed of the second interface passivation layer 40 and the second doped semiconductor portion 16 can achieve selective carrier collection and reduce the carrier recombination rate in the second region 13 of the first surface of the semiconductor substrate 11. The principle of setting the material and thickness of the second interface passivation layer 40 can refer to the principle of setting the material and thickness of the first interface passivation layer 39 described above, and will not be elaborated here.

[0074] Regarding the edge morphology of the first doped semiconductor portion and the second doped semiconductor portion near the isolation region, it can be determined according to the morphologies of the first region and the second region, the conduction types of the first doped semiconductor portion and the second doped semiconductor portion, and the manufacturing sequence of the two, and no specific limitation is made here.

[0075] Exemplarily, as Figure 7 and Figure 8As shown, both the first region 12 and the second region 13 on the first surface include a strip region 31 and a connection region 32. The strip region 31 included in the first region 12 and the strip region 31 included in the second region 13 both extend in the first direction and are alternately spaced along the second direction. The first direction is different from the second direction. Moreover, the connection region 32 included in the first region 12 and the connection region 32 included in the second region 13 both extend in the second direction and are alternately spaced along the first direction. The connection region 32 included in the first region 12 is connected to at least a part of the strip region 31 included in the first region 12, and the connection region 32 included in the second region 13 is connected to at least a part of the strip region 31 included in the second region 13. The strip region 31 included in the first region 12 is disconnected at the intersection with the connection region 32 included in the second region 13, and the strip region 31 included in the second region 13 is disconnected at the intersection with the connection region 32 included in the first region 12. In the above case, as Figure 13 shown, the first surface has a chamfer, and the first region 12 has an extension 33 at the chamfer. The extension 33 extends in the second direction, and the extension 33 and the strip region 31 included in the second region 13 are spaced along the first direction. In the first doped semiconductor portion 15, the edge line of the portion near the chamfer has a first undulating morphology, and the edge line of the portion near the contour line continuous with the chamfer has a second undulating morphology. Among them, along the direction from the edge to the center of the first surface, the undulating height of the first undulating morphology is greater than that of the second undulating morphology, and / or the width of the convex portion in the first undulating morphology is smaller than the width of the convex portion in the second undulating morphology.

[0076] In the case of adopting the above technical solution, there is no need to strictly control the manufacturing accuracy in order to obtain a straight edge line, which is beneficial to reducing the difficulty of the manufacturing process. In addition, due to the influence of factors such as cutting, there are more surface defects at the chamfer of the first surface. Therefore, when the undulating height of the first undulating morphology near the chamfer is greater than the undulating height of the second undulating morphology near the contour line continuous with the chamfer, the distance between the concave portion of the first doped semiconductor portion at the chamfer and the chamfer boundary is greater, which is beneficial to reducing the leakage risk. And when the width of the convex portion in the first undulating morphology is smaller than the width of the convex portion in the second undulating morphology, the setting density of the concave portion in the first undulating morphology is greater, which can also reduce the leakage risk.

[0077] Specifically, the above first direction and second direction can be any two directions parallel to the first surface and different from each other. Optionally, the first direction and the second direction are orthogonal.

[0078] In addition, the lengths of the connection regions included in the first region and the second region, the number of rows of the strip regions arranged along the second direction included in the first region and the connection region included in the first region, and the number of rows of the strip regions arranged along the second direction included in the second region and the connection region included in the second region can be determined according to the morphological requirements of the positive electrode and the negative electrode in the actual application scenario, and no specific limitation is made here.

[0079] As for the morphologies and sizes of the strip regions and the connection regions included in the first region and the second region, the spacing between the connection region included in the first region and the adjacent strip region included in the second region, and the spacing between the connection region included in the second region and the adjacent strip region included in the first region, they can be determined according to the morphology of the first doped semiconductor part and the second doped semiconductor part on one side of the first surface in the actual application scenario, and no specific limitation is made here.

[0080] As for the extension part at the chamfer of the first region, the morphology of the extension part, the extension length of the extension part along the second direction, and the spacing between the extension part along the first direction and the strip region included in the second region can be determined according to the area ratio of the first doped semiconductor part on one side of the first surface in the actual application scenario and the anti-leakage requirements between the first doped semiconductor part and the semiconductor substrate and the second doped semiconductor part respectively, and no specific limitation is made here.

[0081] As for the types of undulations of the first undulation morphology and the second undulation morphology of the first doped semiconductor part, as well as the dimensional information such as the undulation height and the width of the undulation morphology, they can be determined according to the actual manufacturing process and the leakage risk and passivation effect requirements of the first doped semiconductor part at the chamfer of the first surface in the actual application scenario, and no specific limitation is made here.

[0082] Exemplarily, the first undulation morphology and / or the second undulation morphology can be a serrated undulation morphology, a wavy undulation morphology, a trapezoidal broken line undulation morphology, etc.

[0083] Exemplarily, the undulation height of the first undulation morphology can be greater than or equal to 3 μm and less than or equal to 10 μm. For example: the undulation height of the first undulation morphology can be 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm, etc. In this case, while further reducing the leakage risk, the first doped semiconductor part can have a larger area ratio on one side of the first surface, which is beneficial to improving the carrier collection ability and field passivation effect of the first doped semiconductor part.

[0084] Exemplarily, the width of the convex portion in the first undulating topography is greater than or equal to 15 μm and less than or equal to 40 μm. The width of the convex portion in the first undulating topography can be 15 μm, 18 μm, 20 μm, 22 μm, 25 μm, 28 μm, 30 μm, 32 μm, 35 μm, 38 μm, 40 μm, etc. In this case, while further reducing the leakage risk, the first doped semiconductor portion can have a relatively large area ratio on the first surface side, which is beneficial to improving the carrier collection ability and field passivation effect of the first doped semiconductor portion.

[0085] Exemplarily, as Figure 14 shown, for the second doped semiconductor portion 16, the side line at at least one corner near the first surface can be a wavy concave-convex alternating structure. In this case, there is no need to strictly control the manufacturing precision to obtain a straight side line, which is beneficial to reducing the manufacturing process difficulty. In addition, the side line of the second doped semiconductor portion 16 at at least one corner near the first surface also has a convex portion along the direction approaching the corner, which can increase the area ratio of the second doped semiconductor portion 16 on the first surface side, and is beneficial to improving the carrier collection ability and field passivation effect of the second doped semiconductor portion 16.

[0086] Of course, the side line of the second doped semiconductor portion at at least one corner near the first surface can also be in a straight line shape, a broken line shape or other topographies.

[0087] For the above-mentioned second passivation layer, in terms of structure and material, the specific structure of the second passivation layer can be determined according to the type of the solar cell and the actual application scenario, and no specific limitation is made here. Exemplarily, the passivation layer can include a second surface passivation layer and / or a second antireflection layer.

[0088] As Figure 15 shown, when the second passivation layer 18 includes a second surface passivation layer 37 and / or a second antireflection layer 38, the surface on the side of the second passivation layer 18 facing away from the semiconductor substrate 11 is the surface of the outermost layer among the film layers included in the second passivation layer 18 (i.e., the one with the largest distance from the semiconductor substrate 11 in the thickness direction of the semiconductor substrate 11). The pyramidal-like structure on the surface of the second passivation layer 18 facing away from the semiconductor substrate 11 is provided on the surface of the outermost layer among the film layers included in the second passivation layer 18.

[0089] For example: As Figure 15As shown, when the second passivation layer 18 only includes the second surface passivation layer 37 and the second antireflection layer 38, and the second antireflection layer 38 is disposed on the side of the second surface passivation layer 37 away from the semiconductor substrate 11, the surface of the second passivation layer 18 away from the semiconductor substrate 11 is the surface of the second antireflection layer 38 away from the semiconductor substrate 11. The surface of the second antireflection layer 38 away from the semiconductor substrate 11 is a matte surface.

[0090] In addition, the materials of the second surface passivation layer and the antireflection layer can be set according to actual requirements. Exemplarily, the material of the second surface passivation layer can include any passivation material such as silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride. The material of the second antireflection layer can include silicon nitride or silicon oxynitride, etc.

[0091] The embodiments of the present invention do not specifically limit the morphology, one-dimensional size, and distribution of the pyramid-like structures in the second passivation layer on the side away from the semiconductor substrate, which can be determined according to the requirements for the light trapping effect on the front side of the back contact battery in the actual application scenario.

[0092] Exemplarily, the side length or the diagonal length of the bottom surface of at least one pyramid-like structure in the second passivation layer on the side away from the semiconductor substrate can be greater than or equal to 0.05 μm and less than or equal to 4 μm;

[0093] Exemplarily, the height of at least one pyramid-like structure in the second passivation layer on the side away from the semiconductor substrate can be greater than or equal to 0.1 μm and less than or equal to 3 μm.

[0094] Exemplarily, the apex angle of at least one pyramid-like structure in the second passivation layer on the side away from the semiconductor substrate can be greater than or equal to 65° and less than or equal to 100°.

[0095] Among them, the bottom surface of the pyramid-like structure in the second passivation layer on the side away from the semiconductor substrate can be a polygon such as a quadrilateral, pentagon, or hexagon. The adjacent side lengths of the polygon can be equal or unequal. The pyramid-like structures in the second passivation layer on the side away from the semiconductor substrate can have relatively sharp side edges and apex angles, or can also have a smooth transition at the side edges and apex angles.

[0096] In addition, among all the pyramid-like structures on the surface of the second passivation layer facing away from the semiconductor substrate, a pyramid-like structure with at least four side ridges distributed diagonally is defined as a complete pyramid-like structure, and the remaining pyramid-like structures are incomplete pyramid-like structures. Among them, the proportion of the number of complete pyramid-like structures in all pyramid-like structures per unit area on the surface of the second passivation layer facing away from the semiconductor substrate can be set according to the requirements for the light trapping effect of this surface in the actual application scenario, and no specific limitation is made here. The size of the above unit area can be defined according to actual needs, and no specific limitation is made here. For example: the unit area can be less than or equal to 5μm 2 and less than or equal to 5000μm 2 any value in. For example: the unit area can be greater than or equal to 30μm 2 and less than or equal to 2000μm 2 .

[0097] Exemplarily, among all the pyramid-like structures on the surface of the second passivation layer facing away from the semiconductor substrate, the proportion of the number of complete pyramid-like structures in all pyramid-like structures per unit area on the surface of the second passivation layer facing away from the semiconductor substrate can be greater than or equal to 40% and less than or equal to 90%.

[0098] For the first passivation layer, in terms of structure and material, the specific structure of the first passivation layer can be determined according to the materials of the first doped semiconductor portion and the second doped semiconductor portion, as well as the actual application scenario, and no specific limitation is made here. Exemplarily, the first passivation layer can include at least one of a first surface passivation layer, a first antireflection layer, and a first transparent conductive layer.

[0099] Such as Figure 16 and Figure 17 shown, when the first passivation layer 17 includes at least one of a first surface passivation layer 34, a first antireflection layer 35, and a first transparent conductive layer 36, the surface of the first passivation layer 17 facing away from the semiconductor substrate 11 is the outermost one among the film layers included in the first passivation layer 17 (i.e., the one with the largest distance from the semiconductor substrate 11 in the thickness direction of the semiconductor substrate 11), and its surface facing away from the semiconductor substrate 11. The matte area 20 and the planar area 21 on the side of the first passivation layer 17 facing away from the semiconductor substrate 11 are provided on the surface of the outermost one among the film layers included in the first passivation layer 17, and its surface facing away from the semiconductor substrate 11.

[0100] For example: such as Figure 16As shown, when the first passivation layer 17 only includes the first surface passivation layer 34 and the first antireflection layer 35, and the first antireflection layer 35 is disposed on the side of the first surface passivation layer 34 away from the semiconductor substrate 11, the surface of the first passivation layer 17 away from the semiconductor substrate 11 is the surface of the first antireflection layer 35 away from the semiconductor substrate 11. The matte area 20 and the planar area 21 on the surface of the first passivation layer 17 away from the semiconductor substrate 11 are disposed on the surface of the first antireflection layer 35 away from the semiconductor substrate 11.

[0101] For example: As Figure 17 shown, when the first passivation layer 17 only includes the first transparent conductive layer 36, the surface of the first passivation layer 17 away from the semiconductor substrate 11 is the surface of the first transparent conductive layer 36 away from the semiconductor substrate 11. The matte area 20 and the planar area 21 on the surface of the first passivation layer 17 away from the semiconductor substrate 11 are disposed on the surface of the first transparent conductive layer 36 away from the semiconductor substrate 11.

[0102] In addition, the materials of the above-mentioned first surface passivation layer, first antireflection layer and first transparent conductive layer can be set according to actual requirements. Exemplarily, the material of the first surface passivation layer can include any passivation material such as silicon oxide, aluminum oxide, silicon nitride or silicon oxynitride. The material of the first antireflection layer can include silicon nitride or silicon oxynitride, etc. The material of the above-mentioned first transparent conductive layer can include at least one of tin-doped fluorine oxide, aluminum-doped zinc oxide, indium-tin oxide, indium-tungsten oxide, indium-molybdenum oxide, indium-cerium oxide and indium hydroxide.

[0103] It should be noted that when the first passivation layer includes the first transparent conductive layer, the part of the first transparent conductive layer corresponding to the first region is electrically insulated from the part of the first transparent conductive layer corresponding to the second region to prevent short circuit.

[0104] It can be understood that, as described above, on the side of the first passivation layer facing away from the semiconductor substrate, the surface of the first region corresponding to the isolation region not only has a matte surface region, so that the surface of the first region has a certain light trapping effect, but also the surface of the first region has a plurality of planar regions surrounded by different pyramid-like structures included in the matte surface region. The planar regions and the matte surface region are flatter, so that the surface roughness of the first region surface is relatively low compared to the surface of the side of the second passivation layer facing away from the semiconductor substrate. Correspondingly, the surface roughness of the isolation region is also relatively small, which is beneficial to improving the formation quality and passivation effect of the first passivation layer on the isolation region and reducing the number of surface defects at the isolation region. Therefore, according to the requirements for the light trapping effect of the surface of the first region and the passivation effect of the first passivation layer on the isolation region in the actual application scenario, information such as the area ratio of the matte surface region and the planar region, the distribution of the planar regions, and the size and morphology of the pyramid-like structures included in the matte surface region on the side of the first passivation layer facing away from the semiconductor substrate can be determined, and no specific limitations are made here.

[0105] Exemplarily, as Figures 2 to 5 shown, among all the pyramid-like structures in the surface 19 of the first region, the pyramid-like structures with at least four side ribs distributed diagonally are defined as complete pyramid-like structures 22, and the rest of the pyramid-like structures are incomplete pyramid-like structures 23. And the proportion of the number of complete pyramid-like structures 22 in all the pyramid-like structures per unit area on the side of the second passivation layer 18 facing away from the semiconductor substrate 11 can be greater than the proportion of the number of complete pyramid-like structures 22 in all the pyramid-like structures per unit area on the surface 19 of the first region. In this case, in the unit area of the surface 19 of the first region, the proportion of the number of complete pyramid-like structures 22 is relatively small, so that the number of the top angle undulating microstructures of the incomplete pyramid-like structures 23 in the surface 19 of the first region is larger, which is beneficial to improving the light trapping effect of the surface 19 of the first region and the bifaciality of the back contact battery.

[0106] Among them, the proportion of the number of complete pyramid-like structures in all the pyramid-like structures per unit area on the surface of the first region and the difference in the proportion of the number of complete pyramid-like structures between the surface of the side of the second passivation layer facing away from the semiconductor substrate and the surface of the first region can be determined according to the requirements for the light trapping effect of the surface of the side of the second passivation layer facing away from the semiconductor substrate and the surface of the first region in the actual application scenario, and no specific limitations are made here.

[0107] Specifically, it may be that the proportion of the number of complete pyramid-like structures in the first sub-region surface, the second sub-region surface, and the third sub-region surface in the surface of the first region is greater than the proportion of the number of complete pyramid-like structures in the surface on the side of the second passivation layer facing away from the semiconductor substrate, or it may be that the proportion of the number of complete pyramid-like structures in any one or any two of them is greater than the proportion of the number of complete pyramid-like structures in the surface on the side of the second passivation layer facing away from the semiconductor substrate.

[0108] Optionally, the proportion of the number of complete pyramid-like structures in the third sub-region surface is greater than the proportion of the number of complete pyramid-like structures in the surface on the side of the second passivation layer facing away from the semiconductor substrate.

[0109] Exemplarily, the proportion of the number of complete pyramid-like structures in all pyramid-like structures per unit area of the third sub-region surface may be greater than or equal to 5% and less than or equal to 40%.

[0110] Exemplarily, the proportion of the number of complete pyramid-like structures in all pyramid-like structures per unit area of the first sub-region surface may be greater than or equal to 40% and less than or equal to 90%.

[0111] Exemplarily, the proportion of the number of complete pyramid-like structures in all pyramid-like structures per unit area of the second sub-region surface may be greater than or equal to 40% and less than or equal to 80%.

[0112] Of course, the proportion of the number of complete pyramid-like structures in all pyramid-like structures per unit area on the side of the second passivation layer facing away from the semiconductor substrate may also be less than or equal to the proportion of the number of complete pyramid-like structures in all pyramid-like structures per unit area of the first region surface (which may be at least one of the first sub-region surface, the second sub-region surface, and the third sub-region surface included in the first region surface).

[0113] In addition, the embodiments of the present invention do not specifically limit the morphology of the non-complete pyramid-like structures on the surface on the side of the second passivation layer facing away from the semiconductor substrate and in the first region surface, and can be set according to actual needs.

[0114] Exemplarily, such as Figures 3 to 5As shown, within the suede area 20 included in the surface 19 of the first region, there is a sheet-like protrusion 24 on at least one side surface of a quasi-pyramid-shaped structure. Along the extending direction of the side surface of the quasi-pyramid-shaped structure, the cross-sectional shape of the sheet-like protrusion 24 is quasi-triangular. In this case, in addition to the quasi-pyramid-shaped structure, there is a sheet-like protrusion 24 on at least one side surface of a quasi-pyramid-shaped structure within the suede area 20 included in the surface 19 of the first region. This sheet-like protrusion 24 can superimpose its own undulation degree on the quasi-pyramid-shaped structure with an original undulating morphology, and the cross-sectional shape of the sheet-like protrusion 24 is quasi-triangular. Compared with smooth morphologies such as quasi-spherical shapes, the quasi-triangle has certain sharp microstructures, which is conducive to further increasing the roughness of the surface 19 of the first region, improving the light trapping effect of the surface 19 of the first region, and thus conducive to improving the bifacial rate of the back-contact battery.

[0115] Among them, the size of the above-mentioned sheet-like protrusion can be determined according to the requirements for the light trapping effect of the surface of the first region in the actual application scenario, and no specific limitation is made here. In addition, the side wall and the top angle of the sheet-like protrusion can have a relatively sharp transition or a smooth transition.

[0116] Exemplarily, the top angle of at least one quasi-pyramid-shaped structure on the surface of the first region can be greater than the top angle of the quasi-pyramid-shaped structure on the side of the second passivation layer facing away from the semiconductor substrate. In this case, compared with the quasi-pyramid-shaped structure on the side of the second passivation layer facing away from the semiconductor substrate, at least one quasi-pyramid-shaped structure on the surface of the first region has a relatively larger top angle. At this time, the sharpness of the top of at least one quasi-pyramid-shaped structure on the surface of the first region is smaller. Correspondingly, it is conducive to making the undulation sharpness of the surface of the isolation region lower, thereby reducing the stress of the first passivation layer at the undulations of the isolation region, reducing the risk of damage of the first passivation layer on the isolation region, and further improving the passivation effect of the first passivation layer on the isolation region.

[0117] Exemplarily, the one-dimensional size of at least one quasi-pyramid-shaped structure on the surface of the first region can be greater than the one-dimensional size of the quasi-pyramid-shaped structure on the side of the second passivation layer facing away from the semiconductor substrate. In this case, compared with the quasi-pyramid-shaped structure on the side of the second passivation layer facing away from the semiconductor substrate, at least one quasi-pyramid-shaped structure on the surface of the first region has a relatively larger one-dimensional size, which is conducive to reducing the distribution quantity of the quasi-pyramid-shaped structures on the surface of the first region, reducing the undulation density of the surface of the first region. Correspondingly, it is conducive to making the undulation density of the surface of the isolation region lower, thereby reducing the stress of the first passivation layer at the undulations of the isolation region, reducing the risk of damage of the first passivation layer on the isolation region, and further improving the passivation effect of the first passivation layer on the isolation region.

[0118] Among them, the one-dimensional dimension of the pyramid-like structure on the surface of the first region can be the bottom side length, the bottom diagonal length, the bottom perimeter, the bottom diameter, the side edge length, the height, etc. of the pyramid-like structure.

[0119] As for the apex angle and the one-dimensional dimension of the pyramid-like structure within the surface of the first region, they can be determined according to the requirements for the light trapping effect on the surface of the first region and the passivation effect of the first passivation layer on the isolation region in the actual application scenario, and no specific limitation is made here.

[0120] In addition, the apex angles and the one-dimensional dimensions of the pyramid-like structures in the first sub-region surface, the second sub-region surface, and the third sub-region surface included in the surface of the first region can be the same or different. When the apex angles and / or the one-dimensional dimensions of the pyramid-like structures in the first sub-region surface, the second sub-region surface, and the third sub-region surface are different, they can be set according to the conduction types of the first doped semiconductor portion and the second doped semiconductor portion, as well as the actual requirements, and no specific limitation is made here.

[0121] Exemplarily, in the case where the first doped semiconductor portion is an emitter doping portion, the one-dimensional dimension of the pyramid-like structure in the first sub-region surface can be greater than the one-dimensional dimension of the pyramid-like structure in the second sub-region surface.

[0122] Exemplarily, in the case where the first doped semiconductor portion is an emitter doping portion, the uniformity of the one-dimensional dimension of the pyramid-like structure in the first sub-region surface is greater than the uniformity of the one-dimensional dimension of the pyramid-like structure in the second sub-region surface.

[0123] Exemplarily, the apex angle of the pyramid-like structure in the first sub-region surface is smaller than the apex angle of the pyramid-like structure in the second sub-region surface.

[0124] In the case of adopting the above technical solution, among the surfaces on the side of the first passivation layer away from the semiconductor substrate, at least one of the one-dimensional size, one-dimensional size uniformity, and apex angle of the pyramid-like structure on the surface of the first sub-region corresponding to the first sub-surface (close to the emitter doping part) is larger than that of the pyramid-like structure on the surface of the second sub-region, which is conducive to increasing the undulation degree and surface roughness of the surface of the first sub-region, improving the light trapping effect of the surface of the first sub-region, and making more light refract into the first doped semiconductor part adjacent to the surface of the first sub-region, thereby improving the bifaciality of the back contact battery. At the same time, the first doped semiconductor part is the emitter doping part. Since the emitter doping part is used to provide the injection and separation of electron-hole pairs, when more light is incident on the emitter doping part, it is conducive to exciting more photo-generated carriers, and thus conducive to improving the conversion efficiency of the back contact battery. And the surface of the second sub-region corresponding to the second sub-surface has a relatively low surface roughness. Correspondingly, the second sub-surface also has a low surface roughness, which is conducive to improving the deposition quality and passivation effect of the first passivation layer on the second sub-surface.

[0125] Among them, the one-dimensional size, one-dimensional size uniformity, and apex angle size of the pyramid-like structure in the surfaces of the first sub-region and the second sub-region can be determined according to the requirements for the photo-generated carriers excited by the emitter doping part of the back contact battery in the actual application scenario, and no specific limitation is made here.

[0126] For example: the bottom side length or the bottom diagonal length of the pyramid-like structure in the surface of the first sub-region can be greater than or equal to 0.05 μm and less than or equal to 4 μm.

[0127] For example: the bottom side length or the bottom diagonal length of the pyramid-like structure in the surface of the second sub-region can be greater than or equal to 0.05 μm and less than or equal to 3 μm.

[0128] For example: the height of the pyramid-like structure in the surface of the first sub-region can be greater than or equal to 0.1 μm and less than or equal to 2.5 μm.

[0129] For example: the height of the pyramid-like structure in the surface of the second sub-region can be greater than or equal to 0.01 μm and less than or equal to 2.5 μm.

[0130] For example: the apex angle of the pyramid-like structure in the surface of the first sub-region can be greater than or equal to 70° and less than or equal to 100°.

[0131] For example: the apex angle of the pyramid-like structure in the surface of the second sub-region can be greater than or equal to 70° and less than or equal to 100°.

[0132] Exemplarily, when the conduction types of the second doped semiconductor portion and the semiconductor substrate are the same, the one-dimensional size of the pyramid-like structure on the surface of the second sub-region can be smaller than the one-dimensional size of the pyramid-like structure on the surface of the third sub-region. In this case, the portion of the isolation region located between the first region and the second region is mainly used to isolate the first doped semiconductor portion and the second doped semiconductor portion with opposite conduction types, reducing the leakage current between them. Therefore, when on the side of the first passivation layer facing away from the semiconductor substrate, the surface of the third sub-region corresponding to the third sub-surface has a relatively large one-dimensional size and a small apex corner rounding curvature, the surface of the third sub-region has a relatively large surface roughness, and correspondingly, the third sub-surface also has a large undulating topography, so that the etching degree of the isolation region in the area corresponding to the third sub-surface is relatively high, which is beneficial to further reducing the leakage current risk between the first doped semiconductor portion and the second doped semiconductor portion.

[0133] Exemplarily, the apex corner rounding curvature of the pyramid-like structure on the surface of the second sub-region can be greater than the apex corner rounding curvature of the pyramid-like structure on the surface of the third sub-region. In this case, the second sub-region surface has a smaller pyramid-like structure and a larger apex corner rounding curvature of the pyramid-like structure, which is beneficial to making the surface of the second sub-region and the second sub-surface have a lower surface roughness, improving the passivation effect of the first passivation layer on the second sub-surface, and reducing the number of defects on the second sub-surface.

[0134] As for the one-dimensional size and apex angle of the pyramid-like structure on the surface of the third sub-region, and the apex corner rounding curvature of the pyramid-like structures on the surfaces of the second sub-region and the third sub-region, they can be determined according to the requirements for the light trapping effects of the second sub-region and the third sub-region, and the passivation effects of the first passivation layer on the second sub-surface and the third sub-surface in the actual application scenario, and no specific limitation is made here.

[0135] For example: The bottom side length or the bottom diagonal length of the pyramid-like structure in the surface of the third sub-region can be greater than or equal to 0.05 μm and less than or equal to 6 μm.

[0136] For example: The height of the pyramid-like structure in the surface of the third sub-region can be greater than or equal to 0.1 μm and less than or equal to 4 μm.

[0137] For example: The apex angle of the pyramid-like structure in the surface of the third sub-region can be greater than or equal to 70° and less than or equal to 100°.

[0138] In some cases, the first surface is approximately rectangular. Along the extension direction parallel to the long side of the approximately rectangular shape, the widths of the portions of the first sub-region surface and the second sub-region surface adjacent to one of the short sides in the approximately rectangular shape can be greater than the widths of the portions of the first sub-region surface and the second sub-region surface adjacent to the other short side in the approximately rectangular shape. In this case, when the widths of the portions of the first sub-region surface and the second sub-region surface adjacent to one of the short sides in the approximately rectangular shape are greater than the widths of the portions of the first sub-region surface and the second sub-region surface adjacent to the other short side in the approximately rectangular shape, it indicates that along the extension direction parallel to the long side of the approximately rectangular shape, the etching amounts of the first doped semiconductor portion and the second doped semiconductor portion at the two short sides are different. The difference in the etching amount is because when using equipment such as chain cleaning to remove the circumferential plating on the second surface of the semiconductor substrate, due to the influence of liquid turning, the amount of liquid turning at the front end along the traveling direction is relatively large, and thus the etching amount at the short sides corresponding to the etching front ends of the first doped semiconductor portion and the second doped semiconductor portion is relatively large. It can be seen that the extension direction of the long side of the approximately rectangular shape is consistent with the etching traveling direction, which can reduce the degree of influence on the etching accuracy caused by factors such as structural jitter during the etching process, improve the etching stability and etching accuracy, and thus facilitate improving the yield of the back-contact battery.

[0139] Among them, along the extension direction parallel to the long side of the approximately rectangular shape, the widths of the portions of the first sub-region surface and the second sub-region surface adjacent to the two short sides in the approximately rectangular shape can be determined according to the actual manufacturing process and are not specifically limited here.

[0140] Exemplarily, along the extension direction parallel to the long side, the widths of the portions of the first sub-region surface and the second sub-region surface adjacent to one of the short sides in the approximately rectangular shape are greater than or equal to 10 μm and less than or equal to 50 μm; and / or, the widths of the portions of the first sub-region surface and the second sub-region surface adjacent to the other short side in the approximately rectangular shape are greater than or equal to 3 μm and less than or equal to 10 μm. In this case, while ensuring that the circumferential plating on the second surface of the semiconductor substrate can be completely removed through the etching operation, a certain distance can be maintained between the boundary of the portions of the first doped semiconductor portion and the second doped semiconductor portion at the edge and the first surface, which is beneficial to reducing the leakage risk. In addition, it can also prevent the influence on the area ratio of the first doped semiconductor portion and the second doped semiconductor portion on the first surface due to the excessive above-mentioned widths, which is beneficial for the first doped semiconductor portion and the second doped semiconductor portion to have a high carrier collection ability and field passivation effect.

[0141] For example: along the extension direction parallel to the long side, the widths of the portions of the first sub-region surface and the second sub-region surface adjacent to one of the short sides in the approximately rectangular shape can be 10 μm, 20 μm, 30 μm, 40 μm, or 50 μm, etc.

[0142] For example, the widths of the portions of the first sub-region surface and the second sub-region surface adjacent to the other short side in the quasi-rectangle can be 3 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc.

[0143] In a second aspect, embodiments of the present invention provide a photovoltaic module, which includes the back contact cell provided by the first aspect and its various implementation manners.

[0144] For the beneficial effects of the second aspect and its various implementation manners in the embodiments of the present invention, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementation manners, which will not be elaborated here.

[0145] In the above description, no detailed description is made on technical details such as the composition and etching of each layer. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. with the desired shapes. In addition, for forming the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. In addition, although the above embodiments are described separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0146] The above describes the embodiments of the present invention. However, these embodiments are merely for clearer illustration and not for limiting the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present invention.

Claims

1. A back contact battery, characterized in that: include: A semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other; the first surface comprising a first region, a second region and an isolation region; The first area and the second area are alternately distributed; the first surface has a boundary, and the isolation area is located between the first area and the second area, and between the boundary and the first area at the outermost edge and the second area at the outermost edge; A first doped semiconductor portion is disposed in or on the first region; A second doped semiconductor portion is disposed in or on the second region; the second doped semiconductor portion and the first doped semiconductor portion have opposite conductivity types; a first passivation layer covering the first doped semiconductor portion, the second doped semiconductor portion and the isolation region; The surface of the first passivation layer on the side facing away from the semiconductor substrate, which corresponds to the isolation region, is a first region surface; a second passivation layer covering the second surface; Among them, the surface of the first area has a velvet area, and a plurality of plane areas formed by surrounding different pyramid-like structures included in the velvet area; the surface of the second passivation layer on the side away from the semiconductor substrate is velvet, and adjacent pyramid-like structures on the side of the second passivation layer away from the semiconductor substrate are in contact with each other.

2. The back contact cell according to claim 1, characterized in that: Among all the pyramid-like structures on the surface of the second passivation layer facing away from the semiconductor substrate and the surface of the first region, the pyramid-like structures having at least four diagonally distributed side ridges are complete pyramid-like structures, and the remaining pyramid-like structures are incomplete pyramid-like structures; The proportion of the complete pyramid-like structures in the unit area of ​​the second passivation layer facing away from the semiconductor substrate among all the pyramid-like structures is greater than the proportion of the complete pyramid-like structures in the unit area of ​​the surface of the first region.

3. The back contact cell according to claim 1, characterized in that: In the velvet area included in the surface of the first region, at least one side of the pyramid-like structure has a sheet-like protrusion; along the extension direction of the side of the pyramid-like structure, the cross-sectional shape of the sheet-like protrusion is triangular.

4. The back contact cell according to claim 1, characterized in that: The top angle of at least one of the pyramid-like structures on the surface of the first region is greater than the top angle of the pyramid-like structure on the side of the second passivation layer facing away from the semiconductor substrate; And / or, a one-dimensional size of at least one of the pyramid-like structures on the surface of the first region is greater than a one-dimensional size of the pyramid-like structure on a side of the second passivation layer facing away from the semiconductor substrate.

5. The back contact cell according to claim 1, characterized in that: The first doped semiconductor portion is an emitter doped portion; the surface of the isolation region includes a first sub-surface located between the boundary and the first region at the outermost edge, and a second sub-surface located between the boundary and the second region at the outermost edge; In the surface of the first passivation layer facing away from the semiconductor substrate, the surface of the region corresponding to the first sub-surface is the first sub-region surface, and the surface of the region corresponding to the second sub-surface is the second sub-region surface; the surface of the first sub-region and the surface of the second sub-region have a pyramid-like structure; Among them, the one-dimensional size of the pyramid-like structure in the surface of the first sub-region is larger than the one-dimensional size of the pyramid-like structure in the surface of the second sub-region; and / or, the one-dimensional size uniformity of the pyramid-like structure in the surface of the first sub-region is larger than the one-dimensional size uniformity of the pyramid-like structure in the surface of the second sub-region; and / or, the vertex angle of the pyramid-like structure in the surface of the first sub-region is smaller than the vertex angle of the pyramid-like structure in the surface of the second sub-region.

6. The back contact cell according to claim 1, characterized in that: The isolation region surface includes a first sub-surface located between the boundary and the first region at the outermost edge, a second sub-surface located between the boundary and the second region at the outermost edge, and a third sub-surface located between the first region and the second region; in the surface of the first passivation layer on the side away from the semiconductor substrate, the region surface corresponding to the first sub-surface is the first sub-region surface, the region surface corresponding to the second sub-surface is the second sub-region surface, and the region surface corresponding to the third sub-surface is the third sub-region surface; the second sub-region surface and the third sub-region surface have a pyramid-like structure; When the second doped semiconductor portion has the same conductivity type as the semiconductor substrate, the one-dimensional size of the pyramid-like structure on the surface of the second sub-region is smaller than the one-dimensional size of the pyramid-like structure on the surface of the third sub-region, and / or the top corner rounding curvature of the pyramid-like structure on the surface of the second sub-region is greater than the top corner rounding curvature of the pyramid-like structure on the surface of the third sub-region.

7. The back contact cell according to claim 6, characterized in that: The first surface is rectangular; along the extension direction parallel to the long side of the rectangle, the width of the first sub-area surface and the second sub-area surface respectively adjacent to one short side of the rectangle is greater than the width of the first sub-area surface and the second sub-area surface respectively adjacent to the other short side of the rectangle.

8. The back contact battery according to claim 7, characterized in that: Along the extension direction parallel to the long side, the width of the portion of the first sub-region surface and the second sub-region surface adjacent to a short side of the quasi-rectangle is greater than or equal to 10 μm and less than or equal to 50 μm; And / or, the width of the portion of the first sub-region surface and the second sub-region surface respectively adjacent to another short side of the quasi-rectangle is greater than or equal to 3 μm and less than or equal to 10 μm.

9. The back contact battery according to claim 6, characterized in that: The second doped semiconductor portion has a side line at at least one corner close to the first surface that is in a wavy alternating concave-convex structure.

10. The back contact cell according to claim 6, characterized in that: The first region and the second region both include strip regions and connection regions; the strip regions included in the first region and the strip regions included in the second region both extend along a first direction and are alternately spaced along a second direction; the first direction is different from the second direction; the connection regions included in the first region and the connection regions included in the second region both extend along the second direction and are alternately spaced along the first direction; the connection regions included in the first region are connected to at least part of the strip regions included in the first region, and the connection regions included in the second region are connected to at least part of the strip regions included in the second region; the strip regions included in the first region are disconnected at the intersection with the connection regions included in the second region, and the strip regions included in the second region are disconnected at the intersection with the connection regions included in the first region; The first surface has a chamfer, the first region has an extension portion at the chamfer, the extension portion extends along the second direction, and the extension portion and the strip region included in the second region are spaced apart and distributed along the first direction; in the first doped semiconductor portion, the edge line of the portion close to the chamfer has a first undulating morphology, and the edge line of the portion close to the contour line continuous with the chamfer has a second undulating morphology; Among them, along the direction from the edge to the center of the first surface, the undulation height of the first undulating morphology is greater than the undulation height of the second undulating morphology, and / or the width of the convex portion in the first undulating morphology is smaller than the width of the convex portion in the second undulating morphology.

11. The back contact cell according to claim 10, characterized in that: The first undulating shape has an undulation height greater than or equal to 3 μm and less than or equal to 10 μm; And / or, the width of the convex portion in the first undulating topography is greater than or equal to 15 μm and less than or equal to 40 μm.

12. A photovoltaic module, characterized in that: Comprising a back contact battery as claimed in any one of claims 1 to 11.

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