Solar cell, photovoltaic module and manufacturing method of solar cell

Abstract

The invention discloses a solar cell, a photovoltaic module and a manufacturing method of the solar cell, relates to the technical field of solar cells, and aims to solve the problem of poor quality of a patterned film layer in the prior art. The solar cell includes a semiconductor substrate and a first doped semiconductor layer. The semiconductor substrate comprises a first surface and a second surface which are opposite, and the first surface is provided with first areas and second areas which are alternately distributed along a first direction. The first doped semiconductor layer is arranged in the first region, and the first doped semiconductor layer is not arranged on the second region. The side surface of the first doped semiconductor layer close to the second region is wave-shaped along a second direction, and the first direction is different from the second direction. In the first direction, the distance between a wave crest and a wave trough of the wave shape is greater than or equal to 1 mu m and less than or equal to 4 mu m; and / or the average roughness of the wave shape extending in the second direction is smaller than or equal to 2.4 microns.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a solar cell, a photovoltaic module and a method for manufacturing a solar cell. Background Art

[0002] A solar cell is a device that utilizes solar energy and directly converts light energy into electrical energy through the photoelectric effect.

[0003] Current solar cells include BC cells (Back Contact), and patterning BC cells is an important step in the preparation of solar cells. Specifically, in the preparation of BC cells, precise patterning is required to form the required film layer after patterning.

[0004] However, the quality of the patterned film layer in the prior art is poor. Therefore, how to improve the film forming quality of at least part of the film layer in the solar cell is a technical problem that needs to be solved urgently in the current industry. Summary of the invention

[0005] The object of the present invention is to provide a solar cell, a photovoltaic module and a method for manufacturing a solar cell, which are used to improve the film-forming quality of at least part of the film layer in the solar cell.

[0006] In order to achieve the above-mentioned purpose, in a first aspect, the present invention provides a solar cell. The solar cell includes: a semiconductor substrate and a first doped semiconductor layer. The semiconductor substrate includes a first surface and a second surface opposite to each other, and the first surface has a first region and a second region alternately distributed along a first direction. The first doped semiconductor layer is arranged in the first region, and there is no first doped semiconductor layer on the second region. The side surface of the first doped semiconductor layer close to the second region is wavy along the second direction, and the first direction is different from the second direction. Along the first direction, the distance between the crest and the trough of the wavy shape is greater than or equal to 1μm and less than or equal to 4μm; and / or, the average roughness of the wavy shape extending along the second direction is less than or equal to 2.4μm.

[0007] Compared with the prior art, in the solar cell provided by the present invention, the side surface of the first doped semiconductor layer close to the second region is wavy along the second direction, and the first direction is different from the second direction. Along the first direction, the distance between the peak and the valley of the wavy shape is greater than or equal to 1 μm and less than or equal to 4 μm; and / or, the average roughness of the wavy shape extending along the second direction is less than or equal to 2.4 μm. It can be seen that the wavy shape of the side surface of the first doped semiconductor layer has regularity, so that the film formation quality of the film layer formed subsequently at the junction of the first region and the second region is better, and the film layer is more uniform and neat. Further, a preset region is selected, and the junction of the first region and the second region is located within the preset region. When a film layer needs to be formed within the preset region and the formed film layer avoids the junction (in other words, the junction in the preset region is not used for forming the film layer), the region where the film layer is actually formed within the preset region is the effective region. Since the wavy shape of the side surface of the first doped semiconductor layer has regularity, the area of the effective region is larger than that when the wavy shape of the side surface of the first doped semiconductor layer has no regularity. Based on this, a larger error space can be provided for subsequent processing (such as patterning process), improving the process precision, and further improving the quality of the solar cell.

[0008] In one implementation, along the first direction, the distance between the peak of the wavy shape and the valley adjacent to the peak is greater than or equal to 1 μm and less than or equal to 4 μm.

[0009] There will be an edge recombination problem of carriers at the edge of the first region (this edge is close to the junction of the first region and the second region), and the magnitude of the recombination current is directly related to the edge length. A flat edge, small roughness, etc. can all reduce the length of the edge region, reduce carrier recombination, and improve the battery performance. Therefore, when the distance between the peak of the wavy shape and the valley adjacent to the peak satisfies the above value range, the length of the edge region can be reduced, carrier recombination can be reduced, and the battery performance can be improved. On the other hand, the edge is more flat and regular, which can make the gas atmosphere more uniform during subsequent chemical vapor deposition of the film layer, facilitating the formation of a more uniform film layer at the junction of the first region and the second region.

[0010] In one implementation, along the second direction, the distance between two adjacent peaks of the wavy shape is greater than or equal to 5 μm and less than or equal to 20 μm.

[0011] In the case of adopting the above technical solution, the edge of the first doped semiconductor layer close to the second region is more flat. At this time, not only can the film formation quality of the film layer formed at the junction of the first region and the second region be further improved; at the same time, the length of the edge region can be reduced, carrier recombination can be reduced, and the battery performance can be improved.

[0012] In one implementation, the root mean square roughness of the wavy shape extending in the second direction is less than or equal to 2.7 μm.

[0013] At the edge of the first region (the edge close to the junction of the first region and the second region), there will be an edge recombination problem of carriers, and the magnitude of the recombination current is directly related to the edge length. A flat edge and small roughness can reduce the length of the edge region, reduce carrier recombination, and improve the battery performance. Therefore, when the root mean square roughness of the wavy shape extending in the second direction is less than or equal to 2.7 μm, the length of the edge region can be reduced, carrier recombination can be reduced, and the battery performance can be improved. On the other hand, a flatter and more regular edge can make the gas atmosphere more uniform during the subsequent chemical vapor deposition film layer, which is beneficial to form a more uniform film layer at the junction of the first region and the second region.

[0014] In one implementation, along the first direction, the second region includes a third region adjacent to the first region and a fourth region far from the first region, and the third region is located between the fourth region and the first region. The surfaces of both the third region and the fourth region have a pyramidal texture structure, and the dimensional uniformity of the pyramidal texture structures on the surfaces of the third region and the fourth region is approximately equal; and / or, along the direction from the first surface to the second surface, the height difference between the surface of the semiconductor substrate of the third region and the surface of the semiconductor substrate of the first region is greater than the height difference between the surface of the semiconductor substrate of the fourth region and the surface of the semiconductor substrate of the first region.

[0015] In the case of adopting the above technical solution, since the surfaces of both the third region and the fourth region have a pyramidal texture structure, when a film layer is subsequently formed on the third region and the fourth region, the contact area between the film layer and the semiconductor substrate can be increased. Especially when the film layer is a passivation layer, the passivation effect of the passivation layer on the third region and the fourth region can be improved, the carrier recombination rate on the surfaces of the third region and the fourth region can be reduced, and thus the photoelectric conversion efficiency of the solar cell can be improved. Further, the dimensional uniformity of the pyramidal texture structures on the surfaces of the third region and the fourth region is approximately equal. In this case, the film layers subsequently formed on the surfaces of the third region and the fourth region are more uniform, the film forming quality of the film layer is better, the compactness of the film layer is better, which is beneficial to improving the quality and working performance of the solar cell.

[0016] In one implementation, along the direction from the first surface to the second surface, the height difference between the surface of the semiconductor substrate of the second region and the surface of the semiconductor substrate of the first region is greater than or equal to 1 μm and less than or equal to 10 μm.

[0017] In the case of adopting the above technical solution, the first doped semiconductor layer and the film layers formed subsequently on at least part of the surface of the second region can be offset in the thickness direction of the semiconductor substrate, so as to avoid the mutual influence between the first doped semiconductor layer and the subsequently formed film layers, or the relative influence between the structures corresponding to the first doped semiconductor layer and the subsequently formed film layers. For example, when the film layer is a second doped semiconductor layer with a conductivity type opposite to that of the first doped semiconductor layer, the height difference between the surface of the semiconductor substrate in the second region and the surface of the semiconductor substrate in the first region is within the above range, which can prevent the electrode structure in ohmic contact with the first doped semiconductor layer and the second doped semiconductor layer with opposite conductivity types from being offset to a small extent in the thickness direction of the semiconductor substrate, so as to reduce the leakage risk. Further, compared with the differences in the recess depth and the like after subsequent wet etching due to the large and uneven thermal damage to the semiconductor substrate during the laser patterning process; and due to the large damage to the semiconductor substrate, a part of the thickness of the semiconductor substrate (the thermal damage layer is generally 10-20 μm) needs to be wet-etched subsequently, resulting in the need for a thicker silicon wafer for battery preparation. The method of non-destructive laser patterning is adopted in this application, so that the thermal damage to the semiconductor substrate is small, and there is no need for a subsequent wet polishing step to remove the damage layer. Therefore, while reducing the process time, the thinning of the semiconductor substrate is achieved.

[0018] In one implementation, the solar cell further includes: a second doped semiconductor layer. The second doped semiconductor layer is disposed on the second region and extends on part of the first doped semiconductor layer; the conductivity types of the second doped semiconductor layer and the first doped semiconductor layer are opposite. At this time, the above solar cell is a hybrid back contact cell.

[0019] In one implementation, the first doped semiconductor layer includes a first doped polysilicon layer; the second doped semiconductor layer includes a doped amorphous silicon layer and / or a doped microcrystalline silicon layer.

[0020] In the case of adopting the above technical solution, the above first doped semiconductor layer includes a first doped polysilicon layer. In this case, compared with the doped amorphous silicon layer, the doped polysilicon layer has higher carrier transport characteristics. Therefore, when the first doped semiconductor layer is a doped polysilicon layer, the carrier recombination rate can be further reduced, which is beneficial to improving the photoelectric conversion efficiency of the hybrid back contact cell.

[0021] In one implementation, the second region includes a doped region and two spacer regions. Along a first direction, the doped region is located between the two spacer regions; along the first direction, the spacer regions are located between the first region and the doped region; the side surface of the first doped semiconductor layer adjacent to the spacer region is wavy along a second direction. The solar cell further includes: a second doped semiconductor layer and a surface passivation layer. The second doped semiconductor layer is disposed in the doped region, and the second doped semiconductor layer and the first doped semiconductor layer have opposite conduction types. The surface passivation layer is disposed on the first doped semiconductor layer, on the second doped semiconductor layer, and on the spacer regions.

[0022] At this time, the above solar cell is a tunnel oxide passivated back contact solar cell (TOPCon BackContact, abbreviated as TBC). Further, the spacer regions can isolate the first doped semiconductor layer and the second doped semiconductor layer, reducing the carrier recombination rate at the lateral junction of the first doped semiconductor layer and the second doped semiconductor layer, which is beneficial to improving the photoelectric conversion efficiency of the solar cell. Still further, the surface passivation layer can passivate one side of the first surface of the TBC, reducing the carrier recombination rate on one side of the first surface.

[0023] In one implementation, the first doped semiconductor layer includes a second doped polysilicon layer; the second doped semiconductor layer includes a third doped polysilicon layer.

[0024] In one implementation, the solar cell further includes: a surface passivation layer. The surface passivation layer is disposed on the second region and extends onto the first doped semiconductor layer. Combining the foregoing description, at this time, the above solar cell is a tunnel oxide passivated contact cell (Tunnel Oxide Passivated Contact, abbreviated as TOPCon). Further, the above surface passivation layer can passivate one side of the first surface of the TOPCon, reducing the carrier recombination rate on one side of the first surface.

[0025] In a second aspect, the present invention further provides a photovoltaic module. The photovoltaic module includes a battery string and a packaging layer. The battery string is formed by connecting a plurality of the solar cells described in the above technical solutions, and the packaging layer is used to cover the surface of the battery string.

[0026] For the beneficial effects of the second aspect and its various implementations in the present invention, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementations, which will not be elaborated here.

[0027] In a third aspect, the present invention further provides a method for manufacturing a solar cell. The method for manufacturing the solar cell includes:

[0028] First, a semiconductor substrate is provided; the semiconductor substrate includes opposite first and second surfaces; the first surface has first regions and second regions that are alternately distributed in a first direction;

[0029] Next, a first doped semiconductor layer is formed as a whole layer on the first surface;

[0030] Next, a mask layer is formed as a whole layer on the first doped semiconductor layer;

[0031] Next, the mask layer and the first doped semiconductor layer located in the second region are processed to obtain the first doped semiconductor layer located in the first region, and no first doped semiconductor layer is formed on the second region;

[0032] The side surface of the first doped semiconductor layer close to the second region is wavy in a second direction; the first direction is different from the second direction; along the first direction, the distance between the wave crest and the wave trough of the wavy shape is greater than or equal to 1 μm and less than or equal to 4 μm; and / or, the average roughness of the wavy shape extending in the second direction is less than or equal to 2.4 μm.

[0033] For the beneficial effects of the third aspect and its various implementation manners in the present invention, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementation manners, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0035] Figure 1 is a schematic structural diagram of the first type of solar cell in the embodiment of the present invention;

[0036] Figure 2 is a schematic structural diagram of the second type of solar cell in the embodiment of the present invention;

[0037] Figure 3 is a schematic structural diagram of the third type of solar cell in the embodiment of the present invention;

[0038] Figure 4 is a top-view SEM diagram of a partial structure of the solar cell in the embodiment of the present invention;

[0039] Figure 5 is a top-view SEM diagram of a partial structure of the solar cell in the prior art;

[0040] Figure 6 is a top-view SEM diagram of a partial structure of the solar cell in the embodiment of the present invention.

[0041] Reference Signs:

[0042] 1 - semiconductor substrate, 10 - first region, 11 - second region, 110 - doped region, 111 - spacer region, 12 - preset region; 2 - first doped semiconductor layer, 3 - second doped semiconductor layer, 4 - first passivation layer, 5 - second passivation layer, 6 - transparent conductive layer, 7 - surface passivation layer, 8 - first electrode, 9 - second electrode. Detailed implementation manners

[0043] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0044] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0045] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined. "Several" means one or more unless otherwise specifically defined.

[0046] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present invention.

[0047] In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, the terms "mounted", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0048] To solve the above technical problems, in a first aspect, the present invention provides a solar cell. Refer to Figures 1 to 4 , the solar cell includes: a semiconductor substrate 1 and a first doped semiconductor layer 2. The semiconductor substrate 1 includes opposite first and second surfaces, and the first surface has first regions 10 and second regions 11 alternately distributed along a first direction A. The first doped semiconductor layer 2 is disposed on the first regions 10, and no first doped semiconductor layer 2 is formed on the second regions 11. The side surface of the first doped semiconductor layer 2 adjacent to the second regions 11 is wavy along a second direction B, and the first direction A is different from the second direction B. It should be noted that the above Figures 1 to 3 is only a schematic structural diagram of the solar cell for assisting in understanding the present application.

[0049] Wherein, along the first direction, the distance between the peak and the valley of the wavy shape is greater than or equal to 1 μm and less than or equal to 4 μm. Exemplarily, the distance between the peak and the valley of the wavy shape can be 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.3 μm, 2.5 μm, 2.8 μm, 3 μm, 3.3 μm, 3.5 μm, 3.8 μm or 4 μm, etc. It should be noted that the "distance between the peak and the valley of the wavy shape" can refer to the distance between the peak of the wavy shape and the valley adjacent to the peak, or the distance between the peak and the valley not adjacent to the peak. In other words, the "distance between the peak and the valley of the wavy shape" refers to the distance between any peak and any valley.

[0050] Preferably, refer to Figure 4 , along the first direction A, the distance L1 between the peak of the wavy shape and the valley adjacent to the peak is greater than or equal to 1 μm and less than or equal to 4 μm. Exemplarily, the distance L1 between the peak of the wavy shape and the valley adjacent to the peak can be 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.06 μm, 2.3 μm, 2.5 μm, 2.75 μm, 2.8 μm, 3 μm, 3.3 μm, 3.5 μm, 3.8 μm or 4 μm, etc. As Figure 4The L1 shown is 2.06μm and 2.75μm respectively. At the edge of the first region (the edge is close to the junction of the first region and the second region), there will be a problem of edge recombination of carriers, and the size of the recombination current is directly related to the edge length. Smooth edges and low roughness can reduce the length of the edge region, reduce carrier recombination, and improve battery performance. Therefore, when the distance between the crest of the wave shape and the trough adjacent to the crest meets the above range of values, the length of the edge region can be reduced, carrier recombination can be reduced, and battery performance can be improved. On the other hand, a smoother and more regular edge can make the gas atmosphere more uniform during the subsequent chemical vapor deposition of the film layer, which is conducive to the formation of a more uniform film layer at the junction of the first region and the second region.

[0051] And / or, the average roughness Ra of the wavy shape extending along the second direction is less than or equal to 2.4 μm. For example, the average roughness Ra of the wavy shape extending along the second direction may be 2.4 μm, 2.3 μm, 2.2 μm, 2.1 μm, 2.0 μm, 1.9 μm, 1.8 μm, 1.7 μm, 1.6 μm, 1.5 μm or 1.4 μm, etc.

[0052] See also Figures 1 to 5 In the solar cell provided by the embodiment of the present invention, the side surface of the first doped semiconductor layer 2 near the second region 11 is wavy along the second direction B, and the first direction A is different from the second direction B. Along the first direction A, the distance between the crest and the trough of the wavy shape is greater than or equal to 1 μm and less than or equal to 4 μm; and / or, the average roughness of the wavy shape extending along the second direction B is less than or equal to 2.4 μm. It can be seen from this that the wavy shape on the side surface of the first doped semiconductor layer 2 is regular, so that the film layer subsequently formed at the junction of the first region 10 and the second region 11 (for example, the second doped semiconductor layer 3 with the opposite conductivity type to the first doped semiconductor layer 2, or the passivation layer, or the transparent conductive layer 6, etc.) has better film quality, and the film layer is more uniform and neat. For example, when a film layer is formed at the junction of the first region 10 and the second region 11 by chemical vapor deposition (CVD), the wave shape has regularity, so it has a regular effect on the CVD atmosphere, so that the atmosphere is more evenly distributed in the space at the junction of the first region 10 and the second region 11, and the atmosphere environment will not be disrupted due to irregular shielding, which is conducive to the deposition of the film layer at the above-mentioned junction, thereby making the film formation quality of the film layer at the junction better. Further, a preset area 12 is selected, and the junction of the first region 10 and the second region 11 is located in the preset area. When it is necessary to form a film layer in the preset area, and the formed film layer avoids the junction (in other words, the junction in the preset area is not used to form a film layer), the area in the preset area where the film layer is actually formed is the effective area. See.Figure 4 and Figure 5 , due to the regularity of the wavy shape on the side of the first doped semiconductor layer 2, the area of the above-mentioned effective region is larger than that when the wavy shape on the side of the first doped semiconductor layer 2 is irregular (see Figure 5 ). Based on this, a larger error margin can be provided for subsequent processing (such as a patterning process), improving the process accuracy, and thus enhancing the quality of the solar cell.

[0053] In the actual application process, the material of the semiconductor substrate in the embodiments of the present invention is not specifically limited, as long as it can be applied to the solar cell provided by the embodiments of the present invention. For example, the semiconductor substrate can be a substrate of any semiconductor material such as a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a gallium arsenide substrate.

[0054] In some embodiments, the semiconductor substrate can be an N-type semiconductor substrate, a P-type semiconductor substrate, or a semiconductor substrate close to the intrinsic conduction type. The N-type semiconductor substrate is doped with an N-type doping element, and the N-type doping element can be any one of Group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). The P-type semiconductor substrate is doped with a P-type element, and the P-type doping element can be any one of Group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0055] In some embodiments, the crystal type of the semiconductor substrate can be single crystal or polycrystal, etc.

[0056] It should be understood that the above-mentioned first surface is the backlight surface and the second surface is the light-facing surface. The light-facing surface (i.e., the second surface) of the above-mentioned semiconductor substrate can be a flat surface, or, as Figures 1 to 3 shown, the light-facing surface of the semiconductor substrate 1 can also be a textured surface. Among them, due to the light-trapping effect of the textured surface, when the light-facing surface of the semiconductor substrate 1 is a textured surface, the reflectivity of the light-facing surface can be reduced, which is beneficial to allowing more light to be refracted into the semiconductor substrate 1 by the light-facing surface and absorbed and utilized by the semiconductor substrate 1, and is beneficial to improving the photoelectric conversion efficiency of the solar cell.

[0057] The above-mentioned first surface has an alternately distributed first region and second region, and the alternately distributed direction is the first direction. Further, the above-mentioned first direction and second direction can be any two different directions parallel to the surface of the semiconductor substrate. Preferably, see Figure 1 , the above-mentioned first direction A and second direction B are orthogonal.

[0058] In terms of range, the boundary between the first region and the second region on the first surface of the above-mentioned semiconductor substrate is a virtual boundary. As Figures 1 to 3As shown, the first doped semiconductor layer 2 is formed on the first region 10. Therefore, the range of the first region 10 on the first surface of the semiconductor substrate 1 can be determined according to the requirements for the formation range of the first doped semiconductor layer 2 in actual application scenarios. It can be understood that after the range of the first region 10 is determined, the range of the second region 11 on one side of the first surface is determined.

[0059] As a possible implementation, refer to Figure 4 , along the second direction B, the distance L2 between two adjacent wave peaks of the wavy shape is greater than or equal to 5 μm and less than or equal to 20 μm. Exemplarily, the distance L2 between two adjacent wave peaks of the wavy shape can be 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm or 20 μm, etc. At this time, compared with the prior art (refer to Figure 5 ), the edge of the first doped semiconductor layer 2 near the second region 11 in the present application is flatter. At this time, not only can the film formation quality of the film layer formed at the junction of the first region and the second region be further improved; at the same time, the length of the edge region can be reduced, carrier recombination can be reduced, and the battery performance can be improved.

[0060] As a possible implementation, the root mean square roughness Rq of the wavy shape extending along the second direction is less than or equal to 2.7 μm. Exemplarily, the root mean square roughness Rq of the wavy shape extending along the second direction can be 2.7 μm, 2.6 μm, 2.5 μm, 2.4 μm, 2.3 μm, 2.2 μm, 2.1 μm, 2.0 μm, 1.9 μm, 1.8 μm, 1.7 μm, 1.6 μm, 1.5 μm or 1.4 μm, etc. There will be an edge recombination problem of carriers at the edge of the first region (this edge is close to the junction of the first region and the second region), and the magnitude of the recombination current is directly related to the edge length. A flat edge and small roughness can all reduce the length of the edge region, reduce carrier recombination, and improve battery performance. Therefore, when the root mean square roughness of the wavy shape extending along the second direction is less than or equal to 2.7 μm, the length of the edge region can be reduced, carrier recombination can be reduced, and the battery performance can be improved. On the other hand, a flatter and more regular edge can make the gas atmosphere more uniform during subsequent chemical vapor deposition of the film layer, which is beneficial to forming a more uniform film layer at the junction of the first region and the second region. Exemplarily, refer to Figure 6, along the first direction A, a straight line N is selected as a reference line on one side of the boundary line (i.e., the wavy line M) between the first region 10 and the second region 11. The reference line N is located within the first region 10, and the extending direction of the reference line N is consistent with the second direction B. i points are sampled at equal intervals on the wavy line M, where i is greater than or equal to 10. For example, 10 points are sampled at equal intervals along the second direction B on the wavy line M. Then, along the first direction A, the minimum distances between the above 10 points and the reference line N are calculated respectively, so as to obtain 10 data H1 to H10. Then, based on the 10 data H1 to H10, the average value is calculated. Then, based on this average value In the appendix Figure 6 an average value line P extending along the second direction B is obtained. Then, the minimum distances (i.e., deviation heights) between the 10 points on the aforementioned wavy line M and the average value line P are calculated, so as to obtain 10 data h1 to h10. Then, the 10 data h1 to h10 are substituted into h in Formula 1 i so as to obtain the average roughness Ra. The 10 data h1 to h10 are substituted into h in Formula 2 i so as to obtain the root mean square roughness Rq.

[0061] Formula 1 is:

[0062] Formula 2 is:

[0063] where Ra represents the average roughness, n represents the number of measurements, h i represents the deviation height of the i-th sampling point, and Rq represents the root mean square roughness.

[0064] It should be noted that Figure 4 and Figure 6 are substantially the same SEM image.

[0065] As a possible implementation, at least part of the surface of the second region may be a polished surface or may have a pyramid-shaped texture structure.

[0066] In one example, when at least part of the surface of the second region is a polished surface, it is beneficial for more light to be refracted through this surface into the semiconductor substrate and utilized by the semiconductor substrate, improving the reabsorption of light. Specifically, as Figure 2 shown, the surface of the doping region 110 included in the second region 11 is a polished surface.

[0067] In another example, when at least part of the surface of the second region has a pyramidal texture structure, when a film layer is subsequently formed on the second region, the contact area between the film layer and the semiconductor substrate can be increased. In particular, when the film layer is a passivation layer, the passivation effect of the passivation layer on the second region can be improved, the carrier recombination rate on the surface of the second region can be reduced, and thus the photoelectric conversion efficiency of the solar cell can be improved. Specifically, as Figure 1 shown, the surface of the position in the second region 11 that is recessed downward relative to the first region has a pyramidal texture structure. As Figure 2 shown, the surface of the spaced region 111 included in the second region 11 has a pyramidal texture structure. As Figure 3 shown, the surface of the second region 11 has a pyramidal texture structure.

[0068] Exemplarily, along the first direction, the second region includes a third region adjacent to the first region and a fourth region far from the first region, and the third region is located between the fourth region and the first region. Exemplarily, along the first direction, starting from the boundary line between the first region and the second region and extending 5 μm into the second region, this range is the third region. The other regions in the second region except those adjacent to the third region are the fourth regions far from the first region. The surfaces of both the third region and the fourth region have a pyramidal texture structure, and the dimensional uniformity of the pyramidal texture structures on the surfaces of the third region and the fourth region is substantially equal. In this case, the film layer subsequently formed on the surface of the second region by the solar cell provided in this application is more uniform, the film formation quality of the film layer is better, and the compactness of the film layer is better, which is beneficial to improving the quality and working performance of the solar cell. Further, along the direction from the first surface to the second surface, the height difference between the surface of the semiconductor substrate in the third region and the surface of the semiconductor substrate in the first region is greater than the height difference between the surface of the semiconductor substrate in the fourth region and the surface of the semiconductor substrate in the first region.

[0069] As a possible implementation manner, refer to Figures 1 to 3, at least part of the surface of the second region 11 is recessed into the semiconductor substrate 1 by a depth greater than or equal to 1 μm and less than or equal to 10 μm. In other words, along the direction from the first surface to the second surface, the height difference between the surface of the semiconductor substrate in the second region and the surface of the semiconductor substrate in the first region is greater than or equal to 1 μm and less than or equal to 10 μm. Exemplarily, the height difference can be 1 μm, 1.2 μm, 1.5 μm, 1.61 μm, 1.8 μm, 1.94 μm, 2 μm, 2.02 μm, 2.3 μm, 2.5 μm, 2.8 μm, 3 μm, 3.3 μm, 3.5 μm, 3.8 μm, 3.89 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm or 10 μm, etc. Preferably, along the direction from the first surface to the second surface, the height difference between the surface of the semiconductor substrate in the second region and the surface of the semiconductor substrate in the first region is greater than or equal to 1 μm and less than or equal to 4 μm. Further preferably, along the direction from the first surface to the second surface, the height difference between the surface of the semiconductor substrate in the second region and the surface of the semiconductor substrate in the first region is greater than or equal to 1 μm and less than or equal to 3 μm.

[0070] In the case of adopting the above technical solution, the first doped semiconductor layer 2 and the film layers subsequently formed on at least part of the surface of the second region 11 can be staggered in the thickness direction of the semiconductor substrate 1, so as to avoid the mutual influence between the first doped semiconductor layer 2 and the subsequently formed film layers, or the relative influence between the structures corresponding to the first doped semiconductor layer 2 and the subsequently formed film layers. For example, when the film layer is the second doped semiconductor layer 3 with a conductivity type opposite to that of the first doped semiconductor layer 2, and the height difference between the surface of the semiconductor substrate in the second region and the surface of the semiconductor substrate in the first region is within the above range, it can prevent the electrode structure in ohmic contact with the first doped semiconductor layer 2 and the second doped semiconductor layer 3 with opposite conductivity types from being staggered to a small extent in the thickness direction of the semiconductor substrate 1, so as to reduce the leakage risk. Further, compared with the differences in the recessed depth and the like after subsequent wet etching due to the large and uneven thermal damage to the semiconductor substrate during the laser patterning process; and due to the large damage to the semiconductor substrate, resulting in the need to wet-etch a part of the thickness of the semiconductor substrate (the thermal damage layer is generally 10 - 20 μm), which requires a thicker silicon wafer for battery preparation. The present application uses a method of non-destructive laser patterning, so that the thermal damage to the semiconductor substrate is small, and there is no need for a subsequent wet polishing step to remove the damage layer. Therefore, while reducing the process time, the thinning of the semiconductor substrate is achieved.

[0071] When the specific structures in the solar cell provided by the embodiment of the present invention are different, corresponding to different types of solar cells, three types of solar cells are taken as examples for description below. It should be understood that the following description is only for understanding and not for specific limitation.

[0072] The first type: Refer to Figure 1 and Figure 4 , the solar cell includes: a semiconductor substrate 1, a first doped semiconductor layer 2, and a second doped semiconductor layer 3. The semiconductor substrate 1 includes opposite first and second surfaces, and the first surface has first regions 10 and second regions 11 that are alternately distributed along a first direction A. The first doped semiconductor layer 2 is disposed on the first regions 10; the second doped semiconductor layer 3 is disposed on the second regions 11 and extends onto a part of the first doped semiconductor layer 2; the second doped semiconductor layer 3 and the first doped semiconductor layer 2 have opposite conduction types. Wherein, the side surface of the first doped semiconductor layer 2 close to the second regions 11 is wavy along a second direction B, and the first direction A is different from the second direction B. Along the first direction A, the distance between the peaks and valleys of the wavy shape is greater than or equal to 1 μm and less than or equal to 4 μm; and / or, the average roughness of the wavy shape extending along the second direction B is less than or equal to 2.4 μm. At this time, the above solar cell is a hybrid back contact cell.

[0073] For the above first doped semiconductor layer and second doped semiconductor layer, in terms of doping type, the doping type of the first doped semiconductor layer can be N-type, and at this time the doping type of the second doped semiconductor layer is P-type; or, the doping type of the first doped semiconductor layer can also be P-type, and at this time the doping type of the second doped semiconductor layer is N-type. The embodiments of the present invention do not specifically limit the doping types of the first doped semiconductor layer and the second doped semiconductor layer, as long as the doping types of the two are opposite. When the doping type is P-type, generally group III elements are doped. When the doping type is N-type, generally group V elements or group VI elements are doped.

[0074] In terms of material, the material of the first doped semiconductor layer and / or the second doped semiconductor layer can include any semiconductor material such as silicon, silicon germanium, or germanium. In terms of the arrangement form of the substance, the crystal phase of the first doped semiconductor layer and / or the second doped semiconductor layer can be amorphous, microcrystalline, nanocrystalline, single crystal, or polycrystalline, etc. Exemplarily, the first doped semiconductor layer and / or the second doped semiconductor layer can be composed of one or more of polycrystalline silicon, amorphous silicon, and microcrystalline silicon. Preferably, the first doped semiconductor layer includes a first doped polycrystalline silicon layer. In this case, compared with a doped amorphous silicon layer, the doped polycrystalline silicon layer has higher carrier transport characteristics. Therefore, when the first doped semiconductor layer is a doped polycrystalline silicon layer, the carrier recombination rate can be further reduced, which is beneficial to improving the photoelectric conversion efficiency of the hybrid back contact cell. The second doped semiconductor layer includes a doped amorphous silicon layer and / or a doped microcrystalline silicon layer. It should be noted that in the material of the above doped microcrystalline silicon layer, the microcrystal is a limitation on the grain size of the silicon material. Specifically, the microcrystalline silicon material refers to a silicon material with a grain size in the nanometer range.

[0075] In terms of the formation position, the above-mentioned first doped semiconductor layer can be directly formed on the first region of the first surface. Or, as Figure 1 shown, the above-mentioned hybrid back contact cell further includes: a first passivation layer 4, which is located between the first doped semiconductor layer 2 and the semiconductor substrate 1 corresponding to the first region 10. At this time, the first passivation layer 4 and the first doped semiconductor layer 2 can form a passivated contact structure, which has excellent interface passivation effect, can realize selective collection of carriers, reduce the carrier recombination rate of the first region 10 on the first surface of the semiconductor substrate 1, and further improve the photoelectric conversion efficiency of the hybrid back contact cell. Among them, the material of the first passivation layer 4 can be determined according to the material of the first doped semiconductor layer 2. For example: when the first doped semiconductor layer 2 includes a first doped polysilicon layer, the first passivation layer 4 is a tunneling passivation layer. Preferably, the material of the first passivation layer 4 can be silicon oxide, aluminum oxide, titanium oxide, etc. The thickness of the first passivation layer 4 is greater than or equal to 1 nm and less than or equal to 2 nm. For example, the thickness of the first passivation layer 4 can be 1 nm, 1.3 nm, 1.5 nm, 1.8 nm, or 2 nm, etc. The first passivation layer 4 can be a single-layer structure or a stacked structure composed of multiple film layers. For example, the first passivation layer 4 can be a stacked structure of silicon oxide and aluminum oxide; or, a stacked structure of aluminum oxide and titanium oxide; or, a stacked structure of silicon oxide and titanium oxide.

[0076] The above-mentioned second doped semiconductor layer can be directly formed on the second region of the first surface and extend to a part of the first doped semiconductor layer. Or, as Figure 1As shown, the above hybrid back contact cell further includes a second passivation layer 5. The second passivation layer 5 is located between the second doped semiconductor layer 3 and the semiconductor substrate 1 corresponding to the second region 11, and extends onto a part of the first doped semiconductor layer 2. The part of the second doped semiconductor layer 3 corresponding to the first region 10 is located on the part of the second passivation layer 5 corresponding to the first region 10. At this time, the second passivation layer 5 and the second doped semiconductor layer 3 can form a passivated contact structure, which has excellent interface passivation effect, can achieve selective collection of carriers, reduce the carrier recombination rate of the second region 11 on the first surface of the semiconductor substrate 1, and further improve the photoelectric conversion efficiency of the hybrid back contact cell. Among them, the material of the second passivation layer 5 can be determined according to the material of the second doped semiconductor layer 3. For example: when the second doped semiconductor layer 3 includes a doped amorphous silicon layer and / or a doped microcrystalline silicon layer, the second passivation layer 5 includes an intrinsic amorphous silicon layer and / or an intrinsic microcrystalline silicon layer. The thickness of the second passivation layer 5 is greater than or equal to 1 nm and less than or equal to 50 nm. For example, the thickness of the second passivation layer 5 can be 1 nm, 5 nm, 10 nm, 12 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm or 50 nm, etc. Further, the second passivation layer 5 can be a single-layer structure or a stacked structure composed of multiple film layers.

[0077] As a possible implementation, refer to Figure 1 , the above solar cell further includes a transparent conductive layer 6 disposed on the first doped semiconductor layer 2 and the second doped semiconductor layer 3. An insulating groove is provided in the transparent conductive layer 6 to physically insulate the part of the transparent conductive layer 6 corresponding to the first region 10 from the part of the transparent conductive layer 6 corresponding to the second region 11.

[0078] The above transparent conductive layer can be composed of a stack of one or more of an ITO (indium tin oxide) layer, an ITiO (titanium tin oxide) layer, an IWO (tungsten tin oxide) layer, and an ICO (cerium tin oxide) layer. The thickness of the transparent conductive layer is greater than or equal to 10 nm and less than or equal to 500 nm. For example, the thickness of the transparent conductive layer can be 10 nm, 30 nm, 40 nm, 60 nm, 80 nm, 100 nm, 180 nm, 200 nm, 230 nm, 300 nm, 400 nm or 500 nm, etc. Preferably, the thickness of the transparent conductive layer is greater than or equal to 50 nm and less than or equal to 200 nm. The thickness direction of the above transparent conductive layer is the same as the direction from the first surface to the second surface.

[0079] Adopting the above technical solution, the transparent conductive layer 6 covering the first doped semiconductor layer 2 and the second doped semiconductor layer 3 has a high conductivity, which can timely export the carriers collected by the first doped semiconductor layer 2 and the second doped semiconductor layer 3, and reduce the carrier recombination rate. Further, the above transparent conductive layer 6 can not only improve the current collection ability of the hybrid back contact battery, but also act as an antireflection film to improve the light absorption rate of the hybrid back contact battery. Moreover, the above transparent conductive layer 6 also has a passivation property. In addition, as for the insulating groove provided in the transparent conductive layer 6, the insulating groove is used to physically insulate the portion of the transparent conductive layer 6 corresponding to the first region 10 from the portion of the transparent conductive layer 6 corresponding to the second region 11. Specifically, since the portion of the transparent conductive layer 6 corresponding to the first region 10 is used for ohmic connection with the first electrode 8, and the portion of the transparent conductive layer 6 corresponding to the second region 11 is used for ohmic connection with the second electrode 9, these two portions of the transparent conductive layer 6 cannot be directly electrically connected, that is, these two portions of the transparent conductive layer 6 must be physically insulated, that is, not in contact. Based on this, it can be understood that in order to prevent short circuit, there is no limit on the positions of the two ends of the insulating groove, as long as the transparent conductive layer 6 can be insulated from the first electrode 8 and the second electrode 9.

[0080] Further, combining the foregoing description, since the wavy shape on the side of the first doped semiconductor layer 2 has regularity, a larger error space can be provided for subsequent processing (such as patterning process), improving the process precision, and further improving the quality of the solar cell. For the first type of solar cell, the above patterning process can be understood as: a patterning process of opening the second doped semiconductor layer 3 locally in the first region 10 to expose the first doped semiconductor layer 2 and let the carriers of the first doped semiconductor layer 2 be exported. Or, an insulating groove is provided in the transparent conductive layer 6 to isolate the first electrode 8 and the second electrode 9 with different polarities to prevent leakage.

[0081] The second type: Refer to Figure 2 and Figure 4, the solar cell includes: a semiconductor substrate 1, a first doped semiconductor layer 2, and a second doped semiconductor layer 3. The semiconductor substrate 1 includes opposite first and second surfaces, and the first surface has first regions 10 and second regions 11 that are alternately distributed along a first direction A. The first doped semiconductor layer 2 is disposed on the first regions 10, and no first doped semiconductor layer 2 is formed on the second regions 11. The second regions 11 include a doped region 110 and two spaced regions 111. Along the first direction A, the doped region 110 is located between the two spaced regions 111; along the first direction A, the spaced regions 111 are located between the first regions 10 and the doped region 110; the side surface of the first doped semiconductor layer 2 close to the spaced regions 111 is wavy along a second direction B. The second doped semiconductor layer 3 is disposed on the doped region 110, and the second doped semiconductor layer 3 and the first doped semiconductor layer 2 have opposite conduction types. Among them, the side surface of the first doped semiconductor layer 2 close to the second region 11 is wavy along the second direction B, and the first direction A is different from the second direction B. Along the first direction A, the distance between the peaks and valleys of the wavy shape is greater than or equal to 1 μm and less than or equal to 4 μm; and / or, the average roughness of the wavy shape extending along the second direction B is less than or equal to 2.4 μm. At this time, the above solar cell is a hybrid back contact cell.

[0082] At this time, the above solar cell is a tunnel oxide passivated back contact solar cell (TOPCon BackContact, abbreviated as TBC). Further, the spaced regions 111 can isolate the first doped semiconductor layer 2 and the second doped semiconductor layer 3, reducing the carrier recombination rate at the lateral junction of the first doped semiconductor layer 2 and the second doped semiconductor layer 3, which is beneficial to improving the photoelectric conversion efficiency of the solar cell.

[0083] Regarding the doping type, reference can be made to the first solar cell, which will not be elaborated here.

[0084] In terms of materials, the material of the first doped semiconductor layer and / or the second doped semiconductor layer may include any semiconductor material such as silicon, silicon germanium, or germanium. In terms of the arrangement form of substances, the crystal phases of the first doped semiconductor layer and / or the second doped semiconductor layer may be amorphous, microcrystalline, nanocrystalline, single crystal, or polycrystalline, etc. Exemplarily, the first doped semiconductor layer and / or the second doped semiconductor layer may be composed of one or more of polycrystalline silicon, amorphous silicon, and microcrystalline silicon. Preferably, the first doped semiconductor layer includes a second doped polycrystalline silicon layer, and the second doped semiconductor layer includes a third doped polycrystalline silicon layer.

[0085] In terms of the formation position, the above first doped semiconductor layer may be directly formed on the first regions of the first surface. Or, as Figure 2As shown, the above-mentioned solar cell further includes: a first passivation layer 4, which is located between the first doped semiconductor layer 2 and the semiconductor substrate 1 corresponding to the first region 10. At this time, the first passivation layer 4 and the first doped semiconductor layer 2 can form a passivated contact structure, having excellent interface passivation effect, and being able to achieve selective collection of carriers, reducing the carrier recombination rate in the first region 10 on the first surface of the semiconductor substrate 1, and further improving the photoelectric conversion efficiency of the solar cell. Among them, the material of the first passivation layer 4 can be determined according to the material of the first doped semiconductor layer 2. For example: when the first doped semiconductor layer 2 includes a second doped polysilicon layer, the first passivation layer 4 is a tunneling passivation layer. Preferably, the material of the first passivation layer 4 can be alumina, silicon oxide, silicon nitride, silicon oxynitride or silicon carbide, etc., and the thickness of the first passivation layer 4 is greater than or equal to 1 nm and less than or equal to 2 nm. For example, the thickness of the first passivation layer 4 can be 1 nm, 1.3 nm, 1.5 nm, 1.8 nm or 2 nm, etc. The first passivation layer 4 can be a single-layer structure or a stacked structure composed of multiple film layers. For example, the first passivation layer 4 can be a stacked structure of alumina and silicon nitride; or, a stacked structure of alumina and silicon oxide; or, a stacked structure of silicon oxide and silicon nitride.

[0086] The above-mentioned second doped semiconductor layer can be directly formed on the doped region on the first surface. Or, as Figure 2 shown, the above-mentioned solar cell further includes a second passivation layer 5 located between the semiconductor substrate 1 corresponding to the doped region 110 and the second doped semiconductor layer 3. At this time, the second passivation layer 5 and the second doped semiconductor layer 3 can form a selective contact structure to achieve chemical passivation of the doped region 110 on the first surface of the semiconductor substrate 1 and selective collection of carriers of the corresponding conductivity type, reducing the carrier recombination rate on one side of the first surface, which is beneficial to improving the photoelectric conversion efficiency of the solar cell. Among them, the material of the second passivation layer 5 can be determined according to the material of the second doped semiconductor layer 3. For example: when the second doped semiconductor layer 3 includes a third doped polysilicon layer, the second passivation layer 5 is a tunneling passivation layer. Preferably, the material of the second passivation layer 5 can be silicon oxide, alumina or titanium oxide, etc. The thickness of the second passivation layer 5 is greater than or equal to 1 nm and less than or equal to 50 nm. For example, the thickness of the second passivation layer 5 can be 1 nm, 5 nm, 10 nm, 12 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm or 50 nm, etc. Further, the second passivation layer 5 can be a single-layer structure or a stacked structure composed of multiple film layers.

[0087] As a possible implementation, refer to Figure 2, the second type of solar cell described above may further include a surface passivation layer 7, which is disposed on the first doped semiconductor layer 2, the second doped semiconductor layer 3, and the spacer region 111. The surface passivation layer 7 can passivate one side of the first surface of the TBC and reduce the carrier recombination rate on one side of the first surface.

[0088] Specifically, the material of the surface passivation layer may be any insulating material with a passivation effect, such as silicon oxide, aluminum oxide, or silicon nitride. As for the thickness of the surface passivation layer, it can be determined according to the actual application scenario and is not specifically limited here. Further, the surface passivation layer may be a single-layer structure or a stacked structure composed of multiple film layers. As Figure 2 shown, the surface passivation layer 7 is a stacked structure.

[0089] The third type: Refer to Figure 3 and Figure 4 , the solar cell includes: a semiconductor substrate 1, a first doped semiconductor layer 2, and a surface passivation layer 7. The semiconductor substrate 1 includes opposite first and second surfaces. The first surface has a first region 10 and a second region 11 that are alternately distributed along a first direction A. The first doped semiconductor layer 2 is disposed in the first region 10, and no first doped semiconductor layer 2 is formed on the second region 11. The surface passivation layer 7 is disposed on the second region 11 and extends over the first doped semiconductor layer 2. Among them, the side surface of the first doped semiconductor layer 2 close to the second region 11 is wavy along a second direction B, and the first direction A is different from the second direction B. Along the first direction A, the distance between the peaks and valleys of the wavy shape is greater than or equal to 1 μm and less than or equal to 4 μm; and / or, the average roughness of the wavy shape extending along the second direction B is less than or equal to 2.4 μm. At this time, the above solar cell is a tunnel oxide passivated contact cell (abbreviated as TOPCon). Specifically, the third type of solar cell corresponds to the local polyfinger structure in TOPCon. Further, the surface passivation layer 7 can passivate one side of the first surface of the TOPCon and reduce the carrier recombination rate on one side of the first surface.

[0090] Regarding the doping type, material of the first doped semiconductor layer, and the relevant descriptions of the surface passivation layer, reference can be made to the second type of solar cell, and details are not repeated here.

[0091] In terms of the formation position, the first doped semiconductor layer can be directly formed on the first region of the first surface. Or, as Figure 3As shown, the above-mentioned solar cell further includes: a first passivation layer 4, which is located between the first doped semiconductor layer 2 and the semiconductor substrate 1 corresponding to the first region 10. At this time, the first passivation layer 4 and the first doped semiconductor layer 2 can form a passivated contact structure, which has excellent interface passivation effect, can realize selective collection of carriers, reduce the carrier recombination rate of the first region 10 on the first surface of the semiconductor substrate 1, and further improve the photoelectric conversion efficiency of the solar cell. Among them, the material of the first passivation layer 4 can be determined according to the material of the first doped semiconductor layer 2. For example: when the first doped semiconductor layer 2 includes a second doped polysilicon layer, the first passivation layer 4 is a tunneling passivation layer. Preferably, the material of the first passivation layer 4 can be alumina, silicon oxide, silicon nitride, silicon oxynitride or silicon carbide, etc., and the thickness of the first passivation layer 4 is greater than or equal to 1 nm and less than or equal to 2 nm. For example, the thickness of the first passivation layer 4 can be 1 nm, 1.3 nm, 1.5 nm, 1.8 nm or 2 nm, etc. The first passivation layer 4 can be a single-layer structure or a stacked structure composed of multiple film layers. For example, the first passivation layer 4 can be a stacked structure of alumina and silicon nitride; or, a stacked structure of alumina and silicon oxide; or, a stacked structure of silicon oxide and silicon nitride.

[0092] Further, the above surface passivation layer can be a single-layer structure or a stacked structure composed of multiple film layers. As Figure 3 shown, the above surface passivation layer 7 is a stacked structure.

[0093] In a second aspect, an embodiment of the present invention further provides a photovoltaic module. The photovoltaic module includes a battery string and a packaging layer. The battery string is formed by connecting a plurality of the solar cells described in the above technical solutions, and the packaging layer is used to cover the surface of the battery string.

[0094] For the beneficial effects of the second aspect and its various implementation manners in the embodiments of the present invention, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementation manners, which will not be elaborated here.

[0095] Specifically, the above battery string can be directly formed by connecting a plurality of the solar cells described in the first aspect, or the battery string includes a plurality of split battery pieces formed by dividing the solar cells described in the first aspect. In other words, the above solar cell can be a whole-piece solar cell or a half-piece solar cell. When the above solar cell is a half-piece solar cell, the whole-piece solar cell can be cut along the cutting line located in the dividing area. The "dividing area" will not be described in detail here, as long as it can meet the actual needs.

[0096] In a third aspect, the present invention further provides a method for manufacturing a solar cell. The method for manufacturing a solar cell includes:

[0097] First, a semiconductor substrate is provided; the semiconductor substrate includes opposite first and second surfaces; the first surface has first and second regions alternately distributed along a first direction;

[0098] Exemplarily, the above-mentioned first surface is a backlight surface. For the relevant description of the semiconductor substrate, reference can be made to the first aspect, which will not be elaborated here.

[0099] Before actual use, the semiconductor substrate is first polished and cleaned. Specifically, the semiconductor substrate is placed in a tank polishing machine tool. First, the semiconductor substrate is pre-cleaned to remove organic substances and other pollutants generated by the cutting damage and transportation process of the semiconductor substrate. The steps for polishing and cleaning the semiconductor substrate include: cleaning with SC-1 in the RCA (Resist Cleaning) cleaning process. SC-1 consists of NH4OH / KOH - H2O2 - H2O, and the ratio of the three is (1:1:5), and the temperature during cleaning is 65°C. Then, it is rinsed with deionized water to neutralize the chemicals remaining after SC-1 cleaning. Then, an alkali polishing treatment is carried out. The alkali polishing formula is: 5.00% wt of KOH, the original concentration of KOH solution is (45%), the temperature is 80°C, and the time is 300 s. The surface damage layer caused by cutting is removed, and the surface of the silicon wafer is polished. Then, a high-efficiency SC-1 cleaning is carried out, and the ratio of NH4OH / KOH - H2O2 - H2O is (1:1:5), the temperature is 65°C, and the time is 300 s. Then, the residual metal ions are removed by SC-2. SC-2 is a HCl:H2O2:H2O solution, with a ratio of 1:1:5, the temperature is 65°C, and the cleaning time is 200 s. Finally, it is cleaned with 5% wt hydrofluoric acid and dried to complete the polishing of the surface of the semiconductor substrate. The polishing thickness of the first and second surfaces of the semiconductor substrate is 5 μm to 10 μm, and a semiconductor substrate with different crystal orientations is formed on the polished surface of the silicon wafer.

[0100] Next, a first doped semiconductor layer is formed as a whole layer on the first surface;

[0101] Exemplarily, processes such as chemical vapor deposition can be used to form a semiconductor material layer as a whole layer on the first surface. Then, the semiconductor material layer is doped to form a first doped semiconductor layer as a whole layer on the first surface and a first doped silicon glass layer provided as a whole layer on the first doped semiconductor layer. Among them, the material and thickness of the first doped semiconductor layer can refer to the previous description. It should be noted that before forming the mask layer, the above-mentioned first doped silicon glass layer can be removed or not removed.

[0102] For example, the above semiconductor material layer may be a polysilicon layer, and a doped polysilicon layer and a phosphosilicate glass layer on its surface are formed by a phosphorus diffusion device. If it is selected to remove the phosphosilicate glass layer: before forming the mask layer, the phosphosilicate glass layer can be removed through an acid pickling process, and at this time, the passivation effect of the mask layer on the first doped semiconductor layer can be improved. If it is selected not to remove the phosphosilicate glass layer and directly form the mask layer on the phosphosilicate glass layer, the preparation steps of the solar cell can be reduced.

[0103] Next, a mask layer is formed entirely on the first doped semiconductor layer;

[0104] The material of the mask layer may be one or more of silicon nitride, silicon oxynitride, silicon oxide, silicon carbonitride, or intrinsic silicon. The above mask layer may be a single-layer film structure formed of a certain one of the above materials, or a stacked structure formed of a first doped silicon glass layer and silicon nitride. Further, the thickness of the mask layer is greater than or equal to 2 nm and less than or equal to 100 nm. For example, the thickness of the mask layer may be 2 nm, 5 nm, 8 nm, 10 nm, 30 nm, 40 nm, 60 nm, 80 nm, 90 nm, or 100 nm, etc. The formation method of the above mask layer includes one or more of plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, catalytic chemical vapor deposition (Cat-CVD), or atomic layer deposition (ALD).

[0105] Next, the mask layer and the first doped semiconductor layer in the second region are processed to obtain the first doped semiconductor layer in the first region; it should be noted that no first doped semiconductor layer is formed on the second region.

[0106] Exemplarily, when the material of the mask layer is silicon nitride, a laser with a relatively long pulse and a relatively small power density is used to process the mask layer in the second region. After processing, the mask layer is porous and the proportion of N decreases while the proportion of Si increases (specifically, part of the nitrogen element volatilizes in the form of gas, so the proportion of N decreases and the proportion of Si increases), making the processed silicon nitride mask layer less alkali-resistant than the unprocessed one. Therefore, when polishing / etching with an alkaline solution, the processed silicon nitride mask layer can be removed, while the unprocessed silicon nitride mask layer is more alkali-resistant and can be used to protect the corresponding first doped semiconductor layer and semiconductor substrate from being etched by the alkaline wet solution. After polishing and / or etching, an additional pickling step is used to remove the unprocessed silicon nitride mask layer, and thus damage-free patterning can be achieved. In other words, when irradiated with a laser having a relatively long pulse and a relatively small power density, the silicon nitride near the first doped semiconductor layer decomposes under the thermal effect of the first doped semiconductor layer, and part of the nitrogen element volatilizes in the form of gas, so the proportion of N decreases and the proportion of Si increases; the silicon nitride relatively far from the first doped semiconductor layer is oxidized by air to form silicon oxide and silicon oxynitride. The silicon nitride after laser treatment is porous and stratified, and the alkaline solution easily penetrates through the small holes to the silicon-rich silicon nitride layer at the bottom, thereby corroding the underlying silicon nitride and the corresponding semiconductor substrate below. Compared with the method of removing the silicon nitride mask layer by blasting with a high-power laser in the prior art, the laser power used in the embodiment of the present invention is smaller. Therefore, the processing method provided by the embodiment of the present invention causes less damage or basically no damage to the semiconductor substrate, can achieve thinning of the semiconductor substrate, and reduces the manufacturing cost of the solar cell. Further, when the semiconductor substrate is basically undamaged, after polishing and / or etching, there is no need to remove the damaged layer on the semiconductor substrate, saving the preparation steps.

[0107] When the mask layer is a laminated structure of a first doped silicon glass layer and silicon nitride, the processing method for the mask layer remains unchanged, and reference can be made to the description in the foregoing text regarding the case where "the material of the mask layer is silicon nitride". Since the first doped silicon glass layer has heat insulation ability, the thermal effect generated by the absorption of laser by the first doped semiconductor layer is more obvious, and the processing effect on silicon nitride is more obvious under the same laser conditions, that is, more holes are generated in the processed silicon nitride and it is more easily etched by the alkaline solution.

[0108] After the above treatment, the side surface of the first doped semiconductor layer near the second region is wavy along the second direction; the first direction is different from the second direction; along the first direction, the distance between the peaks and valleys of the wavy shape is greater than or equal to 1 μm and less than or equal to 4 μm; and / or, the average roughness of the wavy shape extending along the second direction is less than or equal to 2.4 μm. Exemplarily, the distance between the peaks and valleys of the wavy shape can be 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.3 μm, 2.5 μm, 2.8 μm, 3 μm, 3.3 μm, 3.5 μm, 3.8 μm or 4 μm, etc. The average roughness of the wavy shape extending along the second direction can be 2.4 μm, 2.3 μm, 2.2 μm, 2.1 μm, 2.0 μm, 1.9 μm, 1.8 μm, 1.7 μm, 1.6 μm, 1.5 μm or 1.4 μm, etc. The calculation method of the average roughness of the wavy shape extending along the second direction can refer to the calculation of the average roughness in the first aspect. The beneficial effects of the third aspect and its various implementation manners in the present invention can refer to the analysis of the beneficial effects in the first aspect and its various implementation manners, and will not be elaborated here.

[0109] Next, a second doped semiconductor layer is deposited and formed according to the type of the solar cell.

[0110] Exemplarily, the second doped semiconductor layer is prepared by a low-temperature method such as Plasma Enhanced Chemical Vapor Deposition (PECVD). The formation position, material and thickness of the second doped semiconductor layer can refer to the previous description.

[0111] It should be noted that structures such as a first passivation layer, a second passivation layer, a surface passivation layer, and a transparent conductive layer can be selectively formed according to actual needs, and the specific formation process will not be described in detail here.

[0112] In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0113] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other; The first surface has first areas and second areas alternately distributed along a first direction; A first doped semiconductor layer, disposed in the first region; The first doped semiconductor layer is not formed on the second region; A side surface of the first doped semiconductor layer close to the second region is wavy along a second direction; the first direction is different from the second direction; Along the first direction, the distance between the crest and the trough of the wave shape is greater than or equal to 1 μm and less than or equal to 4 μm; And / or, an average roughness of the wave shape extending along the second direction is less than or equal to 2.4 μm.

2. The solar cell according to claim 1, characterized in that Along the first direction, a distance between a crest of the wave shape and a trough adjacent to the crest is greater than or equal to 1 μm and less than or equal to 4 μm.

3. The solar cell according to claim 1, characterized in that Along the second direction, a distance between two adjacent wave crests of the wave shape is greater than or equal to 5 μm and less than or equal to 20 μm.

4. The solar cell according to claim 1, characterized in that The root mean square roughness of the wave shape extending along the second direction is less than or equal to 2.7 μm.

5. The solar cell according to claim 1, characterized in that: Along the first direction, the second area includes a third area adjacent to the first area and a fourth area away from the first area, and the third area is located between the fourth area and the first area; The surface of the third region and the surface of the fourth region both have a pyramid-type texture structure, and the size uniformity of the pyramid-type texture structures of the surface of the third region and the surface of the fourth region are approximately equal; and / or, along the direction from the first surface to the second surface, the height difference between the surface of the semiconductor substrate in the third region and the surface of the semiconductor substrate in the first region is greater than the height difference between the surface of the semiconductor substrate in the fourth region and the surface of the semiconductor substrate in the first region.

6. The solar cell according to claim 1, characterized in that Along the direction from the first surface to the second surface, a height difference between a surface of the semiconductor substrate in the second region and a surface of the semiconductor substrate in the first region is greater than or equal to 1 μm and less than or equal to 10 μm.

7. The solar cell according to claim 1, characterized in that The solar cell further comprises: The second doped semiconductor layer is disposed on the second region and is extended on a portion of the first doped semiconductor layer; the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types.

8. The solar cell according to claim 7, characterized in that: The first doped semiconductor layer includes a first doped polycrystalline silicon layer; the second doped semiconductor layer includes a doped amorphous silicon layer and / or a doped microcrystalline silicon layer.

9. The solar cell according to claim 1, characterized in that: The second region includes a doped region and two spacer regions; along the first direction, the doped region is located between the two spacer regions; along the first direction, the spacer region is located between the first region and the doped region; and the side surface of the first doped semiconductor layer close to the spacer region is wavy along the second direction; The solar cell further comprises: A second doped semiconductor layer is disposed in the doped region; the second doped semiconductor layer and the first doped semiconductor layer have opposite conductivity types; A surface passivation layer is disposed on the first doped semiconductor layer, the second doped semiconductor layer and the spacing region.

10. The solar cell according to claim 9, characterized in that: The first doped semiconductor layer includes a second doped polysilicon layer; and the second doped semiconductor layer includes a third doped polysilicon layer.

11. The solar cell according to claim 1, characterized in that: The solar cell further includes: a surface passivation layer disposed on the second region and extending on the first doped semiconductor layer.

12. A photovoltaic module, characterized in that: The photovoltaic module comprises: A battery string, wherein the battery string is formed by connecting a plurality of solar cells according to any one of claims 1 to 11; The encapsulation layer is used to cover the surface of the battery string.

13. A method for manufacturing a solar cell, characterized in that: include: Providing a semiconductor substrate; The semiconductor substrate comprises a first surface and a second surface opposite to each other; the first surface comprises a first region and a second region alternately distributed along a first direction; forming a first doped semiconductor layer entirely on the first surface; forming a mask layer entirely on the first doped semiconductor layer; Processing the mask layer and the first doped semiconductor layer in the second region to obtain the first doped semiconductor layer in the first region, and the first doped semiconductor layer is not formed on the second region; A side surface of the first doped semiconductor layer close to the second region is wavy along a second direction; the first direction is different from the second direction; Along the first direction, the distance between the crest and the trough of the wave shape is greater than or equal to 1 μm and less than or equal to 4 μm; And / or, an average roughness of the wave shape extending along the second direction is less than or equal to 2.4 μm.

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