Light emitting diode chip, display module and lighting device

Abstract

The embodiment of the invention provides a light-emitting diode chip, a display module and a lighting device, and relates to the technical field of semiconductors, the light-emitting diode chip comprises a chip body and an adjusting layer arranged on the chip body, the adjusting layer is located on the light-emitting side of the light-emitting diode chip, and the adjusting layer is located on the light-emitting side of the light-emitting diode chip. And the refractive index of the adjusting layer is greater than that of a film layer in contact with the adjusting layer in the chip body. Light emitted by the chip body enters the adjusting layer and enters the optically denser medium from the optically thinner medium, so that the light is refracted into the adjusting layer at the maximum efficiency, the light emitting efficiency from the chip body to the adjusting layer is improved, and the light emitting efficiency of the adjusting layer is improved by processing the surface of the adjusting layer. Meanwhile, light entering the optically thinner medium from the optically denser medium returns to the chip body in a small proportion due to the effects of total reflection and the like, so that the reflection times and the refraction times of the light in the chip body are reduced, and the light emitting efficiency of the light emitting diode chip is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technologies, and particularly to a light-emitting diode chip, a display module, and a lighting device. Background Art

[0002] In semiconductor lighting technology, a light-emitting diode (LED), as a light-emitting device that converts electrical energy into light energy, has the advantages of energy conservation, environmental protection, long service life, and high luminous efficiency, and is widely used in many fields such as indication, display, decoration, and lighting. However, the light extraction efficiency of LEDs is relatively low. Summary of the Invention

[0003] Embodiments of this application provide a light-emitting diode chip, a display module, and a lighting device, which can improve the light extraction efficiency of the light-emitting diode chip.

[0004] In a first aspect, an embodiment of this application provides a light-emitting diode chip, including a chip body and an adjustment layer disposed on the chip body. The adjustment layer is located on the light-emitting side of the light-emitting diode chip, and the refractive index of the adjustment layer is greater than the refractive index of the film layer in the chip body that contacts the adjustment layer.

[0005] In a second aspect, an embodiment of this application provides a display module, including a driving backplane and the above-mentioned light-emitting diode chip. The light-emitting diode chip is disposed on the driving backplane and electrically connected to the driving backplane.

[0006] In a third aspect, an embodiment of this application provides a lighting device, including a circuit board and the above-mentioned light-emitting diode chip. The light-emitting diode chip is disposed on the circuit board and electrically connected to the circuit board.

[0007] In the light-emitting diode chip, display module, and lighting device according to the embodiments of the present application, by disposing the adjustment layer on the chip body, the adjustment layer can be directly formed on the chip body, with a simple process and low cost. The adjustment layer is on the light-emitting side of the light-emitting diode chip, enabling the light generated by the chip body to be emitted to the outside of the light-emitting diode chip through the adjustment layer. The refractive index of the adjustment layer is greater than that of the film layer in the chip body in contact with the adjustment layer, making the adjustment layer an optically denser medium and the corresponding film layer in the chip body an optically rarer medium. The light emitted by the chip body enters the adjustment layer, going from an optically rarer medium to an optically denser medium, so that the incident angle of the emitted light is greater than the refraction angle, thus maximizing the refraction of the light emitted by the chip body into the adjustment layer and improving the light-emitting efficiency from the chip body to the adjustment layer. Moreover, by treating the surface of the adjustment layer facing away from the chip body, the light can also be focused, improving the light-emitting efficiency of the adjustment layer and further enhancing the light-emitting efficiency of the light-emitting diode chip. At the same time, considering the effects such as total reflection when light goes from an optically denser medium to an optically rarer medium, less light is emitted, so that only a small proportion of the light entering the adjustment layer from the chip body returns to the chip body, thereby reducing the number of internal reflections and refractions of light in the chip body, greatly reducing side emission, increasing normal emission, further improving the light-emitting efficiency of the light-emitting diode chip, and enhancing the uniformity of the light-emitting distribution of the light-emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0009] Figure 1 is the optical path diagram of a light-emitting diode chip in the related art;

[0010] Figure 2 is the optical path diagram of the packaged light-emitting diode chip in the related art;

[0011] Figure 3 is the optical path diagram of the light-emitting diode chip according to the embodiment of the present application;

[0012] Figure 4 is the first simplified diagram of the light-emitting diode chip according to the embodiment of the present application;

[0013] Figure 5 is the second simplified diagram of the light-emitting diode chip according to the embodiment of the present application;

[0014] Figure 6 is the third simplified diagram of the light-emitting diode chip according to the embodiment of the present application;

[0015] Figure 7 The fourth simplified diagram of the light-emitting diode chip in the embodiment of the present application;

[0016] Figure 8 The first schematic diagram of the photonic crystal in the embodiment of the present application;

[0017] Figure 9 The second schematic diagram of the photonic crystal in the embodiment of the present application;

[0018] Figure 10 The third schematic diagram of the photonic crystal in the embodiment of the present application;

[0019] Figure 11 The fourth schematic diagram of the photonic crystal in the embodiment of the present application;

[0020] Figure 12 The fifth schematic diagram of the photonic crystal in the embodiment of the present application;

[0021] Figure 13 The sixth schematic diagram of the photonic crystal in the embodiment of the present application;

[0022] Figure 14 The seventh schematic diagram of the photonic crystal in the embodiment of the present application;

[0023] Figure 15 The eighth schematic diagram of the photonic crystal in the embodiment of the present application;

[0024] Figure 16 One schematic diagram of the first reflective layer in the embodiment of the present application;

[0025] Figure 17 Another schematic diagram of the first reflective layer in the embodiment of the present application;

[0026] Figure 18 The first structural diagram of the light-emitting diode chip in the embodiment of the present application;

[0027] Figure 19 The second structural diagram of the light-emitting diode chip in the embodiment of the present application;

[0028] Figure 20 The third structural diagram of the light-emitting diode chip in the embodiment of the present application;

[0029] Figure 21 The fourth structural diagram of the light-emitting diode chip in the embodiment of the present application;

[0030] Figure 22 One schematic diagram of the display module in the embodiment of the present application;

[0031] Figure 23 Another schematic diagram of the display module in the embodiment of the present application.

[0032] Description of reference numerals:

[0033] 100 - Chip body;

[0034] 101 - Substrate;

[0035] 102 - Buffer layer;

[0036] 103 - N-type electrode;

[0037] 104 - N-type semiconductor layer;

[0038] 105 - P-type electrode;

[0039] 106 - Light-emitting layer;

[0040] 107 - P-type semiconductor layer;

[0041] 108 - Current spreading layer;

[0042] 109 - Second reflective layer;

[0043] 110 - First insulating layer;

[0044] 111 - Second insulating layer;

[0045] 112 - Bonding substrate;

[0046] 113 - Bonding layer;

[0047] 114 - Film layer;

[0048] 200 - Adjustment layer;

[0049] 201 - Optical microstructure;

[0050] 202 - Photonic crystal;

[0051] 203 - Through hole;

[0052] 300 - Driving backplane;

[0053] 301 - Driving substrate;

[0054] 302 - Driving unit;

[0055] 400 - Encapsulation layer;

[0056] 500 - First reflective layer. Detailed implementation manners

[0057] The material of the light-emitting side film layer of the light-emitting diode chip is usually gallium nitride (GaN), whose refractive index is n1, and n1 is equal to 2.4. The refractive index of air is n3, and n3 is equal to 1. The refractive index of this film layer differs greatly from that of air, resulting in a relatively small critical angle for the light-emitting diode chip, usually about 22°. Refer to Figure 1 , and the light rays equal to or greater than this critical angle undergo total internal reflection, resulting in a relatively low light extraction efficiency. At the same time, the light rays undergoing total internal reflection are reflected and refracted multiple times inside the light-emitting diode chip, and a relatively large proportion of them will exit from the sidewall of the light-emitting diode chip, resulting in a relatively large side light extraction ratio of the light-emitting diode chip, further reducing the light extraction efficiency and also causing problems of uneven light extraction distribution.

[0058] Refer to Figure 2 , after the light-emitting diode chip is encapsulated, materials such as epoxy resin are usually used as the encapsulation layer 400. The refractive index of the encapsulation layer 400 is n4, where n3 < n4 < n1, that is, the refractive index of the encapsulation layer 400 is less than the refractive index of the corresponding film layer of the light-emitting diode chip and greater than the refractive index of air. In this way, the critical angle of the encapsulated light-emitting diode chip can be increased, the light extraction efficiency can be improved, and the light extraction distribution will be more uniform. However, as Figure 2 shown, the use of the encapsulation layer has limited improvement in the light extraction efficiency and the uniformity of the light extraction distribution of the light-emitting diode chip, and the effect is not good.

[0059] In view of this, the light-emitting diode chip, display module, and lighting device provided by the embodiments of the present application are such that by disposing the adjustment layer on the chip body, the adjustment layer can be directly formed on the chip body, with a simple process and low cost. The adjustment layer is on the light-emitting side of the light-emitting diode chip, so that the light generated by the chip body exits to the outside of the light-emitting diode chip through the adjustment layer. The refractive index of the adjustment layer is greater than the refractive index of the film layer in the chip body that contacts the adjustment layer, making the adjustment layer an optically denser medium and the corresponding film layer in the chip body an optically rarer medium. The light emitted from the chip body enters the adjustment layer, from an optically rarer medium into an optically denser medium, so that the incident angle of the emitted light is greater than the refraction angle, thus maximizing the refraction of the light emitted from the chip body into the adjustment layer, improving the light extraction efficiency from the chip body to the adjustment layer. Moreover, by treating the surface of the adjustment layer facing away from the chip body, the light can also be focused, improving the light extraction efficiency of the adjustment layer, and further improving the light extraction efficiency of the light-emitting diode chip.

[0060] Furthermore, considering the effect of total reflection when light travels from an optically denser medium to an optically less dense medium, less light is emitted, resulting in only a small proportion of the light entering the adjustment layer from the chip body returning to the chip body. This can reduce the number of internal reflections and refractions of light within the chip body, significantly reducing side emission and increasing normal light emission, thus shaping the light and further improving the light extraction efficiency of the light-emitting diode chip and enhancing the uniformity of the light extraction distribution of the light-emitting diode. At the same time, by using the chip body and the adjustment layer to adjust the phase, amplitude distribution, etc. of the light, precise control of the light angle, intensity, etc. is also achieved.

[0061] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the preferred embodiments of this application will be described in more detail below with reference to the accompanying drawings. In the drawings, the same or similar reference numerals represent the same or similar components or components with the same or similar functions from beginning to end. The described embodiments are some, but not all, of the embodiments of this application. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain this application and should not be construed as a limitation of this application. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of this application. The embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0062] In a first aspect, an embodiment of this application provides a light-emitting diode chip, which can be applied to fields such as lighting and display. The shape of the light-emitting diode chip can be rectangular, square, circular, oval, triangular, rhombic, parallelogram, or other polygons, etc.

[0063] The size of the light-emitting diode chip can be 0.001 - 200 microns, or a larger size, and this size may vary depending on the use of the light-emitting diode. The above-mentioned "size" refers to the extension length of the light-emitting diode chip in a certain extension direction. For example, it can be the length or width of a rectangular light-emitting diode chip, or the major axis length or minor axis length of an oval light-emitting diode chip, or the diameter of a circular light-emitting diode chip, etc.

[0064] The following gives an exemplary description of the size of the light-emitting diode chip in different usage scenarios. When the light-emitting diode chip is applied to display products such as household TVs and desktop computers, the size of the light-emitting diode chip can be greater than 100 microns. When the light-emitting diode chip is applied to display products such as laptops and tablets, the size of the light-emitting diode chip can be greater than 60 microns. When the light-emitting diode chip is applied to display products such as mobile phones and electronic watches, the size of the light-emitting diode chip can be greater than 50 microns.

[0065] Refer to Figures 3 to 21, the light-emitting diode chip includes a chip body 100 and an adjustment layer 200. The adjustment layer 200 is located on the light-emitting side of the light-emitting diode chip, and the refractive index of the adjustment layer 200 is greater than that of the film layer 114 in the chip body 100 that contacts the adjustment layer 200. Among them, the chip body 100 may have multiple film layers, and at least some of the film layers are stacked. The chip body 100 generates and emits light. Among them, the light may be white light or light of other colors. The chip body 100 may be electro-luminescence (EL for short), and may also have both electro-luminescence and photo-luminescence (PL for short) as two light-emitting forms.

[0066] The architecture of the chip body 100 is not limited. The chip body 100 may be a front-mounted structure, a flip-chip structure, a vertical structure, a thin-film front-mounted structure, a thin-film flip-chip structure, a thin-film vertical structure, etc. Among them, the front-mounted structure is as Figure 4 shown, the flip-chip structure is as Figure 5 shown, and the vertical structure is as Figure 6 shown. In this way, the chip body 100 can adopt conventional processes and technologies. The adjustment layer 200 is directly formed on the chip body 100, with low cost and simple process.

[0067] The adjustment layer 200 is arranged on one side of the chip body 100, and the light emitted by the chip body 100 passes through the adjustment layer 200 and is emitted to the outside of the light-emitting diode chip. As Figure 3 and Figure 4 shown, the adjustment layer 200 is located above the chip body 100, and the light-emitting side of the light-emitting diode chip is the upper side. The refractive index of the adjustment layer 200 is n2, the refractive index of the film layer 114 in the chip body 100 that contacts the adjustment layer 200 is n1, and the refractive index of air is n3. Among them, n2 > n1 > n3. In this way, the refractive index of the adjustment layer 200 is relatively large, the refractive index of the film layer 114 in the chip body 100 that contacts the adjustment layer 200 is relatively small. The adjustment layer 200 is an optically denser medium, and the film layer 114 in the chip body 100 that contacts the adjustment layer 200 is an optically thinner medium. The light emitted by the chip body 100 enters the adjustment layer 200, from an optically thinner medium to an optically denser medium, so that the incident angle of the emitted light is greater than the refraction angle, so that the light emitted by the chip body 100 is refracted into the adjustment layer 200 with the highest efficiency, improving the light-emitting efficiency from the chip body 100 to the adjustment layer 200. And by treating the surface of the adjustment layer facing away from the chip body, the light can also be converged, improving the light-emitting efficiency of the adjustment layer, and further improving the light-emitting efficiency of the light-emitting diode chip.

[0068] Furthermore, considering the effects such as total reflection when light enters from an optically denser medium to an optically thinner medium, less light is emitted, resulting in only a small proportion of the light entering the adjustment layer 200 from the chip body 100 returning to within the chip body 100. Thus, the number of internal reflections and refractions of light within the chip body 100 can be reduced, significantly decreasing side emission and increasing normal emission, thereby further improving the light extraction efficiency of the light-emitting diode chip. Meanwhile, by using the chip body and the adjustment layer to adjust the phase, amplitude distribution, etc. of light, precise control over the light angle, intensity, etc. can also be achieved.

[0069] It can be understood that when the light-emitting diode chip further includes a packaging layer covering the chip body 100 and the adjustment layer 200, the refractive index of the packaging layer is n4, where n2 > n1 > n4 > n3. In this way, the critical angle of the light-emitting diode chip can be increased, enabling the light emitted from the chip body 100 to be refracted into the air with maximum efficiency, thereby enhancing the light extraction efficiency and making the light extraction distribution more uniform.

[0070] Among them, the adjustment layer 200 can be formed by epitaxial processes such as Metal-organic Chemical Vapor Deposition (abbreviated as MOCVD), physical film-forming processes such as magnetron sputtering, chemical film-forming processes such as Chemical Vapor Deposition (abbreviated as CVD), or other film-forming processes. The adjustment layer 200 can be a single-layer structure or a stacked-layer structure. When the adjustment layer 200 is a single-layer structure, it is convenient to control the thickness of the adjustment layer 200, avoid making the light-emitting diode chip too thick, and is also convenient for the film-forming production of the adjustment layer 200. When the adjustment layer 200 is a stacked-layer structure, along the direction away from the chip body 100, the refractive indices of the multiple layers of the adjustment layer 200 increase sequentially and are all greater than the refractive index of the film layer 114 adjacent to the adjustment layer 200 in the chip body 100. With such a setting, the light in the chip body 100 can be emitted with maximum efficiency after entering the adjustment layer 200, improving the light extraction efficiency of the light-emitting diode chip.

[0071] Refer to Figures 3 to 7 , an optical microstructure 201 is also formed on the surface of the adjustment layer 200 facing away from the film layer 114. The optical microstructure 201 is used to improve the light extraction rate of the adjustment layer 200. By treating the surface of the adjustment layer 200 to form the optical microstructure 201, the light that diverges and is unevenly distributed during refraction within the adjustment layer 200 can be converged and uniformly emitted through the optical microstructure 201, so as to be refracted into the air with maximum efficiency, further improving the light extraction efficiency of the light-emitting diode chip.

[0072] Among them, the height of the optical microstructure 201 is 30%-80% of the thickness of the adjustment layer 200, and the thickness of the adjustment layer 200 is 0.1-10 μm. In this way, on the one hand, the adjustment layer 200 is relatively thin, which can avoid excessive total thickness of the light-emitting diode chip and is conducive to the miniaturization of the product. On the other hand, the height of the optical microstructure 201 is appropriate, which will neither damage the integrity of the adjustment layer 200 and avoid exposure of the chip body 100, nor can it have sufficient height to ensure the light extraction efficiency.

[0073] Exemplarily, the height of the optical microstructure 201 is 35%-45%, 50%-60%, or 65%-75% of the thickness of the adjustment layer 200. For example, the height of the optical microstructure 201 is 40%, 55%, or 70% of the thickness of the adjustment layer 200. Additionally, the thickness of the adjustment layer 200 can be 0.5-1 μm, 1.5-5 μm, or 6-8 μm. For example, the thickness of the adjustment layer 200 is 1 μm, 4 μm, or 7 μm.

[0074] It should be noted that the height of the optical microstructure 201 is related to the thickness of the adjustment layer 200. When the thickness of the adjustment layer 200 is larger, the height of the optical microstructure 201 can be higher; when the thickness of the adjustment layer 200 is smaller, the height of the optical microstructure 201 can be lower, which is convenient for the fabrication of the optical microstructure 201 on the basis of ensuring the integrity of the adjustment layer 200. Exemplarily, when the thickness of the adjustment layer 200 is 6-8 μm, the height of the optical microstructure 201 can be 65%-75% of the thickness of the adjustment layer 200; when the thickness of the adjustment layer 200 is 0.5-1 μm, the height of the optical microstructure 201 is 35%-45% of the thickness of the adjustment layer 200.

[0075] It can be understood that the optical microstructure 201 can be located on a partial surface of the adjustment layer 200 facing away from the chip body 100, or on the entire surface of the adjustment layer 200 facing away from the chip body 100. By selectively performing partial surface treatment on the surface of the adjustment layer 200 facing away from the chip body 100, the formed optical microstructure 201 can be only located in the required area, so as to flexibly adjust the position of the optical microstructure 201 to control the light extraction range and light extraction angle of the light-emitting diode chip.

[0076] Based on the above embodiments, in some possible implementation manners, refer to Figure 7, the optical microstructure 201 is a concavo-convex structure, which is formed by a surface roughening process. In this way, through the surface roughening process, an irregular concavo-convex structure is formed on the surface of the adjustment layer 200 facing away from the chip body 100, reducing or destroying the total reflection at the interface between the adjustment layer 200 and the air, thereby improving the light extraction efficiency of the adjustment layer 200 and improving the light extraction efficiency of the light-emitting diode chip. Among them, the roughening depth of the surface roughening process is 30-80% of the thickness of the adjustment layer 200.

[0077] Among them, the surface roughening process can be realized by physical means or by chemical means. Physical means include manual grinding, etc., and chemical means include wet etching, dry etching or a combination of both. Wet etching can be solution corrosion, electrochemical corrosion, etc., and dry etching can be reactive ion etching (Reactive Ion Etching, abbreviated as RIE), high density plasma (High Density Plasma, abbreviated as HDP) etching, electron cyclotron resonance (Electron Cyclotron Resonance, abbreviated as ECR) plasma etching, inductively coupled plasma (Inductively Coupled Plasma, abbreviated as ICP) etching, etc. Different methods can be selected according to the different materials selected for the adjustment layer 200, and different etching solutions or etching gases can be selected according to the different materials selected for the adjustment layer 200.

[0078] Exemplarily, the material of the adjustment layer 200 is indium gallium nitride (InGaN) material, and the optical microstructure 201 can be formed by the process steps of ICP etching, cleaning, potassium hydroxide (KOH) solution corrosion, and cleaning on the corresponding surface of the adjustment layer 200. Another exemplarily, the material of the adjustment layer 200 is indium tin oxides (Indium Tin Oxides, abbreviated as ITO), and the optical microstructure 201 can be formed by the process steps of spin coating, mask lithography, and immersion in 98% concentrated sulfuric acid on the corresponding surface of the adjustment layer 200. When immersed in 98% concentrated sulfuric acid, the temperature is 60°C and the immersion time is 8 min.

[0079] Based on the above embodiments, refer to Figures 4 to 6 , in some possible implementation manners, the optical microstructure 201 is a photonic crystal 202, and the photonic crystal 202 is formed by electron beam lithography technology, nanoimprint technology or holographic exposure technology. In this way, by forming a regular photonic crystal 202 on the surface of the adjustment layer 200 facing away from the chip body 100, the light can be shaped, facilitating the control of the light extraction distribution, and improving the light extraction efficiency of the adjustment layer 200 to improve the light extraction efficiency of the light-emitting diode chip.

[0080] Among them, the height (i.e., depth) of the photonic crystal 202 is 30-80% of the thickness of the adjustment layer 200. The photonic crystals 202 are arranged periodically, and the period of the photonic crystals 202 is 1-5 μm, and this period is adapted to the dimension of the photonic crystals 202. Among them, the height direction of the photonic crystal 202 is the same as the thickness direction of the adjustment layer 200.

[0081] In some possible examples, refer to Figures 8 to 11 , among any three adjacent rows of photonic crystals 202, the photonic crystals 202 in adjacent rows are arranged in a staggered manner, and the photonic crystals 202 in every other row are arranged opposite to each other. Refer to Figures 12 to 15 , a through hole 203 is further provided on the end face of the photonic crystal 202 facing away from the film layer 114. By providing the through hole 203, the light transmittance of the photonic crystal 202 can be improved. The cross-sectional shape of the through hole 203 can be circular, elliptical, triangular, polygonal, etc.

[0082] The photonic crystal 202 can be a two-dimensional photonic crystal or a three-dimensional photonic crystal. The surface shape of the two-dimensional photonic crystal is circular, elliptical, triangular, square, rhombic, parallelogram, rectangular or polygonal. The shape of the three-dimensional photonic crystal is a triangular column, cube, face-centered cube, hexagonal close-packed, or cylinder. As Figure 8 shown, the surface shape of the two-dimensional photonic crystal is square, as Figure 9 shown, the surface shape of the two-dimensional photonic crystal is circular, as Figure 10 shown, the surface shape of the two-dimensional photonic crystal is regular hexagon, as Figure 11 shown, the surface shape of the two-dimensional photonic crystal is triangular.

[0083] Exemplarily, the period of the photonic crystal 202 is 2 μm, the depth is 0.1 μm, the shape is a cube, and it is formed by nanoimprint technology. Its process flow includes preparing a template and transferring the pattern of the photonic crystal 202. Among them, the process of preparing the template is: making a silicon template, pressing a polymer (IPS) on the silicon template, and demolding to obtain an IPS soft template. The process of transferring the pattern of the photonic crystal 202 is: cleaning the chip body 100 with deionized water, drying, spin-coating 150 nm ultraviolet imprinting glue, pre-baking for 3 min, ultraviolet soft imprinting, demolding and removing glue, dry etching, and removing glue. During ultraviolet soft imprinting, the IPS soft template is covered on the ultraviolet imprinting glue for 15 min, ultraviolet exposure for 10 s, and the pressure is 35×10 5 Pa.

[0084] In an embodiment of the present application, the adjustment layer 200 covers at least a part of the surface of the film layer, and the optical microstructure 201 is disposed on at least a part of the surface of the adjustment layer 200 facing away from the chip body. By adjusting the size of the adjustment layer 200 and the position of the optical microstructure 201, the light-emitting range on the light-emitting side of the light-emitting diode chip is adjusted, so as to control the light-emitting angle of the light-emitting diode chip. Among them, the material of the adjustment layer 200 can be a transparent, high refractive index material to improve the light transmittance of the adjustment layer 200. Further, the material of the adjustment layer 200 can also be conductive. For example, the material of the adjustment layer 200 is indium tin oxide (Indium Tin Oxides, abbreviated as ITO). In this way, in an example where the adjustment layer 200 covers a part of the surface of the film layer, the adjustment layer 200 can also be used to weaken the edge effect of the light-emitting diode chip.

[0085] Exemplarily, referring to Figure 3 , the adjustment layer 200 can cover the entire surface of the corresponding side of the chip body 100, and the optical microstructure 201 is disposed on the entire surface of the corresponding side of the adjustment layer 200, so that the entire surface of the light-emitting side of the light-emitting diode chip emits light, and the light inside the light-emitting diode chip is converged and uniformly emitted, improving the light-emitting efficiency of the diode chip.

[0086] Further, the light-emitting diode chip may further include a first reflective layer 500. By providing the first reflective layer 500, it is controlled that light is uniformly emitted only from a specified area (such as the middle area) of the light-emitting diode chip. The first reflective layer 500 is disposed on the same layer as the adjustment layer 200, or the first reflective layer 500 is disposed on the side of the adjustment layer 200 facing away from the chip body, and the optical microstructure 201 is exposed, so that light is emitted from the area not covered by the first reflective layer 500.

[0087] As a possible example, referring to Figure 16 , the film layer 114 in the chip body 100 in contact with the adjustment layer 200 includes a central area and an edge area surrounding the central area. The first reflective layer 500 is located on the edge area of the film layer 114, and the adjustment layer 200 is located on the central area of the film layer 114.

[0088] Among them, the edge region of the chip body 100 corresponding to the film layer 114 can completely surround the central region of the film layer 114, that is, the edge region of the film layer 114 surrounds the central region of the film layer 114 for a full circle. The first reflective layer 500 is disposed on the edge region of the film layer 114, and the adjustment layer 200 is disposed on the central region of the film layer 114, so that the first reflective layer 500 surrounds the adjustment layer 200, reducing the coverage area of the adjustment layer 200 on the chip body 100. And the first reflective layer 500 is used to reflect light back to the chip body, and then through refraction and reflection in the chip body, the light is uniformly emitted from the middle region of the light-emitting diode chip. In this example, the coverage area of the optical microstructure 201 is not limited. For example, the optical microstructure 201 can be disposed on the entire surface of the adjustment layer 200.

[0089] As another possible example, refer to Figure 17 , the adjustment layer 200 includes a central region and an edge region surrounding the central region. The optical microstructure 201 is located in the central region of the adjustment layer 200, and the first reflective layer 500 is located on the edge region of the adjustment layer 200. Among them, the adjustment layer 200 can cover the entire surface of the corresponding side of the chip body 100, and the first reflective layer 500 is disposed on the side of the adjustment layer 200 away from the chip body 100, that is, the chip body 100, the adjustment layer 200, and the first reflective layer 500 are stacked in sequence.

[0090] The edge region of the adjustment layer 200 can completely surround the central region of the adjustment layer 200, that is, the edge region of the adjustment layer 200 surrounds the central region of the adjustment layer 200 for a full circle. The first reflective layer 500 is located on the edge region of the adjustment layer 200, and the optical microstructure 201 is located in the central region of the adjustment layer 200, so that the first reflective layer 500 surrounds the optical microstructure 201, and the first reflective layer 500 is used to reflect light back to the chip body, and then through refraction and reflection in the chip body, the light is uniformly emitted from the middle region of the light-emitting diode chip.

[0091] Refer to Figures 18 to 20, in some possible embodiments, the chip body 100 includes a buffer layer 102, an N-type electrode 103, a P-type electrode 105, an N-type semiconductor layer 104, a P-type semiconductor layer 107, a light-emitting layer 106, and a first insulating layer 110. The buffer layer 102 and the N-type semiconductor layer 104 are stacked, the light-emitting layer 106 is disposed on a side of the N-type semiconductor layer 104 away from the buffer layer 102, the P-type semiconductor layer 107 is disposed on a side of the light-emitting layer 106 away from the buffer layer 102, the N-type electrode 103 is in contact with the N-type semiconductor layer 104, the P-type electrode 105 is in contact with the P-type semiconductor layer 107, and the first insulating layer 110 is disposed on a side of the P-type semiconductor layer 107 away from the buffer layer 102. An adjustment layer 200 is disposed on a side of the buffer layer 102 away from the N-type semiconductor layer 104, or an adjustment layer 200 is disposed on a side of the first insulating layer 110 away from the P-type semiconductor 107.

[0092] Specifically, the N-type semiconductor layer 104 is disposed on a side surface of the buffer layer 102, the light-emitting layer 106 is disposed on a surface of the N-type semiconductor 104 away from the buffer layer 102, and the P-type semiconductor layer 107 is disposed on a surface of the light-emitting layer 106 away from the buffer layer 102, that is, the buffer layer 102, the N-type semiconductor layer 104, the light-emitting layer 106, and the P-type semiconductor layer 107 are stacked in sequence. The N-type semiconductor layer 104 is also in contact conduction with the N-type electrode 103, and the P-type semiconductor layer 107 is in contact conduction with the P-type electrode 105. In the energized state, an electric field is formed between the N-type electrode 103 and the P-type electrode 105. The light-emitting layer 106 is located in the electric field and is electrically conducted with the N-type electrode 103 through the N-type semiconductor layer 104 and is electrically conducted with the P-type electrode 105 through the P-type semiconductor layer 107. The first insulating layer 110 is disposed on a side of the P-type semiconductor 107 away from the buffer layer 102, and it may be in contact with the P-type semiconductor 107, or other film layers 114, such as a current spreading layer 108, etc., may be provided.

[0093] Among them, the material of the buffer layer 102 may be one or more of gallium nitride, aluminum gallium nitride, and aluminum indium gallium nitride, and the thickness of the buffer layer 102 may be 10 - 40 nanometers. The material of the N-type semiconductor layer 104 may be N-type doped gallium nitride, and the material of the P-type semiconductor layer 107 may be P-type doped gallium nitride. The material of the first insulating layer 110 may be silicon oxide or silicon nitride. The light-emitting layer 106 includes a light-emitting material of at least one wavelength to emit light of a specific wavelength.

[0094] Based on the above embodiments, the buffer layer 102 or the first insulating layer 110 is in contact with the adjustment layer 200. The material of the adjustment layer 200 includes indium gallium nitride, gallium arsenide, gallium phosphide, and silicon carbide. The refractive index of the adjustment layer 200 is greater than 2.4. Among them, the refractive index of indium gallium nitride is 2.48 - 2.8, the refractive index of gallium arsenide is 3.927, the refractive index of gallium phosphide is 3.5, and the refractive index of silicon carbide is 2.65. Of course, the material of the adjustment layer 200 can also be other materials that meet the refractive index requirements, and the embodiments of the present application are not limited thereto.

[0095] The adjustment layer 200 can be disposed on the buffer layer 102 or the first insulating layer 110. As Figure 18 shown, when the chip body 100 is a front-mounted structure, the adjustment layer 200 is in contact with the first insulating layer 110. As Figure 19 shown, when the chip body 100 is a flip-chip structure (thin-film flip-chip structure) without the substrate 101, the adjustment layer 200 is in contact with the buffer layer 102. The refractive index of the adjustment layer 200 is greater than the refractive index of the buffer layer 102 or the first insulating layer 110 in contact therewith. For example, the material of the adjustment layer 200 is indium gallium nitride, which is formed by an epitaxial process or vacuum coating, so that the transmittance of the light emitted by the chip body 100 through the adjustment layer 200 is relatively high.

[0096] The chip body 100 further includes a current spreading layer 108 and a second reflective layer 109. The current spreading layer 108 is disposed between the P-type semiconductor layer 107 and the first insulating layer 110 and is in contact with the P-type electrode 105. The second reflective layer 109 is disposed on the side of the buffer layer 102 away from the light-emitting layer 106, or the second reflective layer 109 is disposed on the side of the first insulating layer 110 away from the buffer layer 102. A second insulating layer 111 is further disposed on the side of the second reflective layer 109 away from the buffer layer 102. When the second reflective layer 109 is disposed on the side of the buffer layer 102 away from the light-emitting layer 106, the adjustment layer 200 is in contact with the first insulating layer 110. Among them, the current spreading layer 108 can improve the distribution ability of the P-type electrode 105, making the holes as evenly distributed as possible in the region where the P-type semiconductor layer 107 is located. The material of the current spreading layer 108 can be a transparent conductive material or silver, etc. The reflective layer is used to adjust the light-emitting direction of the light-emitting diode chip.

[0097] As an example, refer to Figure 18, a buffer layer 102 and an N-type semiconductor 104 are stacked in sequence, a light-emitting layer 106 is disposed on a side of the N-type semiconductor layer 104 away from the buffer layer 102, and a P-type semiconductor layer 107 is disposed on a side of the light-emitting layer 106 away from the buffer layer 102. A current spreading layer 108 is in contact with a surface of the P-type semiconductor layer 107 away from the buffer layer 102, an N-type electrode 103 is in contact with the N-type semiconductor layer 104, and a P-type electrode 105 is in contact with both the P-type semiconductor layer 107 and the current spreading layer 108. A first insulating layer 110 is disposed on a side of the current spreading layer 108 away from the buffer layer 102, and a second reflective layer 109 is disposed on a side of the buffer layer 102 away from the light-emitting layer 106.

[0098] In this way, a chip body 100 of a front-mounted structure is formed, and the light-emitting direction of the light-emitting diode chip is toward the direction away from the buffer layer 102, that is Figure 18 the upward arrow direction shown. An adjustment layer 200 is disposed on a side of the first insulating layer 110 away from the buffer layer 102 and is in contact with the first insulating layer 110.

[0099] As another example, refer to Figure 19 and Figure 20 , a buffer layer 102 and an N-type semiconductor 104 are stacked in sequence, a light-emitting layer 106 is disposed on a side of the N-type semiconductor layer 104 away from the buffer layer 102, and a P-type semiconductor layer 107 is disposed on a side of the light-emitting layer 106 away from the buffer layer 102. A current spreading layer 108 is in contact with a surface of the P-type semiconductor layer 107 away from the buffer layer 102, an N-type electrode 103 is in contact with the N-type semiconductor layer 104, and a P-type electrode 105 is in contact with both the P-type semiconductor layer 107 and the current spreading layer 108. A first insulating layer 110 is disposed on a side of the current spreading layer 108 away from the buffer layer 102, a second reflective layer 109 is disposed on a side of the first insulating layer 110 away from the buffer layer 102, and a second insulating layer 111 is further disposed on a side of the second reflective layer 109 away from the buffer layer 102.

[0100] In this way, a chip body 100 of a flip-chip structure is formed, and the light-emitting direction of the light-emitting diode chip is toward the direction of the buffer layer 102, that is Figure 19 and Figure 20 the downward arrow direction shown. An adjustment layer 200 is disposed on a side of the buffer layer 102 away from the light-emitting layer 106 and is in contact with the adjustment layer 200.

[0101] Among them, the chip body 100 further includes a substrate 101, such as Figure 18 and Figure 20As shown, the substrate 101 is disposed on the side of the buffer layer 102 away from the N-type semiconductor 104. When the adjustment layer 200 is located on the side of the buffer layer 102 away from the N-type semiconductor layer 104, the adjustment layer 200 is disposed on the side of the substrate 101 away from the N-type semiconductor 104. The material of the substrate 101 can be one of sapphire, gallium nitride, aluminum nitride, silicon, and silicon carbide.

[0102] As an example, as Figure 18 shown, in the chip body 100 of the front-mounted structure, the substrate 101 is disposed between the buffer layer 102 and the second reflective layer 109, and the adjustment layer 200 is in contact with the first insulating layer 110.

[0103] As another example, as Figure 20 shown, in the chip body 100 of the flip-chip structure with a substrate 101, the substrate 101 is disposed between the buffer layer 102 and the adjustment layer 200, that is, the substrate 101 is in contact with the adjustment layer 200. The material of the adjustment layer 200 includes indium tin oxide, titanium oxide, or tantalum oxide, and the refractive index of the adjustment layer 200 is greater than 1.78. Among them, the refractive index of indium tin oxide is 1.858. Titanium oxide includes titanium dioxide, tri-titanium pentoxide, and titanium sesquioxide, and their refractive indices are all 2.35. The refractive index of tantalum oxide is 2.1. Exemplarily, the material of the adjustment layer 200 is ITO and is formed by a magnetron sputtering process. In this way, the adjustment layer 200 has a relatively high transmittance for the light emitted by the chip body 100. Of course, the material of the adjustment layer 200 can also be other materials that meet the refractive index requirements, and the embodiments of the present application are not limited thereto.

[0104] Referring to Figure 21 , in some possible embodiments, the chip body 100 includes a bonding substrate 112, a bonding layer 113, an N-type semiconductor layer 104, a P-type semiconductor layer 107, an N-type electrode 103, a P-type electrode 105, a light-emitting layer 106, and a first insulating layer 110. The bonding substrate 112 and the bonding layer 113 are sequentially disposed on the P-type electrode 105. The P-type semiconductor layer 107 is disposed on the side of the bonding layer 113 away from the bonding substrate 112 and is in contact with the bonding layer 113. The light-emitting layer 106 is disposed on the side of the P-type semiconductor layer 107 away from the bonding substrate 112. The N-type semiconductor layer 104 is disposed on the side of the light-emitting layer 106 away from the bonding substrate 112. The first insulating layer 110 is disposed on the side of the N-type semiconductor 104 away from the light-emitting layer 106. The N-type electrode 103 contacts the side of the N-type semiconductor layer 104 away from the bonding substrate 112. The adjustment layer 200 is disposed on the side of the first insulating layer 110 away from the N-type semiconductor 104.

[0105] As Figure 21As shown, the bonding substrate 112 is disposed on the surface of the P-type electrode 105, and the bonding layer 113 is disposed on the surface of the bonding substrate 112 facing away from the P-type electrode 105. The P-type semiconductor layer 107 is disposed on the surface of the bonding layer 113 facing away from the bonding substrate 112, and the light-emitting layer 106 is disposed on the surface of the P-type semiconductor layer 107 facing away from the bonding substrate 112. The N-type semiconductor layer 104 is disposed on the surface of the light-emitting layer 106 facing away from the bonding substrate 112, and the first insulating layer 110 is disposed on the surface of the N-type semiconductor 104 facing away from the light-emitting layer 106. The adjustment layer 200 is disposed on the surface of the first insulating layer 110 facing away from the N-type semiconductor 104, that is, the adjustment layer 200 is in contact with the first insulating layer 110. The N-type electrode 103 penetrates through the adjustment layer 200 and the first insulating layer 110 to contact the surface of the N-type semiconductor layer 104 facing away from the bonding substrate 112.

[0106] Wherein, the material of the adjustment layer 200 includes indium gallium nitride, gallium arsenide, gallium phosphide, hydrogenated silicon, chromium oxide or chromium, and the refractive index of the adjustment layer 200 is greater than 2.4. The chip body 100 further includes a second reflective layer 109, and the second reflective layer 109 is disposed between the P-type semiconductor layer 107 and the bonding layer 113. The second reflective layer 109 may be located within the region enclosed by the P-type semiconductor layer 107 and the bonding layer 113.

[0107] Exemplarily, the second reflective layer 109 is embedded in the bonding layer 113, and the surface of the second reflective layer 109 facing away from the bonding substrate 112 is flush with the surface of the bonding layer 113 facing away from the bonding substrate 112. By providing the second reflective layer 109, the light-emitting direction of the light-emitting diode chip can be Figure 7 the upward direction indicated by the arrow in, forming a vertical-structured light-emitting diode chip.

[0108] Referring to Figure 22 and Figure 23 , an embodiment of the present application further provides a display module, including a driving backplane 300 and the above-mentioned light-emitting diode chip. The light-emitting diode chip is disposed on the driving backplane 300 and is electrically connected to the driving backplane 300. The driving backplane 300 may be a TFT (Thin Film Transistor) driving backplane 300 or a CMOS (Complementary Metal Oxide Semiconductor) driving backplane 300.

[0109] As an implementable embodiment, a plurality of light-emitting diode chips may be disposed on the driving backplane 300, and the plurality of light-emitting diode chips are arranged in an array on the driving backplane 300. The driving backplane 300 may provide driving current for the plurality of light-emitting diode chips to drive the plurality of light-emitting diode chips to emit light. As Figure 22As shown, light-emitting diode chips C1, C2, C3, and C4 are arranged on the driving backplane 300. In some examples, there may also be 5, 6, or more light-emitting diode chips, and the multiple light-emitting diode chips are arranged in an array. The number of light-emitting diode chips can be adjusted, and this embodiment does not limit this.

[0110] As another possible implementation, the driving backplane 300 includes a driving substrate 301 and multiple driving units 302. One driving unit 302 is electrically connected to multiple light-emitting diode chips correspondingly, and multiple driving units 302 are all electrically connected to the driving substrate 301. The driving unit 302 and the driving substrate 301 can also be TFT and CMOS. As Figure 23 shown, the light-emitting diode chip C1 and the light-emitting diode chip C2 are electrically connected to one driving unit 302, and the light-emitting diode chip C3 and the light-emitting diode chip C4 are connected to another driving unit 302. These two driving units 302 are both electrically connected to the driving substrate 301. The number of driving units 302 and the number of light-emitting diode chips connected to each driving unit 302 can both be adjusted, and this embodiment also does not limit this.

[0111] The embodiment of the present application also provides a full-color display screen, and this full-color display screen can be obtained by encapsulating the above-mentioned display module.

[0112] The embodiment of the present application also provides an electronic device, and this electronic device includes the above-mentioned full-color display screen. The electronic device can be a television, an electronic watch, an e-book, a desktop computer, a laptop computer, a tablet computer, a mobile phone, an AR device (Augmented Reality), or a VR device (Virtual Reality), etc. When the light-emitting diode chips of the electronic device include ultraviolet light pixels, the electronic device can also be an ultraviolet curing lamp or an ultraviolet detection lamp, etc.

[0113] The embodiment of the present application also provides an illumination device, including a circuit board and the above-mentioned light-emitting diode chips. The light-emitting diode chips are arranged on the circuit board and are electrically connected to the circuit board. The illumination device can be a lighting fixture, such as a street lamp, a decorative lamp, etc. The circuit board can be a printed circuit board (Printed Circuit Board, abbreviated as PCB) or a flexible printed circuit (Flexible Printed Circuit, abbreviated as FPC). Among them, multiple light-emitting diode chips can be arranged on the circuit board, and the multiple light-emitting diode chips are arranged in an array on the circuit board, and the circuit board drives the multiple light-emitting diode chips to emit light.

[0114] In the description of the embodiments of the present application, it should be understood that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, or an indirect connection through an intermediate medium, or the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances. The orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically and precisely defined.

[0115] The terms "first", "second", "third", "fourth", etc. (if any) in the specification, claims and drawings of the present application are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0116] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, and not to limit them; although the embodiments of the present application have been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A light emitting diode chip, characterized in that: It comprises a chip body and an adjustment layer arranged on the chip body, wherein the adjustment layer is located at the light emitting side of the light emitting diode chip, and the refractive index of the adjustment layer is greater than the refractive index of the film layer in the chip body that contacts the adjustment layer.

2. The light emitting diode chip according to claim 1, characterized in that: An optical microstructure is also formed on a surface of the adjustment layer away from the film layer, and the optical microstructure is used to increase the light extraction rate of the adjustment layer.

3. The light emitting diode chip according to claim 2, characterized in that: The optical microstructure is a concave-convex structure, and the concave-convex structure is formed by a surface roughening process.

4. The light emitting diode chip according to claim 2, characterized in that: The optical microstructure is a photonic crystal, which is formed by electron beam lithography, nanoimprinting or holographic exposure technology.

5. The light emitting diode chip according to claim 4, characterized in that: The end surface of the photonic crystal facing away from the film layer is also provided with a through hole.

6. The light emitting diode chip according to claim 4, characterized in that: The period of the photonic crystal is 1-5 μm.

7. The light emitting diode chip according to claim 4, characterized in that: The photonic crystal is a two-dimensional photonic crystal, and the plane shape of the two-dimensional photonic crystal is a circle, an ellipse, a triangle, a square, a rhombus, a parallelogram, a rectangle or a polygon; Alternatively, the photonic crystal is a three-dimensional photonic crystal, and the shape of the three-dimensional photonic crystal is a triangular prism, a cube, a face-centered cube, a hexagonal close-packed, or a cylinder.

8. The light emitting diode chip according to claim 2, characterized in that: The height of the optical microstructure is 30%-80% of the thickness of the adjustment layer, and the thickness of the adjustment layer is 0.1-10 μm.

9. The light emitting diode chip according to any one of claims 2 to 8, characterized in that: The adjustment layer covers at least a portion of the surface of the film layer, and the optical microstructure is arranged on at least a portion of the surface of the adjustment layer away from the chip body.

10. The light emitting diode chip according to claim 9, characterized in that: It also includes a first reflective layer, which is disposed on the same layer as the adjustment layer; Alternatively, the first reflective layer is disposed on a side of the adjustment layer away from the chip body, and exposes the optical microstructure.

11. The light emitting diode chip according to claim 10, characterized in that: The film layer in the chip body that contacts the adjustment layer includes a central area and an edge area surrounding the central area. The first reflective layer is located on the edge area of ​​the film layer, and the adjustment layer is located on the central area of ​​the film layer.

12. The light emitting diode chip according to claim 10, characterized in that: The adjustment layer includes a central area and an edge area surrounding the central area. The optical microstructure is located in the central area of ​​the adjustment layer, and the first reflective layer is located on the edge area of ​​the adjustment layer.

13. The light emitting diode chip according to claim 1, characterized in that: The chip body comprises a buffer layer, an N-type electrode, a P-type electrode, an N-type semiconductor layer, a P-type semiconductor layer, a light-emitting layer and a first insulating layer; The buffer layer and the N-type semiconductor layer are stacked, the light-emitting layer is arranged on a side of the N-type semiconductor layer away from the buffer layer, the P-type semiconductor layer is arranged on a side of the light-emitting layer away from the buffer layer, the N-type electrode is in contact with the N-type semiconductor layer, the P-type electrode is in contact with the P-type semiconductor layer, and the first insulating layer is arranged on a side of the P-type semiconductor layer away from the buffer layer; The adjustment layer is disposed on a side of the buffer layer away from the N-type semiconductor layer, or the adjustment layer is disposed on a side of the first insulating layer away from the P-type semiconductor layer.

14. The light emitting diode chip according to claim 1, characterized in that: The chip body includes a bonding substrate, a binding layer, an N-type semiconductor layer, a P-type semiconductor layer, an N-type electrode, a P-type electrode, a light-emitting layer and a first insulating layer; The bonding substrate and the binding layer are sequentially arranged on the P-type electrode, the P-type semiconductor layer is arranged on a side of the binding layer away from the bonding substrate and in contact with the binding layer, the light-emitting layer is arranged on a side of the P-type semiconductor layer away from the bonding substrate, the N-type semiconductor layer is arranged on a side of the light-emitting layer away from the bonding substrate, the first insulating layer is arranged on a side of the N-type semiconductor away from the light-emitting layer, and the N-type electrode contacts a side of the N-type semiconductor layer away from the bonding substrate; The adjustment layer is arranged on a side of the first insulating layer away from the N-type semiconductor.

15. The light emitting diode chip according to claim 13, characterized in that: The buffer layer or the first insulating layer is in contact with the adjustment layer. The material of the adjustment layer includes indium gallium nitride, gallium arsenide, gallium phosphide, and silicon carbide. The refractive index of the adjustment layer is greater than 2.

4.

16. The light emitting diode chip according to claim 15, characterized in that: The chip body further comprises a substrate, and the substrate is arranged on a side of the buffer layer away from the N-type semiconductor; When the adjustment layer is located on a side of the buffer layer away from the N-type semiconductor layer, the adjustment layer is disposed on a side of the substrate away from the N-type semiconductor layer.

17. The light emitting diode chip according to claim 16, characterized in that: The substrate contacts the adjustment layer, the material of the adjustment layer includes indium gallium nitride, gallium arsenide, gallium phosphide, silicon carbide, indium tin oxide, titanium oxide or tantalum oxide, and the refractive index of the adjustment layer is greater than 1.

78.

18. The light emitting diode chip according to claim 13, characterized in that: The chip body further includes a current spreading layer and a second reflective layer, wherein the current spreading layer is disposed between the P-type semiconductor layer and the first insulating layer and contacts the P-type electrode; The second reflective layer is arranged on a side of the buffer layer away from the light-emitting layer, or the second reflective layer is arranged on a side of the first insulating layer away from the buffer layer, and a second insulating layer is further arranged on a side of the second reflective layer away from the buffer layer; When the second reflective layer is disposed on a side of the buffer layer away from the light-emitting layer, the adjustment layer is in contact with the first insulating layer.

19. A display module, characterized in that: It comprises a driving backplane and a light-emitting diode chip as described in any one of claims 1 to 18, wherein the light-emitting diode chip is arranged on the driving backplane and is electrically connected to the driving backplane.

20. A lighting device, characterized in that: It comprises a circuit board and the light-emitting diode chip according to any one of claims 1 to 18, wherein the light-emitting diode chip is arranged on the circuit board and electrically connected to the circuit board.

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