Display device

Abstract

A display device includes: a substrate on which a plurality of light emitting elements are disposed; a transistor on the substrate; a plurality of signal lines on the substrate; a plurality of connecting lines under the substrate; and a plurality of upper pads on the substrate and connected to the plurality of signal lines, in which the plurality of upper pads are disposed to overlap with at least one of the plurality of signal lines and the plurality of transistors. Accordingly, a high-resolution display device with zero bezel may be implemented by reducing a bezel area of the display device.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more particularly, to a display device having a reduced bezel area. Background Art

[0002] As display devices for displays of computers, televisions, mobile phones, etc., there are organic light-emitting displays (OLEDs) configured to emit light autonomously and liquid crystal displays (LCDs) that require a separate light source.

[0003] The application range of display devices is diverse from displays of computers and televisions to personal mobile devices, and research is being conducted on display devices having a wide display area and having a reduced volume and weight.

[0004] In addition, recently, display devices including (organic) light-emitting diodes (LEDs) such as micro LEDs have received attention as next-generation display devices. Since LEDs are made of inorganic materials rather than organic materials, LEDs are more reliable and have a longer lifespan than liquid crystal display devices or organic light-emitting display devices.

[0005] In addition, LEDs can be turned on or off quickly, have excellent luminous efficiency, high impact resistance, and high stability, and display high-brightness images. Summary of the Invention

[0006] The present disclosure provides a display device having a reduced bezel area.

[0007] More specifically, the present disclosure provides a display device having a reduced bezel area that can achieve high resolution.

[0008] The present disclosure also provides a display device in which the problem of disconnection between a plurality of pads is reduced.

[0009] In addition, the present disclosure provides a display device that solves the problem that the material constituting the side line is not properly applied to the side surface of the substrate of the display device.

[0010] The present disclosure is not limited to the above features, and other features not mentioned above can be clearly understood by those skilled in the art from the following description.

[0011] According to one aspect of the present disclosure, a display device includes: a substrate on which a plurality of light-emitting elements are provided; transistors on the substrate; a plurality of signal lines on the substrate; a plurality of connection lines under the substrate; and a plurality of upper pads located on the substrate and connected to the plurality of signal lines, wherein the plurality of upper pads are provided to overlap at least one of the plurality of signal lines and the plurality of transistors. Accordingly, a high-resolution display device with zero bezel (or minimized bezel) can be achieved by reducing the bezel area of the display device.

[0012] Other details of the embodiments are included in the detailed description and the drawings.

[0013] According to the present disclosure, the pad can be arranged to overlap at least one of a plurality of signal lines and a plurality of transistors, thereby reducing the border area of the display device.

[0014] According to the present disclosure, a high-resolution display device can be achieved by reducing the border area.

[0015] According to the present disclosure, the problem that a plurality of pads are disconnected due to physical impact can be solved.

[0016] According to the present disclosure, the side lines provided on the side surface of the substrate can be uniformly arranged.

[0017] The effects according to the present disclosure are not limited to those illustrated above, and more different effects are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the drawings, in which:

[0019] Figure 1 is a schematic top view (or plan view) of a display device according to a first embodiment;

[0020] Figure 2A is a schematic top view of the display device in a state before a grinding process is performed on the display device according to the first embodiment;

[0021] Figure 2B is along Figure 2A a line II-II' of the display device, a schematic cross-sectional view;

[0022] Figure 3A is a schematic top view of the display device in a state after the grinding process is performed on the display device according to the first embodiment;

[0023] Figure 3B is along Figure 3A a line III-III' of the display device, a schematic cross-sectional view;

[0024] Figure 4A is a schematic cross-sectional view of the display device in a state before the grinding process is performed on the display device according to a second embodiment;

[0025] Figure 4B is a schematic cross-sectional view of the display device in a state after the grinding process is performed on the display device according to the second embodiment; and

[0026] Figure 5 It is a schematic cross-sectional view of a display device according to the third embodiment. Detailed implementation manners

[0027] Advantages and features of the present disclosure and methods for achieving these advantages and features will become clear by referring to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed herein, but will be implemented in various forms. The embodiments are provided by way of example only so that those skilled in the art can fully understand the disclosure content of the present disclosure and the scope of the present disclosure.

[0028] The shapes, dimensions, ratios, angles, quantities, etc. shown in the drawings for describing the embodiments are merely examples, and the present disclosure is not limited thereto. Throughout the disclosure, like reference numerals generally denote like elements. In addition, in the following description of the present disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including", "having", and "consisting of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". Any reference to the singular may include the plural unless otherwise explicitly stated.

[0029] Even if not explicitly stated, components are interpreted to include a general error range.

[0030] When describing the positional relationship between two parts using terms such as "on", "above", "below", "next to", etc., one or more parts may be located between these two parts, unless these terms are used together with the terms "immediately" or "directly".

[0031] When an element or layer is provided "on" another element or layer, another layer or another element may be directly interposed on the other element or interposed between them.

[0032] Although terms such as "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, in the technical concept of the present disclosure, the first component to be mentioned below may be the second component.

[0033] Throughout the disclosure, like reference numerals generally denote like elements.

[0034] The dimensions and thicknesses of each component shown in the drawings are shown for convenience of description, and the present disclosure is not limited to the dimensions and thicknesses of the components shown.

[0035] Features of various aspects of the present disclosure can be combined or combined in part or in whole with each other, and can be technically related and operated in various ways, and each aspect can be executed independently or related to each other.

[0036] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings.

[0037] Figure 1 is a schematic top view (or top view) of a display device according to a first embodiment. For ease of description, Figure 1 only the substrate 110, data lines DL, scan lines SL, a plurality of sub-pixels SP, and the upper pad PAD1 of the display device 100 are shown. In addition, reference will be made to Figure 2A to describe Figure 1 the area X shown in

[0038] Referring to Figure 1 , it can be seen that the substrate 110 can be a substrate, for example, an insulating substrate that supports components disposed on the upper part of the display device 100. For example, the substrate 110 can be made of glass, resin, etc. In addition, the substrate 110 can include polymers or plastics. In an embodiment, the substrate 110 can be made of a flexible plastic material.

[0039] The substrate 110 can have a display area AA and a non-display area NA configured to surround the display area AA.

[0040] The display area AA is an area where the display device 100 displays an image. The display area AA can include a plurality of sub-pixels SP that make up a plurality of pixels and a circuit configured to operate the sub-pixels SP.

[0041] The sub-pixel SP is the smallest unit that makes up the display area AA. A light-emitting element, a thin-film transistor for operating the light-emitting element, etc. can be provided in each of the sub-pixels SP. The sub-pixels SP will be described in more detail with reference to Figures 2A to 3B

[0042] A plurality of signal lines for transmitting various types of signals to the plurality of sub-pixels SP are provided in the display area AA. For example, the plurality of signal lines can include a plurality of data lines DL for supplying data voltages to the plurality of sub-pixels SP and a plurality of scan lines SL for supplying scan voltages to the plurality of sub-pixels SP. The plurality of signal lines will be described in more detail with reference to Figures 2A to 3B

[0043] The non-display area NA can be defined as an area where an image is not displayed, i.e., an area surrounding the display area AA. The non-display area NA may include connection lines and pad electrodes for transmitting signals to the sub-pixels SP in the display area AA. Alternatively, or additionally, the non-display area NA may include driving ICs such as a gate driver IC and a data driver IC.

[0044] A plurality of upper pads PAD1 for transmitting various types of signals to the plurality of sub-pixels SP on the substrate 110 are provided in the non-display area NA. The plurality of upper pads PAD1 are arranged to overlap with a plurality of signal lines described below. In addition, the plurality of upper pads PAD1 can be electrically connected to side lines and a plurality of signal lines in the display area AA, and provide signals received from a plurality of flexible films and printed circuit boards provided on the rear surface of the substrate 110 to the plurality of sub-pixels SP. A more detailed description of the plurality of upper pads PAD1 will be made with reference to Figures 2A to 3B the plurality of upper pads PAD1 will be made in more detail.

[0045] The embodiments are not limited to upper pads overlapping with signal lines. That is, the upper pads may not overlap with the signal lines. The signal lines and the upper pads may be alternately arranged (for example, the signal lines are arranged between the upper pads). In such an arrangement, the upper pads can still be connected to the signal lines via the side lines, for example, if the side lines extend in width to cover the ends of the upper pads as well as the ends of the signal lines.

[0046] Meanwhile, in the present disclosure, a configuration in which the display area AA and the non-display area NA are defined on the front surface of the display device 100 is described. However, the present disclosure is not limited thereto. The non-display area NA may not be defined on the front surface of the display device 100. In the case where a plurality of display devices 100 according to the first embodiment are connected to implement a tiled display with a large screen, the interval between the outermost sub-pixels SP of one display device 100 and the outermost sub-pixels SP of another display device 100 adjacent to one display device 100 can be made equal to the interval between the plurality of sub-pixels SP in one display device 100, so that a zero bezel with substantially no bezel area can be achieved. Therefore, only the display area AA where an image is displayed can be defined on the front surface of the display device 100. However, the present disclosure is not limited thereto.

[0047] Figure 2A is a schematic top view of the display device in a state before the grinding process of the display device according to the first embodiment. Figure 2B is along Figure 2A a schematic cross-sectional view of the display device taken along the line II-II′. Figure 2A is Figure 1 an enlarged top view of the area X shown in Figure 2AOnly multiple upper pads PAD1, multiple signal lines, multiple light-emitting elements LED, and multiple pixels P on the substrate 110 are shown.

[0048] Referring to Figure 2A , multiple display modules include multiple signal lines and multiple pixels P.

[0049] Multiple pixels P may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be sub-pixels that emit light of different colors. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be a red sub-pixel configured to emit red light, a green sub-pixel configured to emit green light, and a blue sub-pixel configured to emit blue light, respectively. However, the present disclosure is not limited thereto. For example, multiple pixels P may further include a white sub-pixel configured to emit white light.

[0050] Each of the multiple sub-pixels SP1, SP2, and SP3 may include a light-emitting region and a circuit region. The region where the light emitted from the light-emitting element LED can propagate to the outside may be defined as the light-emitting region. The light-emitting region is a region that can independently emit light of a single color. The light-emitting element LED may be disposed in the light-emitting region. For example, a first light-emitting element LED1 configured to emit red light may be disposed on the first sub-pixel SP1. A second light-emitting element LED2 configured to emit green light may be disposed on the second sub-pixel SP2. A third light-emitting element LED3 configured to emit blue light may be disposed on the third sub-pixel SP3.

[0051] The circuit region is the remaining region other than the light-emitting region. A drive circuit for operating the multiple light-emitting elements LED may be disposed in the circuit region. For example, a drive circuit including a transistor TR and a storage capacitor SC may be disposed in the circuit region.

[0052] Multiple signal lines are disposed on the substrate 110. The side surface of each of the multiple signal lines may be disposed in Figure 2A and Figure 2B the plane indicated by the first line L1 in, and this plane is the end position of the grinding process of the substrate 110.

[0053] Multiple signal lines may be lines for transmitting various signals to the drive circuit, and include a scan line SL, a data line DL, a high-potential voltage line VDDL, a reference line RL, a low-potential voltage line VSSL, etc. However, the present disclosure is not limited thereto.

[0054] Each data line DL is a line for transmitting a data signal to each of the sub-pixels SP1, SP2, or SP3. A plurality of data lines DL may be provided to extend in a column direction among the plurality of sub-pixels SP1, SP2, and SP3, and include a first data line DL1, a second data line DL2, and a third data line DL3. The first data line DL1, the second data line DL2, and the third data line DL3 may transmit data voltages to the sub-pixels SP1, SP2, and SP3, respectively. For example, the first data line DL1 may transmit a data voltage to the first sub-pixel SP1, the second data line DL2 may transmit a data voltage to the second sub-pixel SP2, and the third data line DL3 may transmit a data voltage to the third sub-pixel SP3.

[0055] A plurality of high potential voltage lines VDDL are lines for transmitting a high potential power supply voltage to the plurality of sub-pixels SP1, SP2, and SP3. The plurality of high potential voltage lines VDDL may extend in the column direction.

[0056] The plurality of sub-pixels SP1, SP2, and SP3 may share a single high potential voltage line VDDL. For example, a single high potential voltage line VDDL may be provided between the first sub-pixel SP1 and the third sub-pixel SP3 and supply a high potential power supply voltage to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0057] A plurality of reference lines RL include lines that extend in the column direction and transmit a reference voltage to the plurality of sub-pixels SP1, SP2, SP3. The plurality of sub-pixels SP1, SP2, and SP3 may share a single reference line RL. For example, a single reference line RL may be provided between the third sub-pixel SP3 and the first sub-pixel SP1 and transmit a reference voltage to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0058] The low potential voltage line VSSL is a line for applying a low potential power supply voltage to the plurality of sub-pixels SP1, SP2, and SP3. The low potential voltage line VSSL may extend in the column direction. The sub-pixels SP1, SP2, and SP3 may share a single low potential voltage line VSSL. For example, a single low potential voltage line VSSL may be provided between the first sub-pixel SP1 and the third sub-pixel SP3 and supply a low potential power supply voltage to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0059] Hereinafter, with reference to Figure 2B various components of the display device 100 will be described in more detail.

[0060] With reference to Figure 2B , a substrate 110 for supporting various components provided on the display device 100 may be provided on the display device 100.

[0061] The substrate 100 may include a first substrate 101 and a second substrate 102.

[0062] The first substrate 101 may be a substrate, for example, an insulating substrate that supports components disposed on the upper portion of the display device 100. For example, the first substrate 101 may be made of glass, resin, etc. Alternatively, or additionally, the first substrate 101 may include a polymer or plastic.

[0063] The second substrate 102 is disposed below the first substrate 101. The second substrate 102 may be a substrate, for example, an insulating substrate that supports components disposed on the lower portion of the display device 100. For example, the second substrate 102 may be made of glass, resin, etc. Alternatively, or additionally, the second substrate 102 may include a polymer or plastic. The second substrate 102 may be made of the same material as the first substrate 101.

[0064] A first adhesive layer 121 is disposed between the first substrate 101 and the second substrate 102. The first adhesive layer 121 may be made of a material that can be cured in various curing manners to bond the first substrate 101 and the second substrate 102. The first adhesive layer 121 may be disposed on a partial area or the entire area between the first substrate 101 and the second substrate 102.

[0065] Referring Figure 2B , a light blocking layer LS may be disposed on the first substrate 101.

[0066] The light blocking layer LS may be disposed to overlap with the first active layer ACT of the transistor TR and block light from entering the first active layer ACT. If light is emitted to the first active layer ACT, a leakage current is generated, which may reduce the reliability of the transistor TR as a driving transistor. In this case, when the light blocking layer LS made of an opaque conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), and their alloys is disposed to overlap with the first active layer ACT, the light blocking layer LS can suppress light from entering the first active layer ACT from the lower portion of the substrate 110, thereby improving the reliability of the transistor TR.

[0067] A buffer layer 111 is disposed on the first substrate 101 and the light blocking layer LS. The buffer layer 111 may reduce the penetration of moisture or impurities through the first substrate 101. For example, the buffer layer 111 may be configured as a single layer or multiple layers made of silicon oxide (SiO x ) or silicon nitride (SiN x ). However, the present disclosure is not limited thereto. In addition, depending on the type of the first substrate 101 or the type of the transistor TR, the buffer layer 111 may not be included. However, the present disclosure is not limited thereto.

[0068] The transistor TR is disposed on the buffer layer 111 of each of the plurality of sub-pixels SP1, SP2, and SP3.

[0069] The transistor TR includes a first active layer ACT, a gate GE, a source SE, and a drain DE.

[0070] The first active layer ACT is disposed on the buffer layer 111. The first active layer ACT may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon. However, the present disclosure is not limited thereto. For example, in the case where the first active layer ACT is made of an oxide semiconductor, the first active layer ACT may include a channel region, a source region, and a drain region, and the source region and the drain region may be regions having conductivity. However, the present disclosure is not limited thereto.

[0071] A gate insulating layer 112 is disposed on the first active layer ACT. The gate insulating layer 112 may be a layer for insulating the gate GE from the first active layer ACT and is made of an insulating material. For example, the gate insulating layer 112 may be configured as a single layer or a multi-layer made of silicon oxide (SiO x ) or silicon nitride (SiN x ). However, the present disclosure is not limited thereto.

[0072] The gate insulating layer 112 may be formed in the same pattern as the gate GE. However, the present disclosure is not limited thereto. The gate insulating layer 112 may be formed on the front surface (or upper surface) of the first substrate 101.

[0073] The gate GE is disposed on the gate insulating layer 112. The gate GE may be disposed to overlap the gate insulating layer 112. The gate GE may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.

[0074] An interlayer insulating layer 113 is disposed on the gate GE and the buffer layer 111. The interlayer insulating layer 113 may be a layer for insulating the gate GE, the source SE, and the drain DE. The interlayer insulating layer 113 may be made of an inorganic material like the gate insulating layer 112. For example, the interlayer insulating layer 113 may be configured as a single layer or a multi-layer made of silicon oxide (SiO x ) or silicon nitride (SiN x ). However, the present disclosure is not limited thereto.

[0075] The source SE and the drain DE are disposed on the interlayer insulating layer 113 and spaced apart from each other. The source SE and the drain DE can be electrically connected to the first active layer ACT through vias formed in the interlayer insulating layer 113. The source SE and the drain DE can be disposed on the same layer and made of the same conductive material as the gate GE. However, the present disclosure is not limited thereto. For example, the source SE and the drain DE can each be made of copper (Cu), aluminum (A1), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto.

[0076] The drain DE is electrically connected to the low potential voltage line VSSL. For example, the drain DE of each of the second sub-pixel SP2 and the third sub-pixel SP3 can be electrically connected to the low potential voltage line VSSL disposed on the left side of the first sub-pixel SP1.

[0077] The source SE can be electrically connected to the light blocking layer LS through vias formed in the interlayer insulating layer 113 and the buffer layer 111. If the light blocking layer LS floats, the threshold voltage of the transistor TR changes, which may affect the operation of the display device 100. Therefore, the light blocking layer LS can be electrically connected to the source SE so that a voltage can be applied to the light blocking layer LS and the operation of the transistor TR can be unaffected. However, the present disclosure is not limited thereto. Both the first active layer ACT and the source SE can be in direct contact with the light blocking layer LS. A plurality of signal lines can be disposed on the interlayer insulating layer 113. For example, the plurality of signal lines can include a plurality of scan lines SL, a plurality of high potential voltage lines VDDL, a plurality of data lines DL, and a plurality of reference lines RL. However, the present disclosure is not limited thereto. The plurality of signal lines can be disposed on the same layer on the first substrate 101 and made of the same conductive material. The plurality of scan lines SL, the plurality of high potential voltage lines VDDL, the plurality of data lines DL, and the plurality of reference lines RL can each be made of a conductive material such as copper (Cu), aluminum (A1), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present disclosure is not limited thereto. The plurality of signal lines can be disposed on different layers on the first substrate 101 and made of different conductive materials. In addition, the plurality of signal lines can be made of the same material as the drain DE and the source SE. At the same time, the plurality of signal lines can be disposed on different layers on the first substrate 101 and made of different conductive materials. In this case, the plurality of signal lines can all be disposed on the same layer and made of the same material as any one of the components constituting the transistor TR.

[0078] The storage capacitor SC is provided in the circuit region of each of the plurality of sub-pixels SP1, SP2, and SP3. The storage capacitor SC can store the voltage between the gate GE and the source SE of the transistor TR so that the light-emitting element LED can continuously maintain the same state during a single frame. The storage capacitor SC includes a first capacitor electrode SC1 and a second capacitor electrode SC2.

[0079] The first capacitor electrode SC1 is provided between the first substrate 101 and the buffer layer 111 in each of the plurality of sub-pixels SP. The first capacitor electrode SC1 can be provided to be closest to the first substrate 101 among the conductive components provided on the first substrate 101. The first capacitor electrode SC1 can be integrated with the light-blocking layer LS and can be electrically connected to the source SE through the light-blocking layer LS.

[0080] The buffer layer 111 and the gate insulating layer 112 are provided on the first capacitor electrode SC1, and the second capacitor electrode SC2 is provided on the buffer layer 111 and the gate insulating layer 112. The second capacitor electrode SC2 can be provided to overlap with the first capacitor electrode SC1. The second capacitor electrode SC2 can be made of the same material as the gate GE. For example, the gate GE and the second capacitor electrode SC2 can be formed by forming a semiconductor material on the gate insulating layer 112 and patterning a part of the semiconductor material.

[0081] The protective layer 114 is provided on the transistor TR and the storage capacitor SC. The passivation layer 114 is an insulating layer for protecting the components provided below the passivation layer 114. For example, the passivation layer 114 can be configured as a single layer or a multi-layer made of silicon oxide (SiO x ) or silicon nitride (SiO x ). However, the present disclosure is not limited thereto. In addition, according to some embodiments, the passivation layer 114 may not be included.

[0082] A plurality of reflective layers 117 are provided on the passivation layer 114. The reflective layer 117 can be provided to overlap with the light-emitting region including the light-emitting element LED. The reflective layer 117 reflects the light entering from the light-emitting element LED upward to the light-emitting element LED, thereby improving the light-emitting efficiency of the display device 100. However, in the case where the display device 100 is a backlight type display device, the reflective layer 117 may not be included or the reflective layer 117 is provided above the light-emitting element LED.

[0083] A second adhesive layer 118 covering the reflective layer 117 is provided on the reflective layer 117. The second adhesive layer 118 is an adhesive layer for bonding the light-emitting element LED to the reflective layer 117. The second adhesive layer 118 can insulate the reflective layer 117, both made of a metal material, from the light-emitting element LED. The second adhesive layer 118 can be made of a thermosetting or photocuring material. However, the present disclosure is not limited thereto. Figure 2B It is shown that the second adhesive layer 118 is provided to cover only the reflective layer 117. However, the arrangement position of the second adhesive layer 118 is not limited thereto.

[0084] A plurality of light-emitting elements LED are provided on the second adhesive layer 118. The plurality of light-emitting elements LED are arranged to overlap with the plurality of reflective layers 117. Each of the plurality of light-emitting elements LED can be a micro-LED including an inorganic active layer. Each of the plurality of light-emitting elements LED includes an n-type layer, an active layer, a p-type layer, an n electrode, and a p electrode. Hereinafter, a configuration in which a light-emitting element LED having a lateral structure is used as the light-emitting element LED will be described. However, the structure of the light-emitting element LED is not limited thereto. The n electrode or the p electrode can be provided on the top of the light-emitting element LED. The n electrode and the p electrode can be arranged to be spaced apart in the horizontal direction.

[0085] Specifically, the n-type layer NL of the light-emitting element LED is provided on the second adhesive layer 118. The n-type layer NL can be formed by implanting n-type impurities into gallium nitride having excellent crystallinity. A second active layer EL is provided on the n-type layer NL. The second active layer EL can be a light-emitting layer provided in the light-emitting element LED and configured to emit light. The second active layer EL can be made of a nitride semiconductor, such as indium gallium nitride. A p-type layer PL is provided on the second active layer EL. The p-type layer PL can be formed by implanting p-type impurities into gallium nitride. However, the constituent materials of the n-type layer NL, the second active layer EL, and the p-type layer PL are not limited thereto.

[0086] The p - electrode PE is disposed on the p - type layer PL of the light - emitting element LED. In addition, the n - electrode NE is disposed on the n - type layer NL of the light - emitting element LED. The n - electrode NE is arranged to be spaced apart from the p - electrode PE. Specifically, the light - emitting element LED can be manufactured by sequentially stacking the n - type layer NL, the active layer EL, and the p - type layer PL, etching predetermined portions of the active layer EL and the p - type layer PL, and forming the n - electrode NE and the p - electrode PE. In this case, the predetermined portion is a space for separating the n - electrode NE and the p - electrode PE. The predetermined portion can be etched such that a part of the n - type layer NL is exposed. In other words, the surface of the light - emitting element LED on which the n - electrode NE and the p - electrode PE are to be disposed can be a surface with different heights rather than a planarized surface. Thus, the p - electrode PE is disposed on the p - type layer PL, and the n - electrode NE is disposed on the n - type layer NL. The p - electrode PE and the n - electrode NE are arranged to be spaced apart from each other at different heights. Therefore, the n - electrode NE can be arranged closer to the second adhesive layer 118 than the p - electrode PE. In addition, the n - electrode NE and the p - electrode PE can be made of a conductive material such as a transparent conductive oxide. In addition, the n - electrode NE and the p - electrode PE can be made of the same material. However, the present disclosure is not limited thereto.

[0087] The first planarization layer 115a is disposed on the transistor TR. The first planarization layer 115a can be disposed in a region other than the region where the light - emitting element LED is disposed. The first planarization layer 115a planarizes the upper surface of the transistor TR.

[0088] The first planarization layer 115a can be configured as a single layer or multiple layers made of an organic material such as polyimide or photo - acrylic. However, the present disclosure is not limited thereto.

[0089] The second planarization layer 115b is disposed on the first planarization layer 115a and the light - emitting element LED. The second planarization layer 115b is a layer for planarizing the upper surface of the transistor TR and the upper surface of the light - emitting element LED. Figure 2B The setting of the first planarization layer 115a and the second planarization layer 115b is shown. However, the present disclosure is not limited thereto. A single planarization layer can be formed. In the case of setting a single planarization layer, an excessive increase in the amount of time required for the process can be suppressed. In addition, more than two planarization layers can be provided. The second planarization layer 115b can be made of the same material as the first planarization layer 115a. However, the present disclosure is not limited thereto.

[0090] The first electrode CE1 is an electrode that electrically connects the transistor TR and the light-emitting element LED. The first electrode CE1 is connected to the n electrode NE of the light-emitting element LED through a through hole formed in the second planarization layer 115b. In addition, the first electrode CE1 is connected to the source electrode SE of the transistor TR through through holes formed in the planarization layers 115a and 115b and the passivation layer 114. However, the present disclosure is not limited thereto. Depending on the type of the transistor TR, the first electrode CE1 may be connected to the drain electrode DE of the transistor TR.

[0091] The second electrode CE2 is an electrode that electrically connects the light-emitting element LED and the high-potential voltage line VDDL. Specifically, the second electrode CE2 is connected to the high-potential voltage line VDDL through through holes formed in the planarization layers 115a and 115b and the passivation layer 114. The second electrode CE2 is connected to the p electrode PE of the light-emitting element LED through a through hole formed in the second planarization layer 115b. Thus, the high-potential voltage line VDDL is electrically connected to the p electrode PE of the light-emitting element LED.

[0092] The first electrode CE1 and the second electrode CE2 are spaced apart from each other. Specifically, the first electrode CE1 may be surrounded by the first planarization layer 115a, the second planarization layer 115b, and the third planarization layer 115c. The second electrode CE2 may be surrounded by the first planarization layer 115a, the second planarization layer 115b, and the third planarization layer 115c. The second planarization layer 115b and the third planarization layer 115c may be in contact with each other in the region between the first electrode CE1 and the second electrode CE2. The third planarization layer 115c may be disposed between the first electrode CE1 and the second electrode CE2. Thus, the first electrode CE1 and the second electrode CE2 are electrically insulated from each other.

[0093] The bank 119 is disposed on the second planarization layer 115b, the first electrode CE1, and the second electrode CE2. The bank 119 is an insulating layer that defines a light-emitting region. The bank 119 may be made of an organic insulating material. The bank 119 may be made of the same material as the planarization layers 115a and 115b. In addition, the bank 119 may be configured to include a light-absorbing material, such as a black material, to suppress color mixing caused when light emitted from the light-emitting element LED is transmitted to adjacent sub-pixels SP1, SP2, and SP3. The bank 119 may have an inclination. Specifically, the side surface of the bank 119 may be formed as an inclined surface having a specific inclination. Additionally, the bank 119 may overlap with the upper pad PAD1 or the lower pad PAD2. The bank 119 may cover the region where the upper pad PAD1 and the lower pad PAD2 are disposed.

[0094] The third planarization layer 115c is disposed on the bank portion 119. The third planarization layer 115c can planarize the upper portion of the first substrate 101 and protect the components disposed below the third planarization layer 115c. The third planarization layer 115c can be configured as a single layer or multiple layers made of an organic material such as polyimide or photoacrylic. However, the present disclosure is not limited thereto.

[0095] Referring to Figure 2B , a plurality of signal lines are disposed on the first substrate 101 and are disposed at one end of the first substrate 101. The plurality of signal lines can include a plurality of scan lines SL, a plurality of high potential voltage lines VDDL, a plurality of low potential voltage lines VSSL, a plurality of data lines DL, and a plurality of reference lines RL. For ease of description, Figure 2B the second data line DL2 among the plurality of signal lines is shown.

[0096] The second data line DL2 can include a first layer DL2-1, a second layer DL2-2, and a third layer DL2-3. The second data line DL2 can have a jumper structure passing through the first layer DL2-1, the second layer DL2-2, and the third layer DL2-3. In other words, at least one of the first layer DL2-1, the second layer DL2-2, and the third layer DL2-3 can be used as a jumper. The first layer DL2-1, the second layer DL2-2, the third layer DL2-3, and the upper pad PAD1 can be electrically connected to each other in parallel through holes in the insulating layer disposed therebetween. Therefore, the resistance of the second data line DL2 can be reduced.

[0097] More generally, each signal line includes at least two overlapping signal line layers connected in parallel to each other. An insulating layer can be disposed between each adjacent pair of the at least two overlapping signal line layers. The insulating layer can include through holes for accommodating corresponding connection portions connecting adjacent pairs of signal line layers. The signal line can be electrically connected to the upper pad. Optionally, wherein the signal lines are electrically connected to the upper pad in parallel. An insulating layer can be disposed between the upper pad and the signal line. The insulating layer includes through holes for accommodating connection portions connecting the signal line and the upper pad.

[0098] The first layer DL2-1 can be disposed on the same layer as the light blocking layer LS and made of the same conductive material as the light blocking layer LS. However, the present disclosure is not limited thereto.

[0099] The buffer layer 111 and the second layer DL2-2 can be disposed on the first layer DL2-1.

[0100] The second layer DL2-2 can be disposed on the same layer as the gate GE and made of the same conductive material as the gate GE. However, the present disclosure is not limited thereto.

[0101] The outer end portion of the second layer DL2-2 can be disposed in the same plane as the outer end portion of the first layer DL2-1 (e.g.,Figure 2A and Figure 2B on the plane indicated by the line L1 in Figure 2B . In addition, the second layer DL2-2 may be arranged to overlap with the first layer DL2-1 provided on the lower part (i.e., the lower side) of the second layer DL2-2. Figure 2B shows that the second layer DL2-2 is arranged to overlap with a part of the first layer DL2-1. However, the present disclosure is not limited thereto. For example, the second layer DL2-2 may be arranged to completely overlap with the first layer DL2-1. The second layer DL2-2 may be arranged to overlap with the front surface (or upper surface) of the first layer DL2-1.

[0102] The second layer DL2-2 can be electrically connected to the first layer DL2-1 through a contact hole formed in the buffer layer 111. Therefore, the second layer DL2-2 can achieve a structure connected in parallel with the first layer DL2-1, thereby reducing the resistance of the second data line DL2.

[0103] The interlayer insulating layer 113 and the third layer DL2-3 are provided on the second layer DL2-2. The third layer DL2-3 may be arranged to overlap with a plurality of upper pads PAD1 provided on the upper part (i.e., the upper side) of the third layer DL2-3.

[0104] The third layer DL2-3 may be provided on the same layer as the source electrode SE and the drain electrode DE and made of the same conductive material as the source electrode SE and the drain electrode DE. However, the present disclosure is not limited thereto.

[0105] The outer end portion of the third layer DL2-3 may be provided on the same plane as the end portion of the first layer DL2-1 and the end portion of the second layer DL2-2 (for example, Figure 2A and Figure 2B the plane indicated by the line L1 in Figure 2B ). In addition, the third layer DL2-3 may be arranged to overlap with the second layer DL2-2 and the first layer DL2-1. Figure 2B shows that the inner end portion (i.e., the end portion farthest from the line L1) of the third layer DL2-3 is provided between the inner end portion of the second layer DL2-2 and the inner end portion of the first layer DL2-1. However, the position of the inner end portion of the third layer DL2-3 is not limited thereto.

[0106] The third layer DL2-3 can be electrically connected to the second layer DL2-2 through a contact hole formed in the interlayer insulating layer 113. Therefore, the second layer DL2-2 and the third layer DL2-3 can be implemented as a structure connected in parallel with each other, thereby reducing the resistance of the second data line DL2.

[0107] Meanwhile, the electrostatic discharge circuit can be disposed on the substrate 110 and overlap with a plurality of upper pads PAD1. The electrostatic discharge circuit is disposed in the region between the plurality of upper pads PAD1 and the display area AA. The electrostatic discharge circuit can be electrically connected to the second data line DL2. When static electricity is introduced through the second data line DL2, the electrostatic discharge circuit can be turned on and discharge the static electricity to the ground wire, thereby blocking (reducing or eliminating) the static electricity. In other words, the electrostatic discharge circuit can be selectively electrically connected to the ground wire and electrically connected to the signal line (e.g., the second data line DL2), and vice versa. Therefore, the electrostatic discharge circuit can suppress damage to the display device 100 by blocking or releasing the overcurrent caused by static electricity. The electrostatic discharge circuit can be electrically connected to the signal line via the side line 140.

[0108] The electrostatic discharge circuit can overlap with the upper pad PAD1 and / or the lower pad PAD2, so as to provide a more compact layout at the edge of the display device, such that the bezel can be reduced or eliminated.

[0109] The bank 119 can be disposed on the electrostatic discharge circuit and partially or completely overlap with the electrostatic discharge circuit. The bank can extend to the edge of the display device. The bank 119 can include a light-absorbing material (e.g., a black material). Therefore, the bank can prevent external light from impinging on the electrostatic discharge circuit and prevent light from being reflected from the electrostatic discharge circuit. Thus, the edge of the display can have the same appearance as the area between the sub-pixels.

[0110] The passivation layer 114 and one of the plurality of upper pads PAD1 are disposed on the third layer DL2-3.

[0111] The side surface of each of the plurality of upper pads PAD1 can be disposed in the same plane (e.g., Figure 2A and Figure 2B the plane indicated by the line L1 in) as the side surface of each of the plurality of signal lines including the second data line DL2.

[0112] Meanwhile, Figure 2B It is shown that the upper pad PAD1 only overlaps with the second data line DL2 which is a signal line. However, each of the upper pads PAD1 can be arranged to overlap with at least one signal line and / or at least one transistor TR.

[0113] The upper pad PAD1 can overlap with the signal line DL2 or the TFT or both of them. This has the technical effect of reducing the size of the region between the LED and the edge of the display panel, thereby reducing the bezel size or completely eliminating the bezel (e.g., reducing the bezel size in such a way that the distance between the LED and the edge of the display panel is half of the pitch between adjacent LEDs).

[0114] At the edge of the display device, the bank 119 may partially or completely overlap with signal lines (e.g., the second data line DL2), and / or the upper pad PAD1 and / or the lower pad PAD2. The bank 119 may include a light-blocking material (e.g., a black material) and may extend to the edge of the substrate 110. Thus, the bank can prevent external light from affecting the upper pad PAD1 and / or the signal line (e.g., the second data line DL2) and prevent light from being reflected from the upper pad PAD1 and / or the signal line (e.g., the second data line DL2). Thereby, the edge of the display device can have the same appearance as the area between sub-pixels.

[0115] A plurality of upper pads PAD1 (provided on the front surface or the top side of the substrate 110) may be electrically connected to the side lines 140 described below and a plurality of signal lines in the display area AA, and supply signals received from a plurality of flexible films and printed circuit boards provided on the rear surface (i.e., the bottom side) of the substrate 110 to the plurality of sub-pixels SP.

[0116] A plurality of lower pads PAD2 are provided on the lower surface (i.e., the rear surface or the bottom side) of the second substrate 102.

[0117] A plurality of lower pads PAD2 may transmit the signals received from the driving unit provided on the rear surface of the second substrate 102 to the plurality of side lines 140 and thus to the plurality of upper pads PAD1 and the plurality of signal lines. The plurality of lower pads PAD2 may be provided at the ends of the second substrate 102 in the non-display area NA and are electrically connected to the side lines 140 covering (or provided on) the side surface of the second substrate 102 (and the side surfaces of other layers at the edge of the display device).

[0118] The plurality of lower pads PAD2 may be provided at positions where the plurality of lower pads PAD2 overlap with the plurality of upper pads PAD1. The plurality of upper pads PAD1 and the plurality of lower pads PAD2 may overlap and be electrically connected to each other through the side lines 140. The plurality of lower pads PAD2 and the signal lines may also overlap and be electrically connected to each other through the side lines 140. Meanwhile, although Figure 2B not shown in the figure, a plurality of connection lines, a plurality of flexible films, a printed circuit board, etc. may be provided below the second substrate 102.

[0119] Multiple connection lines can supply various signals and voltages received from the driving unit to multiple signal lines of the display device 100. For example, according to their connection to the corresponding signal lines, the multiple connection lines can include multiple gate connection lines, multiple data connection lines, multiple high-potential voltage connection lines, multiple low-potential voltage connection lines, and a reference voltage connection line. However, the present disclosure is not limited thereto. Here, the driving unit can include multiple flexible films and a printed circuit board. However, the present disclosure is not limited thereto. The connection lines can directly electrically connect the driving unit to the side lines or can electrically connect the driving unit to the side lines via other components such as lower pads or upper pads.

[0120] The multiple flexible films supply signals to the multiple sub-pixels SP. The flexible films are configured such that various types of components such as a gate driver IC and a data driver IC are provided on a flexible base film. The printed circuit board is a component that is electrically connected to the multiple flexible films and supplies signals to the driving IC. Various types of components for supplying various signals such as driving signals and data signals to the driving IC can be provided on the printed circuit board. The multiple lower pads PAD2 can be electrically connected to the multiple flexible films or the printed circuit board through multiple connection lines.

[0121] For example, the multiple lower pads PAD2 can be electrically connected to the multiple flexible films through multiple connection lines. The multiple flexible films can supply various types of signals to the multiple side lines 140, the multiple upper pads PAD1, the multiple signal lines, and the multiple sub-pixels SP through the multiple lower pads PAD2 and the multiple connection lines. Therefore, the signals received from the driving unit can be transmitted to the multiple sub-pixels SP and the signal lines on the front surface of the first substrate 101 through the multiple lower pads PAD2 of the second substrate 102, the side lines 140, and the multiple upper pads PAD1 of the first substrate 101. More generally, the signals from the driving unit on the bottom side (or the rear surface or the lower surface) of the substrate 110 can be transmitted to the multiple sub-pixels SP on the top side (or the front surface or the upper surface) via the side lines 140. The side lines 140 are connected to the driving unit through the lower pads PAD2 and are connected to the sub-pixels SP via the signal lines and the upper pads PAD1. The side lines 140 can be directly connected to the signal lines and / or can be connected to the signal lines via the upper pads PAD1.

[0122] Refer to Figure 2B , after the first substrate 101 and the second substrate 102 are joined by the first adhesive layer 121, the first substrate 101 and the second substrate 102 can be ground (for example, ground using a mechanical grinding device) to the plane indicated by the first line L1.

[0123] A grinder GR disposed outside the first substrate 101 and the second substrate 102 can grind the side surfaces of the first substrate 101 and the second substrate 102 while rotating about a rotation axis. The grinder GR can grind the side surfaces of the first substrate 101 and the second substrate 102 while moving to the side surfaces of the first line L1 overlapping with a plurality of signal lines and a plurality of pads including an upper pad PAD1 and a lower pad PAD2. Accordingly, a ground surface can be formed on the side surfaces of the first substrate 101 and the second substrate 102 by the grinder GR. However, the present disclosure is not limited thereto, and a portion of the substrate 110 protruding from the plane indicated by the line L1 can be removed by other means (e.g., cutting, polishing, or filing).

[0124] For ease of description, the drawings show that the plurality of pads PAD remaining on the substrate 110 after the grinding process have a relatively large area. However, the area of the plurality of pads PAD remaining on the substrate 110 can be very small to eliminate heterogeneity between adjacent display devices 100 when the bezel area is significantly reduced and a tiled display is achieved. In other words, the entire end of the display can be ground (or otherwise fabricated) such that the area including the plurality of pads PAD is minimized. This can reduce the distance between the nearest edge of the nearest sub-pixel SP and the line L1 to, for example, half the distance between the edges of adjacent sub-pixels, so that in a tiled display including one or more adjacent displays as shown in Figure 2A and Figure 2B (or Figure 3A and Figure 3B ; or Figure 4A and Figure 4B ; or Figure 5 ), there is no discontinuity in the spacing of sub-pixels at the junction between adjacent displays in the tiled array. Accordingly, the appearance and performance of the tiled display are improved.

[0125] According to the shape of the grinder GR, the ground surfaces of the first substrate 101 and the second substrate 102 formed by the grinder GR can have a straight shape. In other words, the surface can be ground evenly such that the final result is a flat ground surface. Hereinafter, the side surfaces of the first substrate 101 and the second substrate 102 will be described with reference to Figure 3A and Figure 3B .

[0126] Figure 3A is a schematic top view of a sub-pixel of a display device according to a first embodiment. Figure 3B is a schematic cross-sectional view of the display device taken along line III-III' of Figure 3A . Figure 3A and Figure 3B show the state after the grinding process is completed. Figure 3AShows a plurality of upper pads PAD1, a plurality of signal lines, a plurality of light emitting elements LED, a plurality of side lines 140, and a plurality of pixels P on a substrate 110. Since the display device 100 in the state where the grinding process is completed, except for adding a plurality of side lines 140 and a side insulating layer 150 and not including the removed portion of the substrate 110, is substantially the same as the display device in the state before performing the grinding process (e.g., Figure 2A and Figure 2B of the display device), the repeated description of the components, features, and arrangements described with reference to Figure 2A and Figure 2B will be omitted.

[0127] Referring to Figure 3A and Figure 3B , the side surfaces of the first substrate 101 and the second substrate 102 of the display device 100 are set to be flat (i.e., are planar). The side surfaces of the first substrate 101 and the second substrate 102 are on the same plane as the side surfaces of the components of the display device 100 provided on the upper and lower portions of the substrate 110. For example, the side surface of the first substrate 101 can be on the same plane as the side surfaces of the plurality of signal lines and the plurality of upper pads PAD1 and on the same plane as the side surfaces of the plurality of insulating layers provided on the first substrate 101. The side surface of the second substrate 102 can also be on the same plane as the side surfaces of the plurality of lower pads PAD2 provided below the second substrate 102.

[0128] After the removal (e.g., grinding) process, a plurality of side lines 140 are provided on the side surfaces of the first substrate 101 and the second substrate 102. The plurality of side lines 140 can electrically connect the plurality of upper pads PAD1 formed on the upper surface of the first substrate 101 to the plurality of lower pads PAD2 formed on the lower surface of the second substrate 102, thereby connecting the plurality of signal lines formed on the upper surface of the first substrate 101 to the plurality of connection lines formed on the rear surface (i.e., on the back, bottom, below, or under the second substrate 102) of the second substrate 102. However, the present disclosure is not limited to including lower pads, and the connection lines can be directly connected to the side lines without lower pads.

[0129] The plurality of side lines 140 can be provided to surround the side surface of the display device 100. The side lines can be spaced apart from each other. The plurality of side lines 140 can respectively contact the side surfaces of the plurality of upper pads PAD1 provided at the end of the first substrate 101, the side surfaces of the plurality of signal lines, the side surface of the first substrate 101, the side surface of the second substrate 102, and the side surfaces of the plurality of lower pads PAD2 provided at the end of the second substrate 102. In this case, when the side surface of the substrate 110 is on a plane perpendicular to the plane of the upper surface of the substrate 110, the plurality of side lines 140 can also be provided in a direction perpendicular to the upper surface of the substrate 110.

[0130] A plurality of side lines 140 may be formed by a pad printing method using a conductive ink (e.g., a conductive ink including silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), etc.).

[0131] A side insulating layer 150 is provided to cover the plurality of side lines 140. The side insulating layer 150 may be formed to cover the side lines 140 on the upper surface of the first substrate 101, the side surface of the first substrate 101, the side surface of the second substrate 102, and the rear surface of the second substrate 102. In other words, the side insulating layer 150 may cover the upper surface, lower surface, and side surfaces of the side lines 140. The side insulating layer 150 may protect the plurality of side lines 140.

[0132] Meanwhile, when the plurality of side lines 140 are made of a metal material, there may be a problem that external light is reflected by the plurality of side lines 140 or light emitted from the light-emitting element LED is reflected by the plurality of side lines 140, and the user visually recognizes the light. Therefore, the side insulating layer 150 may be configured to include a black material to suppress the reflection of external light. For example, the side insulating layer 150 may be formed by a pad printing method using an insulating material including a black material (e.g., black ink).

[0133] Meanwhile, although Figure 3A and Figure 3B not shown, a sealing member and an optical film covering the side insulating layer 150 may be additionally provided. The sealing member may be provided to surround the side surface of the display device 100 and protect the display device 100 from external impact or moisture and oxygen. For example, the sealing member may be made of a material such as polyimide (PI), polyurethane, epoxy resin, and acrylic. However, the present disclosure is not limited thereto.

[0134] The optical film may be provided on the sealing member, the side insulating layer 150, and the protective layer. The optical film may be a functional film that realizes an image with higher image quality while protecting the display device 100. For example, the optical film may include an antiglare film, an antireflection film, a low-reflection film, an OLED light transmittance controllable film, or a polarizing plate. However, the present disclosure is not limited thereto.

[0135] A plurality of pads are provided on the upper and lower sides of the substrate in the non-display area of the display device to transmit various types of signals to the plurality of sub-pixels. The plurality of pads may be connected between the side lines in the display area and the plurality of signal lines, and provide signals received from a printed circuit board and a plurality of flexible films provided below the substrate to the plurality of sub-pixels. In this case, the plurality of pads are provided on the peripheral portion of the display device, i.e., the bezel area. In addition, the plurality of pads are provided outside the plurality of signal lines and the plurality of transistors, which requires a separate area to provide the plurality of pads and results in a reduced limitation on the bezel of the display device.

[0136] Meanwhile, the interval between the outermost light-emitting element LED of one panel and the outermost light-emitting element LED of another panel adjacent to one panel (and having the same edge structure and side lines as described in any of the embodiments described herein) is implemented to be equal to the interval between the light-emitting elements LED in one panel, thereby realizing a tiled display achieved by arranging a plurality of panels in a tiled shape. Therefore, in the case where the border area of the display device is larger than the interval between the light-emitting elements in one display panel due to the limitation of the reduced size of a plurality of pads, the boundary between the display modules can be visually recognized by the user, which causes an interruption in the displayed image and particularly causes a limitation in achieving a large-sized panel by tiling.

[0137] Therefore, in the display device 100 according to the first embodiment, a plurality of pads PAD are arranged to overlap at least one of a plurality of signal lines and a plurality of transistors TR, so that a separate area for setting the pads PAD can be removed from the design, and the border area of the display device 100 can be reduced.

[0138] In addition, in the display device 100 according to the first embodiment, side lines 140 are formed on the side surfaces of the first upper pad PAD1 and a plurality of lower pads PAD2, so that the side surface 110 of the substrate can be ground to form a flat portion (i.e., a plane). That is, a plurality of side lines 140 can be formed without obliquely grinding the side surface of the substrate 110 to more smoothly connect a plurality of signal lines (e.g., gate lines GL and / or data lines DL) provided on the upper surface of the first substrate 101 and a plurality of connection lines on the rear surface of the second substrate 102, thereby simplifying the manufacturing process. In the case where the term "side surface" is used to describe the surface of a feature, this can be understood to represent the surface of the end portion of the feature, such as at the edge of the display device.

[0139] In addition, in the display device 100 according to the first embodiment, the side surface of the substrate 110 is not obliquely ground, which can reduce the problems caused when the side surface of the substrate 110 is obliquely ground.

[0140] First, defects that may occur on the side lines and a plurality of pads during the grinding process can be suppressed. In the case where a grinding process is performed on the edges of the first substrate and the second substrate using a grinding machine, a plurality of pads and side lines provided on the upper and lower portions of the substrate are partially removed together with the substrate, causing a problem that the side lines are disconnected from a plurality of pads. In addition, there is also a problem that cracks start to form in the ground side surface and propagate. Therefore, in the display device 100 according to the first embodiment, the grinding process is not performed on the side surface of the substrate 110, which can suppress defects that may occur on the side lines 140 and a plurality of pads PAD.

[0141] In addition, the side insulating layer 150 covering the plurality of side lines 140 can be coated by coating from the bottom of the substrate 110 and filling in the direction from the side surface to the upper surface of the substrate 110 (i.e., in the direction within the plane of the side surface to the upper surface). For this purpose, when the side surface of the substrate is inclinedly ground, due to the inclined surface formed on the side surface of the substrate, the side insulating layer may not be uniformly formed on the side surface of the substrate. For this reason, the side insulating layer may not be filled at local points without covering a part of the upper surface of the substrate or without covering the entire side surface. For this reason, when the side lines are exposed at the points where the side insulating layer is not filled, the following problems may occur: external light is reflected by the plurality of side lines at the corresponding points, or light emitted from the light-emitting element is reflected by the plurality of side lines, and the light is visually recognized by the user. Therefore, in the display device 100 according to the first embodiment, the inclined surface is not formed on the side surface of the substrate 110 through the grinding process. Therefore, the side insulating layer 150 can be uniformly provided on the side surface of the substrate 110, which makes it possible to suppress the reflection of the side lines 140 on the external light at the points where the side insulating layer 150 is not filled.

[0142] Figure 4A FIG. 5 is a schematic cross-sectional view of a display device in a state before the process of grinding the display device according to the second embodiment. Figure 4B FIG. 6 is a schematic cross-sectional view of a display device according to the second embodiment. Since the display device 400 according to the second embodiment is substantially the same as the display device 100 according to the first embodiment except for the substrate 410, the plurality of side lines 440, and the plurality of pads PAD, the repeated descriptions of the components, features, and arrangements described with reference to Figure 1 、 Figure 2A 、 Figure 2B 、 Figure 3A and Figure 3B will be omitted.

[0143] Referring to Figure 4A , the side surfaces of the first substrate 101 and the second substrate 402 can be ground. The grinding machine GR can grind the side surfaces of the first substrate 101 and the second substrate 402 while moving to the first line L1. Therefore, the ground surfaces can be formed on the side surfaces of the first substrate 101 and the second substrate 402 by the grinding machine GR. In this case, the ground surface of the first substrate 101 formed by the grinding machine GR can be formed to be flat according to the shape of the grinding machine GR. At the same time, the side surface of the second substrate 402 and the side surface of the first substrate 101 can be configured as different surfaces (for example, where the planes of the surfaces have different orientations).

[0144] Hereinafter, the side surfaces of the first substrate 101 and the second substrate 402 will be described with reference to Figure 4B .

[0145] Reference Figure 4B , the substrate 410 of the display device 400 may include side surfaces formed as inclined surfaces inclined with respect to the upper surface of the substrate 410. That is, a part of the side surface of the substrate 410 may be an inclined surface inclined with respect to the upper surface of the substrate 410.

[0146] First, the side surface of the first substrate 101 of the display device 400 and the side surfaces of the components provided above the substrate 410 of the display device 400 are provided in the same plane. For example, the side surface of the first substrate 101 may be provided in the same plane as the side surfaces of a plurality of signal lines and a plurality of upper pads PAD1 and may be provided in the same plane as the side surfaces of a plurality of insulating layers provided on the first substrate 101. In this case, the side surface of the first substrate 101 may be a surface perpendicular to the upper surface of the substrate 110.

[0147] The side surface of the second substrate 402 may include side surfaces provided in a direction (i.e., orientation) different from the direction (i.e., orientation) of the side surfaces of the components provided above the substrate 410 of the display device 400. For example, a part of the side surface of the second substrate 402 may include an inclined surface inclined with respect to the upper surface of the substrate 110.

[0148] Meanwhile, the side surface of each of the plurality of lower pads PAD2 and the plurality of connection lines provided below the second substrate 402 may include an inclined surface formed at the same angle (and in the same plane) as the side surface of the second substrate 402. Thus, as Figure 4B shown, the ends of the plurality of lower pads PAD2 and the plurality of connection lines provided below the second substrate 402 may be provided inside the end of the substrate 410 (i.e., the end defined by the line L1).

[0149] Next, a plurality of side lines 440 are provided on the side surfaces of the first substrate 101 and the second substrate 402. The plurality of side lines 440 may connect a plurality of upper pads PAD1 having flat side surfaces and a plurality of lower pads PAD2 including side surfaces having inclined surfaces. In this case, the plurality of side lines 440 may contact the side surface of the first substrate 101 and the inclined side surface of the second substrate 402. Thus, when the plurality of lower pads PAD2 are provided inside the side surface of the second substrate 402, the plurality of side lines 440 may also contact the lower surface of the substrate 410.

[0150] The side insulating layer 450 is provided to cover the plurality of side lines 440. The side insulating layer 450 may be formed to cover the upper portion of the first substrate 101, the side surface of the first substrate 101, the side surface of the second substrate 402, and the side lines 440 on the lower portion of the second substrate 402. In other words, the side insulating layer 450 may cover the upper surface, the lower surface, and the side surface of the side lines 440. The side insulating layer 450 may protect the plurality of side lines 440.

[0151] In the display device 400 according to the second embodiment, each pad PAD is provided to overlap at least one signal line and / or at least one transistor TR, thereby reducing the bezel area of the display device 400.

[0152] In addition, in the display device 400 according to the second embodiment, the side surface of the substrate 410 may be provided as an inclined surface, thereby reducing the contact resistance between the side lines 440 and the plurality of pads PAD. When the side surface of the substrate 410 is inclined, the contact area between the plurality of pads PAD and the plurality of side lines 440 may be increased. Therefore, the total resistance of the plurality of signal lines and the plurality of pads PAD may be reduced.

[0153] Figure 5 is a schematic cross-sectional view of a display device according to a third embodiment. Since the display device 500 according to the third embodiment is substantially the same as the display device 100 according to the first embodiment except for the plurality of side lines and the plurality of pads PAD, the reference to Figure 1 , Figure 2A , Figure 2B , Figure 3A and Figure 3B the repeated descriptions of the components, features, and arrangements described will be omitted.

[0154] Referring to Figure 5 , a plurality of signal lines are provided on the first substrate 101 and are provided at the end of the first substrate 101. For ease of description, Figure 5 the second data line DL2 among the plurality of signal lines is shown.

[0155] The second data line DL2 may include a first layer DL2-1, a second layer DL2-2, and a third layer DL2-3. The first layer DL2-1, the second layer DL2-2, and the third layer DL2-3 are the same as the first layer DL2-1, the second layer DL2-2, and the third layer DL2-3 described with reference to Figures 1 to 3B .

[0156] A passivation layer 114 and a first planarization layer 115a are provided on the third layer DL2-3.

[0157] Meanwhile, at least one of the first layer DL2-1, the second layer DL2-2, and the third layer DL2-3 that constitutes the second data line DL2 can be electrically connected to a plurality of lower pads PAD2 through the side line 140 and supply various types of signals to the plurality of sub-pixels SP. Accordingly, at least one of the first layer DL2-1, the second layer DL2-2, and the third layer DL2-3 that constitutes the second data line DL2 can be referred to as an upper pad, and each of the plurality of upper pads can be a part of a corresponding signal line.

[0158] In the display device 500 according to the third embodiment, a plurality of side lines 140 can be formed without obliquely grinding the side surface of the substrate 110, thereby simplifying the manufacturing process.

[0159] In addition, in the display device 500 according to the third embodiment, the side surface of the substrate 110 is not obliquely ground. Accordingly, it is possible to suppress a problem in which a part of the side line 140 and the plurality of pads PAD are removed and the side line 140 and the plurality of pads PAD are disconnected during the grinding process.

[0160] In addition, in the display device 500 according to the third embodiment, an inclined surface is not formed on the side surface of the substrate 110 through the grinding process. Accordingly, the side insulating layer 150 can be uniformly provided on the side surface of the substrate 110, which can suppress reflection of external light by the side line 140. Alternatively, the display device 500 can be configured with reference to Figure 4A and Figure 4B the described display device (i.e., having an inclined surface of the second substrate), but without upper pads, but having a direct connection between the side line 140 and one or more layers of the signal lines DL2-1, DL2-2, DL2-3 as described above with reference to Figure 5

[0161] In addition, in the display device 500 according to the third embodiment, a part of the plurality of signal lines can be used as pads without providing separate pads at the ends of the display device 500. In the display device 500 according to the third embodiment, a plurality of side lines 140 can be in contact with the side surfaces of the plurality of signal lines. Accordingly, signals applied from the driving unit can be transmitted to the plurality of pixels SP without providing a conductive material for forming pads. Accordingly, in the display device 500 according to the third embodiment, a separate process of forming a conductive material for forming pads is not performed, thereby reducing costs and simplifying the manufacturing process of the display device.

[0162] The embodiment can also be described as follows:

[0163] According to one aspect of the present disclosure, a display device includes: a substrate on which a plurality of light-emitting elements are provided; transistors on the substrate; a plurality of signal lines on the substrate; a plurality of connection lines under the substrate; and a plurality of upper pads located on the substrate and connected to the plurality of signal lines, wherein the plurality of upper pads are arranged to overlap at least one of the plurality of signal lines and the plurality of transistors.

[0164] The display device may further include a plurality of side lines that can connect the plurality of signal lines and the plurality of connection lines. The plurality of upper pads and the plurality of signal lines may be in contact with the plurality of side lines.

[0165] The side surfaces of the plurality of upper pads may be disposed in the same plane as the side surfaces of the plurality of signal lines.

[0166] The plurality of side lines may be in contact with the side surface and the lower surface of the substrate.

[0167] The display device may further include a plurality of lower pads located on the lower surface of the substrate and connected to the plurality of connection lines. The plurality of lower pads may be arranged to overlap the plurality of upper pads.

[0168] A part of the side surface of the substrate may be an inclined surface that is inclined with respect to the upper surface of the substrate, and the plurality of side lines may partially cover the side surface and the lower surface of the substrate.

[0169] The substrate may include a first substrate and a second substrate located below the first substrate. A part of the side surface of the second substrate may be an inclined surface that is inclined with respect to the upper surface of the substrate.

[0170] The display device may further include a plurality of lower pads located on the lower surface of the substrate and connected to the plurality of connection lines. The ends of the plurality of lower pads may be disposed at positions that are more inward than the ends of the substrate.

[0171] The display device may further include a plurality of insulating layers that are located on the substrate and are disposed above or below the plurality of upper pads and the plurality of signal lines. The side surfaces of the plurality of insulating layers may be disposed in the same plane as the side surface of the substrate.

[0172] The side surfaces of the plurality of insulating layers may be disposed in the same plane as the side surfaces of the plurality of upper pads.

[0173] Each of the plurality of upper pads may be a part of each of the plurality of signal lines.

[0174] The display device may further include an electrostatic discharge circuit that is located on the substrate and overlaps the plurality of upper pads.

[0175] Although the embodiments have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms. Therefore, the embodiments are provided for illustrative purposes only and are not intended to limit the present disclosure. Accordingly, it should be understood that the above embodiments are exemplary in all aspects and do not limit the present disclosure. The scope of the present disclosure should be construed based on the following claims and their equivalents.

[0176] The following numbered examples are also described herein:

[0177] Example 1. A display device, comprising:

[0178] a substrate on which a plurality of light-emitting elements are provided;

[0179] a plurality of transistors provided on the substrate;

[0180] a plurality of signal lines provided on the substrate;

[0181] a plurality of connection lines provided under the substrate; and

[0182] a plurality of upper pads provided on the substrate and connected to the plurality of signal lines,

[0183] wherein the plurality of upper pads overlap at least one of the plurality of signal lines and the plurality of transistors.

[0184] Example 2. The display device according to Example 1, further comprising a plurality of side lines connecting the plurality of signal lines and the plurality of connection lines,

[0185] wherein the plurality of upper pads and the plurality of signal lines are in contact with the plurality of side lines.

[0186] Example 3. The display device according to Example 1 or 2, wherein side surfaces of the plurality of upper pads and side surfaces of the plurality of signal lines are disposed in the same plane.

[0187] Example 4. The display device according to Example 1, 2 or 3, wherein the plurality of side lines are in contact with a side surface and a lower surface of the substrate.

[0188] Example 5. The display device according to Example 4, further comprising a plurality of lower pads located on a lower surface of the substrate and connected to the plurality of connection lines,

[0189] wherein the plurality of lower pads are arranged to overlap the plurality of upper pads.

[0190] Example 6. The display device according to Example 4 or 5, wherein a part of a side surface of the substrate is an inclined surface inclined with respect to an upper surface of the substrate, and

[0191] wherein the plurality of side lines partially cover the side surface and the lower surface of the substrate.

[0192] Example 7. The display device according to any one of the foregoing examples, wherein the substrate includes a first substrate and a second substrate located below the first substrate, and

[0193] wherein a part of the side surface of the second substrate is an inclined surface inclined with respect to the upper surface of the substrate.

[0194] Example 8. The display device according to any one of the foregoing examples, further comprising a plurality of lower pads, the plurality of lower pads being located on the lower surface of the substrate and connected to a plurality of connection lines,

[0195] wherein the ends of the plurality of lower pads are provided inside the ends of the substrate.

[0196] Example 9. The display device according to any one of the foregoing examples, further comprising a plurality of insulating layers, the plurality of insulating layers being located on the substrate and provided above or below the plurality of upper pads and the plurality of signal lines,

[0197] wherein the side surfaces of the plurality of insulating layers are provided in the same plane as the side surface of the substrate.

[0198] Example 10. The display device according to Example 9, wherein the side surfaces of the plurality of insulating layers are provided in the same plane as the side surfaces of the plurality of upper pads.

[0199] Example 11. The display device according to any one of the foregoing examples, wherein each of the plurality of upper pads is a part of each of the plurality of signal lines.

[0200] Example 12. The display device according to any one of the foregoing examples, further comprising an electrostatic discharge circuit, the electrostatic discharge circuit being provided on the substrate and overlapping with the plurality of upper pads.

[0201] Example 13. A display device, comprising:

[0202] a plurality of scan lines and a plurality of data lines, provided on a first substrate;

[0203] a light-emitting element, provided between adjacent data lines among the plurality of data lines;

[0204] a transistor, provided on the first substrate;

[0205] a plurality of upper pads, provided on the first substrate and connected to the plurality of scan lines and the plurality of data lines; and

[0206] a plurality of lower pads, provided on the second substrate and overlapping with the plurality of upper pads; and

[0207] a plurality of side lines, provided on the side surfaces of the first substrate and the second substrate and connecting the plurality of upper pads, the plurality of lower pads and the plurality of data lines.

[0208] Example 14. The display device according to Example 13 further includes a plurality of insulating layers provided on the plurality of signal lines and the plurality of lower pads.

[0209] Example 15. The display device according to Example 14, wherein side surfaces of the plurality of insulating layers are disposed in the same plane as side surfaces of the first substrate and the second substrate.

[0210] Example 16. The display device according to any one of Examples 13 to 15, wherein the second substrate has a side surface that is inclined with respect to the second substrate.

[0211] Example 17. The display device according to any one of Examples 13 to 16, wherein the plurality of lower pads have ends disposed inside one end of the second substrate.

[0212] Example 18. The display device according to any one of Examples 13 to 17, wherein the plurality of upper pads have side surfaces disposed in the same plane as side surfaces of the plurality of data lines.

[0213] Example 19. The display device according to any one of Examples 13 to 18, wherein the plurality of side lines are formed by a pad printing method using conductive ink.

[0214] Example 20. The display device according to any one of Examples 13 to 16 further includes an electrostatic discharge circuit provided on the first substrate and overlapping with the plurality of upper pads.

[0215] The following numbered clauses are also described herein:

[0216] Clause 1. A display device, comprising:

[0217] A substrate on which a plurality of light-emitting elements are provided;

[0218] A plurality of transistors provided on the substrate;

[0219] A plurality of signal lines provided on the substrate, each signal line being electrically connected to one or more transistors;

[0220] An electrostatic discharge circuit provided on the substrate and configured to selectively connect the signal lines to a ground line.

[0221] Clause 2. The display device according to Clause 1, further comprising:

[0222] A plurality of connection lines provided under the substrate; and

[0223] A plurality of side lines provided on a side surface of the substrate, each side line providing at least a part of an electrical connection between a corresponding one of the plurality of connection lines and a corresponding one of the plurality of signal lines,

[0224] Among them, the electrostatic discharge circuit is electrically connected to the signal line via a side line.

[0225] Clause 3. The display device according to Clause 1 or 2 further includes an upper pad provided on the substrate, wherein the electrostatic discharge circuit overlaps with the upper pad.

[0226] Clause 4. The display device according to Clause 1, 2, or 3 further includes a lower pad provided below the substrate, wherein the electrostatic discharge circuit overlaps with the lower pad.

[0227] Clause 5. The display device according to Clause 1 or 2 further includes an upper pad provided on the substrate and a lower pad provided below the substrate, wherein the upper pad overlaps with the lower pad, and optionally, the electrostatic discharge circuit overlaps with the upper pad and / or the lower pad.

[0228] Clause 6. The display device according to any of the preceding clauses further includes a bank provided on the substrate, wherein the bank overlaps with the electrostatic discharge circuit.

[0229] Clause 7. The display device according to Clause 6, wherein the bank includes a light-blocking material.

[0230] Clause 8. The display device according to Clause 7, wherein the bank includes a black material.

[0231] Clause 9. The display device according to any of the preceding clauses, wherein each of the light-emitting elements is a micro LED including an inorganic active layer.

[0232] Clause 10. The display device according to any of the preceding clauses, wherein each of the light-emitting elements includes:

[0233] an n-type layer;

[0234] an active layer on the n-type layer;

[0235] a p-type layer on the active layer;

[0236] an n electrode on the n-type layer; and

[0237] a p electrode on the p-type layer,

[0238] wherein the p electrode and the n electrode are arranged to be spaced apart from each other at different heights.

[0239] Clause 11. The display device according to Clause 10 further includes:

[0240] a first electrode connected to the n electrode; and

[0241] a second electrode connected to the p electrode.

[0242] Clause 12. The display device according to Clause 11 further comprises:

[0243] A first planarization layer;

[0244] A second planarization layer, located on the first planarization layer; and

[0245] A third planarization layer, located on the second planarization layer,

[0246] wherein the first electrode and the second electrode are spaced apart from each other and the third planarization layer is disposed between the first electrode and the second electrode.

[0247] Clause 13. The display device according to Clause 12, wherein the second planarization layer and the third planarization layer are in contact with each other in a region between the first electrode and the second electrode.

[0248] Clause 14. The display device according to any one of Clauses 11 to 13 further comprises:

[0249] A bank, located on the first electrode and the second electrode; and

[0250] A plurality of upper pads, disposed on the substrate,

[0251] wherein the bank overlaps at least a part of at least one upper pad. Optionally, wherein the bank comprises a light-blocking material. Optionally, wherein the light-blocking material is a black material.

[0252] Clause 15. The display device according to any one of Clauses 9 to 14 further comprises a reflective layer corresponding to each of the light-emitting elements, wherein the light-emitting element overlaps with the reflective layer.

[0253] Clause 16. The display device according to any one of the foregoing clauses further comprises a plurality of upper pads disposed on the substrate, wherein an electrostatic discharge circuit is disposed in a region between the upper pad and the display region where the light-emitting elements are disposed.

[0254] Clause 17. The display device according to any one of the foregoing clauses, wherein each signal line comprises at least two overlapping signal line layers connected in parallel with each other.

[0255] Clause 18. The display device according to any one of the foregoing clauses further comprises a first insulating layer, and the first insulating layer is disposed between each adjacent pair of at least two overlapping signal line layers.

[0256] Clause 19. The display device according to Clause 18, wherein the first insulating layer comprises a first through hole for accommodating a corresponding connection portion connecting adjacent pairs of signal line layers.

[0257] Clause 20. The display device according to any one of the preceding clauses, wherein the signal line is electrically connected to the upper pad, and optionally, wherein the signal lines are electrically connected to the upper pad in parallel.

[0258] Clause 21. The display device according to any one of the preceding clauses, further comprising a second insulating layer disposed between the upper pad and the signal line.

[0259] Clause 22. The display device according to Clause 21, wherein the second insulating layer includes a second through hole that houses a connection portion connecting the signal line and the upper pad.

[0260] Clause 23. The display device according to any one of the preceding clauses, further comprising a plurality of upper pads disposed on the substrate,

[0261] wherein each of the plurality of upper pads overlaps with one of the plurality of signal lines; and / or

[0262] each of the plurality of upper pads overlaps with one of the plurality of transistors.

[0263] Clause 24. The display device according to any one of the preceding clauses, wherein an edge of the display device includes at least one plane, and

[0264] the substrate, the electrostatic discharge circuit, and the signal lines terminate at the at least one plane.

[0265] Clause 25. The display device according to Clause 24, wherein the at least one plane includes a first plane disposed perpendicular to an upper surface of the substrate.

[0266] Clause 26. The display device according to Clause 24 or 25, wherein the at least one plane includes a second plane inclined with respect to the upper surface of the substrate.

[0267] Clause 27. The display device according to Clause 24, 25, or 26, further comprising a plurality of side lines, wherein the plurality of side lines partially cover the at least one plane, and optionally, the plurality of side lines partially cover a lower surface of the substrate.

[0268] Clause 28. The display device according to Clause 28, wherein each side line contacts a corresponding one of the plurality of signal lines and the electrostatic discharge circuit.

[0269] The following numbered items are also described herein:

[0270] Item 1. A display device, comprising:

[0271] a substrate;

[0272] a plurality of light-emitting elements disposed on the substrate;

[0273] Multiple transistors, disposed on a substrate;

[0274] Multiple signal lines, disposed on the substrate, each signal line being electrically connected to one or more transistors;

[0275] An upper pad, disposed on the substrate, wherein the upper pad is disposed at an edge region of the substrate; and

[0276] A bank, disposed on the upper pad to overlap with the upper pad.

[0277] Item 2. The display device according to Item 1, further comprising a plurality of lower pads disposed below the substrate, wherein the upper pad overlaps with the lower pad.

[0278] Item 3. The display device according to Item 1 or 2, wherein the bank comprises a light-blocking material, optionally, the bank comprises a black material.

[0279] Item 4. The display device according to any one of the foregoing items, wherein the bank extends to the edge of the substrate.

[0280] Item 5. The display device according to any one of the foregoing items, wherein the bank extends between the edge of the substrate and the light-emitting element.

[0281] Item 6. The display device according to any one of the foregoing items, wherein each signal line comprises at least two overlapping signal line layers connected in parallel with each other.

[0282] Item 7. The display device according to Item 6, further comprising a first insulating layer disposed between each adjacent pair of the at least two overlapping signal line layers.

[0283] Item 8. The display device according to Item 7, wherein the first insulating layer comprises a first through hole for accommodating a corresponding connection portion connecting the adjacent pair.

[0284] Item 9. The display device according to any one of the foregoing items, wherein the signal line is electrically connected to the upper pad, optionally, wherein the signal line is electrically connected to the upper pad in parallel.

[0285] Item 10. The display device according to any one of the foregoing items, further comprising a second insulating layer disposed between the upper pad and the signal line.

[0286] Item 11. The display device according to Item 10, wherein the second insulating layer comprises a second through hole for accommodating a connection portion connecting the signal line and the upper pad.

[0287] Item 12. The display device according to any one of the foregoing items, wherein each of the light-emitting elements is a micro-LED including an inorganic active layer.

[0288] Item 13. The display device according to any one of the preceding items, wherein each of the light-emitting elements includes:

[0289] an n-type layer;

[0290] an active layer on the n-type layer;

[0291] a p-type layer on the active layer;

[0292] an n electrode on the n-type layer; and

[0293] a p electrode on the p-type layer,

[0294] wherein the p electrode and the n electrode are arranged to be spaced apart from each other at different heights.

[0295] Item 14. The display device according to Item 13, further comprising:

[0296] a first electrode connected to the n electrode; and

[0297] a second electrode connected to the p electrode.

[0298] Item 15. The display device according to Item 14, further comprising:

[0299] a first planarization layer;

[0300] a second planarization layer located on the first planarization layer; and

[0301] a third planarization layer located on the second planarization layer,

[0302] wherein the first electrode and the second electrode are spaced apart from each other and the third planarization layer is disposed between the first electrode and the second electrode.

[0303] Item 16. The display device according to Item 15, wherein the second planarization layer and the third planarization layer are in contact with each other in a region between the first electrode and the second electrode.

[0304] Item 17. The display device according to any one of Items 14 to 16, wherein a bank is disposed on the first electrode and the second electrode.

[0305] Item 18. The display device according to any one of the preceding items, further comprising a reflective layer corresponding to each of the light-emitting elements, wherein the light-emitting element overlaps with the reflective layer.

[0306] Item 19. The display device according to any one of the preceding items, further comprising an electrostatic discharge circuit, the electrostatic discharge circuit being disposed on the substrate and configured to selectively electrically connect a signal line to a ground line, wherein a bank is disposed on the electrostatic discharge circuit and overlaps with the electrostatic discharge circuit.

[0307] Item 20. The display device according to any one of the preceding items, wherein the bank is arranged to overlap with a plurality of signal lines.

[0308] Item 21. The display device according to any one of the preceding items, wherein the edge of the display device includes at least one plane, and

[0309] the substrate and the signal lines terminate at the at least one plane.

[0310] Item 22. The display device according to Item 21, wherein the at least one plane includes a first plane disposed perpendicular to the upper surface of the substrate.

[0311] Item 23. The display device according to Item 21 or 22, wherein the at least one plane includes a second plane inclined with respect to the upper surface of the substrate.

[0312] Item 24. The display device according to Item 21, 22 or 23, further comprising a plurality of side lines, wherein the plurality of side lines partially cover the at least one plane, and optionally, the plurality of side lines partially cover the lower surface of the substrate.

[0313] Item 25. The display device according to Item 24, wherein each side line contacts a corresponding one of the plurality of signal lines.

[0314] The following numbered embodiments are also described herein:

[0315] Embodiment 1. A display device, comprising:

[0316] a substrate;

[0317] a plurality of light-emitting elements disposed on the substrate;

[0318] a plurality of transistors disposed on the substrate;

[0319] a plurality of signal lines disposed on the substrate, each signal line being electrically connected to one or more transistors;

[0320] a plurality of connection lines disposed under the substrate; and

[0321] a plurality of side lines disposed on the side surface of the substrate, each side line providing at least a part of the electrical connection between a corresponding one of the plurality of connection lines and a corresponding one of the plurality of signal lines.

[0322] Embodiment 2. The display device according to Embodiment 1, wherein the edge of the display device includes at least one plane, and

[0323] the substrate and the signal lines terminate at the at least one plane.

[0324] Example 3. The display device according to Example 2, wherein at least one plane includes a first plane disposed perpendicular to the upper surface of the substrate.

[0325] Example 4. The display device according to Example 2 or 3, wherein at least one plane includes a second plane inclined with respect to the upper surface of the substrate.

[0326] Example 5. The display device according to Example 2, 3 or 4, wherein a plurality of side lines partially cover at least one plane, and optionally, a plurality of side lines partially cover the lower surface of the substrate.

[0327] Example 6. The display device according to any one of the preceding examples, wherein each side line contacts a corresponding one of the plurality of signal lines.

[0328] Example 7. The display device according to any one of the preceding examples, wherein the substrate includes a first substrate and a second substrate below the first substrate, and

[0329] wherein at least a part of the side surface of the second substrate forms at least a part of the second plane.

[0330] Example 8. The display device according to any one of the preceding examples, further comprising a plurality of upper pads disposed on the substrate, each upper pad being electrically connected to a corresponding one of the plurality of signal lines.

[0331] Example 9. The display device according to any one of the preceding examples, further comprising a plurality of upper pads disposed on the substrate,

[0332] wherein each of the sub-pixels includes a transistor, and

[0333] wherein each of the upper pads overlaps with one of the plurality of signal lines; and / or each of the upper pads overlaps with one of the plurality of transistors.

[0334] Example 10. The display device according to Example 8 or 9, wherein each side line contacts a corresponding one of the plurality of upper pads.

[0335] Example 11. The display device according to Example 8, 9 or 10, wherein the side surface of the upper pad and the side surface of the signal line are in the same plane.

[0336] Example 12. The display device according to any one of Examples 8 to 11, further comprising a plurality of lower pads located on the lower surface of the substrate, each lower pad being electrically connected to a corresponding one of the plurality of connection lines,

[0337] wherein each of the lower pads overlaps with a corresponding one of the plurality of upper pads.

[0338] Example 13. The display device according to any one of Examples 8 to 12 further includes a plurality of insulating layers located on the substrate and disposed above or below the plurality of upper pads and / or the plurality of signal lines,

[0339] wherein a side surface of the insulating layer is in the same plane as a side surface of the substrate.

[0340] Example 14. The display device according to Example 13, wherein a side surface of the insulating layer is in the same plane as a side surface of the upper pad and / or a side surface of the signal line.

[0341] Example 15. The display device according to any one of Examples 8 to 14, wherein each of the upper pads is a part of a corresponding one of the plurality of signal lines.

[0342] Example 16. The display device according to any one of Examples 8 to 15 further includes an electrostatic discharge circuit disposed on the substrate and overlapping with the plurality of upper pads.

[0343] Example 17. The display device according to any one of the foregoing examples further includes a plurality of lower pads located on a lower surface of the substrate, and each lower pad is electrically connected to a corresponding one of the plurality of connection lines,

[0344] wherein an end portion of the lower pad is disposed inside an end portion of the substrate.

[0345] Example 18. The display device according to any one of the foregoing examples further includes:

[0346] a plurality of upper pads disposed on the substrate, and each upper pad is connected to a corresponding one of the signal lines; and

[0347] a plurality of lower pads disposed below the substrate, and each lower pad overlaps with a corresponding one of the plurality of upper pads,

[0348] wherein a side line electrically connects the lower pad to the upper pad and / or the plurality of signal lines.

[0349] Example 19. The display device according to any one of the foregoing examples further includes a side insulating layer configured to cover the plurality of side lines, and optionally, wherein the side insulating layer includes a light-blocking material.

[0350] Example 20. The display device according to any one of the foregoing examples, wherein each signal line includes at least two overlapping signal line layers connected in parallel with each other.

[0351] Example 21. The display device according to any one of the foregoing examples further includes a first insulating layer disposed between each adjacent pair of the at least two overlapping signal line layers.

[0352] Example 22. The display device according to Example 21, wherein the first insulating layer includes a first through hole that accommodates corresponding connection portions connecting a pair of adjacent ones.

[0353] Example 23. The display device according to any one of the foregoing examples, further including a plurality of upper pads, wherein each signal line is electrically connected to a corresponding upper pad, and optionally, each signal line is electrically connected to the corresponding upper pad in parallel.

[0354] Example 24. The display device according to any one of the foregoing examples, further including a second insulating layer disposed between the upper pad and the signal line, wherein the second insulating layer includes a second through hole that accommodates a connection portion connecting the signal line and the upper pad.

[0355] Example 25. The display device according to any one of the foregoing examples, further including a bank portion disposed on the substrate, and optionally, wherein the bank portion includes a light-blocking material, and optionally, the bank portion includes a black material.

[0356] Example 26. The display device according to any one of the foregoing examples, wherein each of the plurality of light-emitting elements is a micro LED including an inorganic active layer.

[0357] Example 27. The display device according to any one of the foregoing examples, wherein each of the plurality of light-emitting elements includes:

[0358] an n-type layer;

[0359] an active layer on the n-type layer;

[0360] a p-type layer on the active layer;

[0361] an n electrode on the n-type layer; and

[0362] a p electrode on the p-type layer,

[0363] wherein the p electrode and the n electrode are arranged to be spaced apart from each other at different heights.

[0364] Example 28. The display device according to Example 27, further including:

[0365] a first electrode connected to the n electrode; and

[0366] a second electrode connected to the p electrode.

[0367] Example 29. The display device according to Example 28, further including:

[0368] a first planarization layer;

[0369] a second planarization layer located on the first planarization layer; and

[0370] A third planarization layer, located on the second planarization layer,

[0371] wherein the first electrode and the second electrode are spaced apart from each other and the third planarization layer is disposed between the first electrode and the second electrode.

[0372] Example 30. The display device according to Example 29, wherein the second planarization layer and the third planarization layer are in contact with each other in a region between the first electrode and the second electrode.

[0373] Example 31. The display device according to any one of Examples 28 to 30, further comprising:

[0374] Bank portions, located on the first electrode and the second electrode; and

[0375] A plurality of upper pads, disposed on the substrate,

[0376] wherein the bank portions overlap at least a part of at least one of the upper pads. Optionally, wherein the bank portions comprise a light-blocking material. Optionally, wherein the light-blocking material is a black material.

[0377] Example 32. The display device according to any one of Examples 26 to 31, further comprising a reflective layer overlapping each of the light-emitting elements, wherein the light-emitting elements overlap the reflective layer.

[0378] Example 33. The display device according to any of the foregoing examples, further comprising an electrostatic discharge circuit, the electrostatic discharge circuit being disposed on the substrate and configured to selectively connect a signal line to a ground line, and

[0379] wherein the electrostatic discharge circuit is electrically connected to the signal line via a side line,

[0380] Optionally, wherein the electrostatic discharge circuit is disposed in a region between the upper pad and the display area where the light-emitting elements are disposed.

[0381] Example 34. A method of manufacturing a display device, comprising:

[0382] Providing a display panel, the display panel comprising: a substrate; a plurality of sub-pixels disposed on the substrate; a plurality of signal lines disposed on the substrate, each signal line being electrically connected to one or more sub-pixels; a plurality of connection lines disposed under the substrate, wherein a part of the substrate protrudes beyond the ends of the plurality of signal lines;

[0383] Removing at least the part of the substrate to provide a planar side surface of the display panel including the side surface of the substrate and the side surface of each signal line that lies in the same plane as the side surface of the substrate;

[0384] Deposit a plurality of side lines on a side surface of the display panel.

[0385] Example 35. The method according to Example 34, wherein depositing a plurality of side lines includes depositing a plurality of side lines by pad printing using a conductive ink.

[0386] Example 36. The method according to Example 34 or 35, wherein removing at least that portion of the substrate includes grinding a protruding portion of the substrate, optionally further including grinding the substrate other than the protruding portion, and optionally further including grinding the signal lines.

[0387] Example 37. The method according to Example 34 or 35, further including removing an end portion of the substrate other than the protruding portion, and optionally further including removing an end portion of the signal lines.

Claims

1. A display device, comprising: a substrate; a plurality of light-emitting elements disposed on the substrate; a plurality of transistors disposed on the substrate; a plurality of signal lines disposed on the substrate; a plurality of connection lines disposed under the substrate; and a plurality of upper pads disposed on the substrate, wherein each of the upper pads overlaps with one of the plurality of signal lines and / or one of the plurality of transistors.

2. The display device according to claim 1, wherein an edge of the display device includes a plane, and the substrate and the signal lines terminate at the plane.

3. The display device according to claim 1 or 2, further comprising a plurality of side lines disposed on a side surface of the substrate, each side line providing at least a part of an electrical connection between a corresponding one of the plurality of connection lines and a corresponding one of the plurality of signal lines.

4. The display device according to claim 3, wherein the side line contacts the side surface of the substrate, optionally, the side line contacts the lower surface of the substrate.

5. The display device according to claim 3 or 4, further comprising: a plurality of lower pads disposed under the substrate, each lower pad overlapping with a corresponding one of the plurality of upper pads, wherein the side line electrically connects the lower pad to the upper pad and / or the signal line.

6. The display device according to any one of claims 3 to 5, further comprising a side insulating layer disposed to cover the plurality of side lines, optionally, wherein the side insulating layer includes a light-blocking material, optionally, the side insulating layer includes a black material.

7. The display device according to any one of claims 3 to 6, wherein a part of the side surface of the substrate is an inclined surface inclined with respect to an upper surface of the substrate, and wherein the plurality of side lines partially cover the side surface, and optionally, the plurality of side lines partially cover the lower surface of the substrate.

8. The display device according to claim 7, wherein the substrate includes a first substrate and a second substrate located under the first substrate, and wherein a part of the side surface of the second substrate forms at least a part of the inclined surface.

9. The display device according to any one of claims 3 to 8, wherein each side line contacts a corresponding one of the plurality of upper pads and / or a corresponding one of the plurality of signal lines.

10. The display device according to any one of the foregoing claims, wherein each upper pad is electrically connected to a corresponding one of the plurality of signal lines, and / or wherein a side surface of the upper pad is in the same plane as a side surface of the signal line.

11. The display device according to any one of the foregoing claims, further comprising a plurality of lower pads located on a lower surface of the substrate, each lower pad being electrically connected to a corresponding one of the plurality of connection lines, wherein each of the lower pads overlaps with a corresponding one of the plurality of upper pads, and / or wherein an end of the lower pad is disposed inside an end of the substrate.

12. The display device according to any one of the preceding claims further comprises a plurality of insulating layers, the plurality of insulating layers being located on the substrate and disposed above or below the upper pad and / or the signal line, wherein, a side surface of the insulating layer is in the same plane as a side surface of the substrate and / or a side surface of the upper pad.

13. The display device according to any one of the preceding claims, wherein, each of the light-emitting elements is a micro LED including an inorganic active layer, and / or wherein each of the light-emitting elements comprises: an n-type layer; an active layer on the n-type layer; a p-type layer on the active layer; an n electrode on the n-type layer; and a p electrode on the p-type layer, wherein the p electrode and the n electrode are arranged to be spaced apart from each other at different heights.

14. The display device according to claim 13 further comprises: a first electrode connected to the n electrode; and a second electrode connected to the p electrode.

15. The display device according to claim 14 further comprises: a first planarization layer; a second planarization layer located on the first planarization layer; and a third planarization layer located on the second planarization layer, wherein the first electrode and the second electrode are spaced apart from each other and the third planarization layer is disposed between the first electrode and the second electrode, optionally, wherein the second planarization layer and the third planarization layer are in contact with each other in a region between the first electrode and the second electrode.

16. The display device according to claim 14 or 15 further comprises a bank, the bank being located on the first electrode and the second electrode, wherein, the bank overlaps at least a part of at least one of the upper pads, optionally, wherein the bank comprises a light-blocking material, optionally, wherein the light-blocking material is a black material.

17. The display device according to any one of claims 13 to 16 further comprises a reflective layer corresponding to each of the light-emitting elements, wherein, the light-emitting element overlaps with the reflective layer.

18. The display device according to any one of the preceding claims further comprises an electrostatic discharge circuit, the electrostatic discharge circuit being disposed on the substrate and configured to selectively connect the signal line to the ground wire, wherein, the electrostatic discharge circuit is disposed in a region between the plurality of upper pads and a display area provided with a plurality of sub-pixels, or wherein the electrostatic discharge circuit overlaps with the plurality of upper pads.

19. The display device according to any one of the preceding claims, wherein, each of the signal lines comprises at least two overlapping signal line layers connected in parallel to each other, optionally, wherein the display device further comprises an insulating layer disposed between each adjacent pair of the at least two overlapping signal line layers, wherein the insulating layer comprises a through hole accommodating a corresponding connection portion connecting the adjacent pair of signal line layers.

20. The display device according to any one of the preceding claims, wherein, each signal line is electrically connected in parallel to a corresponding upper pad, Optionally, the display device further includes an insulating layer disposed between the upper pad and the signal line, wherein the insulating layer includes a through hole accommodating a connection portion connecting the signal line and the upper pad.

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