Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a display area, the display area comprises a plurality of data signal lines, a plurality of initial signal connection lines, a plurality of first fan-out lines and a plurality of first power supply lines on a substrate, the plurality of data signal lines, the plurality of initial signal connection lines, the plurality of first fan-out lines and the plurality of first power supply lines are arranged along a first direction and extend along a second direction; wherein at least one initial signal connection line and at least one first fan-out line are located between two adjacent data signal lines, and the two adjacent data signal lines are located between two adjacent first power supply lines, and the data signal lines, the initial signal connection lines, the first power supply lines and the first fan-out lines are located in the same conductive layer, which can optimize the layout of the wires, increase the distance between the adjacent wires and avoid signal crosstalk.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost.

[0003] Currently, there is a problem of signal crosstalk in some areas of the display area of ​​the display substrate. Summary of the Invention

[0004] This disclosure provides a display substrate and a display device that can solve the problem of local signal crosstalk in the display area of ​​existing display substrates.

[0005] On one hand, embodiments of this disclosure provide a display substrate, including a display area and a bonding area located on one side of the display area; the display area includes:

[0006] Base;

[0007] Multiple data signal lines are located on the substrate, the multiple data signal lines are spaced apart along a first direction and extend along a second direction; the first direction and the second direction intersect and the plane formed by them is parallel to the plane of the substrate;

[0008] Multiple initial signal connection lines are located on the substrate, the multiple initial signal connection lines are spaced apart along the first direction and extend along the second direction;

[0009] A plurality of first fan-out lines located on the substrate, the plurality of first fan-out lines being spaced apart along the first direction and extending along the second direction, and the first fan-out lines being connected to the data signal lines; and

[0010] The substrate contains multiple first power lines and multiple pixel driving circuits, the multiple first power lines being arranged along the first direction and extending along the second direction, and the first power lines being configured to provide a high-level signal to the pixel driving circuits;

[0011] Wherein, at least one of the initial signal connection lines and at least one of the first fan-out lines are located between two adjacent data signal lines, and the two data signal lines are located between two adjacent first power lines, and the data signal lines, the initial signal connection lines, the first fan-out lines and the first power lines are located on the same conductive layer.

[0012] In some exemplary embodiments, the display area further includes at least one of a first initial signal line, a second initial signal line, and a third initial signal line, wherein the first initial signal line, the second initial signal line, and the third initial signal line all extend along the first direction; the plurality of initial signal connection lines include at least one of the first initial signal connection line, the second initial signal connection line, and the third initial signal connection line.

[0013] The first initial signal line is connected to the first initial signal connection line to form a mesh structure for transmitting the first initial signal; the second initial signal line is connected to the second initial signal connection line to form a mesh structure for transmitting the second initial signal; the third initial signal line is connected to the third initial signal connection line to form a mesh structure for transmitting the third initial signal.

[0014] In some exemplary embodiments, the first initial signal connection line, the second initial signal connection line, the third initial signal connection line, and the second initial signal connection line are arranged alternately along the first direction.

[0015] In some exemplary embodiments, the first power cord includes an extension portion and a pad portion connected together, and the extension portion extends along the second direction, wherein the pad portions of at least two adjacent first power cords are an integral structure connected to each other.

[0016] The display area further includes multiple light-emitting devices, and the multiple light-emitting devices are located on the side of the multiple first power lines away from the substrate; the light-emitting devices include anodes, organic light-emitting layers and cathodes stacked together, the anodes are closer to the substrate than the cathodes, and the anodes are connected to the pixel driving circuit; wherein, at least one anode and at least one pad portion that is interconnected as an integral structure at least partially overlap in orthographic projection on the plane where the substrate is located.

[0017] In some exemplary embodiments, the pixel driving circuit includes a compensation transistor, and the compensation transistor is a dual-gate transistor; the display area further includes at least one first shielding electrode, and the active layer between the first shielding electrode and the two gate electrodes of the compensation transistor at least partially overlaps the orthographic projection of the substrate onto the plane.

[0018] In some exemplary embodiments, the display area further includes a first initial signal line and at least one second shielding electrode; the pixel driving circuit includes a first initialization transistor and a compensation transistor, the first electrode of the first initialization transistor is connected to the first initial signal line, and the first electrode of the compensation transistor is connected to the second electrode of the first initialization transistor; the second shielding electrode and the active layer between the second electrode and the gate electrode of the first initialization transistor at least partially overlap in the orthographic projection of the substrate plane, and the second shielding electrode and the first initial signal line are an integral structure interconnected.

[0019] In some exemplary embodiments, the display area further includes a first initial signal line and at least one third shielding electrode. The pixel driving circuit includes a first initialization transistor and a data writing transistor. The first electrode of the first initialization transistor is connected to the first initial signal line, and the first electrode of the data writing transistor is connected to the data signal line. At least a portion of the third shielding electrode is projected onto the plane of the substrate between the second electrode of the first initialization transistor and the first electrode of the data writing transistor projected onto the plane of the substrate. The third shielding electrode and the first initial signal line are an integral structure interconnected.

[0020] In some exemplary embodiments, the display area further includes a first initial signal line, a second initial signal line, and a third initial signal line; the first initial signal line and the third initial signal line are located in the same conductive layer, and the second initial signal line and the first initial signal line are located in different conductive layers; the first initial signal line, the second initial signal line, and the initial signal connection line are located in different conductive layers.

[0021] In some exemplary embodiments, the plurality of initial signal connection lines include a first initial signal connection line; the display area further includes at least one first connection electrode, and the first connection electrode and the second initial signal line are located in the same conductive layer, and the first connection electrode and the first initial signal line overlap in the orthographic projection portion of the plane where the substrate is located;

[0022] The first connecting electrode includes a first segment, a second segment, and a third segment connected to each other. The first segment and the third segment both extend along the second direction, the second segment extends along the first direction, and the second segment is located between the first segment and the third segment. The first segment is connected to the first initial signal line, and the third segment is connected to the first initial signal connection line.

[0023] In some exemplary embodiments, the plurality of initial signal connection lines include a second initial signal connection line; the display area further includes at least one second connection electrode, and the second connection electrode and the second initial signal line are located in the same conductive layer;

[0024] The second connection electrode extends along the second direction and includes a first end and a second end disposed opposite to each other. The first end is connected to the second initial signal line, and the second end is located on the side of the second initial signal line opposite to the second direction. The second end is also connected to the second initial signal connection line.

[0025] In some exemplary embodiments, the plurality of initial signal connection lines include a third initial signal connection line; the display area further includes at least one third connection electrode, and the third connection electrode and the second initial signal line are located in the same conductive layer; the orthographic projections of the third connection electrode and the third initial signal line onto the plane of the substrate at least partially overlap;

[0026] The third connection electrode extends along the first direction and includes a first end, a second end, and a middle portion located between the first end and the second end, the middle portion being connected to the third initial signal line, and the first end being connected to the third initial signal connection line.

[0027] On the other hand, embodiments of this disclosure provide a display device including the display substrate described in any of the foregoing embodiments.

[0028] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings. Attached Figure Description

[0029] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0030] Figure 1 This is a schematic diagram of the structure of a display device;

[0031] Figure 2 This is a schematic diagram of a planar structure of a display substrate;

[0032] Figure 3 This is a schematic diagram of a cross-sectional structure of a display substrate;

[0033] Figure 4 This is an equivalent circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure;

[0034] Figure 5 This is a partial planar structure schematic diagram of a display substrate according to an embodiment of the present disclosure;

[0035] Figure 6 This is a schematic diagram of a display substrate after a semiconductor layer pattern has been formed, according to an embodiment of the present disclosure.

[0036] Figure 7A and Figure 7B This is a schematic diagram of a display substrate after the formation of a first conductive layer pattern according to an embodiment of the present disclosure;

[0037] Figure 8A and Figure 8B This is a schematic diagram of a display substrate after the formation of a second conductive layer pattern according to an embodiment of the present disclosure;

[0038] Figure 9A and Figure 9B This is a schematic diagram of a display substrate after the formation of a third conductive layer pattern according to an embodiment of the present disclosure;

[0039] Figure 10A and Figure 10B This is a schematic diagram of a display substrate after the formation of a fourth conductive layer pattern according to an embodiment of the present disclosure;

[0040] Figure 11 This is a schematic diagram of a display substrate after an anode conductive layer pattern has been formed, according to an embodiment of the present disclosure.

[0041] Figure 12 This is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an embodiment of the present disclosure. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0043] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0044] The ordinal numbers such as "first," "second," and "third" in this disclosure are used to avoid confusion among the constituent elements, not to limit the quantity. "Multiple" in this disclosure includes two or more quantities.

[0045] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0046] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0047] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0048] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0049] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components having one or more functions.

[0050] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore can include a state in which the angle is greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore can include a state in which the angle is greater than or equal to 85° and less than 95°.

[0051] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0052] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0053] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, clock signals, scan start signals, etc., of specifications suitable for the scan driver to the scan driver, and clock signals, transmit stop signals, etc., of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, the light-emitting driver can sequentially provide transmit signals with cutoff level pulses to the light-emitting signal lines E1 to Eo. For example, the light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0054] Figure 2This is a schematic diagram of a planar structure of a display substrate. In an exemplary embodiment, the display substrate may include a display area and a border area surrounding the display area. Figure 2 As shown, the display area of ​​the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting unit may include at least a light-emitting device, which is connected to the pixel driving circuit of the sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0055] In some exemplary embodiments, at least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, and two third sub-pixels P3, arranged in the order of first sub-pixel P1, third sub-pixel P3, second sub-pixel P2, and third sub-pixel P3. The first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 may be a green sub-pixel (G) emitting green light. In exemplary embodiments, the shape of the sub-pixels may be rectangular, rhomboid, pentagonal, or hexagonal.

[0056] Figure 3 This is a cross-sectional structural diagram of a display substrate, illustrating the structure of three sub-pixels within the substrate. Figure 3 As shown, on a plane perpendicular to the display substrate, the display area of ​​the display substrate may include a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0057] In some exemplary embodiments, the substrate 101 may be a flexible substrate or a rigid substrate. The rigid substrate may be one or more of glass and quartz, while the flexible substrate may be one or more of polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers, among others.

[0058] In some exemplary embodiments, the driving circuit layer 102 may include multiple circuit units, each of which may include at least a pixel driving circuit, and the pixel driving circuit may include multiple transistors and a storage capacitor. The light-emitting structure layer 103 may include multiple light-emitting units, each of which may include at least a light-emitting device. The light-emitting device may include an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and the cathode.

[0059] In some exemplary embodiments, the encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0060] In some exemplary embodiments, the organic light-emitting layer may include a light-emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0061] Figure 4 This is an equivalent circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure. Figure 4 As shown, in an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C, or 9T2C structure, etc. Figure 4 As shown, the pixel driving circuit of the exemplary embodiment of this disclosure can be an 8T1C structure, which may include 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C. The pixel driving circuit is connected to 9 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, light emission signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA and first power supply line VDD).

[0062] In some exemplary embodiments, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second terminal of a first transistor, the first terminal of a second transistor T2, the gate electrode of a third transistor T3, and the first terminal of a storage capacitor C. The second node N2 is connected to the first terminal of a third transistor T3, the second terminal of an eighth transistor T8, the second terminal of a fifth transistor T5, and the second terminal of a fourth transistor T4. The third node N3 is connected to the second terminals of a second transistor T2, a third transistor T3, and a sixth transistor T6. The fourth node N4 is connected to the second terminals of a sixth transistor T6 and a seventh transistor T7. The first terminal (first plate) of the storage capacitor C is connected to the first node N1, and the second terminal (second plate) of the storage capacitor C is connected to the first terminal of the fifth transistor T5.

[0063] In some exemplary embodiments, the gate electrode of the first transistor T1 is connected to the third scan signal line S3, the first terminal of the first transistor T1 is connected to the first initial signal line INIT1, and the second terminal of the first transistor T1 is connected to the first node N1. The gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first terminal of the second transistor T2 is connected to the first node N1, and the second terminal of the second transistor T2 is connected to the third node N3. The gate electrode of the third transistor T3 is connected to the first node N1, that is, the gate electrode of the third transistor T3 is connected to the first terminal of the storage capacitor C, the first terminal of the third transistor T3 is connected to the second node N2, and the second terminal of the third transistor T3 is connected to the third node N3. The gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first terminal of the fourth transistor T4 is connected to the data signal line DATA, and the second terminal of the fourth transistor T4 is connected to the second node N2. The gate electrode of the fifth transistor T5 is connected to the light emission signal line EM, the first terminal of the fifth transistor T5 is connected to the first power supply line VDD, and the second terminal of the fifth transistor T5 is connected to the second node N2. The gate electrode of the sixth transistor T6 is connected to the light-emitting signal line EM, the first terminal of the sixth transistor T6 is connected to the third node N3, and the second terminal of the sixth transistor T6 is connected to the fourth node N4. The gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first terminal of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second terminal of the seventh transistor T7 is connected to the fourth node N4. The gate electrode of the eighth transistor T8 is connected to the second scan signal line S2, the first terminal of the eighth transistor T8 is connected to the third initial signal line INIT3, and the second terminal of the eighth transistor T8 is connected to the second node N2.

[0064] In some exemplary embodiments, the first transistor T1 can be referred to as the first initialization transistor, the second transistor T2 can be referred to as the compensation transistor, the third transistor T3 can be referred to as the driving transistor, the fourth transistor T4 can be referred to as the data writing transistor, the fifth transistor T5 can be referred to as the first light-emitting transistor, the sixth transistor T6 can be referred to as the second light-emitting transistor, the seventh transistor T7 can be referred to as the second initialization transistor, and the eighth transistor T8 can be referred to as the third initialization transistor.

[0065] In some exemplary embodiments, the light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode). The first electrode of the light-emitting device EL is connected to a fourth node N4, and the second electrode of the light-emitting device EL is connected to a second power line VSS. The signal of the second power line VSS is a continuously provided low-level signal, and the signal of the first power line VDD is a continuously provided high-level signal.

[0066] In some exemplary embodiments, the first transistor T1 to the eighth transistor T8 can be P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include both P-type and N-type transistors.

[0067] In some exemplary embodiments, the first transistor T1 to the eighth transistor T8 can be a low-temperature polysilicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS thin-film transistor is made of low-temperature polysilicon (LTPS), while the active layer of the oxide thin-film transistor is made of oxide semiconductor. LTPS thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0068] Figure 5 This is a partial planar structural diagram of a display substrate according to an embodiment of the present disclosure. The display substrate may include a display area, a bonding area located on one side of the display area, and a border area located on other sides of the display area. Figure 5As shown, the display substrate can adopt a fanout-in-panel (FIP) structure. Multiple data fanout lines can be arranged in the display area. One end of each data fanout line is connected to a corresponding data signal line in the display area, and the other end is located in the bonding area, connected to the integrated circuit via multiple data leads. Since the bonding area reduces the number of diagonal traces in the fan shape, it narrows the bottom bezel of the display substrate, which is beneficial for narrow bezel design. The data fanout lines can include a first fanout line 40 and a second fanout line 30 connected together. The first fanout line 40 can extend along a second direction Y, and the second fanout line 30 can extend along a first direction X. For example, both the first fanout line 40 and the second fanout line 30 include a first end and a second end arranged opposite each other. The first end of the second fanout line 30 is connected to the data signal line DATA, and the second end of the second fanout line 30 is connected to the first end of the first fanout line 40. The second end of the first fanout line 40 can be located in the bonding area.

[0069] like Figure 5 As shown, the display area may include multiple circuit unit rows (only the Mth and M+1th unit rows are shown) and multiple circuit unit columns (only the Nth and N+1th to N+7th unit columns are shown). Each circuit unit row includes multiple circuit units arranged sequentially along a first direction X, and each circuit unit column includes multiple circuit units arranged sequentially along a second direction Y. The multiple circuit unit rows and columns constitute an array of circuit units. Within the same circuit unit column, a data signal line DATA is connected to multiple pixel driving circuits, and the data signal line DATA is configured to provide data signals to the connected pixel driving circuits.

[0070] like Figure 5 As shown, the display area may include multiple data signal lines DATA and multiple initial signal lines. The multiple data signal lines DATA are spaced apart along a first direction X and extend along a second direction Y. The multiple initial signal lines may extend along the first direction X and be spaced apart along the second direction Y. The multiple initial signal lines may include at least a first initial signal line INIT1, a second initial signal line INIT2, and a third initial signal line INIT3, located in the same circuit cell row on the plane of the substrate. The second initial signal line INIT2 is located between the first initial signal line INIT1 and the third initial signal line INIT3. The plane formed by the intersection of the first direction X and the second direction Y is parallel to the plane of the substrate.

[0071] The display area may further include multiple first fan-out lines 40, multiple first power lines VDD, and multiple initial signal connection lines INIT. The multiple first fan-out lines 40 and multiple initial signal connection lines INIT are arranged at intervals along a first direction X and extend along a second direction Y. At least one first fan-out line 40 and at least one initial signal connection line INIT are located between two adjacent data signal lines DATA, and the two adjacent data signal lines DATA are located between two adjacent first power lines VDD. Furthermore, the multiple first fan-out lines 40, multiple initial signal connection lines INIT, multiple first power lines VDD, and multiple data signal lines DATA are located on the same conductive layer. In this embodiment, by placing at least one first fan-out line and at least one initial signal connection line between two adjacent data signal lines, and placing the two adjacent data signal lines between two adjacent first power lines VDD, the overall number of signal lines located on the same conductive layer can be reduced, the distance between two adjacent signal lines can be increased, signal crosstalk can be avoided, and display quality can be improved.

[0072] like Figure 5 As shown, the multiple initial signal connection lines INIT can include at least the first initial signal connection line 41. The first initial signal line INIT1 and the first initial signal connection line 41 are interconnected, forming a mesh structure on the display substrate to transmit the first initial signal. This not only effectively reduces the resistance of the first initial signal line and the voltage drop of the first initial signal, but also effectively improves the uniformity of the first initial signal in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0073] like Figure 5 As shown, the multiple initial signal connection lines INIT can include at least a second initial signal connection line 42. The second initial signal line INIT2 and the second initial signal connection line 42 are interconnected, forming a mesh structure on the display substrate to transmit the second initial signal. This not only effectively reduces the resistance of the second initial signal lines and decreases the voltage drop of the second initial signal, but also effectively improves the uniformity of the second initial signal in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0074] like Figure 5As shown, the multiple initial signal connection lines INIT can include at least a third initial signal connection line 43. The third initial signal line INIT3 and the third initial signal connection line 43 are interconnected, forming a mesh structure on the display substrate to transmit the third initial signal. This not only effectively reduces the resistance of the third initial signal lines and decreases the voltage drop of the third initial signal, but also effectively improves the uniformity of the third initial signal in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0075] like Figure 5 As shown, the first initial signal connection line 41, the second initial signal connection line 42, the third initial signal connection line 43, and the second initial signal connection line 42 can be arranged alternately along the first direction X in a periodic manner, which increases the density of the mesh structure for transmitting the second initial signal. This can match the pixel structure layout of the RGBG of the display substrate. Furthermore, the second initial signal is beneficial for the anode reset of the light-emitting device, which can improve the display quality of the display device.

[0076] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0077] In some exemplary embodiments, taking only the Mth unit row and the M+1th unit row of the display substrate as examples, and taking only the Nth unit column, the N+1th unit column to the N+7th unit column of the display substrate as examples, the fabrication process of the display substrate in the embodiments of this disclosure may include the following operations.

[0078] (11) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film using a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, such as... Figure 6 As shown. The semiconductor layer pattern may include at least the active layers of the first transistor T1 to the eighth transistor T8.

[0079] like Figure 6 As shown, the active layers of two adjacent circuit cell columns can be symmetrically arranged about the boundary line between the two adjacent circuit cell columns. The active layers of the first transistor T1 to the seventh transistor T7 can be an integral structure interconnected. The active layers of the seventh transistor T7 in two adjacent circuit cell columns can be an integral structure interconnected.

[0080] (12) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed; patterning the first conductive film using a patterning process to form a second insulating layer covering the semiconductor layer pattern; and a first conductive layer pattern disposed on the second insulating layer, such as... Figure 7A and Figure 7B As shown, Figure 7B for Figure 7A A schematic diagram of the first conductive layer. In an exemplary embodiment, the first conductive layer may be referred to as the first gate metal (GATE1) layer.

[0081] In some exemplary embodiments, the first conductive layer pattern may include at least a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a light-emitting signal line EM, and a first electrode C11 of a storage capacitor. The main bodies of the first scan signal line S1, the second scan signal line S2, and the third scan signal line S3 may all extend along a first direction X. The first electrode C11 may simultaneously serve as one electrode of the storage capacitor and the gate electrode of the third transistor T3. The region where the third scan signal line S3 overlaps with the active layer of the first transistor T1 serves as the gate electrode of the first transistor T1. The region where the first scan signal line S1 overlaps with the active layer of the second transistor T2 serves as the gate electrode of the second transistor T2 with a dual-gate structure. The region where the first scan signal line S1 overlaps with the active layer of the fourth transistor T4 serves as the gate electrode of the fourth transistor T4. The region where the light-emitting signal line EM overlaps with the active layer of the fifth transistor T5 serves as the gate electrode of the fifth transistor T5. The region where the light-emitting signal line EM overlaps with the active layer of the sixth transistor T6 serves as the gate electrode of the sixth transistor T6. The region where the second scan signal line S2 overlaps with the active layer of the seventh transistor T7 serves as the gate electrode of the seventh transistor T7. The region where the second scan signal line S2 overlaps with the active layer of the eighth transistor T8 serves as the gate electrode of the eighth transistor T8.

[0082] (13) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the third insulating layer, such as... Figure 8A and Figure 8B As shown, Figure 8B for Figure 8A A schematic diagram of the second conductive layer. In an exemplary embodiment, the second conductive layer may be referred to as the second gate metal (GATE2) layer.

[0083] In some exemplary embodiments, the second conductive layer pattern may include at least: a first initial signal line INIT1, a third initial signal line INIT3, and a second electrode C12 of a storage capacitor. The orthographic projection of the second electrode C12 onto the substrate at least partially overlaps with the orthographic projection of the first electrode C11 onto the substrate, and the first electrode C11 and the second electrode C12 constitute the storage capacitor of the pixel driving circuit. The main body portions of the first initial signal line INIT1 and the third initial signal line INIT3 may both extend along the first direction X.

[0084] In some exemplary embodiments, the second conductive layer pattern may include at least: a first shielding electrode 21, a second shielding electrode 22, and a third shielding electrode 23. The first shielding electrode 21 may extend along a second direction Y, and includes a first end and a second end disposed opposite to each other. The first end may be connected to a first initial signal line INIT1, and the second end may be located on one side of the first initial signal line INIT1 in the second direction Y. The orthographic projection of the first shielding electrode 21 on the substrate at least partially overlaps with the orthographic projection of the active layer between the two gate electrodes of the second transistor T2 in this circuit unit on the substrate. The first shielding electrode 21 is configured to shield the second transistor T2 from the influence of data voltage transitions, preventing data voltage transitions from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0085] In some exemplary embodiments, the first shielding electrode 21, the second shielding electrode 22, and the third shielding electrode 23 may be arranged sequentially along a first direction X. The second shielding electrode 22 may extend along a second direction Y. The second shielding electrode 22 may include a first end and a second end disposed opposite to each other, the first end and the second end being located on opposite sides of the first initial signal line INIT1, respectively. The orthographic projection of the second shielding electrode 22 on the substrate at least partially overlaps with the orthographic projection of the active layer between the second electrode and the gate electrode of the first transistor T1 in this circuit unit on the substrate. The second shielding electrode 22 is configured to shield the first transistor T1 from the influence of data voltage transitions, preventing data voltage transitions from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0086] In some exemplary embodiments, the third shielding electrode 23 may extend along the second direction Y. The third shielding electrode 23 includes a first end and a second end disposed opposite to each other. The first end may be connected to the first initial signal line INIT1, and the second end may be located on one side of the first initial signal line INIT1 in the second direction Y. In the plane of the substrate, the second end of the third shielding electrode 23 may be located between the second electrode of the first transistor T1 and the first electrode of the fourth transistor T4 in this circuit unit. The third shielding electrode 23 is configured to shield the first transistor T1 and the fourth transistor T4 from the influence of data voltage transitions, preventing data voltage transitions from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0087] In some exemplary embodiments, the first transistor T1 is a dual-gate transistor, and the orthographic projection of the third initial signal line INIT3 on the substrate at least partially overlaps with the orthographic projection of the active layer between the two gate electrodes of the first transistor T1 on the substrate. A portion of the third initial signal line INIT3 can be used as a shielding electrode to shield the first transistor T1 from the influence of data voltage transitions, preventing data voltage transitions from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0088] (14) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein the fourth insulating layer has a plurality of vias, such as... Figure 9A As shown, the vias are represented by dashed lines.

[0089] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on a fourth insulating layer, such as... Figure 9A and Figure 9B As shown, Figure 9B for Figure 9A A schematic diagram of the third conductive layer. In an exemplary embodiment, the third conductive layer may be referred to as the first source / drain metal (SD1) layer.

[0090] In some exemplary embodiments, the third conductive layer may include at least a second fan-out line 30, a second initial signal line INIT2, and a plurality of connection electrodes, which are configured to enable connections between transistors, between a transistor and a signal line, or between signal lines. The main portions of the second fan-out line 30 and the second initial signal line INIT2 may both extend along a first direction X.

[0091] In some exemplary embodiments, the plurality of connection electrodes may include at least a first connection electrode 31, a second connection electrode 32, and a third connection electrode 33. The orthographic projection of the first connection electrode 31 onto the plane of the substrate overlaps with the orthographic projection of the first initial signal line INIT1 onto the plane of the substrate, and the portion of the orthographic projection of the first connection electrode 31 onto the plane of the substrate is located between the orthographic projections of the first initial signal line INIT1 and the second initial signal line INIT2 onto the plane of the substrate in the same circuit cell row.

[0092] The first connecting electrode 31 may include a first segment 31-1, a second segment 31-2, and a third segment 31-3 connected to each other. The first segment 31-1 and the third segment 31-3 may both extend along a second direction Y, and the second segment 31-2 may extend along a first direction X, with the second segment 31-2 located between the first segment 31-1 and the third segment 31-3. The first segment 31-1 of the first connecting electrode 31 is connected to the first initial signal line INIT1 via a via, and the first connecting electrode 31 is connected to the first terminal of the first transistor T1 via a via. The first connecting electrode 31 may be configured to connect the first initial signal line INIT1 to a subsequently formed first initial signal connection line to form a mesh structure for transmitting the first initial signal. For example, the third segment 31-3 is configured to be connected to the subsequently formed first initial signal connection line.

[0093] In some exemplary embodiments, the orthographic projection of the second connection electrode 32 onto the plane of the substrate lies between the orthographic projections of the first initial signal line INIT1 and the second initial signal line INIT2 on the same circuit cell row onto the plane of the substrate. The second connection electrode 32 may extend along a second direction Y. The second connection electrode 32 includes a first end and a second end disposed opposite to each other. The first end is connected to the second initial signal line INIT2, and the second end is located on the side of the second initial signal line INIT2 opposite to the second direction Y, and is configured to connect to a subsequently formed second initial signal connection line. The second connection electrode 32 may be configured to connect the second initial signal line INIT2 to a subsequently formed second initial signal connection line to achieve the formation of a mesh structure for transmitting the second initial signal.

[0094] In some exemplary embodiments, the orthographic projection of the third connection electrode 33 onto the plane of the substrate at least partially overlaps with the orthographic projection of the third initial signal line INIT3 onto the plane of the substrate, and the third connection electrode 33 may extend along a first direction X. The third connection electrode 33 may include a first end and a second end disposed opposite to each other, the first end being connected to the first electrode of an eighth transistor T8 through a via, the second end being connected to the first electrode of another eighth transistor T8 through a via, and the middle portion of the third connection electrode 33 being connected to the third initial signal line INIT3 through a via. For example, the first end of the third connection electrode 33 is configured to be connected to a subsequently formed third initial signal connection line. The third connection electrode 33 may be configured to connect the third initial signal line INIT3 to a subsequently formed third initial signal connection line to realize the formation of a mesh structure for transmitting the third initial signal.

[0095] (16) Forming a fifth insulating layer pattern. In an exemplary embodiment, forming the fifth insulating layer pattern may include: depositing a fifth insulating film on a substrate on which the aforementioned pattern is formed, patterning the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer, wherein the fifth insulating layer has a plurality of vias, such as... Figure 10A As shown, the vias are represented by dashed lines.

[0096] (17) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on a fifth insulating layer, such as... Figure 10A and Figure 10B As shown, Figure 10B for Figure 10A A schematic diagram of the fourth conductive layer. In an exemplary embodiment, the fourth conductive layer may be referred to as the second source / drain metal (SD2) layer. Subsequently, a planarization layer pattern is formed, on which a plurality of anode vias are provided, exposing portions of the anode connection electrodes, thus completing the fabrication of the drive circuit layer.

[0097] In some exemplary embodiments, the fourth conductive layer may include at least: a data signal line DATA, a first power supply line VDD, a first fan-out line 40, a first initial signal connection line 41, a second initial signal connection line 42, a third initial signal connection line 43, and an anode connection electrode 44. The main portions of the data signal line DATA, the first power supply line VDD, the first fan-out line 40, the first initial signal connection line 41, the second initial signal connection line 42, and the third initial signal connection line 43 may all extend along the second direction Y. The anode connection electrode 44 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 through vias to connect the pixel driving circuit to the subsequently formed light-emitting device.

[0098] In some exemplary embodiments, the first fan-out line 40 is located between two adjacent data signal lines DATA, and one of the first initial signal connection lines 41, 42, and 43 is located between the first fan-out line 40 and two adjacent data signal lines DATA, and the two adjacent data signal lines DATA are located between two adjacent first power lines VDD. In this embodiment, by designing the position of the first fan-out line 40, the first power line VDD can present a large metal pattern, reducing the number of traces in the fourth conductive layer and increasing the distance between adjacent traces in the fourth conductive layer, thereby improving the yield rate of the display substrate. Furthermore, the large metal pattern of the first power line VDD facilitates the diversification of design shapes and the layout of pixel structures. By reducing the width of the first power line VDD along the first direction X and increasing the distance between the first power line VDD and the adjacent data signal lines DATA, the risk of crosstalk caused by the switching of data signal lines DATA can be reduced.

[0099] In some exemplary embodiments, the first power line VDD may include at least an extension portion 45 and a pad portion 46. The main body of the extension portion 45 may be a zigzag line extending along the second direction Y, and may be a zigzag line of non-uniform width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power line VDD and the data signal line DATA. The pad portion 46 may be block-shaped (e.g., rectangular), and may be disposed on one side of the extension portion 45 in the first direction X or on the opposite side of the first direction X, and connected to the extension portion 45. Two partially adjacent pad portions 46 may be disposed facing each other and connected together to form a large metal pattern, which can improve the flatness of the subsequently formed anode and improve the uniformity of light emission from the light-emitting device.

[0100] In some exemplary embodiments, the orthographic projections of the first initial signal connection line 41 and the first connection electrode 31 on the plane of the substrate can partially overlap. The first initial signal connection line 41 can be connected to the first connection electrode 31 through a via. This design realizes the connection between the first initial signal connection line 41 and the first initial signal line INIT1, realizes the mesh structure for transmitting the first initial signal, reduces the load on the first initial signal, and improves the stability of the first initial signal transmission.

[0101] In some exemplary embodiments, the orthographic projections of the second initial signal connection line 42 and the second connection electrode 32 on the plane of the substrate can partially overlap. The second initial signal connection line 42 can be connected to the second connection electrode 32 through a via. This design realizes the connection between the second initial signal connection line 42 and the second initial signal line INIT2, realizes the mesh structure for transmitting the second initial signal, reduces the load on the second initial signal, and improves the stability of the second initial signal transmission.

[0102] In some exemplary embodiments, the orthographic projections of the third initial signal connection line 43 and the third connection electrode 33 on the plane of the substrate can partially overlap. The third initial signal connection line 43 can be connected to the third connection electrode 33 through a via. This design realizes the connection between the third initial signal connection line 43 and the third initial signal line INIT3, realizes the mesh structure for transmitting the third initial signal, reduces the load on the third initial signal, and improves the stability of the third initial signal transmission.

[0103] In some exemplary embodiments, the first initial signal connection line 41, the second initial signal connection line 42, the third initial signal connection line 43, and the second initial signal connection line 42 can be arranged alternately in a periodic manner along the first direction X, which increases the density of the mesh structure for transmitting the second initial signal and can match the pixel structure layout of the RGBG of the display substrate.

[0104] (18) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer may include: depositing an anode conductive film on a substrate on which the aforementioned pattern is formed, patterning the anode conductive film using a patterning process, and forming an anode conductive layer disposed on a planarization layer, such as... Figure 11 As shown. The anode conductive layer includes multiple anodes 50, and the multiple anodes 50 can be connected to the pixel driving circuit of the circuit unit through anode vias K.

[0105] In some exemplary embodiments, the orthographic projections of at least one anode 50 and at least one interconnected pad portion 46 on the plane of the substrate at least partially overlap, which can improve the flatness of the anode 50 and is beneficial to the uniformity of light emission from the light-emitting device.

[0106] (19) A pixel definition layer pattern is formed, wherein a plurality of pixel openings 51 are provided on the pixel definition layer, and the plurality of pixel openings 51 respectively expose at least a portion of the anode 50, such as Figure 12 As shown, Figure 12 The middle pixel definition layer only illustrates the pixel openings. At least one pixel opening 51 at least partially overlaps with the orthographic projection of at least one pad portion 46 onto the plane of the substrate.

[0107] Subsequently, an organic light-emitting layer is formed by vapor deposition or inkjet printing. At least part of the organic light-emitting layer is located within the pixel opening 51. Then, a cathode is formed on the organic light-emitting layer. The cathode, the organic light-emitting layer, and the anode constitute a light-emitting device.

[0108] Subsequently, an encapsulation structure layer is formed, which may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, while the second encapsulation layer may be made of organic materials. The second encapsulation layer is placed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer.

[0109] In this embodiment, by placing the first fan-out line and the initial signal connection line between two adjacent data signal lines, and placing the two adjacent data signal lines between two adjacent first power lines, the number of traces in the second source / drain metal layer can be reduced as a whole, the distance between two adjacent signal lines can be increased, and signal crosstalk can be avoided.

[0110] This embodiment of the disclosure sets up a first initial signal line and a first initial signal connection line, and the first initial signal line and the first initial signal connection line are interconnected, so that the first initial signal line and the first initial signal connection line form a mesh structure on the display substrate for transmitting the first initial signal. This can not only effectively reduce the resistance of the first initial signal line and reduce the voltage drop of the first initial signal, but also effectively improve the uniformity of the first initial signal in the display substrate, effectively improve display uniformity, and improve display quality.

[0111] This embodiment of the disclosure provides a second initial signal line and a second initial signal connection line, which are interconnected. This forms a mesh structure on the display substrate to transmit the second initial signal. This not only effectively reduces the resistance of the second initial signal line and decreases the voltage drop of the second initial signal, but also effectively improves the uniformity of the second initial signal in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0112] This embodiment of the present disclosure sets up a third initial signal line and a third initial signal connection line, and the third initial signal line and the third initial signal connection line are interconnected, so that the third initial signal line and the third initial signal connection line form a mesh structure on the display substrate for transmitting the third initial signal. This can not only effectively reduce the resistance of the third initial signal line and reduce the voltage drop of the third initial signal, but also effectively improve the uniformity of the third initial signal in the display substrate, effectively improve display uniformity, and improve display quality.

[0113] The preparation process disclosed herein is well compatible with existing preparation processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0114] In some exemplary embodiments, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, etc. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0115] In some exemplary embodiments, the first, second, third, and fourth conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the aforementioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first, second, third, fourth, and fifth insulating layers can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers. The first insulating layer is called a buffer layer, the second and third insulating layers are called gate insulating (GI) layers, the fourth insulating layer is called an interlayer insulating (ILD) layer, and the fifth insulating layer is called a passivation (PVX) layer. The planarization layer can be made of organic materials, such as resin. The active layer can be made of amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc. That is, this disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, or organic technology. The structure and fabrication process described above are merely illustrative examples. In exemplary embodiments, the corresponding structure and patterning processes can be modified and added or reduced according to actual needs, and this disclosure does not limit the scope of the invention.

[0116] In some exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0117] This disclosure also provides a display device, which includes the display substrate of any of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

[0118] While the embodiments disclosed in this invention have been described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. It should be noted that the above embodiments or implementation methods are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the content specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. A display substrate, characterized in that, Includes a display area and a binding area located on one side of the display area; the display area includes: Base; Multiple data signal lines are located on the substrate, the multiple data signal lines are spaced apart along a first direction and extend along a second direction; the first direction and the second direction intersect and the plane formed by them is parallel to the plane of the substrate; Multiple initial signal connection lines are located on the substrate, the multiple initial signal connection lines are spaced apart along the first direction and extend along the second direction; A plurality of first fan-out lines located on the substrate, the plurality of first fan-out lines being spaced apart along the first direction and extending along the second direction, and the first fan-out lines being connected to the data signal lines; and The substrate includes multiple first power lines and multiple pixel driving circuits, the multiple first power lines being arranged along a first direction and extending along a second direction, and the first power lines being configured to provide a high-level signal to the pixel driving circuits; the pixel driving circuits include compensation transistors, and the compensation transistors are dual-gate transistors; the display area also includes at least one first shielding electrode, and the active layer between the first shielding electrode and the two gate electrodes of the compensation transistor at least partially overlaps the orthographic projection of the layer on the plane of the substrate; Wherein, at least one of the initial signal connection lines and at least one of the first fan-out lines are located between two adjacent data signal lines, and the two data signal lines are located between two adjacent first power lines, and the data signal lines, the initial signal connection lines, the first fan-out lines and the first power lines are located on the same conductive layer.

2. The display substrate as described in claim 1, characterized in that, The display area further includes at least one of a first initial signal line, a second initial signal line, and a third initial signal line, wherein the first initial signal line, the second initial signal line, and the third initial signal line all extend along the first direction; the plurality of initial signal connection lines include at least one of a first initial signal connection line, a second initial signal connection line, and a third initial signal connection line. The first initial signal line is connected to the first initial signal connection line to form a mesh structure for transmitting the first initial signal; the second initial signal line is connected to the second initial signal connection line to form a mesh structure for transmitting the second initial signal; the third initial signal line is connected to the third initial signal connection line to form a mesh structure for transmitting the third initial signal.

3. The display substrate as described in claim 2, characterized in that, The first initial signal connection line, the second initial signal connection line, the third initial signal connection line, and the second initial signal connection line are arranged alternately along the first direction.

4. The display substrate as described in claim 1, characterized in that, The first power cord includes an extension portion and a pad portion connected together, and the extension portion extends along the second direction. The pad portions of at least two adjacent first power cords are an integral structure connected to each other. The display area further includes multiple light-emitting devices, and the multiple light-emitting devices are located on the side of the multiple first power lines away from the substrate; the light-emitting devices include anodes, organic light-emitting layers and cathodes stacked together, the anodes are closer to the substrate than the cathodes, and the anodes are connected to the pixel driving circuit; wherein, at least one anode and at least one pad portion that is interconnected as an integral structure at least partially overlap in orthographic projection on the plane where the substrate is located.

5. The display substrate according to any one of claims 1 to 4, characterized in that, The display area further includes a first initial signal line and at least one second shielding electrode; the pixel driving circuit includes a first initialization transistor, the first electrode of the first initialization transistor is connected to the first initial signal line, and the first electrode of the compensation transistor is connected to the second electrode of the first initialization transistor; the second shielding electrode and the active layer between the second electrode and the gate electrode of the first initialization transistor at least partially overlap in the orthographic projection of the substrate plane, and the second shielding electrode and the first initial signal line are an integral structure interconnected.

6. The display substrate according to any one of claims 1 to 4, characterized in that, The display area further includes a first initial signal line and at least one third shielding electrode. The pixel driving circuit includes a first initialization transistor and a data writing transistor. The first electrode of the first initialization transistor is connected to the first initial signal line, and the first electrode of the data writing transistor is connected to the data signal line. At least a portion of the third shielding electrode is projected onto the plane of the substrate between the second electrode of the first initialization transistor and the first electrode of the data writing transistor projected onto the plane of the substrate. The third shielding electrode and the first initial signal line are an integral structure interconnected.

7. The display substrate according to any one of claims 1 to 4, characterized in that, The display area further includes a first initial signal line, a second initial signal line, and a third initial signal line; the first initial signal line and the third initial signal line are located in the same conductive layer, and the second initial signal line and the first initial signal line are located in different conductive layers; the first initial signal line, the second initial signal line, and the initial signal connection line are located in different conductive layers.

8. The display substrate as described in claim 7, characterized in that, The plurality of initial signal connection lines include a first initial signal connection line; the display area also includes at least one first connection electrode, and the first connection electrode and the second initial signal line are located in the same conductive layer, and the first connection electrode and the first initial signal line overlap in the orthographic projection portion of the plane where the substrate is located; The first connecting electrode includes a first segment, a second segment, and a third segment connected to each other. The first segment and the third segment both extend along the second direction, the second segment extends along the first direction, and the second segment is located between the first segment and the third segment. The first segment is connected to the first initial signal line, and the third segment is connected to the first initial signal connection line.

9. The display substrate as described in claim 7, characterized in that, The plurality of initial signal connection lines include a second initial signal connection line; the display area further includes at least one second connection electrode, and the second connection electrode and the second initial signal line are located in the same conductive layer; The second connection electrode extends along the second direction and includes a first end and a second end disposed opposite to each other. The first end is connected to the second initial signal line, and the second end is located on the side of the second initial signal line opposite to the second direction. The second end is also connected to the second initial signal connection line.

10. The display substrate as claimed in claim 7, characterized in that, The plurality of initial signal connection lines include a third initial signal connection line; the display area further includes at least one third connection electrode, and the third connection electrode and the second initial signal line are located in the same conductive layer; the orthographic projections of the third connection electrode and the third initial signal line on the plane where the substrate is located at least partially overlap; The third connection electrode extends along the first direction and includes a first end, a second end, and a middle portion located between the first end and the second end, the middle portion being connected to the third initial signal line, and the first end being connected to the third initial signal connection line.

11. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 10.

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