Display panel and display device

Abstract

The present disclosure relates to the technical field of display, and discloses a display panel and a display device. The display area of the display panel comprises a first reference voltage line and a second reference voltage line electrically connected, the first reference voltage line extends along a first direction, and the second reference voltage line extends along a second direction; the display area further comprises a first conducting line extending along the first direction; the display panel comprises a substrate, a first metal layer, a capacitor metal layer, a second metal layer and a third metal layer; the first reference voltage line is located in the capacitor metal layer, and the first conducting line is located in the second metal layer; the same second reference voltage line comprises a first sub-section and a second sub-section electrically connected, the first sub-section is located in the second metal layer, the second sub-section partially overlaps with the first conducting line in the projection of the substrate, and the second sub-section is located between the second metal layer and the substrate. The display device comprises the above display panel. The present disclosure can optimize the layout space of the pixel, improve the pixel density, and realize high-resolution display.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) display panels are widely used due to their self-emissive nature, low driving voltage, and fast response. In display panels, pixel circuits provide the driving current required for the display to the light-emitting elements and control whether the light-emitting elements enter the light-emitting stage, thus becoming an indispensable component in most self-emissive display panels.

[0003] With the development of display technology, users have increasingly higher requirements for the image quality of display panels. High-end monitors and gaming monitors need to have high pixel density (Pixels Per Inch, the number of pixels contained in each inch of screen) and high resolution (higher resolution usually means higher pixel density). However, existing pixel circuits have more components and more complex layout space design, resulting in a larger layout area occupied by the pixel circuits. The higher the number of pixels per inch, the tighter the layout space of the pixel circuits becomes, and the higher the requirements for process precision, which is not conducive to the realization of high pixel density and high resolution displays.

[0004] Therefore, providing a display panel and display device that can optimize the pixel layout space in a display device, increase pixel density, and facilitate high-resolution display is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] To address the aforementioned technical problems, this disclosure provides a display panel and a display device to solve the problem that existing display devices cannot further optimize the layout space of pixel circuits and improve pixel density.

[0006] This disclosure provides a display panel, including: a display area;

[0007] The display area includes a first reference voltage line and a second reference voltage line that are electrically connected. The first reference voltage line extends along a first direction, and the second reference voltage line extends along a second direction. The first direction and the second direction intersect in a direction parallel to the plane of the display panel.

[0008] The display area also includes a first wire, which extends along a first direction;

[0009] The display panel includes a substrate and a first metal layer, a capacitor metal layer, a second metal layer and a third metal layer located on one side of the substrate;

[0010] The first reference voltage line is located in the capacitor metal layer, and the first wire is located in the second metal layer;

[0011] The same second reference voltage line includes a first sub-segment and a second sub-segment that are electrically connected. The first sub-segment is located in the second metal layer, and the orthographic projection of the second sub-segment onto the substrate overlaps with the orthographic projection of the first wire onto the substrate.

[0012] The second segment is located between the second metal layer and the substrate.

[0013] Based on the same inventive concept, this disclosure also provides a display device, which includes the above-described display panel.

[0014] The technical solution provided in this disclosure has the following advantages compared with the prior art:

[0015] This disclosure provides a display area for a display panel that includes a first reference voltage line extending along a first direction, the first reference voltage line being located in a capacitor metal layer. It also includes a second reference voltage line, which is on a different layer from the first reference voltage line and electrically connected to it. The second reference voltage line intersects with the first reference voltage line to form a grid structure. The display area further includes a first conductive line extending along the first direction. The same second reference voltage line includes an electrically connected first segment and a second segment. The first segment is located in a second metal layer. The orthographic projection of the second segment onto the substrate overlaps with the orthographic projection of the first conductive line onto the substrate. That is, the second segment can be understood as a cross-line structure where the second reference voltage line runs to the vicinity of the first conductive line. The second segment is located between the second metal layer and the substrate, meaning the second segment can be fabricated using any metal layer on the side of the second metal layer facing the substrate. This disclosure uses any metal layer on the side of the second metal layer facing the substrate to make the crossing portion of the second reference voltage line, i.e., the second sub-segment. Then, the via for electrically connecting one end of the second sub-segment to the first sub-segment of the second metal layer can be opened in any inorganic layer on the side of the second metal layer facing the substrate. After the second sub-segment crosses the first conductor, the via for electrically connecting the other end of the second sub-segment to the other first sub-segment of the second metal layer can also be opened in any inorganic layer on the side of the second metal layer facing the substrate. This avoids opening a large number of vias in the thicker organic layer during the manufacturing of the display panel, making the process more efficient and convenient. Since the inorganic layer is generally thinner, the aperture of one via and the other via at both ends of the second sub-segment can be greatly reduced, which can optimize the layout space of each sub-pixel in the display panel, which is conducive to improving pixel density and achieving high-resolution display. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0017] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of this disclosure;

[0019] Figure 2 yes Figure 1 A magnified view of a portion of region J1;

[0020] Figure 3 yes Figure 1 A schematic diagram of the cross-sectional structure of a portion of a neutron pixel;

[0021] Figure 4 It is a layout screenshot of the pixel circuit of a sub-pixel area of ​​a display panel in the prior art;

[0022] Figure 5 yes Figure 1 Another enlarged view of the J1 region;

[0023] Figure 6 This is a schematic diagram of an electrical connection structure of a sub-pixel provided in an embodiment of this disclosure;

[0024] Figure 7 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of this disclosure;

[0025] Figure 8 yes Figure 7 A magnified view of a portion of region J2;

[0026] Figure 9 yes Figure 7 Another enlarged view of the J2 region;

[0027] Figure 10 yes Figure 7 Another enlarged view of the J2 region;

[0028] Figure 11 yes Figure 7 Another enlarged view of the J2 region;

[0029] Figure 12 yes Figure 7 Another enlarged view of the J2 region;

[0030] Figure 13 This is a schematic diagram of a planar structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0031] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0032] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0033] Please refer to the reference. Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of a planar structure of a display panel provided in an embodiment of this disclosure. Figure 2 yes Figure 1 A partially enlarged schematic diagram of the J1 region (the diagram is filled with transparency to clearly illustrate the structure of this embodiment). The display panel 000 provided in this embodiment includes: a display area AA;

[0034] The display area AA includes a first reference voltage line REF1 and a second reference voltage line REF2 that are electrically connected. The first reference voltage line REF1 extends along a first direction X, and the second reference voltage line REF2 extends along a second direction Y. The first direction X and the second direction Y intersect in a direction parallel to the plane where the display panel 000 is located.

[0035] The display area AA also includes a first wire L1, which extends along a first direction X;

[0036] The display panel 000 includes a substrate 10 and a first metal layer 20, a capacitor metal layer 30, a second metal layer 40 and a third metal layer 50 located on one side of the substrate 10.

[0037] The first reference voltage line REF1 is located in the capacitor metal layer 30, and the first conductor L1 is located in the second metal layer 40.

[0038] The same second reference voltage line REF2 includes a first sub-segment REF2A and a second sub-segment REF2B that are electrically connected. The first sub-segment REF2A is located in the second metal layer 40, and the orthographic projection of the second sub-segment REF2B on the substrate 10 overlaps with the orthographic projection of the first conductor L1 on the substrate 10.

[0039] The second sub-segment REF2B is located between the second metal layer 40 and the substrate 10.

[0040] Specifically, the display panel 000 provided in this embodiment can be an organic light-emitting diode (OLED) display panel. The display panel 000 includes a display area AA, and optionally, a non-display area NA of the display panel 000 is at least partially disposed around the display area AA. The display area AA may include a plurality of sub-pixels 00. Figure 1 Different fill patterns are used to represent sub-pixels 00 of different colors; optionally, in this embodiment... Figure 1 The following example illustrates the arrangement of multiple sub-pixels 00. In practice, the arrangement of multiple sub-pixels 00 may include, but is not limited to, this. A sub-pixel 00 may include a light-emitting element 02 and a pixel circuit 01 electrically connected to it. Figure 1 The pixel circuit 01 is represented by a dashed box (in specific implementations, the electrical connection structure of the pixel circuit 01 can be set according to actual needs). The pixel circuit 01 is used to provide driving signals to drive the light-emitting element 02 to emit light. Optionally, the light-emitting element 02 of each sub-pixel 00 can be an organic light-emitting diode, or the light-emitting element can also be a micro light-emitting diode or a sub-millimeter light-emitting diode, etc. This embodiment does not limit it. It is understood that this embodiment does not limit the type of display panel 000. The structure of the display area AA can be set according to the type of display panel 000. The design structure of the pixel circuit 01 included in the sub-pixels 00 of the display area AA can be understood by referring to the structure of the display panel in related technologies. For example, the pixel circuit 01 can be an electrical connection structure including multiple thin-film transistors and capacitors. This embodiment will not elaborate on this.

[0041] When the pixel circuit 01 is located in the display panel 000, multiple drive signal lines are generally required to provide drive signals to the pixel circuit. For example, the reference voltage line provides a reference voltage signal or reset signal to the pixel circuit, the data line S provides a data voltage signal to the pixel circuit 01, and the scan line ( Figure 1 (Not shown in the image) provides scanning control signals to pixel circuit 01, and the power line ( Figure 1 (Not shown in the image) Provides power supply voltage to pixel circuit 01, etc.

[0042] In this embodiment, the display area AA of the display panel 000 includes a first reference voltage line REF1 and a second reference voltage line REF2 that are electrically connected. The first reference voltage line REF1 extends along a first direction X, and the second reference voltage line REF2 extends along a second direction Y. The first direction X and the second direction Y intersect in a direction parallel to the plane of the display panel 000. It can be understood that in this embodiment, the first direction X is used as... Figure 1 The horizontal direction in the middle, the second direction Y is Figure 1The following example illustrates how the vertical direction, the first direction X, and the second direction Y are perpendicular to each other in a direction parallel to the plane where the display panel 000 is located. The display panel 000 may include multiple first reference voltage lines REF1 arranged along the second direction Y and multiple second reference voltage lines REF2 arranged along the first direction X to drive sub-pixels 00 in different rows or columns.

[0043] It should be noted that in this embodiment, the first reference voltage line REF1 extends along the first direction X, and the second reference voltage line REF2 extends along the second direction Y. This means that the overall extension direction of the first reference voltage line REF1 is along the first direction X, and does not mean that the first reference voltage line REF1 and the second reference voltage line REF2 are straight lines. In actual manufacturing, the first reference voltage line REF1 and the second reference voltage line REF2 can be traces with bends or curves, as long as the overall extension direction of the first reference voltage line REF1 is the first direction X and the overall extension direction of the second reference voltage line REF2 is the second direction Y.

[0044] It is understood that, for example, the pixel circuit 01 in this embodiment can be an electrical connection structure including 8 transistors and 1 capacitor. The first reference voltage line REF1 and the second reference voltage line REF2 can be reset signal lines electrically connected to the gate of the driving transistor of the pixel circuit 01, or the first reference voltage line REF1 and the second reference voltage line REF2 can be reset signal lines electrically connected to the anode of the light-emitting element 02 of the sub-pixel 00. The reset signal lines electrically connected to the gate of the driving transistor of the pixel circuit 01 and the reset signal lines electrically connected to the anode of the light-emitting element 02 of the sub-pixel 00 can be the same or different. This embodiment does not limit this. In specific implementation, it can be understood according to the structure of the pixel circuit. This embodiment will not elaborate further here.

[0045] The film layer structure of the display panel 000 includes a substrate 10 and a first metal layer 20, a capacitor metal layer 30, a second metal layer 40, and a third metal layer 50 located on one side of the substrate 10. The film layer structure of the display panel 000 can be a combination of multiple conductive film layers and multiple inorganic layers, or a combination of multiple conductive film layers and multiple inorganic or organic layers. This embodiment does not limit this; in specific implementation, the film layer structure of the display panel 000 can be set according to the actual design requirements of the panel. Optionally, such as Figure 3 As shown, Figure 3 yes Figure 1 A cross-sectional structural diagram of a portion of a neutron pixel (understandably, this is to clearly illustrate the film structure of the display panel). Figure 3 (An example is given by showing the cross-sectional structure of the electrical connection between a thin-film transistor and a light-emitting element in a sub-pixel.) Figure 3For example, in the direction Z perpendicular to the plane where the substrate 10 is located, the film structure of the display panel 000 may include the substrate 10 and a semiconductor layer 60, a first metal layer 20, a capacitor metal layer 30, a second metal layer 40 and a third metal layer 50 located on one side of the substrate. The active part of the thin film transistor 01T may be located in the semiconductor layer 60. The gate of the thin film transistor 01T in the pixel circuit may be located in the first metal layer 20. The capacitor plate in the pixel circuit may be located in the capacitor metal layer 30. The source and drain of the thin film transistor 01T may be located in the second metal layer 40. Power signal lines, data lines S, etc. may be located in the third metal layer 50. One of the source and drain of the thin film transistor 01T is electrically connected to the anode 021 of the light-emitting element 02 (organic light-emitting diode) through the connection part provided in the third metal layer 50. When the light-emitting element 02 is an organic light-emitting diode, the light-emitting principle is that electrons and holes migrate to the light-emitting layer through the electron and hole transport layers respectively, meet in the light-emitting layer, form excitons and excite the light-emitting molecules.

[0046] It is understood that this embodiment will not elaborate on the film structure and light emission principle of sub-pixel 00 when the display panel 000 is an organic light-emitting diode display panel. For details, please refer to the film structure of organic light-emitting diode display panels in related technologies.

[0047] In this embodiment, a first reference voltage line REF1 extending along the first direction X is located on the capacitor metal layer 30, and a second reference voltage line REF2 extending along the second direction Y is on a different layer from the first reference voltage line REF1. The second reference voltage line REF2 intersects with and is electrically connected to the first reference voltage line REF1. Therefore, the multiple first reference voltage lines REF1 and multiple second reference voltage lines REF2 included in the display panel 000 can form an electrically connected mesh structure (e.g., ...). Figure 1 As shown in the figure, this helps to reduce the trace impedance during the transmission of the overall reference voltage signal, improve display uniformity, and ensure display effect.

[0048] If the first reference voltage line extending along the first direction is located in the capacitor metal layer, the second reference voltage line, which is on a different layer and electrically connected to the first reference voltage line, is generally located in the second metal layer on the side of the capacitor metal layer away from the substrate. Since the second reference voltage line extends along the second direction, and among the many driving traces included in the display panel, there will inevitably be other signal traces that also run along the second metal layer but extend along the first direction, when the second reference voltage line extending along the second direction and also located in the second metal layer is laid near the signal trace, it is necessary to perform a cross-line processing.

[0049] like Figure 4 As shown, Figure 4This is a layout screenshot of the pixel circuit in a sub-pixel area of ​​a display panel in the prior art. Taking the circuit layout of the sub-pixel area in a relevant display panel design project as an example, the display panel in this design project includes a first reference voltage line REF1' extending along the first direction X' located in the capacitor metal layer 30', and a second reference voltage line REF2', which is on a different layer but electrically connected to the first reference voltage line REF1', located in the second metal layer 40' on the side of the capacitor metal layer 30' away from the substrate. Since the second reference voltage line REF2' extends along the second direction Y', and the display panel has many driving traces including a first conductor L1', which extends along the first direction X' and is located in the second metal layer 40', when the second reference voltage line REF2', which extends along the second direction Y' and is also located in the second metal layer 40', is laid near the first conductor L1', the second reference voltage... Line REF2' has a cross-segment REF20' that is on a different layer from the second metal layer 40', avoiding the first conductor L1'. This cross-segment REF20' is generally located in the third metal layer 50'. That is, the same second reference voltage line REF2' extending along the second direction Y' includes the body segment REF21' located in the second metal layer 40' and the cross-segment REF20' located in the third metal layer 50'. The cross-segment REF20' on a different layer has a partial overlap area with the first conductor L1'. One end of the cross-segment REF20' is electrically connected to the body segment REF21' through a via K11'. After the cross-segment REF20' crosses the first conductor L1', the other end of the cross-segment REF20' is electrically connected to another body segment REF21' through another via K12'. Both via K11' and K12' are vias from the second metal layer 40' to the third metal layer 50'.

[0050] In the film layer structure of the display panel, the first metal layer 20' and the capacitor metal layer 30' are generally made of molybdenum (Mo), while the second metal layer 40' and the third metal layer 50' are generally made of titanium / aluminum / titanium (Ti / Al / Ti) metal. That is, the second metal layer 40' has a larger film thickness. After the second metal layer 40' is patterned, in order to ensure the flatness of the subsequent third metal layer 50', an organic layer is generally placed between the second metal layer 40' and the third metal layer 50'. The organic layer can reduce the step difference of the third metal layer 50', similar to the planarization effect. In addition, when the third metal layer 50' is used to make data lines, the thicker organic layer can reduce the signal crosstalk between the third metal layer 50' where the data lines are located and the first metal layer 20' where the scan lines are located, thus improving the display effect. Therefore, in the prior art, the above-mentioned crossing method of the second reference voltage line REF2' is generally adopted. That is, the same second reference voltage line REF2' extending along the second direction Y' includes the body segment REF21' located in the second metal layer 40' and the crossing segment REF20' located in the third metal layer 50'. The crossing segment REF20' of different layers has a partial overlap area with the first conductor L1'. One end of the crossing segment REF20' is electrically connected to the body segment REF21' through a via K11', and the other end of the crossing segment REF20' is electrically connected to another body segment REF21' through another via K12'. That is, the second reference voltage line REF2' is crossed near the first conductor L1' and then returns to the second metal layer 40' to continue the routing. Figure 4 Both vias K11' and K12' shown are vias in the second metal layer 40' to the third metal layer 50'. In the circuit layout design of the display panel, a second reference voltage line REF2 crossing near the first conductor requires two additional vias. Since both vias K11' and K12' are in the second metal layer 40' to the third metal layer 50', holes need to be drilled in the organic layer between the second metal layer 40' and the third metal layer 50'. The diameters of the vias K11' and K12' formed by drilling in the organic layer are relatively large (compared to the diameters of vias set in the inorganic insulating layer). Therefore... Figure 4 The cross-line design of the second reference voltage line REF2' in the existing technology greatly increases the space occupied by the via, which is detrimental to the layout space design and increases the layout area occupied by the pixel circuit, which is not conducive to the realization of high pixel density and high resolution display.

[0051] It should be noted that, Figure 4 This is merely to illustrate that the vias used in the cross-line design of the second reference voltage line REF2' in the prior art require a large layout space. Therefore, it only shows the location of the vias and the approximate size of the space they occupy, and does not represent the specific layout design of the pixel circuit.

[0052] Understandably, in the film structure of a display panel, the aperture of vias in the organic layer is generally larger than that in the inorganic layer. This is limited by the differences in material properties and processes between the organic and inorganic layers. For example, organic materials (such as polyimide PI) are usually softer, have lower mechanical strength, and poor thermal stability, making them prone to deformation or decomposition at high temperatures. Organic materials also have poor resistance to certain chemical reagents (such as etching solutions). The aperture creation process in organic layers typically employs dry etching (such as plasma etching) or wet etching. However, due to their softness and poor chemical stability, uneven edges or inaccurate aperture control can easily occur during the etching process. Because of the characteristics of organic materials, a larger aperture is required to ensure the feasibility and stability of the process.

[0053] To address the aforementioned issues, this embodiment configures the display area AA of the display panel 000 to include a first reference voltage line REF1 extending along the first direction X. The first reference voltage line REF1 is located on the capacitor metal layer 30. It also includes a second reference voltage line REF2, which is on a different layer from the first reference voltage line REF1 and electrically connected to it. Furthermore, it includes a first conductor L1 extending along the first direction X. It can be understood that the first conductor L1 in this embodiment can be understood as a conductor that inevitably exists in the layout structure of the display panel 000, extending along the first direction X and disposed on the second metal layer 40. For example, it can be a conductor electrically connected to the data line S, used to directly provide the data voltage signal provided by the driver chip or flexible circuit board subsequently bonded to the non-display area NA to the data line S through the first conductor L1 of the display area AA. For details, please refer to the description of the following embodiments.

[0054] In this embodiment, the same second reference voltage line REF2 includes a first sub-segment REF2A and a second sub-segment REF2B that are electrically connected. The first sub-segment REF2A is located in the second metal layer 40. The orthographic projection of the second sub-segment REF2B onto the substrate 10 overlaps with the orthographic projection of the first conductor L1 onto the substrate 10. That is, the second sub-segment REF2B can be understood as a cross-line structure where the second reference voltage line REF2 is routed to the vicinity of the first conductor L1. The second sub-segment REF2B is located between the second metal layer 40 and the substrate 10. That is, the second sub-segment REF2B can be made using any metal layer on the side of the second metal layer 40 facing the substrate 10. In the film structure of the display panel, the first metal layer 20 and the capacitor metal layer 30 are generally made of molybdenum (Mo). The capacitor metal layer 30 is usually used to make the electrode of the capacitor or the reference voltage line. The transmitted signal is generally a constant voltage signal, and there is no need to consider signal crosstalk. Therefore, a thin inorganic layer is generally set between the capacitor metal layer 30 and the second metal layer 40 above it for insulation. A thin inorganic layer is also generally set between the capacitor metal layer 30 and the first metal layer 20 below it for insulation. Therefore, in this embodiment, the crossing part of the second reference voltage line REF2, i.e., the second sub-segment REF2B, is made of any metal layer on the side of the second metal layer 40 facing the substrate 10. Then, a via (e.g., a via for electrically connecting one end of the second sub-segment REF2B to the first sub-segment REF2A of the second metal layer 40) is used. Figure 2 A via (K11) shown can be formed in any inorganic layer on the side of the second metal layer 40 facing the substrate 10. After the second segment REF2B crosses the first conductor L1, the other end of the second segment REF2B is electrically connected to another first segment REF2A of the second metal layer 40 via (e.g., Figure 2 The other via K12 shown can be formed in any inorganic layer on the side of the second metal layer 40 facing the substrate 10, avoiding the need to form a large number of vias in the thicker organic layer during the manufacturing of the display panel, making the process more efficient and convenient. Since both via K11 and via K12 are vias formed in an inorganic layer below the second metal layer 40, and since inorganic layers are generally thin (such as interlayer insulating layers), the apertures of one via K11 and the other via K12 at both ends of the second sub-segment REF2B can be greatly reduced. This can optimize the layout space of each sub-pixel 00 in the display panel 000, which is beneficial to improving pixel density and achieving high-resolution display.

[0055] It should be noted that in this embodiment... Figure 2 This diagram only illustrates the electrical connection structure and relationship of the first conductor L1, the first reference voltage line REF1, and the second reference voltage line REF2. It does not represent the actual layout position and shape of each trace during the manufacturing of the display panel 000. In actual implementation, the traces can be laid out according to the actual layout of the pixel circuits in the display panel.

[0056] Understandably, in the film structure of a display panel, the aperture of vias in the inorganic layer is generally smaller than that in the organic layer. This is because the materials of the inorganic layer (such as silicon nitride SiNx and silicon oxide SiO2) are usually harder, have higher mechanical strength, can withstand high-temperature processes, and are more resistant to chemical reagents. The aperture opening process in the inorganic layer typically uses dry etching (such as reactive ion etching, RIE), which can achieve high-precision openings. The hardness and chemical stability of inorganic materials allow for smaller apertures and smoother edges. Therefore, in the film structure of a display panel, the aperture of vias in the inorganic layer is generally smaller than that in the organic layer.

[0057] like Figure 1 , Figure 5 and Figure 6 As shown, Figure 5 yes Figure 1 Another enlarged view of region J1 (transparency filler has been added to the figure to clearly illustrate the structure of this embodiment). Figure 6 This is a schematic diagram of an electrical connection structure for a sub-pixel provided in an embodiment of this disclosure. For example, the pixel circuit 01 in this embodiment can be an electrical connection structure including 8 transistors and 1 capacitor Cst, such as... Figure 6 As shown, the eight transistors can be the driving transistor DT and the other seven thin-film transistors (first transistor M1, second transistor M2, third transistor M3, fourth transistor M4, fifth transistor M5, sixth transistor M6, and seventh transistor M7). The first reference voltage line REF1 and the second reference voltage line REF2, which are electrically connected to form a grid structure, can be reset signal lines electrically connected to the gates of the driving transistors of the pixel circuit 01. The reset signal lines electrically connected to the anodes of the light-emitting element 02 of the sub-pixel 00 can be the third reference voltage line REF3 and the fourth reference voltage line REF4, which are electrically connected to form a grid structure. In this embodiment, the electrical connection structure and working principle between the pixel circuit 01 and the light-emitting element 02 are not described in detail. In specific implementation, the electrical connection structure of the sub-pixel can be understood according to the relevant technology. This embodiment will not describe it in detail here.

[0058] Taking a layout area containing a sub-pixel 00 as an example, the first reference voltage line REF1 and the second reference voltage line REF2 electrically connected to the pixel circuit 01 can be reset signal lines electrically connected to the gate of the driving transistor of the pixel circuit 01, and the reset signal line electrically connected to the anode of the light-emitting element 02 of the sub-pixel 00 can be a separately set, electrically connected third reference voltage line REF3 and fourth reference voltage line REF4 forming a grid structure (the setting method of the third reference voltage line REF3 is the same as that of the first reference voltage line REF1, and the setting method of the fourth reference voltage line REF4 is the same as that of the second reference voltage line REF2), and... Figure 4 The existing technology solutions are compared to the layout space occupied, resulting in the via space area comparison table shown in Table 1 below;

[0059] Table 1:

[0060]

[0061] like Figure 4 As shown, the applicant uses the prior art where the cross segment REF20' of the second reference voltage line REF2' is routed through the third metal layer 50', and the cross segment of the fourth reference voltage line REF4' is also routed through the third metal layer 50'. The reset signal line electrically connected to the anode of the light-emitting element of the sub-pixel is a separately configured mesh structure formed by the electrically connected third reference voltage line REF3' and fourth reference voltage line REF4' (the configuration of the third reference voltage line REF3' is the same as that of the first reference voltage line REF1', and the configuration of the fourth reference voltage line REF4' is the same as that of the second reference voltage line REF2'). Therefore, if the cross segment REF20' of the second reference voltage line REF2' and the cross segment REF40' of the fourth reference voltage line REF4' are to be configured in the layout area of ​​a sub-pixel in the prior art, at least four vias opened in the organic layer are required (respectively...). Figure 4 The four vias K11', K12', K13', and K14' located in the organic layer increase the total area on the plane by approximately 4 × 5.5 × 5.5 = 121 μm. 2 Where 5.5×5.5 represents the approximate area of ​​a via, and vias K11', K12', K13', and K14' are approximately the same size. It should be noted that in this embodiment, the orthographic projection shape of the via on the plane of the substrate is approximately square to facilitate the calculation of the layout area occupied by the via.

[0062] And using this embodiment Figure 5After the scheme, taking the reset signal line electrically connected to the anode 021 of the light-emitting element 02 of sub-pixel 00 as an example, which is a separately set and electrically connected third reference voltage line REF3 and fourth reference voltage line REF4 forming a mesh structure (the setting method of the third reference voltage line REF3 is the same as the setting method of the first reference voltage line REF1, and the setting method of the fourth reference voltage line REF4 is the same as the setting method of the second reference voltage line REF2), assuming that the second sub-segment REF2B of the second reference voltage line REF2 runs through any metal layer below the second metal layer 40 (such as the first metal layer 20), and the second sub-segment REF4B of the fourth reference voltage line REF4 also runs through any metal layer below the second metal layer 40 (such as the first metal layer 20), then in this embodiment, if the second sub-segment REF2B of the second reference voltage line REF2 and the second sub-segment REF4B of the fourth reference voltage line REF4 are to be set in the layout area where a sub-pixel 00 is located, at least four vias opened in the inorganic layer need to be added (respectively...). Figure 5 The four vias (K11, K12, K13, and K14) opened in the inorganic layer increase the total area on the plane by approximately 4 × 4.64 × 4.64 = 86.11 μm. 2 Where 4.64×4.64 represents the approximate area of ​​a via, and vias K11, K12, K13, and K14 are approximately the same size; after adopting the scheme of this embodiment, the space occupied by the layout of a sub-pixel 00 can be reduced by about 28.82%. It should be noted that in this embodiment, the orthographic projection shape of the via on the plane where the substrate is located is approximately square to facilitate the calculation of the layout area occupied by the via.

[0063] It should be noted that the diagram in this embodiment is only an example of the structure of the display panel 000. In specific implementation, the structure of the display panel includes, but is not limited to, this. The structure of the sub-pixels in the diagram of this embodiment is also only an example. In specific implementation, the structure, shape, number, area, etc. of the sub-pixels are only examples. In specific implementation, they can be designed according to actual needs.

[0064] In some alternative embodiments, please refer to the references. Figure 7 and Figure 8 , Figure 7 This is a schematic diagram of another planar structure of the display panel provided in an embodiment of this disclosure. Figure 8 yes Figure 7 A partially enlarged schematic diagram of the J2 region (the diagram is filled with transparency to clearly illustrate the structure of this embodiment). In this embodiment, the display panel 000 includes a non-display area NA, and the non-display area NA includes multiple fan-out traces F1.

[0065] Display area AA includes multiple first data lines S1 extending along the second direction Y. The first data lines S1 are electrically connected to fan-out traces F1 through at least one first connection line LF. The first connection line LF is located in display area AA.

[0066] The first connection line LF includes at least a first conductor L1, one end of which is electrically connected to a first data line S1, which is located in the third metal layer 50.

[0067] Optionally, the same first connection line LF includes a second conductor L2 and a first conductor L1 that are electrically connected. The extension direction of the second conductor L2 is the same as the extension direction of the first data line S1. The second conductor L2 is located in the third metal layer 50.

[0068] This embodiment explains that the display panel 000 includes a display area AA and a non-display area NA that is at least partially surrounding the display area AA. The display area AA includes multiple first data lines S1 extending along a second direction Y. Optionally, along the first direction X, the first data lines S1 are closer to the edge of the display panel 000 than the other data lines S. Optionally, the non-display area NA may include a fan-out area FNA and a bonding area BNA. The fan-out area FNA may have multiple fan-out traces F1, and the bonding area BNA may have multiple conductive pads. The fan-out traces F1 are used to electrically connect the first data lines S1 of the display area AA to the conductive pads of the bonding area BNA. The conductive pads are used for subsequent bonding and electrical connection with a driver chip or flexible circuit board to provide display drive signals to the display panel 000 through the driver chip or flexible circuit board.

[0069] With the development of display technology, consumers are increasingly demanding higher screen-to-body ratios, especially for small and medium-sized displays. To reduce the non-display area and increase the display area, fan-out traces are typically designed to converge towards the bonding area, forming a fan-out region. This fan-out region contains numerous fan-out traces used to output display drive signals from the driver chip to the data lines within the display area. Therefore, the fan-out region usually occupies a large area, resulting in a wide fan-out region that makes it difficult to further compress the display panel bezel and achieve narrower bezel designs. Furthermore, for high-resolution, high-definition displays, the number of data signal channels is even greater. Even with extreme process limits, current technology lacks sufficient space for the traditional design method of connecting fan-out traces to the data lines in the display area one-to-one. New design solutions must be found to meet customer demands for narrower bezel specifications.

[0070] In this embodiment, the fan-out area FNA of the non-display area NA includes multiple fan-out traces F1. The first data line S1 located in the third metal layer 50 is electrically connected to the fan-out traces F1 through at least one first connecting line LF. The first connecting line LF is located in the display area AA, and its two ends are respectively connected to the fan-out traces F1 of the non-display area NA and the first data line S1 of the display area AA. Optionally, along the first direction X in the display panel 000, the display area AA includes a second display area AA2 and first display areas AA1 located on opposite sides of the second display area AA2. The first display area AA1 can be understood as the display area closer to the two side edges of the display panel 000 in the first direction X, and the second display area AA2 can be understood as the area of ​​the display area AA closer to the center. Multiple first data lines S1 extending along the second direction Y in the display panel 000 are disposed in the first display area AA1. The first data lines S1 are electrically connected to the fan-out trace F1 of the non-display area NA through the first connecting line LF located in the display area AA. The fan-out trace F1 is electrically connected to the conductive pad of the bonding area BNA, thereby realizing signal transmission between the first data lines S1 and the conductive pad. Optionally, the second display area AA2 of the display panel 000 may include multiple second data lines S2. One end of the second data line S2 can be directly electrically connected to other fan-out traces of the non-display area NA within the area corresponding to the second display area AA2.

[0071] In this embodiment, the first connecting line LF is located in the display area AA. That is, when the first data line S1 in the first display area AA1 located near the two side edges of the display panel 000 on the first direction X is electrically connected to the solder pad of the bonding area BNA, the electrical connection is achieved through the first connecting line LF located in the display area AA, which can avoid the first connecting line LF occupying the space of the non-display area NA. Figure 7 As shown, the first connecting line LF includes at least a first conductor L1. One end of the first conductor L1 located in the second metal layer 40 is electrically connected to the first data line S1 located in the third metal layer 50. A portion of the first connecting line LF (such as...) Figure 7 The first conductor L1 (illustrated in the diagram) can gradually extend towards the second display area AA2 within the display area AA, and then extend to the boundary between the display area AA and the non-display area NA. This allows the connection point between the first connecting line 10 and the fan-out routing line F1 to be as far away from the first display area AA1 as possible in the first direction X. Compared with the solution in the prior art, the structure of setting the first connecting line LF in the display area AA in this embodiment is beneficial to reducing the width occupied by multiple fan-out routing lines F1 in the first direction X, thereby further reducing the lower bezel of the display panel 000.

[0072] In this embodiment, the same first connecting line LF includes a second conductor L2 and a first conductor L1 that are electrically connected. The optional second conductor L2 and first conductor L1 may include multiple conductors that are alternately connected end to end, thereby gradually forming a stepped first connecting line LF. The extension direction of the second conductor L2 is the same as the extension direction of the first data line S1. The second conductor L2 may be in the same layer as the first data line S1, that is, located in the third metal layer 50. The stepped first connecting line LF may gradually extend towards the second display area AA2 within the display area AA, and then extend to the boundary position between the display area AA and the non-display area NA, so that the connection between the first connecting line 10 and the fan-out routing line F1 is as far away from the first display area AA1 as possible in the first direction X.

[0073] It is understood that the design structure of the first connecting line LF in this embodiment, located in the display area AA, can meet the high resolution requirements of the display panel 000. Even if the display area AA includes more data lines, the first connecting line LF can be routed from inside the display area AA, which can reduce the space occupied by the fan-out routing line F1 connected to the first connecting line LF in the non-display area NA in the first direction X. Therefore, the width of the non-display area NA in the first direction X can still be further compressed, which can meet the high resolution requirements while ensuring the display function and achieving a narrower bezel.

[0074] Optionally, in this embodiment, the first conductor L1 of the first connecting line LF located in the display area AA is disposed on the second metal layer 40, and the second conductor L2 is disposed on the third metal layer 50. The first connecting line LF is made using the conductive film layer included in the display panel 000 itself, which helps to save manufacturing costs and achieve a thinner panel design. Furthermore, in this embodiment, by disposing the first conductor L1 of the first connecting line LF located in the display area AA on the second metal layer 40 and the second conductor L2 on the third metal layer 50, the impedance is relatively small compared to disposing the first connecting line LF on other metal layers such as the first metal layer 20 and the capacitor metal layer 30, which helps to improve the transmission effect of data voltage signals on the first connecting line LF.

[0075] Optional, please continue to refer to Figures 1-3 , Figures 5-8 In the film layer structure of the display panel 000 in this embodiment, a first inorganic layer 001 is included between the first metal layer 20 and the capacitor metal layer 30, a second inorganic layer 002 is included between the capacitor metal layer 30 and the second metal layer 40, and a first organic layer 003 is included between the second metal layer 40 and the third metal layer 50.

[0076] This embodiment explains the film structure of the display panel 000. The first metal layer 20 and the capacitor metal layer 30 are generally made of molybdenum (Mo), while the second metal layer 40 and the third metal layer 50 are generally made of titanium / aluminum / titanium (Ti / Al / Ti) metal. That is, the second metal layer 40' has a larger film thickness. After the second metal layer 40 is patterned, in order to ensure the flatness of the subsequent third metal layer 50, a first organic layer 003 is generally set between the second metal layer 40 and the third metal layer 50. The first organic layer 003 is made of organic material, which can reduce the step difference of the third metal layer 50 and achieve the effect of flattening the thicker second metal layer 40 after patterning. In addition, when the third metal layer 50 is used to make data lines S, the thicker first organic layer 003 can reduce the signal crosstalk between the third metal layer 50 where the data line S is located and the first metal layer 20 where the scan line is located, thereby improving the display effect.

[0077] A first inorganic layer 001 is included between the first metal layer 20 and the capacitor metal layer 30, and a second inorganic layer 002 is included between the capacitor metal layer 30 and the second metal layer 40. The first inorganic layer 001 and the second inorganic layer 002 can be understood as interlayer insulating layers. The same second reference voltage line REF2 includes an electrically connected first sub-segment REF2A and a second sub-segment REF2B. The first sub-segment REF2A is located in the second metal layer 40, and the second sub-segment REF2B is a cross-line structure from the second reference voltage line REF2 to the vicinity of the first conductor L1. The second sub-segment REF2B is located between the second metal layer 40 and the substrate 10, that is, the second sub-segment REF2B can be made of any metal layer on the side of the second metal layer 40 facing the substrate 10. In this case, the via connecting the second sub-segment REF2B and the first sub-segment REF2A can be formed in the first inorganic layer 001 or the second inorganic layer 002, without needing to be formed in the thicker first organic layer 003. This reduces the via diameter of the via connecting the second sub-segment REF2B and the first sub-segment REF2A. Since the materials used in the first inorganic layer 001 and the second inorganic layer 002 as interlayer insulating layers, such as silicon nitride (SiNx) and silicon oxide (SiO2), are typically hard, have high mechanical strength, can withstand high-temperature processes, and are highly resistant to chemical reagents, the via formation process usually employs dry etching, which can achieve high-precision via formation. Therefore, the hardness and chemical stability of inorganic materials allow for smaller via diameters and smoother edges. Thus, in the film structure of the display panel, the via diameter W1 formed in the first inorganic layer 001 and the second inorganic layer 002 is generally smaller than the via diameter W2 formed in the first organic layer 003 (e.g., ...). Figure 3 As shown, it is understandable that Figure 3This is merely an example. The aperture W1 of the vias opened in the first inorganic layer 001 and the second inorganic layer 002 is generally smaller than the aperture W2 of the vias opened in the first organic layer 003. Apertures W1 and W2 do not represent the vias that electrically connect the second sub-segment REF2B and the first sub-segment REF2A in the above embodiment. This is beneficial for reducing the aperture of the vias that electrically connect the second sub-segment REF2B and the first sub-segment REF2A, optimizing the layout space of the sub-pixels, improving pixel density, and enhancing display quality.

[0078] In some alternative embodiments, please refer to the references. Figure 7 and Figure 9 , Figure 9 yes Figure 7 Another enlarged schematic diagram of the J2 region (the diagram is filled with transparency to clearly illustrate the structure of this embodiment). In this embodiment, the same second reference voltage line REF2 includes a first sub-segment REF2A and a second sub-segment REF2B that are electrically connected. The first sub-segment REF2A is located in the second metal layer 40, and the orthographic projection of the second sub-segment REF2B on the substrate 10 overlaps with the orthographic projection of the first wire L1 on the substrate 10.

[0079] The second sub-segment REF2B is located in the capacitor metal layer 30 between the second metal layer 40 and the substrate 10.

[0080] When the first segment REF2A of the same second reference voltage line REF2 is located in the second metal layer 40 and the second segment REF2B is located in the capacitor metal layer 30, the first reference voltage line REF1 is electrically connected to a first segment REF2A through the first via K1; the first end of the second segment REF2B is electrically connected to the first segment REF2A through the fifth via K5; and the second end of the second segment REF2B is electrically connected to another first segment REF2A through the sixth via K6.

[0081] This embodiment explains that when the first segment REF2A of the same second reference voltage line REF2 is located in the second metal layer 40 and the second segment REF2B is located between the second metal layer 40 and the substrate 10, the second segment REF2B can be located in the capacitor metal layer 30, that is, the second segment REF2B is in the same layer as the first reference voltage line REF1. At this time, the first reference voltage line REF1 and the second reference voltage line REF2 of the capacitor metal layer 30 intersect to form a grid structure. The first reference voltage line REF1 of the capacitor metal layer 30 and the first segment REF2A of the second metal layer 40 are electrically connected through the first via K1. The first via K1 is opened in the second inorganic layer 002 between the capacitor metal layer 30 and the second metal layer 40, and the aperture is small.

[0082] The first segment REF2A of the second reference voltage line REF2 is located in the second metal layer 40. When the first segment REF2A is routed to the vicinity of the first conductor L1 in the second metal layer 40, it is routed to the second segment REF2B of the capacitor metal layer 30. The first end of the first segment REF2A of the second metal layer 40 and the first end of the second segment REF2B of the capacitor metal layer 30 are electrically connected through the fifth via K5. The fifth via K5 is opened in the second inorganic layer 002 between the capacitor metal layer 30 and the second metal layer 40, and the aperture is relatively small.

[0083] The orthographic projection of the second segment REF2B of the capacitor metal layer 30 onto the plane of the substrate 10 overlaps with the orthographic projection of the first conductor L1 of the second metal layer 40 onto the plane of the substrate 10. The second segment REF2B of the capacitor metal layer 30 crosses the first conductor L1 of the second metal layer 40 and then switches to another first segment REF2A of the second metal layer 40. At this time, after crossing the first conductor L1 of the second metal layer 40, the second segment REF2B of the capacitor metal layer 30 is electrically connected to the other first segment REF2A of the second metal layer 40 through the sixth via K6. The sixth via K6 is also opened in the second inorganic layer 002 between the capacitor metal layer 30 and the second metal layer 40, and has a small aperture.

[0084] In this embodiment, when the same second reference voltage line REF2 includes an electrically connected first sub-segment REF2A and a second sub-segment REF2B, the first sub-segment REF2A is located in the second metal layer 40 and the second sub-segment REF2B is located in the capacitor metal layer 30. This helps to reduce the aperture of the fifth via K5 and the sixth via K6 that electrically connect the second sub-segment REF2B and the first sub-segment REF2A, optimizes the layout space of the sub-pixels, and helps to improve pixel density and display quality.

[0085] In some alternative embodiments, please refer to the references. Figure 7 and Figure 10 , Figure 10 yes Figure 7 Another enlarged schematic diagram of the J2 region (the diagram is filled with transparency to clearly illustrate the structure of this embodiment). In this embodiment, the same second reference voltage line REF2 includes a first sub-segment REF2A and a second sub-segment REF2B that are electrically connected. The first sub-segment REF2A is located in the second metal layer 40, and the orthographic projection of the second sub-segment REF2B on the substrate 10 overlaps with the orthographic projection of the first wire L1 on the substrate 10.

[0086] The second sub-segment REF2B is located in the capacitor metal layer 30 between the second metal layer 40 and the substrate 10.

[0087] When the first segment REF2A of the same second reference voltage line REF2 is located in the second metal layer 40 and the second segment REF2B is located in the capacitor metal layer 30, the first reference voltage line REF1 is electrically connected to a first segment REF2A through the first via K1; the first end of the second segment REF2B is also electrically connected to the first segment REF2A through the first via K1; the second end of the second segment REF2B is electrically connected to another first segment REF2A through the second via K2.

[0088] Optionally, the second segment REF2B and the first reference voltage line REF1 are integrated into a single structure.

[0089] At this time, the first via K1 penetrates the second inorganic layer 002, and the second via K2 penetrates the second inorganic layer 002.

[0090] This embodiment explains that when the first segment REF2A of the same second reference voltage line REF2 is located in the second metal layer 40 and the second segment REF2B is located between the second metal layer 40 and the substrate 10, the second segment REF2B can be located in the capacitor metal layer 30, that is, the second segment REF2B is in the same layer as the first reference voltage line REF1. At this time, the first reference voltage line REF1 and the second reference voltage line REF2 of the capacitor metal layer 30 intersect to form a grid structure. The first reference voltage line REF1 of the capacitor metal layer 30 and the first segment REF2A of the second metal layer 40 are electrically connected through the first via K1. The first via K1 is opened in the second inorganic layer 002 between the capacitor metal layer 30 and the second metal layer 40, and the aperture is small.

[0091] Furthermore, the first end of the second sub-segment REF2B can also reuse the first via K1 to achieve electrical connection with the first sub-segment REF2A. That is, the second sub-segment REF2B and the first reference voltage line REF1, both located in the capacitor metal layer 30, can be an integral structure. The first sub-segment REF2A, located in the second metal layer 40, is at the intersection of the first reference voltage line REF1 and the second reference voltage line REF2. The first via K1 is reused to achieve electrical connection between the first sub-segment REF2A of the second metal layer 40 and the second sub-segment REF2B of the capacitor metal layer 30. The first segment REF2A of the second reference voltage line REF2 is located in the second metal layer 40. When the first segment REF2A is traced to the first reference voltage line REF1, it is electrically connected to the first reference voltage line REF1 through the first via K1, thereby forming a mesh structure where the first reference voltage line REF1 and the second reference voltage line REF2 intersect. Since the second segment REF2B of the capacitor metal layer 30 is an integral structure with the first reference voltage line REF1, the second segment REF2B of the capacitor metal layer 30 continues to trace on the side of the first reference voltage line REF1 facing the first conductor L1. The orthographic projection of REF2B onto the plane of substrate 10 overlaps with the orthographic projection of the first conductor L1 of the second metal layer 40 onto the plane of substrate 10. After the second sub-segment REF2B crosses the first conductor L1 of the second metal layer 40, it switches to another first sub-segment REF2A of the second metal layer 40. At this time, the second sub-segment REF2B of the capacitor metal layer 30 crosses the first conductor L1 of the second metal layer 40 and is electrically connected to another first sub-segment REF2A of the second metal layer 40 through the second via K2. The second via K2 is also opened in the second inorganic layer 002 between the capacitor metal layer 30 and the second metal layer 40, and the aperture is small.

[0092] Since in this embodiment, when the first reference voltage line REF1 extending in the first direction X and the second reference voltage line REF2 extending in the second direction Y are electrically connected, it is necessary to achieve the electrical connection between the first reference voltage line REF1 of the capacitor metal layer 30 and the first sub-segment REF2A of the second metal layer 40 through the opening of the first via K1, when the second sub-segment REF2B and the first reference voltage line REF1 are both in the capacitor metal layer 30 and are an integral structure, the first via K1 can be reused when the first end of the second sub-segment REF2B is electrically connected to the first sub-segment REF2A.

[0093] In this embodiment, when the same second reference voltage line REF2 includes the electrically connected first sub-segment REF2A and second sub-segment REF2B, the first sub-segment REF2A is located in the second metal layer 40 and the second sub-segment REF2B is located in the capacitor metal layer 30. The second sub-segment REF2B, which is also located in the capacitor metal layer 30, is an integral structure with the first reference voltage line REF1. The first via K1 existing in the panel itself is reused, which helps to reduce the number of vias in the sub-pixel layout space. At the same time, the aperture of the second via K2 that electrically connects the second sub-segment REF2B and the first sub-segment REF2A is reduced, which can more effectively optimize the sub-pixel layout space, further improve pixel density, and enhance display quality.

[0094] like Figure 4 , Figure 7 , Figure 10 and Figure 11 As shown, Figure 11 yes Figure 7 Another enlarged schematic diagram of region J2 (transparency fill is used in the diagram to clearly illustrate the structure of this embodiment). Taking a sub-pixel 00 as an example, the first reference voltage line REF1 and the second reference voltage line REF2 electrically connected to the pixel circuit 01 can be reset signal lines electrically connected to the gate of the driving transistor of the pixel circuit 01. The reset signal line electrically connected to the anode of the light-emitting element 02 of the sub-pixel 00 is a separately provided, electrically connected mesh structure formed by the third reference voltage line REF3 and the fourth reference voltage line REF4 (the setting method of the third reference voltage line REF3 is the same as that of the first reference voltage line REF1, and the setting method of the fourth reference voltage line REF4 is the same as that of the second reference voltage line REF2). Figure 4 The existing technology solutions are compared to the layout space occupied, resulting in the via space area comparison table shown in Table 2 below;

[0095] Table 2:

[0096]

[0097] like Figure 4As shown, the applicant uses the prior art where the cross segment REF20' of the second reference voltage line REF2' is routed through the third metal layer 50', and the cross segment of the fourth reference voltage line REF4' is also routed through the third metal layer 50'. The reset signal line electrically connected to the anode of the light-emitting element of the sub-pixel is a separately configured mesh structure formed by the electrically connected third reference voltage line REF3' and fourth reference voltage line REF4' (the configuration of the third reference voltage line REF3' is the same as that of the first reference voltage line REF1', and the configuration of the fourth reference voltage line REF4' is the same as that of the second reference voltage line REF2'). Therefore, if the cross segment REF20' of the second reference voltage line REF2' and the cross segment REF40' of the fourth reference voltage line REF4' are to be configured in the layout area of ​​a sub-pixel in the prior art, at least four vias opened in the organic layer are required (respectively...). Figure 4 The four vias K11', K12', K13', and K14' located in the organic layer increase the total area on the plane by approximately 4 × 5.5 × 5.5 = 121 μm. 2 , where 5.5×5.5 represents the approximate area of ​​a via, and vias K11', K12', K13', and K14' are basically the same size.

[0098] Using this embodiment Figure 11After the scheme, taking the reset signal line electrically connected to the anode 021 of the light-emitting element 02 of sub-pixel 00 as an example, which is a separately set and electrically connected third reference voltage line REF3 and fourth reference voltage line REF4 forming a grid structure (the setting method of the third reference voltage line REF3 is the same as the setting method of the first reference voltage line REF1, and the setting method of the fourth reference voltage line REF4 is the same as the setting method of the second reference voltage line REF2), assuming that the second sub-segment REF2B of the second reference voltage line REF2 runs through the capacitor metal layer 30 below the second metal layer 40, and the second sub-segment REF4B of the fourth reference voltage line REF4 also runs through the capacitor metal layer 30 below the second metal layer 40, and the second sub-segment REF2B in the capacitor metal layer 30 and the first reference voltage line REF1 are an integral structure. When the first end of the second sub-segment REF2B of the second reference voltage line REF2 is electrically connected to the first sub-segment REF2A, the first sub-via K1-1 required to form a mesh structure using the first reference voltage line REF1 and the second reference voltage line REF2 present in the panel itself is reused. When the first end of the second sub-segment REF4B of the fourth reference voltage line REF4 is electrically connected to the first sub-segment REF4A, the second sub-via K1-2 required to form a mesh structure using the third reference voltage line REF3 and the fourth reference voltage line REF4 present in the panel itself is reused. Therefore, in this embodiment, if the second sub-segment REF2B of the second reference voltage line REF2 and the second sub-segment REF4B of the fourth reference voltage line REF4 are to be set in the layout area where a sub-pixel 00 is located, only two vias opened in the inorganic layer need to be added (respectively). Figure 11 The two vias (K2-1 and K2-2) located in the second inorganic layer 002 increase the total area on the plane by approximately 2 × 4.34 × 4.34 = 37.67 μm. 2 Where 4.34×4.34 represents the approximate area of ​​a via, and the third sub-via K2-1 and the fourth sub-via K2-2 are basically the same size; after adopting the scheme of this embodiment, not only can the number of vias in the layout space of a sub-pixel 00 be reduced, but the space occupied by the layout can also be saved by about 68.87%, which is more conducive to improving pixel density and enhancing display quality.

[0099] In some alternative embodiments, please refer to the references. Figure 7 and Figure 12 , Figure 12 yes Figure 7Another enlarged schematic diagram of the J2 region (the diagram is filled with transparency to clearly illustrate the structure of this embodiment). In this embodiment, the same second reference voltage line REF2 includes a first sub-segment REF2A and a second sub-segment REF2B that are electrically connected. The first sub-segment REF2A is located in the second metal layer 40, and the orthographic projection of the second sub-segment REF2B on the substrate 10 overlaps with the orthographic projection of the first wire L1 on the substrate 10.

[0100] The second sub-segment REF2B is located in the first metal layer 20 between the second metal layer 40 and the substrate 10.

[0101] When the first segment REF2A of the same second reference voltage line REF2 is located in the second metal layer 40 and the second segment REF2B is located in the first metal layer 20, the first reference voltage line REF1 is electrically connected to a first segment REF2A through the first via K1.

[0102] The first end of the second sub-segment REF2B is electrically connected to a first sub-segment REF2A through the third via K3;

[0103] The second end of the second sub-segment REF2B is electrically connected to another first sub-segment REF2A through the fourth via K4.

[0104] At this point, the first via K1 penetrates the second inorganic layer 002; the third via K3 penetrates the second inorganic layer 002 and the first inorganic layer 001; and the fourth via K4 penetrates the second inorganic layer 002 and the first inorganic layer 001.

[0105] This embodiment explains that when the first segment REF2A of the same second reference voltage line REF2 is located in the second metal layer 40 and the second segment REF2B is located between the second metal layer 40 and the substrate 10, the second segment REF2B can be located in the first metal layer 20. In this case, the first reference voltage line REF1 and the second reference voltage line REF2 of the capacitor metal layer 30 intersect to form a mesh structure. The first reference voltage line REF1 of the capacitor metal layer 30 and the first segment REF2A of the second metal layer 40 are electrically connected through a first via K1. The first via K1 is formed in the second inorganic layer 002 between the capacitor metal layer 30 and the second metal layer 40, and has a small aperture.

[0106] The first segment REF2A of the second reference voltage line REF2 is located in the second metal layer 40. When the first segment REF2A is routed to the vicinity of the first conductor L1 in the second metal layer 40, it is switched to the second segment REF2B of the first metal layer 20. The first end of the first segment REF2A of the second metal layer 40 and the first end of the second segment REF2B of the first metal layer 20 are electrically connected through the third via K3. The third via K3 passes through the second inorganic layer 002 between the capacitor metal layer 30 and the second metal layer 40, and the first inorganic layer 001 between the capacitor metal layer 30 and the first metal layer 20. The via has a small aperture.

[0107] The orthographic projection of the second segment REF2B of the first metal layer 20 onto the plane of the substrate 10 overlaps with the orthographic projection of the first conductor L1 of the second metal layer 40 onto the plane of the substrate 10. The second segment REF2B of the first metal layer 20 crosses the first conductor L1 of the second metal layer 40 and then switches to another first segment REF2A of the second metal layer 40. At this time, the second segment REF2B of the first metal layer 20 crosses the first conductor L1 of the second metal layer 40 and is electrically connected to the other first segment REF2A of the second metal layer 40 through the fourth via K4. The fourth via K4 also penetrates the second inorganic layer 002 between the capacitor metal layer 30 and the second metal layer 40, and the first inorganic layer 001 between the capacitor metal layer 30 and the first metal layer 20, and has a small aperture.

[0108] In this embodiment, when the same second reference voltage line REF2 includes an electrically connected first sub-segment REF2A and a second sub-segment REF2B, the first sub-segment REF2A is located in the second metal layer 40 and the second sub-segment REF2B is located in the first metal layer 20. Even if the third via K3 needs to penetrate the second inorganic layer 002 and the first inorganic layer 001, and the fourth via K4 needs to penetrate the second inorganic layer 002 and the first inorganic layer 001, compared to opening the third via K3 and the fourth via K4 in the first organic layer 003, it is still possible to reduce the aperture of the third via K3 and the fourth via K4 that electrically connect the second sub-segment REF2B and the first sub-segment REF2A, optimize the layout space of the sub-pixels, and help improve pixel density and display quality.

[0109] In some alternative embodiments, please refer to Figure 13 , Figure 13 This is a schematic diagram of a planar structure of a display device provided in an embodiment of the present disclosure. The display device 111 provided in this embodiment includes the display panel 000 provided in the above embodiment of the present invention. Figure 13This embodiment uses a mobile phone as an example to illustrate the display device 111. It is understood that the display device 111 provided in this embodiment can be any other display device 111 with display functions, such as a computer, television, or in-vehicle display device; this invention does not impose specific limitations on this. The display device 111 provided in this embodiment has the beneficial effects of the display panel 000 provided in this embodiment. For details, please refer to the specific descriptions of the display panel 000 in the above embodiments; these will not be repeated here.

[0110] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0111] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, include: Display area; The display area includes a first reference voltage line and a second reference voltage line that are electrically connected. The first reference voltage line extends along a first direction, and the second reference voltage line extends along a second direction. The first direction and the second direction intersect in a direction parallel to the plane of the display panel. The display area further includes a first conductor, which extends along the first direction; The display panel includes a substrate and a first metal layer, a capacitor metal layer, a second metal layer and a third metal layer located on one side of the substrate; The first reference voltage line is located in the capacitor metal layer, and the first wire is located in the second metal layer; The same second reference voltage line includes a first sub-segment and a second sub-segment that are electrically connected, the first sub-segment being located in the second metal layer, and the orthographic projection of the second sub-segment onto the substrate overlapping the orthographic projection of the first wire onto the substrate. The second segment is located between the second metal layer and the substrate.

2. The display panel according to claim 1, characterized in that, The display panel includes a non-display area, and the non-display area includes multiple fan-out traces; The display area includes multiple first data lines extending along the second direction. The first data lines are electrically connected to the fan-out routing line through at least one first connecting line, and the first connecting line is located in the display area. The first connection line includes at least the first conductor, one end of which is electrically connected to the first data line, and the first data line is located in the third metal layer.

3. The display panel according to claim 2, characterized in that, The same first connection line includes a second conductor and the first conductor that are electrically connected, the second conductor extending in the same direction as the first data line, and the second conductor located in the third metal layer.

4. The display panel according to claim 1, characterized in that, A first inorganic layer is included between the first metal layer and the capacitor metal layer, a second inorganic layer is included between the capacitor metal layer and the second metal layer, and a first organic layer is included between the second metal layer and the third metal layer.

5. The display panel according to claim 4, characterized in that, The second sub-segment is located in the capacitor metal layer.

6. The display panel according to claim 5, characterized in that, The first reference voltage line is electrically connected to one of the first sub-segments via a first via; The first end of the second sub-segment is electrically connected to one of the first sub-segments through the first via. The second end of the second sub-segment is electrically connected to another first sub-segment via a second via.

7. The display panel according to claim 6, characterized in that, The second sub-segment and the first reference voltage line are an integral structure.

8. The display panel according to claim 6, characterized in that, The first via penetrates the second inorganic layer, and the second via penetrates the second inorganic layer.

9. The display panel according to claim 4, characterized in that, The second sub-segment is located in the first metal layer.

10. The display panel according to claim 9, characterized in that, The first reference voltage line is electrically connected to one of the first sub-segments via a first via; The first end of the second sub-segment is electrically connected to one of the first sub-segments via a third via. The second end of the second sub-segment is electrically connected to another first sub-segment via a fourth via.

11. The display panel according to claim 10, characterized in that, The first via penetrates the second inorganic layer; The third via penetrates the second inorganic layer and the first inorganic layer, and the fourth via penetrates the second inorganic layer and the first inorganic layer.

12. A display device, characterized in that, Includes the display panel as described in any one of claims 1-11.

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