Array substrate, display panel and display device

Abstract

The embodiment of the invention provides an array substrate, a display panel and a display device, relates to the technical field of display, and can release static electricity on a signal line. The array substrate comprises a substrate, a plurality of pixel circuits, a first conductive layer and a second conductive layer. The plurality of pixel circuits are arranged on the substrate, and the plurality of pixel circuits are arranged in a plurality of rows and a plurality of columns. The first conductive layer comprises a plurality of conductive patterns, the plurality of conductive patterns and the plurality of pixel circuits are spaced, and each conductive pattern comprises at least two contact parts which are arranged at intervals. The second conductive layer is arranged on the side, away from the substrate, of the first conductive layer. The second conductive layer comprises a plurality of first signal lines, and the first signal lines are arranged at intervals in the first direction and extend in the second direction; one first signal line is electrically connected with at least one conductive pattern, and the first signal line is connected with at least two contact parts of the conductive pattern. The array substrate is used for preparing a display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to an array substrate, a display panel, and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) display panels have gradually become one of the mainstream products in the display field due to their excellent performance such as self-luminescence, no need for a backlight, high contrast ratio, thin thickness, wide viewing angle, fast response speed, applicability to flexible panels, wide operating temperature range, and relatively simple structure and manufacturing process. OLED display panels can be widely used in terminal products such as smart phones, tablet computers, televisions, and wearable devices (such as watches).

[0003] An OLED display panel includes an array substrate and light-emitting devices disposed on the array substrate. The array substrate includes a plurality of signal lines, and the signal lines are used to transmit corresponding control signals to the array substrate to drive the display panel for image display. How to avoid electrostatic accumulation on the signal lines is a technical problem that urgently needs to be solved in the display panel. Summary of the Invention

[0004] The purpose of the embodiments of the present disclosure is to provide an array substrate, a display panel, and a display device for releasing static electricity on the signal lines and improving the reliability of the display panel.

[0005] To achieve the above object, the embodiments of the present disclosure provide the following technical solutions:

[0006] On the one hand, an array substrate is provided. The array substrate includes a substrate, a plurality of pixel circuits, a first conductive layer, and a second conductive layer. The plurality of pixel circuits are disposed on the substrate, and the plurality of pixel circuits are arranged in multiple rows and multiple columns. The first conductive layer includes a plurality of conductive patterns, the plurality of conductive patterns are spaced apart from the plurality of pixel circuits, and each pixel circuit includes at least two spaced-apart contact portions. The second conductive layer is disposed on a side of the first conductive layer away from the substrate. The second conductive layer includes a plurality of first signal lines, the plurality of first signal lines are spaced apart along a first direction and all extend along a second direction; one of the first signal lines is electrically connected to at least one conductive pattern, and the first signal line is connected to at least two contact portions of the conductive pattern. The first direction is the row direction in which the plurality of pixel circuits are arranged, and the second direction is the column direction in which the plurality of pixel circuits are arranged.

[0007] The array substrate provided by the embodiments of the present disclosure, the fact that the conductive pattern has a gap from the plurality of pixel circuits means that: the conductive pattern is not directly in contact and connected to the pixel circuit, or in other words, the conductive pattern is not used to transmit signals to the pixel circuit. The first signal line located on the second conductive layer is electrically connected to at least one conductive pattern located on the first conductive layer. At the connection position of the first signal line and the conductive pattern, the first signal line bulges towards the side close to the substrate to form a protrusion. In the case of static electricity appearing on the first signal line, the static electricity will accumulate at the protrusion, corner or other protruding sharp corner positions of the first signal line. That is to say, the static electricity will be transmitted to the connection position of the first signal line and the conductive pattern and then transmitted to the conductive pattern. The conductive pattern includes at least two spaced-apart contact portions, and the first signal line is connected to at least two contact portions of the conductive pattern. That is, the first signal line includes two connection positions connected to the contact portions. In this way, two protrusions can be formed at the connection position of the first signal line and the conductive pattern, which is more conducive to the transmission of static electricity to the conductive pattern. After the static electricity is transmitted to the conductive pattern, corona discharge can occur at the end or edge of the conductive pattern, thereby releasing the static electricity into the insulating layer in contact with the conductive pattern. The charge of the static electricity is small, and the insulating layer can absorb and release a small amount of static electricity charges, thereby releasing the static electricity on the first signal line, thus avoiding reliability problems such as breakdown of the first signal line caused by the accumulation of static electricity on the first signal line.

[0008] In some embodiments, the first conductive layer further includes a plurality of first connection lines, the plurality of first connection lines are arranged at intervals along the second direction and all extend along the first direction. The second conductive layer further includes a plurality of data lines, and one data line is electrically connected to a column of pixel circuits; the plurality of data lines include a plurality of first data lines and a plurality of second data lines, and the plurality of first data lines are respectively located on both sides of the plurality of second data lines; one first data line is connected to one first connection line. The plurality of first signal lines include a plurality of fan-out lines, and one fan-out line is electrically connected to one first connection line. The plurality of conductive patterns include a plurality of first conductive patterns, and the fan-out line is electrically connected to at least one first conductive pattern.

[0009] In some embodiments, the fan-out line includes a plurality of fan-out sub-lines arranged at intervals along the second direction, and the mutually close ends of two adjacent fan-out sub-lines are electrically connected to the same first conductive pattern.

[0010] In some embodiments, the first conductive pattern includes an extension portion and two contact portions, the extension portion extends along the second direction, the two contact portions are respectively connected to the two ends of the extension portion along the second direction, and the dimension of the contact portion along the first direction is greater than the dimension of the extension portion along the first direction. There is an opening between two adjacent fan-out sub-lines, and the mutually close ends of two adjacent fan-out sub-lines are respectively electrically connected to the two contact portions of the same first conductive pattern.

[0011] In some embodiments, the fan-out lines are continuous along the second direction; the first conductive pattern includes a plurality of contact portions and at least one extension portion that are alternately connected along the second direction, the extension portion extends along the second direction, and the size of the contact portion along the first direction is greater than the size of the extension portion along the first direction. The fan-out lines are electrically connected to the plurality of contact portions of the first conductive pattern.

[0012] In some embodiments, the plurality of first conductive patterns are arranged in multiple columns along the first direction, and each column includes a plurality of first conductive patterns arranged along the second direction. One fan-out line is electrically connected to the plurality of first conductive patterns in one column.

[0013] In some embodiments, along the second direction, the plurality of first conductive patterns are evenly arranged. The arrangement density of the pixel circuits is an integer multiple of the arrangement density of the first conductive patterns.

[0014] In some embodiments, the array substrate includes a display area and a peripheral area surrounding the display area, and the plurality of pixel circuits are disposed in the display area. The array substrate further includes a first power bus, the first power bus is located in the peripheral area and is configured to be electrically connected to the cathodes of the light-emitting devices. The plurality of first signal lines further include a plurality of first power signal lines, and at least one end of the plurality of first power signal lines is electrically connected to the first power bus along the second direction. The plurality of conductive patterns further include a plurality of second conductive patterns, and one first power signal line is electrically connected to at least one second conductive pattern.

[0015] In some embodiments, along the second direction, one first power signal line is electrically connected to a plurality of second conductive patterns, and the plurality of second conductive patterns are evenly arranged.

[0016] In some embodiments, the plurality of conductive patterns include a plurality of first conductive patterns; the plurality of first conductive patterns have the same structure as the plurality of second conductive patterns, and the plurality of first conductive patterns have the same arrangement density as the plurality of second conductive patterns.

[0017] On the other hand, a display device is provided. The display device includes a plurality of light-emitting devices and the array substrate as described in any of the above embodiments. The plurality of light-emitting devices are disposed on the array substrate, and one light-emitting device is connected to one pixel circuit of the array substrate.

[0018] In yet another aspect, a display device is provided. The display device includes the above display panel.

[0019] The above display panel and display device have the same structure and beneficial technical effects as the array substrate provided in some of the above embodiments, and will not be described in detail herein. Description of the Drawings

[0020] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for use in some embodiments of the present disclosure will be briefly introduced below. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure, and those of ordinary skill in the art can also obtain other drawings based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams and do not limit the actual dimensions of the products involved in the embodiments of the present disclosure, the actual processes of the methods, the actual timings of the signals, etc.

[0021] Figure 1 Schematic diagram of a display device according to some embodiments;

[0022] Figure 2 Drive architecture diagram of a display device according to some other embodiments;

[0023] Figure 3 Cross-sectional structure diagram of a display panel according to some embodiments;

[0024] Figure 4 Top view structure diagram of a first conductive layer and a second conductive layer according to some embodiments;

[0025] Figure 5 For Figure 4 Local enlarged view of area B in

[0026] Figure 6 For the sectional view along Figure 5 Section line A1-A1 in

[0027] Figure 7 Partial structure diagram of an array substrate according to some embodiments;

[0028] Figure 8 Top view structure diagram of a first conductive layer and a second conductive layer according to some embodiments;

[0029] Figure 9 For Figure 8 Local enlarged view of area C in

[0030] Figure 10 For the sectional view along Figure 9 Section line A2-A2 in

[0031] Figure 11 Connection structure diagram of a first signal line and a conductive pattern according to some embodiments;

[0032] Figure 12A top view structural diagram of an array substrate without a second conductive layer according to some embodiments. Detailed implementation manners

[0033] Next, in conjunction with the accompanying drawings, the technical solutions in some embodiments of the present disclosure will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0034] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is interpreted in an open, inclusive sense, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples" or "some examples", etc., are intended to indicate that specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. In addition, the described specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0035] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality" is two or more.

[0036] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or integrated; it may be directly connected or indirectly connected through an intermediate medium.

[0037] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0038] The use of "suitable for" or "configured to" herein means open and inclusive language, which does not exclude a device suitable for or configured to perform additional tasks or steps.

[0039] In addition, the use of "based on" means open and inclusive, because a process, step, calculation or other action "based on" one or more of the said conditions or values may, in practice, be based on additional conditions or values beyond the said ones.

[0040] As used herein, "parallel", "perpendicular", and "equal" include the stated cases and cases similar to the stated cases, where the range of the similar cases is within an acceptable deviation range, and the acceptable deviation range is determined by one of ordinary skill in the art considering the measurements being discussed and the errors associated with the measurements of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism can be, for example, within a deviation of 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, within a deviation of 5°. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality can be, for example, that the difference between the two equal ones is less than or equal to 5% of either one of them.

[0041] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0042] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of the regions are enlarged for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but include shape deviations caused, for example, by manufacturing. For example, an etched region shown as rectangular will generally have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0043] Referring to Figure 1 , embodiments of the present disclosure provide a display device 1000, and the display device 1000 is a product with an image display function. Exemplarily, the display device 1000 can be any device that displays whether it is moving (e.g., video) or stationary (e.g., still image) and whether it is text or image.

[0044] Exemplarily, the display device 1000 can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a personal digital assistant (PDA), a mobile phone (cell phone), a watch, a clock, a calculator, a GPS receiver / navigator, a camera, a display of a camera view (e.g., a display of a rearview camera in a vehicle), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, an in-vehicle display, a flight display, etc. For example, as Figure 1 shown, the display device 1000 can be a mobile phone.

[0045] In terms of the light-emitting type of the display device 1000, the above display device 1000 can be an organic light-emitting diode display device, a quantum dot light-emitting diode (QLED) display device, or a mini / micro light-emitting diode (MLED) display device, etc. In terms of the form of the display device 1000, the above display device 1000 can be a flat display device, a curved display device, or a foldable display device, etc. In terms of the shape of the display device 1000, the above display device 1000 can be rectangular or circular, etc. The embodiments of the present disclosure do not make specific limitations in this regard. Hereinafter, taking the display device as a rectangular and flat organic light-emitting diode display device as an example, some embodiments of the present disclosure will be schematically described. However, the implementation manners of the present disclosure are not limited thereto, and any other display device can also be considered as long as the same technical concept is applied.

[0046] Referring to Figure 2 , in some embodiments, the display device 1000 includes a display panel 1100 and a driving circuit board 1200. The driving circuit board 1200 can include, for example, a timing controller (TCON), a power management chip DC / DC, and a variable resistor voltage dividing circuit (generating Vcom) and other driving circuits. The driving circuit board 1200 can also include other circuit structures, which will not be listed one by one here. The driving circuit board 1200 is electrically connected to the display panel 1100 for transmitting control signals to the display panel 1100, thereby driving the display panel 1100 to realize image display. In addition, the display device 1000 can also include a touch structure, an under-screen camera, and an under-screen fingerprint recognition sensor, etc., so that the display device 1000 can realize various different functions such as touch, photographing, video recording, fingerprint recognition, or face recognition, etc., and no specific limitations are made here.

[0047] Continue to refer to Figure 2 , the display panel 1100 has a display area AA and a peripheral area BB. The peripheral area BB is at least on one side of the display area AA. Exemplarily, the peripheral area BB is arranged around the display area AA.

[0048] The display area AA is an area on the display panel 1100 for displaying images. The display area AA is provided with a plurality of sub-pixels P. The sub-pixel P is the smallest light-emitting unit on the display panel 1100, and the sub-pixel P is used to display images. The peripheral area BB can be used, for example, to set a gate driver circuit (Gate driver on Array, abbreviated as: GOA) and control signal lines (such as clock signal lines, power supply voltage signal lines, etc.). Of course, the functions of the peripheral area BB are not limited to this, and the non-disclosed embodiments will not be elaborated one by one.

[0049] Among them, the plurality of sub-pixels P can emit light of different colors. For example, the plurality of sub-pixels P include red sub-pixels that emit red light, green sub-pixels that emit green light, and blue sub-pixels that emit blue light.

[0050] The plurality of sub-pixels P are arranged in multiple rows and multiple columns. Each row includes a plurality of sub-pixels P arranged along the first direction X, and the multiple rows of sub-pixels P are arranged along the second direction Y. Each column includes a plurality of sub-pixels P arranged along the second direction Y, and the multiple columns of sub-pixels P are arranged along the first direction X. Among them, the first direction X and the second direction Y intersect. For example, the first direction X is perpendicular to the second direction Y.

[0051] The sub-pixel P includes a pixel circuit 120 and a light-emitting device 200. The pixel circuit 120 includes a plurality of thin film transistors (Thin Film Transistor; abbreviated as: TFT) and at least one capacitor Cst. Exemplarily, the pixel circuit 120 can be a "3T1C" circuit, a "7T1C" circuit, an "8T1C" circuit, etc. The embodiments of the present disclosure are not limited to this, and any other pixel circuit can also be considered as long as the same technical idea is applied. Among them, "T" refers to TFT, and the number before "T" refers to the number of TFTs; "C" refers to the capacitor Cst, and the number before "C" refers to the number of capacitor Csts.

[0052] Refer to Figure 3 , in some embodiments, the display panel 1100 includes an array substrate 100, a light-emitting device 200, and a packaging layer 300 that are stacked. Of course, the display panel 1100 may further include a functional stack layer disposed on the side of the packaging layer 300 away from the array substrate 100. The functional stack layer can be, for example, one or more of a touch function layer, an anti-reflection layer, a hardening layer, and an anti-fingerprint layer, so that the display panel can achieve corresponding functions. The embodiments of the present disclosure do not specifically limit the types and numbers of the above functional stack layers.

[0053] Among them, the light-emitting device 200 includes an anode 201, a light-emitting functional layer 202, and a cathode layer 203 that are stacked. The cathode layers 203 of multiple light-emitting devices 200 are interconnected to form a continuous integral layer structure. The display panel 1100 may further include a pixel defining layer PDL. The pixel defining layer PDL is disposed on a side of the anode 201 away from the array substrate 100, and the pixel defining layer PDL includes multiple openings, and at least a part of each light-emitting functional layer 202 is located within one opening.

[0054] The encapsulation layer 300 is configured to reduce the risk of water vapor and oxygen in the external environment entering the light-emitting device 200, thereby improving the service life of the display panel 1100. The encapsulation layer 300 may be an encapsulation film or an encapsulation substrate. Exemplarily, as Figure 3 shown, the encapsulation layer 300 may be an encapsulation film. In this case, the encapsulation layer 300 may include a first inorganic encapsulation layer 301, an organic encapsulation layer 302, and a second inorganic encapsulation layer 303 that are sequentially stacked.

[0055] The array substrate 100 includes a substrate 110 and a pixel circuit disposed on the substrate 110. One pixel circuit is connected to one light-emitting device and is configured to drive the light-emitting device to emit light. Among them, the substrate 110 may be a rigid substrate, and the material of the rigid substrate may include, for example, glass. Alternatively, the substrate 110 may be a flexible substrate, and the material of the flexible substrate may include, for example, any one of polyimide (abbreviation: PI), polycarbonate (abbreviation: PC), or polyvinyl chloride (abbreviation: PVC).

[0056] The array substrate 100 may include multiple conductive layers, and the multiple conductive layers are configured to form multiple pixel circuits and multiple signal lines for driving the pixel circuits. The multiple conductive layers may include, for example, a first semiconductor layer ACT1, a first gate conductive layer GT1, a second gate conductive layer GT2, a second semiconductor layer ACT2, a third gate conductive layer GT3, a first source-drain conductive layer SD1, and a second source-drain conductive layer SD2 that are sequentially disposed in a direction perpendicular to the substrate 110 and away from the substrate 110. Of course, the array substrate may further include other conductive layers, such as a third source-drain conductive layer, which is not specifically limited herein as long as the same technical concept is adopted. Among them, the thin-film transistor TFT may include a semiconductor pattern 101 located in the first semiconductor layer ACT1, a gate 102 located in the first gate conductive layer GT1, and a source 103 and a drain 104 located in the first source-drain conductive layer SD1; the storage capacitor Cst may include a first electrode plate C1 located in the first gate conductive layer GT1 and a second electrode plate C2 located in the second gate conductive layer GT2.

[0057] The array substrate 100 may further include an insulating layer located between adjacent conductive layers. For example, the array substrate 100 may include a first gate insulating layer GI1 located between the first semiconductor layer ACT1 and the first gate conductive layer GT1, a second gate insulating layer GI2 located between the first gate conductive layer GT1 and the second gate conductive layer GT2, a first interlayer dielectric layer ILD1 located between the second gate conductive layer GT2 and the second semiconductor layer ACT2, a second interlayer dielectric layer ILD2 located between the second semiconductor layer ACT2 and the third gate conductive layer GT3, a first planarization layer PLN1 located between the third gate conductive layer GT3 and the first source-drain conductive layer SD1, and a second planarization layer PLN2 located between the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2. Of course, the array substrate 100 may further include other insulating film layers, which will not be elaborated here one by one.

[0058] Referring to Figure 4 、 Figure 5 and Figure 6 , the array substrate 100 provided by an embodiment of the present disclosure includes a first conductive layer 10 and a second conductive layer 20, and the second conductive layer 20 is disposed on a side of the first conductive layer 10 away from the substrate 110.

[0059] The first conductive layer 10 includes a plurality of conductive patterns 11, and there is a gap between the plurality of conductive patterns 11 and the plurality of pixel circuits. The fact that there is a gap between the conductive patterns 11 and the plurality of pixel circuits means that: the conductive patterns 11 are not directly in contact and connected with the pixel circuits 120, or in other words, the conductive patterns 11 are not used to transmit signals to the pixel circuits 120. Exemplarily, when the first conductive layer 10 is the first source-drain conductive layer SD1, the pixel circuit may include a source electrode and a drain electrode located on the first source-drain conductive layer SD1, and there is a gap between the conductive pattern and the source electrode and the drain electrode of the pixel circuit; moreover, the conductive patterns 11 are not connected to other conductive layers (such as the first gate conductive layer and the second gate conductive layer, etc.) and the semiconductor layer on the side of the first conductive layer 10 close to the substrate.

[0060] The second conductive layer 20 includes a plurality of first signal lines 21, and the plurality of first signal lines 21 are arranged at intervals along the first direction X and all extend along the second direction Y. The first direction X is the row direction in which the plurality of pixel circuits 120 are arranged ( Figure 4 the horizontal direction in

[0061] A first signal line 21 is electrically connected to at least one conductive pattern 11. Since there is a gap between the conductive pattern 11 and the pixel circuit, the first signal line 21 does not transmit electrical signals to the pixel circuit through the conductive pattern 11. Based on this, the position of the conductive pattern 11 can be set arbitrarily as long as it does not interfere with other structures of the array substrate (such as contact or electrical coupling).

[0062] In the case of static electricity appearing on the first signal line 21, the static electricity will accumulate at the protrusions, corners or other protruding sharp corners of the first signal line 21. At the connection position between the first signal line 21 and the conductive pattern 11, a via 105 is formed in the insulating layer between the first conductive layer 10 and the second conductive layer 20. A part of the first signal line 21 is located within the via 105 and a protrusion is formed within the via 105. In other words, the first signal line 21 protrudes towards the side close to the substrate 110 to form a protrusion. Based on this, the static electricity will accumulate at the connection position between the first signal line 21 and the conductive pattern 11 (the part of the first signal line 21 located within the via 105), and is transmitted to the conductive pattern 11, and then released through the conductive pattern 11, thereby releasing the static electricity on the first signal line 21. As Figure 6 shown, the conductive pattern 11 includes at least two spaced-apart contact portions 1112, and the first signal line 21 is connected to at least two contact portions 1112 of the conductive pattern 11, that is, the first signal line 21 includes two connection positions with the contact portions 1112. In this way, two protrusions can be formed at the connection position between the first signal line 21 and the conductive pattern 11, which is more conducive to the transmission of static electricity to the conductive pattern 11.

[0063] Among them, the first conductive layer 10 can be any one of the multiple conductive layers included in the array substrate 100 as shown in Figure 3 except for the conductive layer farthest from the substrate 110. The second conductive layer 20 can be any conductive layer on the side of the first conductive layer 10 away from the substrate 110. Exemplarily, the second conductive layer 20 can be a film layer for setting signal traces in the array substrate 100, and the first conductive layer 10 is any conductive layer on the side of the second conductive layer 20 close to the substrate 110. For example, the first conductive layer 10 is a conductive layer adjacent to the second conductive layer 20. In this way, the depth of the via formed in the insulating layer between the first signal line 21 and the conductive pattern 11 and disposed between the first conductive layer 10 and the second conductive layer 20 can be reduced, and the connection difficulty between the first signal line 21 and the conductive pattern 11 can be reduced.

[0064] Exemplarily, the first conductive layer 10 may be the third gate conductive layer GT3, and the second conductive layer 20 may be the first source-drain conductive layer SD1; alternatively, the first conductive layer 10 may be the first source-drain conductive layer SD1, and the second conductive layer 20 may be the second source-drain conductive layer SD2; or, in the case where the array substrate includes a third source-drain conductive layer, the first conductive layer 10 may be the second source-drain conductive layer SD2, and the second conductive layer 20 may be the third source-drain conductive layer. Of course, the first conductive layer 10 and the second conductive layer 20 may also not be adjacent conductive layers. Exemplarily, the first conductive layer 10 may be the third gate conductive layer GT3, and the second conductive layer 20 may be the second source-drain conductive layer SD2. It can be understood that the first conductive layer 10 and the second conductive layer 20 may also be other suitable combinations, and the embodiments of the present disclosure will not be listed one by one, as long as the same technical idea is adopted.

[0065] In the following embodiments of the present disclosure, the first conductive layer 10 is taken as the first source-drain conductive layer SD1, and the second conductive layer 20 is taken as the second source-drain conductive layer SD2 as an example for exemplary illustration. However, the embodiments of the present application are not limited thereto, as long as the same technical idea is adopted.

[0066] In some embodiments, such as Figure 4 and Figure 7As shown, the first conductive layer 10 further includes a plurality of first connection lines 12. The plurality of first connection lines 12 are arranged at intervals along the second direction Y and all extend along the first direction X. The second conductive layer 20 further includes a plurality of data lines 22. One data line 22 is electrically connected to a column of pixel circuits. The plurality of data lines 22 include a plurality of first data lines 221 and a plurality of second data lines 222. The plurality of first data lines 221 are respectively located on both sides of the plurality of second data lines 222 along the first direction X. Exemplarily, the plurality of first data lines 221 may be located in the edge region AA2 of the display area AA along the first direction X, and the plurality of second data lines 222 may be located in the central region AA1 of the display area AA along the first direction X. One first data line 221 is connected to one first connection line 12. The plurality of first signal lines 21 included in the second conductive layer 20 include a plurality of fan-out lines 211. One fan-out line 211 is electrically connected to one first connection line 12. The plurality of fan-out lines 211 may be located in the central region AA1 of the display area AA along the first direction X. Based on this, the first data line 221 located in the edge region AA2 of the display area AA along the first direction X is sequentially connected to the central region AA1 of the display area AA along the first direction X through one first connection line 12 and one fan-out line 211 and is led out from the edge of the central region AA1 close to the peripheral area. The above setting manner of the data line 22 is also called Fanout In AA (abbreviation: FIAA) or Fanout In Panel (abbreviation: FIP). This is beneficial to reducing the size of the peripheral area along the second direction Y, that is, reducing the border width of the array substrate 100, and is beneficial to the display device 1000 achieving a narrow border. The fan-out line 211 is arranged in the central region AA1 of the display area AA and is not used to transmit data signals to the pixel circuits in the central region AA1. That is to say, the fan-out line 211 is electrically insulated from the pixel circuits located on the side of the fan-out line 211 close to the substrate 110.

[0067] In the related art, the fan-out line 211 is arranged in a single film layer and is not connected to other structures except the first connection line 12 in the display area AA, resulting in a lack of a path for releasing the generated static electricity; moreover, the fan-out line 211 extends between sub-pixels and needs to avoid some conductive structures in the pixel circuits, so it has a certain pattern shape, for example, there are corners or protrusions, and static electricity may accumulate at the edges of the corners or protrusions of the fan-out line 211. For the above reasons, static electricity is likely to accumulate in the fan-out line, resulting in low reliability of the array substrate.

[0068] Refer to Figure 5 and Figure 6, in the embodiments of the present disclosure, to solve the above problems, multiple conductive patterns 11 include multiple first conductive patterns 111. A fan-out line 211 is electrically connected to at least one first conductive pattern 111, and at the position where the fan-out line 211 is connected to the first conductive pattern 111, a convex structure protruding towards the substrate 110 side is formed. Based on this, when static electricity appears on the fan-out line 211, the static electricity will be transmitted towards the position where the fan-out line 211 is connected to the first conductive pattern 111 and transmitted to the first conductive pattern 111, and the static electricity is released on the first conductive pattern 111, which can improve the reliability of the array substrate.

[0069] In some embodiments, as Figure 5 and Figure 6 shown, the fan-out line 211 includes multiple fan-out sub-lines 2111 arranged at intervals along the second direction Y. In other words, the fan-out line 211 includes multiple mutually disconnected fan-out sub-lines 2111, and there is an opening 2112 between adjacent two fan-out sub-lines 2111. The two ends that belong to adjacent two fan-out sub-lines 2111 and are close to each other are electrically connected to the same first conductive pattern 111, that is, adjacent two fan-out sub-lines 2111 are electrically connected through a first conductive pattern 111. In this way, during the process of the fan-out line 211 transmitting current, the current can flow through each first conductive pattern 111, ensuring that the static electricity on the fan-out line 211 can be transmitted to the first conductive pattern 111 and released through the first conductive pattern 111.

[0070] Referring to Figure 5 and Figure 6 , the first conductive pattern 111 includes an extension portion 1111 and two contact portions 1112. The extension portion 1111 extends along the second direction Y, and the two contact portions 1112 are respectively connected to the two ends of the extension portion 1111 along the second direction Y. There is an opening 2112 between adjacent two fan-out sub-lines 2111, and the orthographic projection of the opening 2112 on the substrate 110 overlaps with the orthographic projection of the extension portion 1111 on the substrate 110. The two ends that belong to adjacent two fan-out sub-lines 2111 and are close to each other are respectively electrically connected to the two contact portions 1112 of the same first conductive pattern 111. The dimension of the contact portion 1112 along the first direction X is greater than the dimension of the extension portion 1111 along the first direction X. In this way, it is beneficial to reduce the alignment accuracy requirements between the fan-out sub-line 2111 and the contact portion 1112, reduce the connection difficulty between the fan-out sub-line 2111 and the contact portion 1112, and increase the contact area between the fan-out sub-line 2111 and the contact portion 1112, and reduce the resistance at the connection between the fan-out sub-line 2111 and the contact portion 1112.

[0071] In other embodiments, referring to Figure 8 and Figure 9, the fan-out line 211 is continuous along the second direction Y, that is, there is no opening on the fan-out line 211. In this way, the fan-out line 211 is arranged in parallel with the first conductive pattern 111. The first conductive pattern 111 can not only release the static electricity on the fan-out line 211, but also reduce the resistance of the fan-out line 211.

[0072] Refer to Figure 9 , Figure 10 and Figure 11 , the first conductive pattern 111 includes a plurality of contact portions 1112 and at least one extension portion 1111 that are alternately connected along the second direction Y. The dimension of the contact portion 1112 along the first direction X is greater than the dimension of the extension portion 1111 along the first direction X, which is beneficial to reducing the alignment accuracy requirements between the fan-out line 211 and the contact portion 1112, reducing the connection difficulty between the fan-out line 211 and the contact portion 1112, and increasing the contact area between the fan-out line 211 and the contact portion 1112, and reducing the resistance at the connection between the fan-out line 211 and the contact portion 1112. The fan-out line 211 is electrically connected to a plurality of contact portions 1112 of the first conductive pattern 111. In other words, there are a plurality of connection points between the fan-out line 211 and the same first conductive pattern 111. In this way, it is beneficial to increase the connection reliability and stability between the fan-out line 211 and the same first conductive pattern 111, and is beneficial to reducing the resistance of the fan-out line 211.

[0073] Exemplarily, a contact portion 1112 is respectively provided at both ends of the first conductive pattern 111 along the second direction Y, and adjacent two contact portions 1112 are connected by an extension portion 1111. For example, as Figure 10 shown, the first conductive pattern 111 includes two contact portions 1112 and one extension portion 1111; or, refer to Figure 11 , the first conductive pattern 111 may also include three contact portions 1112 and two extension portions 1111. The first conductive pattern 111 may also include other numbers of two contact portions 1112 and extension portions 1111, as long as the same technical idea is adopted.

[0074] In some embodiments, as Figure 12 shown, a plurality of first conductive patterns 111 are arranged in multiple columns along the first direction X, and each column includes at least one first conductive pattern 111 arranged along the second direction Y. One fan-out line 211 is electrically connected to a plurality of first conductive patterns 111 in one column. In this way, the density of the first conductive patterns 111 connected to the fan-out line 211 can be increased, and the static electricity generated at any position on the fan-out line 211 can be transmitted to the adjacent first conductive pattern 111, further improving the static electricity release effect of the fan-out line 211. It can be understood that in Figure 12In order to distinguish the first conductive pattern 111 from the second conductive pattern 112, different filling patterns are used for the two, but they are in the same film layer and are formed together by the same film-forming process.

[0075] As Figure 12 shown, along the second direction Y, a plurality of first conductive patterns 111 are evenly arranged, which is beneficial to improving the uniformity of the first conductive pattern 111 and the pattern uniformity of the first conductive layer 10. The arrangement density of the pixel circuits 120 is an integer multiple of the arrangement density of the first conductive patterns 111. In other words, the pitch of the first conductive patterns 111 in the second direction Y (the pitch of the first conductive patterns 111) is an integer multiple of the pitch of the pixel circuits 120 in the second direction Y (the pitch of the pixel circuits 120), that is, one first conductive pattern 111 is provided on the side of each integer number of pixel circuits 120 away from the substrate, which is beneficial to improving the structural uniformity of the array substrate 100 and reducing the risk of the display panel having a blanking problem due to the distribution difference of the first conductive patterns 111.

[0076] Exemplarily, as Figure 12 shown, the arrangement density of the pixel circuits 120 is equal to the arrangement density of the first conductive patterns 111. In this way, the pattern uniformity of the first conductive layer 10 can be maximally improved, and the structural uniformity of the array substrate can be maximally improved.

[0077] As Figure 7 shown, the array substrate 100 further includes a first power bus VSS. The first power bus VSS is located in the peripheral area BB. The first power bus VSS is configured to be electrically connected to the cathode of the light-emitting device 200, that is, the first power bus VSS is electrically connected to the cathode layer 203. The plurality of first signal lines 21 included in the second conductive layer 20 further includes a plurality of first power signal lines 212. Along the second direction Y, at least one end of the plurality of first power signal lines 212 is electrically connected to the first power bus VSS. The plurality of first power signal lines 212 are arranged at intervals along the first direction X, and the plurality of first power signal lines 212 all extend along the second direction Y and are then electrically connected to the cathode layer. The plurality of first power signal lines 212 can reduce the resistance of the cathode layer, thereby reducing the voltage drop on the cathode layer and improving the display uniformity of the display area AA. The above-described setting method of the power supply auxiliary line 50 is also referred to as the SIP (VSS InPanel) technology.

[0078] As Figure 4 and Figure 8As shown, the plurality of conductive patterns 11 further includes a plurality of second conductive patterns 112. A first power signal line 212 is electrically connected to at least one second conductive pattern 112. At the position where the first power signal line 212 is connected to the second conductive pattern 112, a protrusion is formed protruding towards the substrate side. In the case where static electricity appears on the first power signal line 212, the static electricity will accumulate at the protruding position of the first power signal line 212. That is to say, the static electricity will be transmitted to the connection position of the first power signal line 212 and the second conductive pattern 112, and then transmitted to the second conductive pattern 112, and corona discharge occurs at the edge or end of the second conductive pattern 112, so as to release the static electricity into the insulating layer in contact with the conductive pattern 112. The charge of the static electricity is usually small, and the insulating layer (such as a passivation layer or a planarization layer) can absorb and release a small amount of static charges, thereby releasing the static electricity on the first power signal line 212. It can be understood that the static electricity charge is small. Although the insulating layer is electrically insulating, it can absorb static electricity and release the static electricity.

[0079] Continue to refer to Figure 4 and Figure 8 , along the second direction Y, a first power signal line 212 is electrically connected to a plurality of second conductive patterns 112, and the plurality of second conductive patterns 112 are evenly arranged. In this way, the density of the second conductive patterns 112 connected to the first power signal line 212 can be increased, and the static electricity generated at any position on the first power signal line 212 can be transmitted to the adjacent second conductive patterns 112, further improving the static electricity release effect of the first power signal line 212.

[0080] In some embodiments, as Figure 4 and Figure 8 shown, the plurality of conductive patterns 11 includes a plurality of first conductive patterns 111 and a plurality of second conductive patterns 112. The structures of the plurality of first conductive patterns 111 and the plurality of second conductive patterns 112 are the same. That is to say, the shape of the orthographic projection of the first conductive pattern 111 on the substrate is the same as the shape of the orthographic projection of the second conductive pattern 112 on the substrate, and the size of the orthographic projection of the first conductive pattern 111 on the substrate is equal to the size of the orthographic projection of the second conductive pattern 112 on the substrate. The arrangement densities of the plurality of first conductive patterns 111 and the plurality of second conductive patterns 112 are the same. In this way, the structural uniformity of the first conductive layer 10 can be further improved, and the risk of image disappearance in the display panel can be reduced.

[0081] Of course, in some other embodiments, the first conductive pattern 111 and the second conductive pattern 112 may also have differences. For example, when the first conductive pattern 111 includes two contact portions 1112, the second conductive pattern 112 may include one or three or other numbers of contact portions; the embodiments of the present disclosure are not limited to this, as long as the same technical idea is adopted.

[0082] In some embodiments, as Figure 4 shown, when the fan-out line 211 includes a plurality of fan-out sub-lines 2111 spaced along the second direction Y, the first power supply signal line 212 may also include a plurality of power supply sub-lines 2121 spaced along the second direction Y, and the structure of the fan-out sub-line 2111 is the same as that of the power supply sub-line 2121. That is to say, the shape and size of the orthographic projection of the fan-out sub-line 2111 on the substrate respectively correspond to and are the same as the shape and size of the orthographic projection of the power supply sub-line 2121 on the substrate. Alternatively, as Figure 8 shown, when the fan-out line 211 is continuous along the second direction, the first power supply signal line 212 may also be continuous along the second direction Y. This is beneficial to improving the structural uniformity of the second conductive layer 20.

[0083] It can be understood that in some other embodiments, when the fan-out line 211 includes a plurality of fan-out sub-lines 2111 spaced along the second direction Y, the first power supply signal line 212 may also be continuous along the second direction Y. Alternatively, when the fan-out line 211 is continuous along the second direction, the first power supply signal line 212 may also include a plurality of power supply sub-lines spaced along the second direction Y. Of course, the embodiments of the present disclosure are not limited thereto, as long as the same technical idea is adopted.

[0084] As described above, the above are only the specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure, when thinking of changes or substitutions, should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. An array substrate, characterized in that, comprising: a substrate; a plurality of pixel circuits disposed on the substrate, and the plurality of pixel circuits are arranged in multiple rows and multiple columns; a first conductive layer including a plurality of conductive patterns, the plurality of conductive patterns having a gap from the plurality of pixel circuits, and the conductive pattern includes at least two spaced contact portions; a second conductive layer disposed on a side of the first conductive layer away from the substrate, including a plurality of first signal lines, the plurality of first signal lines being spaced apart along a first direction and all extending along a second direction, one first signal line being electrically connected to at least one conductive pattern, and the first signal line being connected to at least two contact portions of the conductive pattern; the first direction is the row direction in which the plurality of pixel circuits are arranged, and the second direction is the column direction in which the plurality of pixel circuits are arranged.

2. The array substrate according to claim 1, characterized in that, the first conductive layer further includes a plurality of first connection lines, the plurality of first connection lines being spaced apart along the second direction and all extending along the first direction; the second conductive layer further includes a plurality of data lines, one data line being electrically connected to one column of pixel circuits; the plurality of data lines include a plurality of first data lines and a plurality of second data lines, the plurality of first data lines being respectively located on both sides of the plurality of second data lines; one first data line is connected to one first connection line; the plurality of first signal lines include a plurality of fan-out lines, one fan-out line being electrically connected to one first connection line; the plurality of conductive patterns include a plurality of first conductive patterns, and the fan-out line is electrically connected to at least one first conductive pattern.

3. The array substrate according to claim 2, characterized in that, the fan-out line includes a plurality of fan-out sub-lines spaced apart along the second direction, and two mutually adjacent ends of two adjacent fan-out sub-lines are electrically connected to the same first conductive pattern.

4. The array substrate according to claim 3, characterized in that, the first conductive pattern includes an extension portion and two contact portions, the extension portion extending along the second direction, the two contact portions being respectively connected to two ends of the extension portion arranged along the second direction, and the size of the contact portion along the first direction is greater than the size of the extension portion along the first direction; there is an opening between two adjacent fan-out sub-lines, and two mutually adjacent ends of two adjacent fan-out sub-lines are respectively electrically connected to two contact portions of the same first conductive pattern.

5. The array substrate according to claim 2, characterized in that, the fan-out line is continuous along the second direction; the first conductive pattern includes a plurality of contact portions and at least one extension portion alternately connected along the second direction, the extension portion extending along the second direction, and the size of the contact portion along the first direction is greater than the size of the extension portion along the first direction; the fan-out line is electrically connected to a plurality of contact portions of the first conductive pattern.

6. The array substrate according to claim 2, characterized in that, the plurality of first conductive patterns are arranged in multiple columns along the first direction, and one column includes at least one first conductive pattern arranged along the second direction; A fan-out line is electrically connected to a plurality of first conductive patterns in a column.

7. The array substrate according to claim 6, wherein, along the second direction, the plurality of first conductive patterns are uniformly arranged; and the arrangement density of the pixel circuits is an integer multiple of the arrangement density of the first conductive patterns.

8. The array substrate according to any one of claims 1 to 7, wherein, the array substrate includes a display area and a peripheral area surrounding the display area, and the plurality of pixel circuits are disposed in the display area; the array substrate further includes a first power bus located in the peripheral area and configured to be electrically connected to the cathodes of the light-emitting devices; the plurality of first signal lines further include a plurality of first power signal lines, and at least one end of the plurality of first power signal lines is electrically connected to the first power bus along the second direction; the plurality of conductive patterns further include a plurality of second conductive patterns, and a first power signal line is electrically connected to at least one second conductive pattern.

9. The array substrate according to claim 8, wherein, along the second direction, a first power signal line is electrically connected to a plurality of second conductive patterns, and the plurality of second conductive patterns are uniformly arranged.

10. The array substrate according to claim 8, wherein, the plurality of conductive patterns further include a plurality of first conductive patterns; the plurality of first conductive patterns have the same structure as the plurality of second conductive patterns, and the arrangement density of the plurality of first conductive patterns is the same as that of the plurality of second conductive patterns.

11. A display panel, wherein, comprising: the array substrate according to any one of claims 1 to 10; a plurality of light-emitting devices disposed on the array substrate, and one light-emitting device is connected to one pixel circuit of the array substrate.

12. A display device, wherein, comprising: the display panel according to claim 11; a driving circuit board electrically connected to the display panel and configured to transmit control signals to the display panel.

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