Capacitor, method of manufacturing same, and electronic device including same

Abstract

The invention relates to a capacitor, a method of manufacturing the same, and an electronic device including the same. The capacitor includes: a first electrode; a second electrode disposed to face the first electrode; a dielectric layer disposed between the first electrode and the second electrode; and a conductive interface layer disposed between the first electrode and the dielectric layer. The conductive interface layer includes a first conductive interface layer disposed between the first electrode and the dielectric layer, and a second conductive interface layer disposed between the first conductive interface layer and the dielectric layer. The dielectric layer includes a rutile phase dielectric material. The first conductive interface layer includes a conductive metal oxide material having a stable crystal structure in the rutile phase. A conduction band offset between the second conductive interface layer and the dielectric layer is greater than a conduction band offset between the first conductive interface layer and the dielectric layer.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2023-0170036, filed on November 29, 2023, Korean Patent Application No. 10-2024-0026040, filed on February 22, 2024, and Korean Patent Application No. 10-2024-0059420, filed on May 3, 2024, in the Korean Intellectual Property Office, the entire disclosures of which are incorporated herein by reference. Technical field

[0003] The present disclosure relates to a capacitor and an electronic device including the same. Background art

[0004] As the integration degree of electronic devices (e.g., memories) increases, electronic components in the electronic devices are becoming more miniaturized. However, since the capacitance of a capacitor is proportional to the area of the capacitor, the capacitance may decrease as the capacitor is miniaturized. Accordingly, in order to compensate for the reduction in the size of the capacitor and ensure a desired capacitance, methods for further increasing the dielectric constant of the dielectric layer have been studied. In addition, methods for suppressing an increase in leakage current caused by the miniaturization of the capacitor have been studied. Summary of the invention

[0005] Provided are a capacitor including a dielectric layer including a high-k dielectric material and an electronic device including the same.

[0006] Provided are a capacitor having improved leakage current characteristics and an electronic device including the same.

[0007] Additional aspects will be set forth in part in the following description, and in part will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0008] According to an aspect of the present disclosure, a capacitor includes: a first electrode; a second electrode facing the first electrode; a dielectric layer between the first electrode and the second electrode, the dielectric layer including a rutile-phase dielectric material; and a conductive interface layer between the first electrode and the dielectric layer, the conductive interface layer including a first conductive interface layer between the first electrode and the dielectric layer and including a conductive metal oxide material having a stable crystal structure in a rutile phase, and a second conductive interface layer between the first conductive interface layer and the dielectric layer, wherein a conduction band offset between the second conductive interface layer and the dielectric layer is greater than a conduction band offset between the first conductive interface layer and the dielectric layer.

[0009] For example, the first conductive interface layer may include molybdenum oxide (MoO 2 ) doped with tin (Sn).

[0010] The concentration of Sn in the first conductive interface layer may be in the range of about 0.1 atomic % to about 5.0 atomic %, based on the total number of atoms in the first conductive interface layer.

[0011] The concentration of Sn in the first conductive interface layer may be in the range of about 0.1 atomic % to about 3.0 atomic %, based on the total number of atoms in the first conductive interface layer.

[0012] The first conductive interface layer may have a thickness in the range of about 0.3 nm to about 4 nm.

[0013] The second conductive interface layer may include a second conductive metal oxide material having a stable crystal structure in the rutile phase.

[0014] The second conductive interface layer may include tin oxide (SnO 2 ), germanium oxide (GeO 2 ), or a mixture of tin oxide and germanium oxide ((Sn x Ge 1-x )O 2 , 0 < x < 1).

[0015] The second conductive interface layer may have a thickness in the range of about 0.3 nm to about 1 nm.

[0016] The dielectric layer may include rutile phase titanium oxide (TiO 2 ).

[0017] The dielectric layer may include at least one of the following as a dopant: gallium (Ga), aluminum (Al), lanthanum (La), boron (B), indium (In), scandium (Sc), or yttrium (Y).

[0018] The dopant doping concentration in the dielectric layer may be in the range of about 0 atomic % to about 20 atomic %, based on the total number of atoms in the dielectric layer.

[0019] The dielectric layer may have a thickness in the range of about 3 nm to about 7 nm.

[0020] The first electrode may include at least one of the following: titanium nitride (TiN), vanadium nitride (VN), niobium nitride (NbN), tantalum nitride (TaN), molybdenum nitride (MoN), cobalt nitride (CoN), or a combination thereof.

[0021] The first electrode may have a thickness in the range of about 5 nm to about 10 nm.

[0022] According to another aspect of the present disclosure, a method of manufacturing a capacitor includes: forming a first material layer on an upper surface of a first electrode, the first material layer including amorphous molybdenum oxide (MoO x ); forming a second material layer on the upper surface of the first material layer, the second material layer including tin oxide (SnO 2 ); forming a first conductive interface layer including molybdenum oxide (MoO 2 ) doped with tin (Sn) by crystallizing the amorphous molybdenum oxide via heat treatment; forming a second conductive interface layer on the first conductive interface layer, the second conductive interface layer including tin oxide (SnO 2 ), germanium oxide (GeO 2 ), or a mixture of tin oxide and germanium oxide ((Sn x Ge 1-x )O 2 ), where 0 < x < 1); forming a dielectric layer on the second conductive interface layer; and forming a second electrode on the dielectric layer.

[0023] According to another aspect of the present disclosure, an electronic device includes: a transistor; and a capacitor electrically connected to the transistor, where the capacitor includes: a first electrode; a second electrode facing the first electrode; a dielectric layer between the first electrode and the second electrode and including a rutile phase dielectric material; and a conductive interface layer between the first electrode and the dielectric layer, the conductive interface layer including a first conductive interface layer including a conductive metal oxide material having a stable crystal structure in the rutile phase between the first electrode and the dielectric layer, and a second conductive interface layer between the first conductive interface layer and the dielectric layer, where the conduction band offset between the second conductive interface layer and the dielectric layer is greater than the conduction band offset between the first conductive interface layer and the dielectric layer.

[0024] According to another aspect of the present disclosure, an electronic device includes: a transistor; and a capacitor electrically connected to the transistor, where the capacitor includes: two electrodes facing each other; a dielectric layer between the two electrodes, the dielectric layer including titanium oxide (TiO 2 ); a molybdenum oxide (MoO 2 ) layer doped with tin (Sn) between one of the two electrodes and the dielectric layer; and an interface layer including tin (Sn) and / or germanium (Ge) between the molybdenum oxide (MoO 2 ) layer doped with Sn and the dielectric layer.

[0025] The concentration of Sn in the molybdenum oxide (MoO 2 ) layer doped with Sn can be in the range of about 0.1 atomic % to about 5.0 atomic %.

[0026] In the Sn-doped molybdenum oxide (MoO 2 ), the concentration of Sn can range from about 0.1 atomic % to about 3.0 atomic %.

[0027] In the Sn-doped molybdenum oxide (MoO 2 ), the concentration of Sn can range from about 0.5 atomic % to about 3.0 atomic %.

[0028] For example, TiO included in the dielectric layer 2 can be in the rutile phase, and one of the two electrodes can include titanium nitride (TiN). BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects, features, and advantages of some embodiments of the present disclosure will become more apparent from the following description when considered in conjunction with the accompanying drawings, in which:

[0030] Figure 1 is a cross-sectional view schematically illustrating the structure of a capacitor according to at least one embodiment;

[0031] Figure 2 is for illustrating Figure 1 a schematic energy band diagram of the conduction band offset (CBO) between the second conductive interface layer and the dielectric layer of the capacitor shown in ;

[0032] Figures 3A to 3D is for schematically illustrating Figure 1 a cross-sectional view of a method for forming the conductive interface layer of the capacitor shown in ;

[0033] Figure 4 shows a high-resolution transmission electron microscopy (HR-TEM) photograph of an actually manufactured conductive interface layer according to an embodiment;

[0034] Figure 5 shows an HR-TEM photograph of an actually manufactured conductive interface layer according to a comparative example;

[0035] Figures 6A to 6D is a photograph of the surface of the first conductive interface layer, showing the change in the surface roughness of the conductive interface layer according to the change in the content of tin (Sn) in the first conductive interface layer;

[0036] Figure 7 is a graph showing an example of an ultraviolet (UV) photoelectron spectroscopy (UPS) spectrum for the first conductive interface layer, the spectrum being obtained by UPS measurement;

[0037] Figure 8A table showing the change in the work function (Wf) of the first conductive interface layer according to the change in the content of Sn in the first conductive interface layer, obtained by density functional theory (DFT) simulation;

[0038] Figure 9 A graph showing a comparison of the leakage current characteristics between a capacitor including a conductive interface layer according to an embodiment and a capacitor including a conductive interface layer according to a comparative example;

[0039] Figure 10 A graph showing a comparison of the leakage current characteristics between capacitors according to the content of Sn in the first conductive interface layer;

[0040] Figure 11 A circuit diagram for describing the schematic circuit configuration and operation of an electronic device employing a capacitor according to an embodiment;

[0041] Figure 12 A schematic diagram for illustrating an electronic device according to at least one embodiment;

[0042] Figure 13 A schematic diagram for illustrating an electronic device according to another embodiment;

[0043] Figure 14 A plan view for illustrating an electronic device according to another embodiment;

[0044] Figure 15 For along Figure 14 of line A - A' taken Figure 14 a cross - sectional view of the electronic device;

[0045] Figure 16 A cross - sectional view for illustrating an electronic device according to another embodiment; and

[0046] Figure 17 and 18 A conceptual diagram schematically illustrating a device architecture applicable to a device according to at least one embodiment. Detailed Description

[0047] The embodiments will now be described in detail, with examples shown in the accompanying drawings, where the same reference numerals always denote the same elements. In this regard, the present embodiments may have different forms and should not be construed as limited to the description set forth herein. Accordingly, the embodiments are described below only by way of example with reference to the drawings to illustrate aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The expression such as "at least one (kind) of..." when before or after a list of elements modifies the entire list of elements and not individual elements of the list. Additionally, whenever a range of values is recited, the range includes all values within the range as if explicitly and clearly recited, and may further include the boundaries of the range. Thus, the range of "X" to "Y" includes all values between X and Y, including X and Y. Further, when the terms "about" or "substantially" are used in this specification in conjunction with numerical and / or geometric terms, it is intended that the relevant numerical values include manufacturing tolerances (e.g., ±10%) around the stated numerical values. Additionally, whether the numerical and / or geometric terms are modified as "about" or "substantially", it will be understood that these values and / or geometries should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the stated numerical values and / or geometries.

[0048] Hereinafter, a capacitor and an electronic device including the same will be described in detail with reference to the accompanying drawings. In the following figures, the same reference numerals denote the same elements, and for clarity and convenience of explanation, the dimensions of each element in the figures may be enlarged. Additionally, the embodiments described herein are only examples, and various changes can be made thereto.

[0049] Hereinafter, the terms "on", "above", "under", or "below" may include not only those directly on, under, to the left, or to the right in a contacting manner, but also those on, under, to the left, or to the right in a non - contacting manner. For example, it will be understood that such spatial relative terms, such as "on", "top", etc. are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures, and the device may be oriented otherwise (rotated 90 degrees or in other directions), and the spatial relative terms used herein are accordingly interpreted. As used herein, the singular forms "a", "an" (indefinite articles) and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It will be understood that the terms "comprising", "including", or "having" as used herein specify the presence of the stated elements, but do not preclude the presence or addition of one or more other elements.

[0050] The use of the terms "the" and like indicatives may correspond to both the singular and the plural. Operations forming a method may be performed in any suitable order unless otherwise stated herein or otherwise clearly contradicted by the context, and need not be limited to the order stated.

[0051] Moreover, terms described in this specification such as "unit" and "module" refer to units that process at least one function or operation and can be implemented as a processing circuit system including hardware, software, or a combination of hardware and software. For example, the processing circuit system may more particularly include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. The processing circuit system may include at least one electrical component such as transistors, resistors, capacitors, etc. and / or an electronic circuit including such components.

[0052] The connecting lines or connection members shown in the drawings are intended to represent exemplary functional relationships and / or physical or logical connections between the various elements. It should be noted that in actual devices there may be many alternative or additional functional relationships, physical connections or logical connections.

[0053] In the embodiments, the use of all illustrated or illustrative terms is merely for the purpose of describing the technical concept in detail, and the scope of the present disclosure is not limited by the illustrated or illustrative terms unless they are limited by the claims.

[0054] Figure 1 A cross-sectional view illustrating a schematic structure of a capacitor 100 according to at least one embodiment. Referring to Figure 1 , the capacitor 100 may include a first electrode 110, a second electrode 140 disposed to face the first electrode 110, a dielectric layer 130 disposed between the first electrode 110 and the second electrode 140, and a conductive interface layer 120 disposed between the first electrode 110 and the dielectric layer 130. That is, the dielectric layer 130 may be disposed between two electrodes 110 and 140 facing each other. In a method of manufacturing the capacitor 100, the conductive interface layer 120 may be formed on the upper surface of the first electrode 110, the dielectric layer 130 may be formed on the upper surface of the conductive interface layer 120, and the second electrode 140 may be formed on the upper surface of the dielectric layer 130.

[0055] The dielectric layer 130 may include a rutile-phase dielectric material. For example, the dielectric layer 130 may include rutile-phase titanium oxide (TiO 2) Titanium oxide has different dielectric constants depending on its phase. While anatase-phase titanium oxide has a dielectric constant of about 40, rutile-phase titanium oxide can have a large dielectric constant of about 80 to about 170 depending on its growth direction. Therefore, the dielectric layer 130 including rutile-phase titanium oxide can have a dielectric constant of about 80 to about 170.

[0056] The dielectric layer 130 can include only titanium oxide or can further include a dopant for the titanium oxide. In at least one example, the dopant can be a p-type dopant having p-type electrical characteristics. For example, the dielectric layer 130 can include titanium oxide doped with at least one dopant selected from: gallium (Ga), aluminum (Al), lanthanum (La), boron (B), indium (In), scandium (Sc), yttrium (Y), and / or the like. The dopant doping concentration in the dielectric layer 130 can be, for example, about 0 atomic % to about 20 atomic %. The rutile-phase titanium oxide has a high dielectric constant, but leakage current can occur because the rutile-phase titanium oxide has n-type electrical characteristics. Since the dopant doped into the dielectric layer 130 has p-type electrical characteristics, the leakage current characteristics of the dielectric layer 130 can be improved.

[0057] According to at least one embodiment, since the dielectric layer 130 has a high dielectric constant, the thickness of the dielectric layer 130 can be reduced and the capacitor 100 can be further miniaturized. For example, the dielectric layer 130 can have a thickness of about 3 nm to about 7 nm.

[0058] The first electrode 110 can include a conductive metal nitride. In particular, the first electrode 110 can include a metal nitride having thermal stability such that the metal nitride is not easily reduced to a metal during a heat treatment process (e.g., at 400 °C or higher; and / or between about 450 °C and about 600 °C, as described below). For example, the first electrode 110 can include at least one conductive metal nitride selected from: titanium nitride (TiN), vanadium nitride (VN), niobium nitride (NbN), tantalum nitride (TaN), molybdenum nitride (MoN), cobalt nitride (CoN), combinations thereof, and / or the like. The first electrode 110 can have a thickness of about 5 nm to about 10 nm.

[0059] The second electrode 140 includes a conductive material. The conductive material of the second electrode 140 is not particularly limited. For example, the second electrode 140 can have a multi-layer structure or a single-layer structure including a metal, a metal nitride, a metal oxide, combinations thereof, and / or the like. The second electrode 140 can include, for example, TiN, MoN, CoN, TaN, tungsten (W), ruthenium (Ru), ruthenium oxide (RuO 2 )), strontium ruthenate (SRO or SrRuO 3 )), iridium (Ir), iridium oxide (IrO 2) Platinum (Pt), platinum oxide (PtO), barium-strontium-ruthenium oxide (BSRO or (Ba,Sr)RuO 3 ) Calcium-ruthenium oxide (CRO or CaRuO 3 ) Lanthanum-strontium-cobalt oxide (LSCO or (La,Sr)CoO 3 ) Combinations thereof, and / or the like.

[0060] The conductive interface layer 120 can be configured such that the rutile-phase dielectric layer 130 can grow thereon to stabilize the rutile-phase dielectric layer and / or to reduce leakage current. According to at least one embodiment, the conductive interface layer 120 can include a first conductive interface layer 121 disposed on the upper surface of the first electrode 110 and a second conductive interface layer 122 disposed on the upper surface of the first conductive interface layer 121. The dielectric layer 130 can be disposed on the upper surface of the second conductive interface layer 122. Thus, the first conductive interface layer 121 can also be referred to as being disposed between the first electrode 110 and the dielectric layer 130, and in particular between the first electrode 110 and the second conductive interface layer 122, and the second conductive interface layer 122 can be referred to as being disposed between the first conductive interface layer 121 and the dielectric layer 130.

[0061] The first conductive interface layer 121 can include a conductive metal oxide material having a stable crystal structure in the rutile phase such that the rutile-phase dielectric layer 130 can grow on the conductive interface layer 120. Additionally, the first conductive interface layer 121 can include a conductive metal oxide material having thermal stability such that the conductive metal oxide is not easily reduced to a metal during a heat treatment process (e.g., at 400 °C or higher; and / or between about 450 °C and about 600 °C, as described below). The first conductive interface layer 121 can also include a conductive metal oxide material having a high enough work function while having little degradation in film quality during the crystallization process. The first conductive interface layer 121 can include, for example, molybdenum oxide doped with Sn (MoO 2 ). In at least one embodiment, the first conductive interface layer 121 can include both molybdenum oxide (MoO 2 ) and tin oxide (SnO 2 ). Thus, the first conductive interface layer 121 can also be referred to as a "molybdenum oxide doped with Sn (MoO 2 ) layer" disposed between one of the two electrodes 110 and 140, namely the first electrode 110 and the dielectric layer 130.

[0062] Like the first conductive interface layer 121, the second conductive interface layer 122 may include a conductive metal oxide material having a stable crystal structure in the rutile phase. Additionally, the second conductive interface layer 122 may include a conductive metal oxide material having a sufficiently high conduction band offset (CBO) with the dielectric layer 130 to reduce leakage current. For example, the material of the second conductive interface layer 122 may be selected such that the CBO between the second conductive interface layer 122 and the dielectric layer 130 is greater than the CBO between the first conductive interface layer 121 and the dielectric layer 130. In at least one embodiment, the second conductive interface layer 122 may include, for example, tin oxide (SnO 2 ), germanium oxide (GeO 2 ), or a mixture of tin oxide and germanium oxide ((Sn x Ge 1-x )O 2 , 0 < x < 1). Thus, the second conductive interface layer 122 may also be referred to as an "interface layer including tin oxide and / or germanium oxide", which is disposed between the "Sn-doped molybdenum oxide (MoO 2 ) layer" and the dielectric layer 130.

[0063] Figure 2 For illustration Figure 1 is a schematic energy band diagram showing the CBO between the second conductive interface layer and the dielectric layer of the capacitor shown in Figure 2 . In Figure 2 , (a) illustrates an example of the CBO between the second conductive interface layer 122 and the dielectric layer 130, and (b) illustrates an example of the CBO between the first conductive interface layer 121 and the dielectric layer 130 for comparison when the second conductive interface layer 122 is absent. In Figure 2 , the conduction band of the first conductive interface layer 121 is represented by a thick line. Referring to Figure 2 , the CBO between the second conductive interface layer 122 and the dielectric layer 130 may be greater than about 1 eV. For example, the CBO between the second conductive interface layer 122 and the dielectric layer 130 may be about 1.4 eV, or about 1.4 eV to about 1.5 eV. On the other hand, the CBO between the first conductive interface layer 121 and the dielectric layer 130 may be about 1 eV, which is less than the CBO between the second conductive interface layer 122 and the dielectric layer 130.

[0064] Figures 3A to 3D is a cross-sectional view schematically illustrating a method of forming the conductive interface layer 120 of the capacitor 100 shown in Figure 1 .

[0065] Referring to Figure 3A , an amorphous molybdenum oxide (MoO xa first material layer 121'. The first material layer 121' can be formed by, for example, pulsed laser deposition (PLD) or atomic layer deposition (ALD). Alternatively, the first material layer 121' can be formed by other deposition methods, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0066] Referring Figure 3B , a second material layer 121" including tin oxide (SnO 2 ) can be formed on the upper surface of the first material layer 121'. For example, the second material layer 121" can be formed by ALD.

[0067] Referring Figure 3C , the first material layer 121' can be crystallized by post-metallization annealing (PMA). The PMA can include a heat treatment process and can be carried out at a temperature of, for example, about 450°C to about 600°C. Thus, amorphous molybdenum oxide can be crystallized to form crystalline molybdenum oxide (MoO 2 ) in the rutile phase. During this process, the tin oxide (SnO 2 ) of the second material layer 121" on the first material layer 121' can be incorporated into the crystal structure of the crystalline molybdenum oxide (MoO 2 ). Thus, a first conductive interface layer 121 including Sn-doped crystalline molybdenum oxide (MoO 2 ) and / or including both crystalline molybdenum oxide (MoO 2 ) and crystalline tin oxide (SnO 2 ) can be formed on the upper surface of the first electrode 110. In at least some embodiments, the first conductive interface layer 121 can be formed to have a thickness of about 0.3 nm to about 4 nm and / or about 0.3 nm to about 3 nm.

[0068] Referring Figure 3D , a second conductive interface layer 122 can be formed on the first conductive interface layer 121. For example, the second conductive interface layer 122 can be formed on the first conductive interface layer 121 by growing crystalline tin oxide (SnO 2 ), crystalline germanium oxide (GeO 2 ), and / or a mixture of crystalline tin oxide and crystalline germanium oxide ((Sn x Ge 1-x )O 2 , 0 < x < 1) on the first conductive interface layer 121 by ALD. In this way, the conductive interface layer 120 can be completed. In at least some embodiments, the second conductive interface layer 122 can be formed to have a thickness of about 0.3 nm to about 1 nm, or about 0.3 nm to about 0.6 nm.

[0069] In Figure 3DAfter the process, a dielectric layer 130 can be formed on the conductive interface layer 120, particularly the second conductive interface layer 122, and a second electrode 140 can be formed on the dielectric layer 130. In this way, the capacitor 100 can be manufactured. For example, the dielectric layer 130 can be formed as follows: depositing titanium oxide (TiO 2 ) by ALD. The dielectric layer 130 including rutile-phase titanium oxide (TiO 2 ) can be implemented by depositing titanium oxide (TiO 2 ) on the conductive interface layer 120 having a stable crystal structure in the rutile phase by ALD.

[0070] According to at least one embodiment, during the process of forming the first conductive interface layer 121, the film quality degradation of the crystallized molybdenum oxide (MoO x ) can be alleviated by doping with tin when crystallizing amorphous molybdenum oxide (MoO 2 ). Therefore, the conductive interface layer 120 can have a relatively uniform thickness of about 4 nm or less, and the surface roughness of the conductive interface layer 120 can be relatively small. In these cases, the dielectric layer 130 can be formed homogeneously on the conductive interface layer 120; for example, the homogeneous surface of the conductive interface layer 120 can reduce / or prevent the formation of lattice defects in the dielectric layer 130, and thus, the leakage current can be reduced.

[0071] Figure 4 Showing a high-resolution transmission electron microscopy (HR-TEM) photograph of the actually manufactured conductive interface layer 120 according to an embodiment, and Figure 5 Showing an HR-TEM photograph of the actually manufactured conductive interface layer 220 according to a comparative example. In the conductive interface layer 220 of the Figure 5 comparative example, the first conductive interface layer 221 only includes undoped Sn crystallized molybdenum oxide (MoO 2 ) (i.e., MoO 2 ) without Sn. Magnify a part of the conductive interface layer in the Figure 4 lower right corner of 5 . Referring to Figure 4 , it can be confirmed that the thicknesses of the first conductive interface layer 121 and the second conductive interface layer 122 in the conductive interface layer 120 according to the embodiment are relatively uniform. On the other hand, referring to Figure 5 , the thicknesses of the first conductive interface layer 221 and the second conductive interface layer 222 in the conductive interface layer 220 according to the comparative example are not uniform. This is due to the large ionic radius of molybdenum (Mo) during the process of crystallizing molybdenum oxide (MoO 2 ), resulting in molybdenum oxide (MoO 2) As a result of the film quality deterioration. In the case of the conductive interface layer 120 according to the embodiment, due to Sn doped into molybdenum oxide (MoO 2 )), the film quality deterioration of molybdenum oxide (MoO 2 ) can be alleviated.

[0072] Figures 6A to 6D Is a photograph of the surface of the first conductive interface layer, showing the change in the surface roughness of the conductive interface layer according to the change in the content of Sn in the first conductive interface layer. Refer to Figure 6A , the root mean square (RMS) surface roughness (R q ) of the first conductive interface layer 221 according to the comparative example without Sn doping is about 1.8 nm. Refer to Figure 6B And 6C , the RMS surface roughness of the first conductive interface layer 121 according to the embodiment doped with Sn at a concentration of about 1.5 atomic% is about 0.57 nm, and the RMS surface roughness of the first conductive interface layer 121 according to the embodiment doped with Sn at a concentration of about 3.0 atomic% is about 0.53 nm. Therefore, it can be confirmed that the surface roughness of the first conductive interface layer 121 according to the embodiment is significantly lower than that of the conductive interface layer 221 according to the comparative example. In addition, it can be confirmed that as the Sn doping concentration in the first conductive interface layer 121 increases from about 1.5 atomic% to about 3.0 atomic%, the surface roughness of the first conductive interface layer 121 becomes lower.

[0073] Refer to Figure 6D , the RMS surface roughness of the first conductive interface layer 121 according to the embodiment doped with Sn at a concentration of about 4.5 atomic% is about 1.08 nm. It can be confirmed that as the Sn doping concentration in the first conductive interface layer 121 increases from about 3.0 atomic% to about 4.5 atomic%, the surface roughness of the first conductive interface layer 121 increases again. However, even when the Sn doping concentration in the first conductive interface layer 121 is about 4.5 atomic%, the surface roughness of the first conductive interface layer 121 is significantly lower than that of the first conductive interface layer 221 according to the comparative example without Sn doping.

[0074] Figure 7 Is a diagram showing an example of the ultraviolet (UV) photoelectron spectroscopy (UPS) spectrum for the first conductive interface layer, and the spectrum is obtained by UPS measurement. Figure 7 The UPS spectrum shown in Figure 7In the figure, the horizontal axis represents the binding energy, and the vertical axis represents the intensity or kinetic energy of the electrons emitted by the photoelectric effect. The work function of the sample can be obtained from the difference between 21.22 eV and the x-intercept value of the differentiated value of the UPS spectrogram shown in Figure 7 The work function of the first conductive interface layer 221 according to the comparative example without doping Sn is about 5.12 eV. In addition, the work function of the first conductive interface layer 121 according to the example doped with Sn at a concentration of about 1.5 atomic % is about 5.02 eV, and the work function of the first conductive interface layer 121 according to the example doped with Sn at a concentration of about 3.0 atomic % is about 5.03 eV. Therefore, it can be confirmed that the work function of the first conductive interface layer 121 according to the example doped with Sn is slightly lower than the work function of the first conductive interface layer 221 according to the comparative example without doping Sn.

[0075] Refer to Figure 7 , the work function of the first conductive interface layer 221 according to the comparative example without doping Sn is about 5.12 eV. In addition, the work function of the first conductive interface layer 121 according to the example doped with Sn at a concentration of about 1.5 atomic % is about 5.02 eV, and the work function of the first conductive interface layer 121 according to the example doped with Sn at a concentration of about 3.0 atomic % is about 5.03 eV. Therefore, it can be confirmed that the work function of the first conductive interface layer 121 according to the example doped with Sn is slightly lower than the work function of the first conductive interface layer 221 according to the comparative example without doping Sn.

[0076] Figure 8 Table showing the change in the work function of the first conductive interface layer according to the change in the content of Sn in the first conductive interface layer, obtained by density functional theory (DFT) simulation. Refer to Figure 8 According to the simulation results, the work function of the first conductive interface layer 221 according to the comparative example without doping Sn is the highest. In the case of the first conductive interface layer 121 according to the example, as the content of Sn increases, the work function gradually decreases. The simulation results can be roughly matched with the UPS measurement results shown in Figure 7 .

[0077] Figure 9 Figure showing the comparison of the leakage current characteristics between the capacitor 100 including the conductive interface layer 120 according to the example and the capacitor including the conductive interface layer according to the comparative example. Refer to Figure 9 , the leakage current (LKG) of the capacitor according to Comparative Example 1 (▲) including only the first conductive interface layer formed of MoO doped with Sn at a concentration of about 1.5 atomic % and not including the second conductive interface layer is the largest, and its equivalent oxide thickness (T 2 ) is also the largest. The leakage current and the equivalent oxide thickness of the capacitor according to Comparative Example 2 (■) including the first conductive interface layer formed of MoO without doping Sn and the second conductive interface layer formed of SnO oxeq can be respectively smaller than the leakage current and the equivalent oxide thickness of the capacitor according to Comparative Example 1. In addition, it can be confirmed that the first conductive interface layer 121 formed of MoO doped with Sn at a concentration of about 1.5 atomic % and SnO 2 formed, and the second conductive interface layer formed of SnO 2 formed, and the second conductive interface layer formed of SnO 2 formed, and the second conductive interface layer formed of SnO2 The leakage current and equivalent oxide thickness of the capacitor 100 according to the embodiment (●) of the formed second conductive interface layer 122 are minimized.

[0078] Figure 10 A graph showing a comparison of the leakage current characteristics between the capacitors 100 according to the content of Sn in the first conductive interface layer. Refer to Figure 10 , when the Sn doping concentration in the first conductive interface layer 121 is about 1.5 atomic % (●), the leakage current and equivalent oxide thickness of the capacitor 100 are minimized. The leakage current and equivalent oxide thickness of the capacitor 100 (◆) in which the Sn doping concentration in the first conductive interface layer 121 is about 3.0 atomic % are slightly greater than those of the capacitor 100 in which the Sn doping concentration in the first conductive interface layer 121 is about 1.5 atomic %, but less than the leakage current and equivalent oxide thickness of the capacitor according to the comparative example (■). On the other hand, the leakage current and equivalent oxide thickness of the capacitor 100 (▲) in which the Sn doping concentration in the first conductive interface layer 121 is about 4.5 atomic % are greater than the leakage current and equivalent oxide thickness of the capacitor according to the comparative example.

[0079] When comprehensively considering the changes in various characteristics according to the change in the Sn doping concentration in the first conductive interface layer 121 observed through Figures 6A to 6D and 7 to 10, the Sn doping concentration in the first conductive interface layer 121 can be about 0.1 atomic % to about 5.0 atomic %. Alternatively, the Sn doping concentration in the first conductive interface layer 121 can be about 0.1 atomic % to about 4.0 atomic %, about 0.1 atomic % to about 3.0 atomic %, about 0.5 atomic % to about 3.0 atomic %, and / or about 1.5 atomic % to about 3.0 atomic %.

[0080] As described above, in the case of the capacitor 100 according to the embodiment, the dielectric layer 130 including the rutile phase dielectric material can be formed by ALD using the first conductive interface layer 121 doped with Sn. Therefore, the disclosed capacitor 100 can be miniaturized and has a high capacitance. In addition, since the material of the first electrode 110 is chemically stable, the material of the first electrode 110 cannot be reduced to a metal in subsequent processes. In addition, the leakage current can be reduced by using the second conductive interface layer 122 having a sufficiently large CBO with the dielectric layer 130.

[0081] The capacitor can be used in various electronic devices. The capacitor can be used as a dynamic random access memory (DRAM) together with a transistor. In addition, the capacitor can be used together with other circuit elements to form a part of the electronic circuit of an electronic device.

[0082] Figure 11A circuit diagram for schematically depicting the circuit configuration and operation of an electronic device 1000 employing a capacitor according to some embodiments.

[0083] The circuit diagram of the electronic device 1000 is for one cell of a DRAM, and the electronic device 1000 includes a transistor TR, a capacitor CA, a word line WL, and a bit line BL. The capacitor CA can be the capacitor 100 described with reference to Figures 1 - 10 the description.

[0084] A method of writing data to the DRAM is as follows. After applying a gate voltage (high) for turning on (conducting) the transistor TR (“conducting” state) to the gate electrode through the word line WL, a VDD (hereinafter, high voltage) or 0 (hereinafter, low voltage), which is the data voltage value to be input, is applied to the bit line BL. When high voltages are applied to the word line WL and the bit line BL, the capacitor CA is charged, that is, data “1” is written. When a high voltage is applied to the word line WL and a low voltage is applied to the bit line BL, the capacitor CA is discharged, that is, data “0” is written.

[0085] When reading data, a high voltage is applied to the word line WL to conduct the transistor TR of the DRAM, and a voltage of VDD / 2 is applied to the bit line BL. When the data of the DRAM is “1”, that is, when the voltage of the capacitor CA is VDD, the charge stored in the capacitor CA slowly moves to the bit line BL, and the voltage of the bit line BL becomes slightly higher than VDD / 2. On the contrary, when the data of the capacitor CA is “0”, the charge of the bit line BL moves to the capacitor CA, and the voltage of the bit line BL becomes slightly lower than VDD / 2. A sense amplifier can sense and amplify the potential difference of the bit line and determine whether the data is “0” or “1”.

[0086] Figure 12 A schematic diagram for illustrating an electronic device 1001 according to at least one embodiment.

[0087] With reference to Figure 12 , the electronic device 1001 can include a structure in which the capacitor CA1 and the transistor TR are electrically connected to each other through a contact 20. The capacitor CA1 can include: a first electrode 110, a second electrode 140, a dielectric layer 130 between the first electrode 110 and the second electrode 140, and a conductive interface layer 120 between the first electrode 110 and the dielectric layer 130. The capacitor CA1 can be the capacitor 100 described with reference to Figures 1 - 10 the description. Since this has been described above, its detailed description is omitted.

[0088] The transistor TR can be a field effect transistor. The transistor TR includes a semiconductor substrate SU and a gate stack GS. The semiconductor substrate SU can include a source region SR, a drain region DR, and a channel region CH. The gate stack GS is disposed on the semiconductor substrate SU, facing the channel region CH, and includes a gate insulating layer GI and a gate electrode GA.

[0089] The channel region CH is the region between the source region SR and the drain region DR and is electrically connected to the source region SR and the drain region DR. The source region SR can be electrically connected to or in contact with one end of the channel region CH, and the drain region DR can be electrically connected to or in contact with the other end of the channel region CH. The channel region CH can be defined as the substrate region between the source region SR and the drain region DR in the semiconductor substrate SU.

[0090] The semiconductor substrate SU can include a semiconductor material. The semiconductor substrate SU can include, for example, elemental and / or compound semiconductor materials such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), and / or the like. Additionally, the semiconductor substrate SU can include a silicon-on-insulator (SOI) substrate.

[0091] The source region SR, the drain region DR, and the channel region CH can each be independently formed by implanting impurities into different regions of the semiconductor substrate SU. In this case, the source region SR, the channel region CH, and the drain region DR can each include the substrate material as the base material. The source region SR and the drain region DR can each include a conductive material. In this case, the source region SR and the drain region DR can each include, for example, a metal, a metal compound, or a conductive polymer.

[0092] Different from the illustration, the channel region CH can also be implemented as a separate material layer (thin film). In these cases, for example, the channel region CH can include at least one of the following: Si, Ge, SiGe, group III-V semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional (2D) materials, quantum dots (QD), and organic semiconductors. For example, the oxide semiconductor can include InGaZnO and / or the like, the 2D material can include transition metal dichalcogenides (TMD) or graphene, and the QD can include colloidal QD or nanocrystal structures.

[0093] The gate electrode GA can be disposed on the semiconductor substrate SU and can face the channel region CH while being spaced apart from the semiconductor substrate SU. The gate electrode GA can include at least one of the following: metal, metal nitride, metal carbide, and polysilicon. For example, the metal can include at least one of the following: aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and tantalum (Ta), and the metal nitride can include at least one of the following: titanium nitride (TiN) and tantalum nitride (TaN). The metal carbide can include at least one of the following: aluminum-doped (or aluminum-containing) metal carbide and silicon-doped (or silicon-containing) metal carbide. Specific examples of the metal carbide can include TiAlC, TaAlC, TiSiC, or TaSiC.

[0094] In at least one embodiment, the gate electrode GA can have a structure in which multiple materials are stacked. For example, the gate electrode GA can have a structure in which a metal nitride layer and a metal layer are stacked (e.g., TiN / Al), or a structure in which a metal nitride layer, a metal carbide layer, and a metal layer are stacked (e.g., TiN / TiAlC / W). However, the above materials are only examples.

[0095] The gate insulating layer GI can be further disposed between the semiconductor substrate SU and the gate electrode GA. The gate insulating layer GI can include a paraelectric material or a high-k dielectric material and can have a dielectric constant of about 20 to about 70.

[0096] The gate insulating layer GI can include silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, etc., or can include a 2D insulator such as hexagonal boron nitride (h-BN). For example, the gate insulating layer GI can include silicon oxide (SiO 2 ), silicon nitride (SiN x ), etc., or can include hafnium oxide (HfO 2 ), hafnium silicate (HfSiO 4 ), lanthanum oxide (La 2 O 3 ), lanthanum aluminate (LaAlO 3 ), zirconium oxide (ZrO 2 ), hafnium zirconium oxide (HfZrO 2 ), zirconium silicate (ZrSiO 4 ), tantalum oxide (Ta 2 O 5 ), titanium oxide (TiO 2 ), strontium titanate (SrTiO 3 ), yttrium oxide (Y 2 O 3 ), aluminum oxide (Al 2 O 3 ), lead scandium tantalum (PbSc 0.5 Ta0.5 O 3 )), lead zinc niobate (PbZnNbO 3 ), and / or the like. Additionally, the gate insulating layer GI may include metal oxynitrides (e.g., aluminum oxynitride (AlON), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), lanthanum oxynitride (LaON), yttrium oxynitride (YON), etc.), silicates (e.g., ZrSiON, HfSiON, YSiON, LaSiON, etc.), and / or aluminates (e.g., ZrAlON, HfAlON, etc.). Additionally, the gate insulating layer GI and the gate electrode GA may together form a gate stack.

[0097] One of the first electrode 110 and the second electrode 140 of the capacitor CA1 and one of the source region SR and the drain region DR of the transistor TR may be electrically connected to each other, e.g., through a contact 20. The contact 20 may include a suitable conductive material, such as tungsten, copper, aluminum, or polysilicon.

[0098] The arrangement of the capacitor CA1 and the transistor TR may be changed differently. For example, the capacitor CA1 may be disposed on the semiconductor substrate SU and / or may be buried in the semiconductor substrate SU.

[0099] Figure 12 It is illustrated that the electronic device 1001 includes a capacitor CA1 and a transistor TR, but this is only an example, and the electronic device 1001 may include multiple capacitors and multiple transistors.

[0100] Figure 13 A schematic diagram for illustrating an electronic device 1002 according to another embodiment.

[0101] Referring to Figure 13 , the electronic device 1002 may include a structure in which the capacitor CA2 and the transistor TR are electrically connected to each other (e.g., through a contact 21). The transistor TR includes a semiconductor substrate SU and a gate stack GS. The semiconductor substrate SU includes a source region SR, a drain region DR, and a channel region CH. The gate stack GS is disposed on the semiconductor substrate SU, facing the channel region CH, and includes a gate insulating layer GI and a gate electrode GA.

[0102] An intermediate layer insulating layer 25 may be disposed on the semiconductor substrate SU to cover the gate stack GS. The intermediate layer insulating layer 25 may include an insulating material. For example, the intermediate layer insulating layer 25 may include Si oxide (e.g., SiO 2 ), Al oxide (e.g., Al 2 O 3 ), or a high-k material (e.g., HfO 2 ). The contact 21 passes through the intermediate layer insulating layer 25 to electrically connect the transistor TR to the capacitor CA2.

[0103] The capacitor CA2 includes: a first electrode 110, a second electrode 140, a dielectric layer 130 between the first electrode 110 and the second electrode 140, and a conductive interface layer 120 between the first electrode 110 and the dielectric layer 130. The first electrode 110 and the second electrode 140 are provided in a shape that can maximize the contact area with the dielectric layer 130, and the materials of the capacitor CA2 can be substantially the same as those of the capacitor 100 described with reference to Figures 1 - 10 the capacitor 100.

[0104] Figure 14 FIG. is a plan view of an electronic device 1003 according to another embodiment for illustration.

[0105] With reference to Figure 14 , the electronic device 1003 may include a structure in which a plurality of capacitors and a plurality of field effect transistors are repeatedly arranged. The electronic device 1003 may include a field effect transistor, a contact structure 20', and a capacitor CA3. The field effect transistor includes: a semiconductor substrate 11' and a gate stack 12, and the semiconductor substrate 11' includes a source, a drain, and a channel. The contact structure 20' is provided on the semiconductor substrate 11' so as not to overlap with the gate stack 12. The capacitor CA3 is provided on the contact structure 20'. The electronic device 1003 may further include a bit line structure 13 that electrically connects the field effect transistors to each other.

[0106] Although Figure 14 it is illustrated that both the contact structure 20' and the capacitor CA3 are repeatedly arranged in the X and Y directions, the present disclosure is not limited thereto. For example, the contact structure 20' may be arranged in the X and Y directions, and the capacitor CA3 may be arranged in a hexagonal shape, such as a honeycomb structure.

[0107] Figure 15 FIG. is a cross-sectional view of the electronic device 1003 taken along line A-A' of Figure 14 .

[0108] With reference to Figure 15, the semiconductor substrate 11' may have a shallow trench isolation (STI) structure including a device isolation layer 14. The device isolation layer 14 may be a single layer including one type of insulating film, or a multi-layer including a combination of two or more types of insulating layers. The device isolation layer 14 may include device isolation trenches 14T in the semiconductor substrate 11', and the device isolation trenches 14T may be filled with an insulating material. The insulating material may include at least one of the following: fluorosilicate glass (FSG), undoped silicate glass (USG), boron-phosphorus-silicate glass (BPSG), phosphorus-silicate glass (PSG), flowable oxide (FOX), plasma-enhanced tetraethyl orthosilicate (PE-TEOS), and / or tonen silazene (TOSZ), but the present disclosure is not limited thereto.

[0109] The semiconductor substrate 11' may further include a channel region CH defined by the device isolation layer 14, and gate line trenches 12T parallel to the upper surface of the semiconductor substrate 11' and extending in the X direction. The channel region CH may have a relatively long island shape having a short axis and a long axis. As Figure 15 shown, the long axis of the channel region CH may be arranged in the D3 direction parallel to the upper surface of the semiconductor substrate 11'.

[0110] The gate line trenches 12T may be arranged to cross the channel region CH at a certain depth from the upper surface of the semiconductor substrate 11', or may be arranged within the channel region CH. The gate line trenches 12T may also be arranged within the device isolation trenches 14T. The gate line trenches 12T within the device isolation trenches 14T may have a bottom surface lower than the bottom surface of the gate line trenches 12T in the channel region CH. The first source / drain 11'ab and the second source / drain 11"ab may be arranged in the upper portion of the channel region CH located on both sides of the gate line trenches 12T.

[0111] A gate stack 12 may be arranged within the gate line trenches 12T. For example, a gate insulating layer 12a, a gate electrode 12b, and a gate capping layer 12c may be sequentially arranged within the gate line trenches 12T. The gate insulating layer 12a and the gate electrode 12b may be the same as those described above, and the gate capping layer 12c may include at least one of the following: silicon oxide, silicon oxynitride, and silicon nitride. The gate capping layer 12c may be arranged on the gate electrode 12b to fill the remaining portion of the gate line trenches 12T.

[0112] The bit line structure 13 may be disposed on the first source / drain 11'ab. The bit line structure 13 may be arranged parallel to the upper surface of the semiconductor substrate 11' and extend in the Y direction. The bit line structure 13 may be electrically connected to the first source / drain 11'ab and may include a bit line contact 13a, a bit line 13b, and a bit line capping layer 13c that are sequentially stacked on the semiconductor substrate 11'. For example, the bit line contact 13a may include polysilicon, the bit line 13b may include a metal material, and the bit line capping layer 13c may include an insulating material such as silicon nitride or silicon oxynitride.

[0113] Although Figure 15 It is described that the bit line contact 13a has a bottom surface at the same level as the upper surface of the semiconductor substrate 11', but this is only an example and the present disclosure is not limited thereto. For example, in another embodiment, a recess may be further provided that is formed at a certain depth from the upper surface of the semiconductor substrate 11'. The bit line contact 13a may extend into the recess such that the bottom surface of the bit line contact 13a is lower than the upper surface of the semiconductor substrate 11'.

[0114] The bit line structure 13 may further include a bit line intermediate layer (not shown) between the bit line contact 13a and the bit line 13b. The bit line intermediate layer may include a metal silicide such as tungsten silicide or a metal nitride such as tungsten nitride. Additionally, a bit line spacer (not shown) may be further formed on the sidewalls of the bit line structure 13. The bit line spacer may have a single-layer structure or a multi-layer structure and may include an insulating material such as silicon oxide, silicon oxynitride, or silicon nitride. Additionally, the bit line spacer may further include an air space (not shown).

[0115] The contact structure 20' may be disposed on the second source / drain 11"ab. The contact structure 20' and the bit line structure 13 may be disposed on different source / drains on the semiconductor substrate 11'. The contact structure 20' may have a structure in which a lower contact pattern (not shown), a metal silicide layer (not shown), and an upper contact pattern (not shown) are sequentially stacked on the second source / drain 11"ab. The contact structure 20' may further include a barrier layer (not shown) surrounding the side surface and the bottom surface of the upper contact pattern. For example, the lower contact pattern may include polysilicon, the upper contact pattern may include a metal material, and the barrier layer may include a conductive metal nitride.

[0116] The capacitor CA3 can be disposed on the semiconductor substrate 11' and electrically connected to the contact structure 20'. In particular, the capacitor CA3 includes: a first electrode 110 electrically connected to the contact structure 20', a second electrode 140 spaced apart from the first electrode 110, a dielectric layer 130 between the first electrode 110 and the second electrode 140, and a conductive interface layer 120 between the first electrode 110 and the dielectric layer 130. The first electrode 110 can have a cup shape or a cylindrical shape having an internal space with a closed bottom. The second electrode 140 can have a comb shape with comb teeth extending into the internal space formed by the first electrode 110 and the regions between adjacent first electrodes 110. Additionally, the dielectric layer 130 can be disposed between the first electrode 110 and the second electrode 140 parallel to the surfaces of the first electrode 110 and the second electrode 140. The conductive interface layer 120 can be disposed between the first electrode 110 and the dielectric layer 130 parallel to the surfaces of the first electrode 110 and the dielectric layer 130. Since the materials of the first electrode 110, the conductive interface layer 120, the dielectric layer 130, and the second electrode 140 constituting the capacitor CA3 are substantially the same as those of the capacitor 100 described with reference to Figures 1 - 10 the description thereof is omitted for simplicity.

[0117] The interlayer insulating layer 15 can be further disposed between the capacitor CA3 and the semiconductor substrate 11'. The interlayer insulating layer 15 can be disposed in a space between the capacitor CA3 and the semiconductor substrate 11' where no other structures are disposed. In particular, the interlayer insulating layer 15 can be disposed to cover wirings and / or electrode structures on the semiconductor substrate 11', such as the bit line structure 13, the contact structure 20', and the gate stack 12. For example, the interlayer insulating layer 15 can surround the wall of the contact structure 20'. The interlayer insulating layer 15 can include a first interlayer insulating layer 15a surrounding the bit line contact 13a and a second interlayer insulating layer 15b covering the side surfaces and / or the upper surface of the bit line 13b and the bit line capping layer 13c.

[0118] The first electrode 110 of the capacitor CA3 can be disposed on the interlayer insulating layer 15, particularly on the second interlayer insulating layer 15b. Additionally, when multiple capacitors CA3 are disposed, the bottom surfaces of the multiple first electrodes 110 can be separated from each other by the etch stop layer 16. In other words, the etch stop layer 16 can include an opening 16T, and the bottom surface of the first electrode 110 of the capacitor CA3 can be disposed in the opening 16T. As shown, the first electrode 110 can have a cup shape or a cylindrical shape having an internal space with a closed bottom. The capacitor CA3 can further include a support (not shown) for preventing the first electrode 110 from tilting or collapsing. The support can be disposed on the side wall of the first electrode 110.

[0119] Figure 16 A cross-sectional view of the electronic device 1004 according to another embodiment is shown for illustration.

[0120] The cross-sectional view of the electronic device 1004 according to the present embodiment corresponds to the cross-sectional view taken along Figure 14 line A-A', and Figure 16 the electronic device 1004 Figure 15 differs from the electronic device 1003 Figures 1 - 10 only in the shape of the capacitor CA4. The capacitor CA4 is disposed on the semiconductor substrate 11' and electrically connected to the contact structure 20'. The capacitor CA4 includes: a first electrode 110 electrically connected to the contact structure 20', a second electrode 140 spaced apart from the first electrode 110, a dielectric layer 130 between the first electrode 110 and the second electrode 140, and a conductive interface layer 120 between the first electrode 110 and the dielectric layer 130. The materials of the first electrode 110, the conductive interface layer 120, the dielectric layer 130, and the second electrode 140 are substantially the same as those of the capacitor 100 described with reference to

[0121] The first electrode 110 may have a columnar shape extending in the vertical direction (Z direction), such as a cylinder, a square column, or a polygonal column. The second electrode 140 may have a comb shape with comb teeth extending into the regions between adjacent first electrodes 110. The dielectric layer 130 may be disposed between the first electrode 110 and the second electrode 140 parallel to the surfaces of the first electrode 110 and the second electrode 140. The conductive interface layer 120 may be disposed between the first electrode 110 and the dielectric layer 130 parallel to the surfaces of the first electrode 110 and the dielectric layer 130.

[0122] The capacitor and the electronic device according to the above-described embodiment can be applied to various application fields. For example, the electronic device according to the embodiment can be applied as a logic device or a memory device. The electronic device according to the embodiment can be used for arithmetic operations, program execution, temporary data retention, etc. in devices such as mobile devices, computers, laptops, sensors, network devices, and neuromorphic devices. Additionally, the electronic device according to the embodiment can be useful for devices where a large amount of data is transmitted and data transmission occurs continuously.

[0123] Figure 17 and 18 are conceptual diagrams schematically illustrating a device architecture applicable to a device according to at least one embodiment.

[0124] Referring to Figure 17, the electronic device architecture 1100 may include a storage unit 1010, an arithmetic logic unit (ALU) 1020, and a control unit 1030. The storage unit 1010, the ALU 1020, and the control unit 1030 may be electrically connected to each other. For example, the electronic device architecture 1100 may be implemented as a single chip including the storage unit 1010, the ALU 1020, and the control unit 1030.

[0125] The storage unit 1010, the ALU 1020, and the control unit 1030 may be interconnected in an on-chip manner via metal wires for direct communication. The storage unit 1010, the ALU 1020, and the control unit 1030 may be integrally integrated on a single substrate to form a single chip. An input / output device 2000 may be connected to the electronic device architecture (chip) 1100. Additionally, the storage unit 1010 may include both a main memory and a cache memory. The electronic device architecture (chip) 1000 may be an on-chip memory processing unit. The storage unit 1010 may include the capacitors and the electronic devices including them described above. The ALU 1020 or the control unit 1030 may also include the above-described capacitors.

[0126] Refer to Figure 18 , the cache memory 1510, the ALU 1520, and the control unit 1530 may form a central processing unit (CPU) 1500. The cache memory 1510 may include static random access memory (SRAM). Separately from the CPU 1500, a main memory 1600 and a secondary storage 1700 may be provided. The main memory 1600 may be DRAM and may include the capacitors described above. In some cases, the electronic device architecture may be implemented in a form in which the computing unit elements and the storage unit elements are adjacent to each other in a single chip without distinguishing sub-units.

[0127] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of features or aspects within each embodiment should typically be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the drawings, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims.

Claims

1. Capacitors, including: a first electrode; a second electrode facing the first electrode; a dielectric layer between the first electrode and the second electrode, the dielectric layer comprising a rutile phase dielectric material; as well as A conductive interface layer between the first electrode and the dielectric layer, the conductive interface layer comprising: a first conductive interface layer between the first electrode and the dielectric layer and comprising a conductive metal oxide material having a stable crystal structure in a rutile phase; as well as a second conductive interface layer between the first conductive interface layer and the dielectric layer, The conduction band offset between the second conductive interface layer and the dielectric layer is greater than the conduction band offset between the first conductive interface layer and the dielectric layer.

2. The capacitor of claim 1, wherein the first conductive interface layer comprises molybdenum oxide (MoO2) doped with tin (Sn). 3 . The capacitor of claim 2 , wherein a concentration of Sn in the first conductive interface layer is in a range of 0.1 atomic % to 5.0 atomic % based on the total number of atoms in the first conductive interface layer.

4. The capacitor of claim 2, wherein a concentration of Sn in the first conductive interface layer is in a range of 0.1 atomic % to 3.0 atomic % based on the total number of atoms in the first conductive interface layer.

5. The capacitor of claim 1 wherein the first conductive interface layer has a thickness in the range of 0.3 nm to 4 nm.

6. The capacitor of claim 1 wherein the second conductive interface layer comprises a second conductive metal oxide material having a stable crystal structure in a rutile phase.

7. The capacitor of claim 1, wherein the second conductive interface layer comprises tin oxide (SnO2), germanium oxide (GeO2), or a mixture of tin oxide and germanium oxide (SnO2). x Ge 1-x )O2,0 <x<1)。 8. The capacitor of claim 1 wherein the second conductive interface layer has a thickness in a range of 0.3 nm to 1 nm.

9. The capacitor of claim 1 wherein the dielectric layer comprises rutile phase titanium oxide (TiO2).

10. The capacitor of claim 9, wherein the dielectric layer includes at least one of the following as a dopant: gallium (Ga), aluminum (Al), lanthanum (La), boron (B), indium (In), scandium (Sc), or yttrium (Y).

11. The capacitor of claim 10, wherein the concentration of the dopant in the dielectric layer is in the range of 0 atomic % to 20 atomic % based on the total number of atoms in the dielectric layer.

12. The capacitor of claim 1 wherein the dielectric layer has a thickness in the range of 3 nm to 7 nm.

13. The capacitor of claim 1, wherein the first electrode comprises titanium nitride (TiN), vanadium nitride (VN), niobium nitride (NbN), tantalum nitride (TaN), molybdenum nitride (MoN), cobalt nitride (CoN), or a combination thereof.

14. The capacitor of claim 1 wherein the first electrode has a thickness in a range of 5 nm to 10 nm.

15. The capacitor of claim 2, wherein a concentration of Sn in the first conductive interface layer is in a range of 0.5 atomic % to 3.0 atomic % based on the total number of atoms in the first conductive interface layer.

16. A method of manufacturing a capacitor, the method comprising: forming a first material layer on an upper surface of the first electrode, the first material layer comprising amorphous molybdenum oxide; forming a second material layer on an upper surface of the first material layer, wherein the second material layer includes tin oxide (SnO2); forming a first conductive interface layer including molybdenum oxide (MoO2) doped with tin (Sn) by crystallizing the amorphous molybdenum oxide through heat treatment; A second conductive interface layer is formed on the first conductive interface layer, wherein the second conductive interface layer comprises tin oxide (SnO2), germanium oxide (GeO2), or a mixture of tin oxide and germanium oxide (SnO2). x Ge 1-x )O2,0 <x<1); forming a dielectric layer on the second conductive interface layer; and A second electrode is formed on the dielectric layer.

17. Electronic devices, including: transistor; and a capacitor electrically connected to the transistor, Wherein the capacitor is as defined in any one of claims 1-15.

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