Local VDD and VSS power supplies with gate-fixed dummy gates and associated benefits

Abstract

An integrated circuit structure includes a power rail formed on a backside of a semiconductor wafer. The integrated circuit structure also includes a front BEOL wire layer connected to the power rail through a gate, wherein the gate is of a type powered off by a power source coupled from the power rail to the first front BEOL wire layer through the gate. A method of forming an integrated circuit structure includes forming a power rail on a back side of a semiconductor wafer, forming a gate in the semiconductor wafer, and forming a front side BEOL wire layer connected to the power rail through the gate. Likewise, the gate is of the type powered off by a power source coupled through the gate from the power rail to the first front BEOL wire layer.

Description

BACKGROUND OF THE INVENTION

[0001] The present invention generally relates to semiconductors and, more particularly, to local VDD and VSS power supplies with dummy gates having gate tie-downs.

[0002] In semiconductor devices formed using a back-side power distribution network (BSPDN), there are areas that can be improved. For example, source / drain (S / D) epitaxial silicon (epi) regions may have to be connected to the back side through vias to buried power rails (VBPR). As another example and due to VBPR, another S / D epitaxial silicon region may only access one signal track above (e.g., near the back end of line (BEOL) region).

[0003] Regarding VBPR and similar technologies, consider "Buried Power Rails and Back-side Power Grids: Arm CPU Power Delivery Network Design Beyond 5nm" by Divya Prasad et al. in the 2019 IEEE International Electron Devices Meeting (IEDM), which states the following about the power delivery network (PDN): "To completely remove the power tap cells and the overhead of the entire PDN from the front side (which decouples the sharing of wire resources between signal and power delivery), 3D integration technologies have been proposed to implement a back-side PDN, where small ('micro') through-silicon vias (μTSV) landing on buried rails are used to deliver power". Multiple technologies were explored: "Three power rail technologies were explored in this study", "namely, the conventional front-side (FS) PDN, front-side with buried power rails (FS-BPR), and back-side with buried power rails (BS-BPR) power delivery". FS-BPR and BS-BPR do not address the above problems and require a large number of additional processing steps. SUMMARY OF THE INVENTION

[0004] This section is intended to be exemplary and not limiting.

[0005] In an exemplary embodiment, an integrated circuit structure includes a power rail formed on a back side of a semiconductor wafer and a front-end-of-line (BEOL) wire layer on a front side connected to the power rail through a gate. The gate is of a type that is powered off by power coupled from the power rail through the gate to a first front-side BEOL wire layer. This provides power and / or ground access at the front-side BEOL wire layer without using vias to the back-side power rail, which frees up space to allow certain source / drain (S / D) epitaxial regions to contact multiple signal tracks, where one signal track may be in an area not currently accessed, and also allows other S / D regions to be powered from tracks above the area. Manufacturing is also minimally affected, and the technology can be combined with current technologies, each used at different locations on the semiconductor wafer, such that both traditional and new structures can be used on the same wafer.

[0006] Another example is the integrated circuit structure according to the foregoing, where the gate is a first gate and the power rail is a first power rail. The integrated circuit structure further includes: a second power rail formed on the back side of the semiconductor wafer; and another front-side BEOL wire layer connected to the second power rail through a second gate, where the second gate is of a type that is powered off by power coupled from the second power rail through the second gate to the another front-side BEOL wire layer. This allows multiple routings of power to the front-side BEOL wire layer.

[0007] Another example is the integrated circuit structure according to the previous paragraph, where the first gate is an n-type gate and the power for the first gate is grounded; and the second gate is a p-type gate and is powered by the power of the first gate. Additionally, the first gate and the second gate can be formed adjacent to each other and are isolated at least by a gate cut formed between the adjacent first gate and second gate. This allows, for example, routing both power and ground to the front-side BEOL wire layer using adjacent gates.

[0008] Another example is an integrated circuit structure further including front-side BEOL wires connected to one or more source / drain epitaxial silicon regions of corresponding transistors. An additional example is the integrated circuit structure according to the previous sentence, where the front-side BEOL wires are connected to one or more source / drain epitaxial silicon regions of corresponding transistors using corresponding one or more vias. Another example is the integrated circuit structure according to the first sentence of this paragraph, where the front-side BEOL wire layer is connected to the front-side BEOL wires. These provide the ability for source / drain regions to access multiple signal tracks, including one in an N2N (n-type to n-type) semiconductor region or a P2P (p-type to p-type) semiconductor region, and another in an NFET or PFET (respectively) region.

[0009] Another example is a method of forming an integrated circuit structure, comprising the steps of: forming a power rail on the back side of a semiconductor wafer; forming gates in the semiconductor wafer; and forming a front-end-of-line (BEOL) wire layer that is connected to the power rail through the gates, wherein the gates are of a type that is powered off by power coupled from the power rail through the gates to the first front-end BEOL wire layer. This provides power and / or ground access at the front-end BEOL wire layer without using vias to the back-side power rail, which releases space to allow certain source / drain (S / D) epitaxial regions to contact multiple signal tracks, where one signal track may be in a region that is not currently accessed, and also allows other S / D regions to be powered from tracks above the region. Manufacturing is also minimally affected, and the technology can be combined with current technologies, each used at different locations on the semiconductor wafer, such that both traditional and new structures can be used on the same wafer.

[0010] Another example is the method according to the previous paragraph, wherein: forming gates in the semiconductor wafer further comprises forming a plurality of gates on a substrate of the semiconductor wafer, wherein forming the plurality of gates comprises: performing gate patterning to pattern the plurality of gates on the substrate, the gate being one of the plurality of gates; performing source / drain epitaxy to form source / drain regions for the plurality of gates; performing interlayer dielectric deposition to at least cover the source / drain regions and at least partially isolate the plurality of gates; and forming a front-end-of-line (BEOL) wire layer comprises forming BEOL interconnects and bonding a carrier wafer to the substrate on which the plurality of gates have been formed.

[0011] Another method comprises the method according to the previous paragraph, wherein: forming gates in the semiconductor wafer further comprises forming back-side gate-fixing vias at the edges of the gates and filling the back-side gate-fixing vias with a conductive material while the conductive material of the gates is being formed; the method further comprises forming gate via contacts to connect the gates having the gate-fixing vias to the front-end-of-line (BEOL) wire layer; and the method further comprises connecting the power rail to the gate-fixing vias.

[0012] Another exemplary method further comprises forming source / drain contacts that contact corresponding source / drain regions and extend beyond the source / drain regions to provide access to a signal track in a region between two doped regions of the same type and to one of the signal tracks within the doped regions.

[0013] These provide the ability for the source / drain regions to access multiple signal tracks, including one of an N2N (n-type to n-type) semiconductor region or a P2P (p-type to p-type) semiconductor region, and the other of an NFET or PFET (respectively) region.

[0014] Another method also includes connecting one or more source / drain regions of one or more corresponding other gates out of a plurality of gates that require power to one or more corresponding front-end BEOL wires, and the one or more corresponding front-end BEOL wires are connected to a front-end back-end-of-line (BEOL) wire layer.

[0015] Another method includes a method, wherein: the gate is a first gate, and the power rail is a first power rail; the method further includes: forming a second power rail formed on the back side of the semiconductor wafer; and forming another front-end BEOL wire layer connected to the second power rail through a second gate, wherein the second gate is of a type that is powered off by power coupled from the second power rail to the other front-end BEOL wire layer through the second gate; the first gate is an n-type gate, and the power of the first gate is grounded; and the second gate is a p-type gate, and the power of the first gate is supplied.

[0016] Another method includes the method of the previous paragraph, but wherein forming the first gate and the second gate includes forming the first gate and the second gate adjacent to each other, and the method includes forming and filling a gate cut between the adjacent first gate and second gate.

[0017] These examples provide power and / or ground access at the front-end BEOL wire layer without using vias to the back-side power rail, which releases space to allow certain source / drain (S / D) epitaxial regions to contact multiple signal tracks, where one signal track may be in a region that is not currently accessed, and also allows other S / D regions to be powered from tracks above the region.

[0018] In addition, these methods can be combined with current technologies, each technology being used at different positions on the semiconductor wafer, for example, meaning that the current design does not have to be modified to implement the current improvement. Description of the Drawings

[0019] Figure 1A is an example of a conventional POR integrated circuit structure, while Figure 1B is an example of an integrated circuit structure of an exemplary embodiment herein;

[0020] Figure 2A , Figure 2B and Figure 2C are different cross-sectional views X, Y1, and Y2 of the integrated circuit structure after NS and STI formation, respectively, while Figure 2D shows a top view layout of the integrated circuit structure and indicates the positions of the cross-sectional views X, Y1, and Y2 in the layout;

[0021] Figure 3A , Figure 3B and Figure 3Care different cross-sectional views X, Y1, and Y2 of an integrated circuit structure after OPL deposition and patterning, and gate fix opening formation, respectively, while Figure 3D shows a top view layout of the integrated circuit structure and indicates the positions of cross-sectional views X, Y1, and Y2 in the layout;

[0022] Figure 4A 、 Figure 4B and Figure 4C are different cross-sectional views X, Y1, and Y2 of the integrated circuit structure after OPL / HM removal, dummy gate formation, SiGe55 removal, BDI / spacer formation, NS groove, inner spacer formation, S / D epitaxy formation, ILD deposition, and CMP, respectively, while Figure 4D shows a top view layout of the integrated circuit structure and indicates the positions of cross-sectional views X, Y1, and Y2 in the layout;

[0023] Figure 5A 、 Figure 5B and Figure 5C are different cross-sectional views X, Y1, and Y2 of the integrated circuit structure after gate cut formation, respectively, while Figure 5D shows a top view layout of the integrated circuit structure and indicates the positions of cross-sectional views X, Y1, and Y2 in the layout;

[0024] Figure 6A 、 Figure 6B and Figure 6C are different cross-sectional views X, Y1, and Y2 of the integrated circuit structure after dummy gate removal, SiGe release, and replacement HKMG formation, respectively, while Figure 6D shows a top view layout of the integrated circuit structure and indicates the positions of cross-sectional views X, Y1, and Y2 in the layout;

[0025] Figure 7A 、 Figure 7B and Figure 7C are different cross-sectional views X, Y1, and Y2 of the integrated circuit structure after MOL processing, and lower BEOL formation has local supplies of VDD / VSS from dummy gate fixing;

[0026] Figure 8A 、 Figure 8B and Figure 8C are different cross-sectional views X, Y1, and Y2 of the integrated circuit structure after forming more BEOL levels and bonding to a carrier wafer;

[0027] Figure 9A 、 Figure 9B and Figure 9C are different cross-sectional views X, Y1, and Y2 of the integrated circuit structure after wafer flip, substrate removal, and stopping at an etch stop layer;

[0028] Figure 10A , Figure 10B and Figure 10C are different cross-sectional views X, Y1, and Y2 of an integrated circuit structure after etch stop layer removal and remaining Si removal, respectively;

[0029] Figure 11A , Figure 11B and Figure 11C are different cross-sectional views X, Y1, and Y2 of an integrated circuit structure after backside ILD formation and backside power rail formation, respectively;

[0030] Figure 12A , Figure 12B and Figure 12C are different cross-sectional views X, Y1, and Y2 of an integrated circuit structure after formation of the backside power distribution network layer, respectively;

[0031] Figure 13A is an example of a conventional POR integrated circuit structure, while Figure 13B is an example of the integrated circuit structure of the exemplary embodiments herein; and

[0032] Figure 14 provides a detailed top-down layout of the S / D contacts, VBPR, and VA. DETAILED DESCRIPTION

[0033] Abbreviations that can be found in the specification and / or drawings are defined at the end of the following DETAILED DESCRIPTION section.

[0034] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. All embodiments described in this DETAILED DESCRIPTION are provided to enable those skilled in the art to make or use the exemplary embodiments of the present invention, and not to limit the scope of the present invention defined by the claims.

[0035] This disclosure relates to the front-end-of-line (FEOL), middle-of-line (MOL), and back-end-of-line (BEOL). These concepts are now introduced. FEOL covers the processing of the active part of the chip (i.e., the transistors residing on the bottom of the chip). BEOL (the last stage of processing) refers to the metal layer interconnections residing on the top of the chip. FEOL and BEOL are joined together by MOL. MOL typically consists of metal structures that serve as contacts for the source, drain, and gate of the transistors. These structures are connected to the local interconnect layers of BEOL.

[0036] The architecture that constitutes the FEOL may include gate-all-around (GAA) nanosheets, fin-forked sheets, and complementary field-effect transistor (CFET) devices. The architectures of these devices affect the local interconnect layers and require different BEOL materials (such as ruthenium (Ru), molybdenum (Mo), and metal alloys) and various integration schemes (such as hybrid metallization, semi-damascene, and hybrid height with zero via structures). Via to back power rail (VBPR) is part of the power delivery network and can be used in the MOL to wire some terminals of the transistor to the back power distribution network to help reduce congestion in the lower BEOL.

[0037] Now that an introduction to the FEOL, MOL, and BEOL has been provided, as described above, in semiconductor devices formed using a backside power distribution network (BSPDN), there are some areas that can be improved. These are illustrated via the figures described below, but the following are problems with conventional techniques: Source / drain (S / D) epitaxial silicon (epi) regions may have to be connected to the backside via a via to back power rail (VBPR); and / or another S / D epitaxial silicon region may only access one signal track above (e.g., near the back-end-of-line (BEOL) region). Additionally, there is typically no access to the signal tracks in the N2N or P2P regions. Thus, gate fixing to the back power rail provides an opportunity to locally re-design the wiring by providing power from a dummy gate with gate fixing. These problems are addressed herein, and figures of semiconductor devices showing a conventional POR (recording process) are described.

[0038] Consider Figure 1A , which is an example of a conventional POR integrated circuit structure 1. As indicated by reference numeral 10, the S / D epitaxy (epitaxial silicon region) 50 may access only one (1) signal track 55 above (e.g., near the BEOL layer). As indicated by reference numeral 15, the S / D epitaxial region 60 must be connected to the backside via a VBPR 65, and the VBPR 65 is connected to a VSS region 66. Due to the presence of the VBPR at the cell boundary (between the S / D epitaxies 50 and 60), the source / drain contact (CA) above the S / D epitaxy 50 cannot freely extend into the cell boundary region to access other signal tracks above.

[0039] In contrast, Figure 1B is an example of an integrated circuit structure 2 of an exemplary embodiment herein. As indicated by reference numeral 20, the S / D epitaxy 50 may freely access two signal tracks indicated by reference numeral 75. The tracks shown as using vias VA and contacts CA to connect to signal lines are within the N2N or P2P regions. As indicated by reference numeral 30, the S / D epitaxial region 60 is powered from above by a local VSS 25.

[0040] This document describes techniques for removing one or both of VDD or VSS in VBPR, but includes forming and using "dummy" gates to provide a bridge from the backside power rail to the frontside BEOL wires. This is described in more detail below, but at least in Figure 11B such a dummy gate 1130 can be seen. A "dummy" gate is a gate that is turned off and not used as an active gate. Thus, the benefits described in the previous paragraph are achieved by the dummy gates described in this paragraph (and described in more detail below).

[0041] In addition, there are manufacturing advantages. One such advantage is that multiple gates have already been formed, so there are only a few additional steps to create one or more gates with corresponding gate fixings, which then provide the benefits as described above and herein.

[0042] Additionally, the techniques herein are fully compatible with the POR process (e.g., as Figure 1A shown). That is, the new features herein (including those in Figure 1B ) can be added without changing the POR structure, and in fact both the POR structure and the new structure can be fabricated on the same semiconductor wafer.

[0043] These improvements address the above-mentioned deficiencies.

[0044] Thus, an integrated circuit structure can include the following:

[0045] a) At least one power rail formed on the backside of the wafer;

[0046] b) The backside power rail is connected to a local frontside BEOL wire through a gate.

[0047] Additional examples include the following.

[0048] 1) The local frontside BEOL wire can supply power to at least one S / D epitaxial silicon region.

[0049] 2) The backside power rail can be connected to a gate through a gate fixing.

[0050] 3) The local frontside BEOL wire can be connected to a gate through a gate via contact.

[0051] 4) The N gate can be isolated from the P gate through an N2P gate cut.

[0052] 5) The N (or P) gate connected to the backside power can be isolated from another N (or P) active gate not connected to the backside power through an N2N (or P2P) gate cut.

[0053] As an overview of an exemplary embodiment, for example, an example processing flow for at least partially forming an integrated circuit structure 2 is shown below:

[0054] 1) Form back-gate fixing vias at the edges of the gates and fill the vias with dummy gates.

[0055] 2) Form gate patterning, S / D epitaxy, ILD filling, and gate cuts.

[0056] 3) Form gate via contacts to connect the dummy gates with the back-gate fixing vias to local M1 wires.

[0057] 4) Connect some of the S / Ds that require power to the local M1 wires.

[0058] 5) Form BEOL interconnects and bond the carrier wafer.

[0059] 6) Flip the wafer and remove the substrate.

[0060] 7) Form back-side power rails connected to the back-gate fixing vias.

[0061] As will be further described below in the text and the corresponding figures, an overview of an exemplary semiconductor device may include the following:

[0062] The following figures illustrate an exemplary processing flow, for example, for the previously described method and for forming an integrated circuit structure 2.

[0063] Figure 2A 、 Figure 2B and Figure 2C are different cross-sectional views X, Y1, and Y2 of the integrated circuit structure 2 after NS and STI formation, respectively, while Figure 2D shows a top view layout 100 of the integrated circuit structure 2 and indicates the positions of the cross-sectional views X, Y1, and Y2 in the layout.

[0064] Figure 2D shows a plurality of NFET regions 140 and PFET regions 130 doped accordingly (in a later step, see Figure 4C ), and formed in combination with patterned nanosheets (referred to as active regions RX), with a back-side power rail having a VSS region 110 and a VDD region 120. There are also three rows of gate regions 115, five in each row except for the presence of dummy gate (referred to as PC) regions 117. Note that in Figure 2A 、 Figure 2B and Figure 2C , the PC regions 115, the VSS region 110, and the VDD region 120 have not yet been formed. It should be noted that the terms "region" and "zone" are used herein and may sometimes be interchangeable. They both refer to three-dimensional structures in a semiconductor.

[0065] Figure 2A 、 Figure 2B and Figure 2CA silicon (Si) substrate 105 with an etch stop layer 175 such as SiGe is shown, and another silicon substrate 106 formed on the etch stop layer 175. The stack 150 has a layer of a first semiconductor material 160 (e.g., SiGe 55%) formed on the top surface of the substrate 106, and then has alternating layers of a second semiconductor material 161 (e.g., SiGe 25%) and a third semiconductor material 162 (e.g., silicon, such as single-crystalline silicon). The third semiconductor material 162 will be used in the gate to form the channel. These figures show that the stack 150 has been covered with a hard mask (HM) 155, and regions 130 and 140 for PFET and NFET regions respectively (e.g., via etching) have been formed, such as STI regions 180 (e.g., via deposition after etching). The stack 150 can be considered a nanosheet, which is formed via multiple sheet materials.

[0066] Although the gate regions 115 and dummy gate regions 117 are shown in Figure 2D , these gate regions are not actually formed until later. That is, Figure 2A , Figure 2B and Figure 2C the gates are not shown.

[0067] Figure 3A , Figure 3B and Figure 3C are different cross-sectional views X, Y1, and Y2 of the integrated circuit structure after mask layer deposition (such as OPL) and patterning and gate fixation opening formation, while Figure 3D shows a top view layout of the integrated circuit structure and indicates the positions of the cross-sectional views X, Y1, and Y2 in the layout.

[0068] Compared with Figure 2B , Figure 3B shows the gate fixation opening 220. Figure 3A , Figure 3B and Figure 3C show an OPL coating 210 covering the exposed surfaces of the PFET fin 130, NFET fin 140, silicon substrate 106, STI region 180, and HM 155. The OPL coating 210 can be a carbon polymer or the like. The gate fixation opening 220 has been formed in the OPL coating 210 and STI 180 through conventional lithography and etching processes in Figure 3B to provide the opening 220 to one side of the PFET region 130 and NFET region 140 and to the silicon substrate 106 through the corresponding STI region 180. After a plurality of processing steps described below, the gate fixation opening 220 will be formed for gate fixation in the VSS region 110 and VDD region 120.

[0069] Figure 4A ,Figure 4B and Figure 4C are different cross-sectional views X, Y1, and Y2 of an integrated circuit structure after OPL / HM removal, dummy gate formation, SiGe55 removal, BDI / spacer formation, nanosheet trench, inner spacer formation, S / D epitaxy formation, ILD deposition, and CMP, respectively, while Figure 4D shows a top view layout of the integrated circuit structure and indicates the positions of cross-sectional views X, Y1, and Y2 in the layout.

[0070] It can be seen that the OPL coating 210 and HM 155 have been removed. Figure 4A shows that the gate region 115 and the dummy gate region 117 have been formed, while Figure 4B shows a cross-section of the dummy gate region 117. The gate region 115 and the dummy gate region 117 can be formed of a material 490, such as polysilicon or amorphous Si (note that there may be a thin layer of SiO 2 between the material 490 and the nanosheet stack 150, although this is not shown and is deposited and appropriately modified using known techniques). The reference numeral 220 indicates the location where the gate fixing opening used to be. The 55% SiGe layer 160 in the stack 150 has been removed and replaced by a BDI (bottom dielectric isolation) layer 420, see Figure 4B . Figure 4A Also shown is the BDI layer 420 under the channel region and the S / D region 410, and the ILD layer 440 covering the S / D epitaxy (epitaxial) region 410. Figure 4C shows that the previous nanosheet material in the stack 150 has been removed, how the BDI layer 420 surrounds the three-layer S / D epitaxy (epitaxial) region 410, and the S / D epitaxy region 410 has been formed. The ILD layer 440 has been deposited. After the SiGe layer 161 is etched back and then the material 420 is deposited into these regions, the inner spacers 430 have been formed, for example, of an insulating material.

[0071] Figure 5A , Figure 5B and Figure 5C are different cross-sectional views X, Y1, and Y2 of the integrated circuit structure after gate cut formation, respectively, while Figure 5D shows a top view layout of the integrated circuit structure and indicates the positions of cross-sectional views X, Y1, and Y2 in the layout. Figure 5B and Figure 5D show that the gate cuts 510 have been formed and filled with a dielectric material (such as SiO2, SiN, SiBCN, SiOCN, SiOC, etc.).

[0072] Figure 6A , Figure 6B and Figure 6CThey are different cross-sectional views X, Y1, and Y2 of an integrated circuit structure after dummy gate removal, SiGe release, and replacement high-k metal gate formation, respectively, while Figure 6D shows a top view layout of the integrated circuit structure and indicates the positions of cross-sectional views X, Y1, and Y2 in the layout. The dummy gate region 117 is still shown, but the material 490 in this region has been removed. The SiGe 25% layer 161 has been released, such that the second semiconductor material layer 162 remains and is used for the channel region. The gate regions 115 and 117 have replaced their materials from material 490 to the high-k metal gate layer 690. The high-k metal gate layer 690 can include a gate dielectric layer, such as HfO 2 , HfSiO x , HfAlO x , HfLaO x , ZrO x , etc., and a work function metal, such as TiN, TiC, TiAl, TiAlC, etc., and an optional conductive metal, such as W, or Co, or Al, which can be deposited by conformal deposition, as known.

[0073] Figures 7A to 12C Using layout 100 and cross-sections X, Y1, and Y2, as Figure 6D shown.

[0074] Figure 7A , Figure 7B and Figure 7C are different cross-sectional views of X, Y1, and Y2 of the integrated circuit structure after MOL processing, respectively, and the lower BEOL formation has a local supply of VDD / VSS from dummy gate fixing. Figure 7A shows that as part of the MOL processing, contacts 710 (CA) to the S / D epitaxial region 410 have been formed in the ILD layer 440 above the S / D epitaxial region 410. Additionally, the ILD layer 440 has been formed (e.g., as part of the lower BEOL formation), and vias A 720 and B 730 have been formed in Figure 7A , Figure 7B and Figure 7C . As part of the lower BEOL formation, a local Vss 740 (to VA720 and VB 730) has been added, and signal tracks 760 (using the M1 metal layer) have been added to Figure 7A in VB 730. Figure 7B shows multiple signal tracks 760, and the local Vss 740 is connected to VB 730 together with the local VDD 750, and the local VDD 750 is shown as being connected to VB 730. Some of the signal tracks 760 are connected to vias such as Figure 7B in VB 730.Figure 7C Also shown are two contacts CA 710 to respective S / D epitaxial regions in the S / D epitaxial region 410, and vias VA 720 to the contacts CA 710 and then to the respective signal tracks 760 or to the local VSS 740.

[0075] The local VSS 740 or VDD 750 is part of the BEOL (in M1), and it only provides ground or power to a few nearby transistors respectively, so it is called "local" (in contrast to "global"). A more specific definition is as follows: The local VSS / VDD is a section of M1 wires that only powers transistors within 10 contact poly pitches (CPP).

[0076] As shown by reference numeral 780, by introducing the local VSS 740 and / or local VDD 750, the S / D can be directly powered, and adjacent S / D epitaxial regions can access the signal tracks in the N2N and P2P regions. That is, by introducing the local VSS 740-1, the S / D epitaxial region 410-1 can be directly powered using the via VA 720-1 (for example, instead of having to be connected to the backside VSS through VBPR as Figure 1A shown), and the via VA 720-1 is coupled to the local VSS 740-1. In addition, the adjacent S / D epitaxial region 410-2 can access the signal track 760-1 between two NFET regions (see Figure 6D and the NFET region 140, or Figure 14 and N2N). In addition, the CA 710-1 above the S / D epitaxy 410-2 allows this epitaxy 410-2 to be connected to the signal track 760-1 (using the via VA 720-2) or the signal track 760-2 (using a via not shown).

[0077] Figure 8A 、 Figure 8B and Figure 8C are different cross-sectional views X, Y1, and Y2 of the integrated circuit structure after forming more BEOL levels and bonding the carrier wafer. Figure 8A 、 Figure 8B and Figure 8C are the same as the corresponding Figure 7A 、 Figure 7B and Figure 7C but with the addition of the BEOL layer 820 and the carrier wafer 810. The carrier wafer 810 has been bonded to the BEOL layer 820. The reference numeral 800 represents the semiconductor wafer being processed.

[0078] Figure 9A 、 Figure 9B and Figure 9CThey are different cross-sectional views X, Y1, and Y2 of the integrated circuit structure after wafer flip, substrate removal, and after stopping at the etch stop layer, respectively. Figure 9A , Figure 9B and Figure 9C are the same as the corresponding Figure 8A , Figure 8B and Figure 8C respectively, but the wafer 800 has been flipped for processing and the substrate 105 has been removed by etching to the etch stop layer 175.

[0079] Figure 10A , Figure 10B and Figure 10C are different cross-sectional views X, Y1, and Y2 of the integrated circuit structure after etch stop layer removal and remaining Si removal, respectively. These illustrate that the etch stop layer 175 has been removed just like the silicon substrate 106, back to the STI layer 180 and the BDI layer 420. The region 1010 of the gate metal layer 690 will be gate-fixed and is formed by a process to form the gate-fixed opening 220 starting at Figure 3B .

[0080] Figure 11A , Figure 11B and Figure 11C are different cross-sectional views X, Y1, and Y2 of the integrated circuit structure after backside ILD formation and backside power rail formation, respectively. The BILD layer 1110 has been formed on the exposed regions of the STI region 180 and the BDI layer 420. The BILD layer 1110 has been patterned (see Figure 11B and Figure 11C ) and conductive materials are deposited to form the VSS region 110, the ground rail 1160-1, and the VDD region 120, the power rail 1160-2. The regions 1010 of the gate metal layer 690 are now gate-fixed 1010-1 and 1010-2. Note that the gate-fixed 1010-1 and 1010-2 can also be considered vias and can be formed using techniques for forming such vias.

[0081] In addition, the ground rail 1160-1 and the power rail 1160-2 can be generalized to the power rail 1160 because both VSS and VDD are power supplies. That is, VSS is the power supply for NFETs and VDD is the power supply for PFETs.

[0082] Two dummy gates 1130 are shown, an N-type dummy gate 1130-1 and a P-type dummy gate 1130-2. The N-type dummy gate 1130-1 uses the NFET region 140, and the P-type dummy gate 1130-2 uses the PFET region 130. The N-type dummy gate 1130-1 and the P-type dummy gate 1130-2 are isolated from each other at least by the gate cutout 510-1, but other techniques may be used for isolation. The N-type dummy gate 1130-1 may be isolated from the N-type active gate 1140-1 (having the gate of the corresponding NFET formed using the S / D regions of the corresponding NFET region 140) by the gate cutout 510-2. Note that in this example, the gate 1140-1 is not active (e.g., there is no via VB connected to the channel region), but in other examples, the gate may be active. The P-type dummy gate 1130 - 2 may be isolated from the P-active gate 1140 - 2 (having a channel formed in the gate region and forming a corresponding PFET using the corresponding PFET region 130 ) by the gate cut 510 - 3 .

[0083] Gate fixed means that the device is turned off by its gate. For NFET, it needs to be turned off by adding VSS power to the gate. This is how, for example, N-type dummy gate 1130-1 is constructed using ground rail 1160-1. For PFET, it needs to be turned off by adding VDD power to the gate to turn it off. This is how, for example, P-type dummy gate 1130-2 is constructed using power rail 1160-2.

[0084] As shown, the ground rail 1160-1 and its corresponding gate 1130-1 and the power rail 1160-2 and its corresponding gate 1130-2 are adjacent. It should be noted that if desired, there can be two adjacent ground rails 1160-1 and corresponding gates 1130-1, or two adjacent power rails 1160-1 and corresponding gates 1130-2, although the dummy gate 117 must span two NFET regions or two PFET regions, respectively, instead of spanning the NFET region and the PFET region as in the above example.

[0085] Figure 12A , Figure 12B and Figure 12C They are different cross-sectional views X, Y1 and Y2 of the integrated circuit structure after forming the back power distribution network layer. Figure 11A , Figure 11B and Figure 11C , the BSPDN layer 1210 has been formed on the exposed surfaces of the BILD layer 1110 , the VSS region 110 , and the VDD region 120 .

[0086] Figure 13A is from Figure 14An example of a conventional POR integrated circuit structure taken from the cross-sectional view Y3 in, while Figure 13B is an example of the integrated circuit structure of an exemplary embodiment herein. Figure 13A is the same as Figure 1A but is repeated for ease of reference. Figure 13A is an example of a conventional POR integrated circuit structure 1. As indicated by reference numeral 10, the S / D epitaxy (epitaxial silicon region) 50 can access only one (1) signal track 55 above (e.g., near the BEOL layer). As indicated by reference numeral 60, the S / D epitaxial region 60 must be connected to the backside through VBPR 65, and VBPR 65 is connected to the VSS region 66. It should be noted that the technology herein is fully compatible with POR processing, as Figure 13A , Figure 13B and Figure 14 shown. That is, the new features herein can be added without changing the POR structure.

[0087] Figure 13B is Figure 1B , but has been updated with the reference numerals used in the previous figures starting from Figure 2A . This is taken from the cross-sectional view Y2 as shown in Figure 14 . As Figure 13B shown, the integrated circuit structure 2 of an exemplary embodiment is shown herein. As indicated by reference numeral 20, the S / D epitaxy 410-2 can freely access two signal tracks 760-1 and 760-2, as indicated by reference numeral 75. In this example, the signal track 760-1 can be accessed using via VA 720-1, but the signal track 760-2 can alternatively be easily accessed. In this example, the signal track 760-1 is within the N2N region (also see Figure 14 ), but can also be in the P2P region (see Figure 14 ), which provides further opportunities for signal routing. As indicated by reference numeral 30, the S / D epitaxy 410-1 is powered from above (through via VA 720-2) by local VSS 740-1. These improvements address the deficiencies described above regarding Figure 13A .

[0088] Turning to Figure 14 , this figure provides a detailed top-down layout of the S / D contacts, VBPR, and VA. The cross-sections X, Y1, and Y2 shown in the previous figures are indicated in Figure 14 . The cross-section Y3 is also shown, as Figure 13AAs used in. The NFET region of the PC region including the gate metal layer 690 is shown. The VSS region 110, VDD region 120, PFET region 130, and NFET region 140 are shown. The gate notch 510 is illustrated. The dummy PC region 117 is also shown. The local VSS region 740 is above the via VA720-2, the via VA720-2 contacts CA 710-2 and is above CA 710-2, and the via VA 720-1 is above the contact CA 710-1 and both are in the N2N region (VA 720-1 is completely in the N2N region and CA 710-1 is partially in this region). Also see, for example Figure 7C , which shows the Y2 cross-section.

[0089] The local VDD region 750 is in Figure 14 shown, and the three gate notches 510 along the cross-section Y1 can also be in Figure 7B seen, and the local VDD (connected to the underlying via VB 730, Figure 14 not shown in) can also be seen. The local VDD region 750 is above the via VA 1420-2 (similar to 720-2), the via VA 1420-2 contacts CA 1410-2 (similar to 710-2) and is above CA 1410-2, and the via VA 1420-1 (similar to 720-1) is above the contact CA 1410-1 (similar to 710-1), and both are in the P2P region (VA 1420-1 is completely in the P2P region and CA 1410-1 is partially in this region).

[0090] In the foregoing description, numerous specific details such as specific structures, components, materials, dimensions, processing steps, and techniques have been set forth in order to provide a thorough understanding of the exemplary embodiments disclosed herein. However, those of ordinary skill in the art will understand that the exemplary embodiments disclosed herein may be practiced without these specific details. Additionally, details of well-known structures or processing steps may have been omitted or may not have been described to avoid obscuring the presented embodiments. It should be understood that when an element that is a layer, region, or substrate is referred to as being "on" or "above" another element, it can be directly on the other element or there can also be intervening elements. Conversely, when an element is referred to as being "directly on" or "directly" above another element, there are no intervening elements. It will also be understood that when an element is referred to as being "under" or "below" another element, it can be directly under or below the other element or there can be intervening elements. Conversely, when an element is referred to as being "directly under" or "directly below" another element, there are no intervening elements.

[0091] In addition, as used herein, terms such as "right", "left", "vertical", "horizontal", "top", "bottom", "upper", "lower", "under", "beneath", "underlying", "above", "overlying", "parallel", "perpendicular", etc. are intended to describe their relative positions as oriented and shown in the accompanying drawings (unless otherwise specified), and terms such as "contact", "direct contact", "adjacent", "directly adjacent", "immediately adjacent", etc. are intended to indicate that at least one element physically contacts another element (with no other element separating the described elements). The term "laterally" is used herein to describe the relative position of an element, and more specifically, to indicate that the element is positioned to the side of another element, rather than above or below the other element, as those elements are oriented and shown in the accompanying drawings. For example, an element positioned laterally adjacent to another element will be beside the other element, an element positioned laterally immediately adjacent to another element will be directly beside the other element, and an element that laterally surrounds another element will be adjacent and contiguous to the outer sidewall of the other element. All corresponding structures, materials, acts, and equivalents of means or step-plus-function elements in the appended claims are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed.

[0092] The description of the various embodiments of the present invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein were chosen to best explain the principles of the embodiments, the practical application, or the technical improvement of the technology found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

[0093] The following abbreviations, which may be found in the specification and / or the drawings, are defined as follows:

[0094] BDI Bottom Dielectric Isolation

[0095] BEOL Back End of Line

[0096] BILD Backside Interlayer Dielectric

[0097] BSPDN Backside Power Distribution Network

[0098] CA Source / Drain Contact

[0099] CPP Contact Poly Pitch

[0100] epi Epitaxial Silicon (Region)

[0101] HM Hard Mask

[0102] ILD Interlayer Dielectric

[0103] M1 First metal layer

[0104] MOL Middle of line

[0105] N2N n-type (NFET) to n-type (NFET) semiconductor region

[0106] N2P n-type to p-type semiconductor region

[0107] NFET n-type field effect transistor

[0108] NS Nanoscale sheet

[0109] OPL Optical planarization layer

[0110] P2P p-type (PFET) to p-type (PFET) semiconductor region

[0111] PC Gate region

[0112] PFET p-type field effect transistor

[0113] POR Programming operation recording process

[0114] RX Active region

[0115] S / D Source / drain

[0116] S / D epi Source / drain epitaxy

[0117] STI Shallow trench isolation

[0118] VBPR Via to back power rail.

Claims

1. An integrated circuit structure, comprising: a power rail formed on the back side of a semiconductor wafer; and a front-end-of-line (BEOL) wire layer that is connected to the power rail through a gate, where the gate is of a type that is powered off by power coupled from the power rail through the gate to a first front-end BEOL wire layer.

2. The integrated circuit structure according to claim 1, further comprising front-end BEOL wires that are connected to one or more source / drain epitaxial silicon regions of corresponding transistors.

3. The integrated circuit structure according to claim 2, wherein, the front-end BEOL wires are connected to the one or more source / drain epitaxial silicon regions of the corresponding transistors using corresponding one or more vias.

4. The integrated circuit structure according to claim 2, wherein, the front-end BEOL wire layer is connected to the front-end BEOL wires.

5. The integrated circuit structure according to claim 1, wherein, the power rail is connected to the gate through a gate-fixing via that electrically connects the power rail to a portion of the gate.

6. The integrated circuit structure according to claim 1, wherein, the front-end BEOL wire layer is connected to the gate through a gate via contact.

7. The integrated circuit structure according to claim 1, wherein: the gate is a first gate and the power rail is a first power rail; the integrated circuit structure further comprises: a second power rail formed on the back side of the semiconductor wafer; and another front-end BEOL wire layer that is connected to the second power rail through a second gate, where the second gate is of a type that is powered off by power coupled from the second power rail through the second gate to the another front-end BEOL wire layer.

8. The integrated circuit structure according to claim 7, wherein: the first gate is an n-type gate and the power for the first gate is grounded; and the second gate is a p-type gate and the power for the second gate is powered.

9. The integrated circuit structure according to claim 7, wherein, the first gate and the second gate are formed adjacent to each other and are isolated at least by a gate notch formed between the adjacent first gate and second gate.

10. The integrated circuit structure according to claim 9, wherein, the first gate is at least partially formed in a first doped region of a first type, the second gate is at least partially formed in a second doped region of a second type, and the gate notch is formed in a region between the first doped region and the second doped region.

11. The integrated circuit structure according to claim 1, wherein: The integrated circuit structure further includes source / drain contacts that contact corresponding source / drain regions in the doped regions and extend beyond the source / drain regions to provide access to a signal track in a region between the doped region and another doped region of the same type and to a signal track in the doped region.

12. The integrated circuit structure according to claim 1, wherein a gate connected to a power rail formed on the back surface is isolated from an adjacent active gate not connected to the power rail formed on the back surface by a gate cutout.

13. The integrated circuit structure according to claim 12, wherein: the gate connected to the power rail formed on the back surface is of the same type as the adjacent active gate and is at least partially formed in each of two doped regions of the same type; and the gate cutout between the gate connected to the power rail formed on the back surface and the adjacent active gate is formed in a region between the two doped regions of the same type.

14. A method of forming an integrated circuit structure, comprising: forming a power rail on a back surface of a semiconductor wafer; forming gates in the semiconductor wafer; and forming a front-end-of-line (BEOL) wire layer connected to the power rail through the gates, wherein the gates are of a type that is powered off by power coupled from the power rail to a first front-end BEOL wire layer through the gates.

15. The method according to claim 14, wherein: forming the gates in the semiconductor wafer further includes forming a plurality of gates on a substrate of the semiconductor wafer, and forming the plurality of gates includes: performing gate patterning to pattern a plurality of gates on the substrate, the gate being one of the plurality of gates; performing source / drain epitaxy to form source / drain regions for the plurality of gates; performing interlayer dielectric deposition to at least cover the source / drain regions and at least partially isolate the plurality of gates; and forming the front-end-of-line (BEOL) wire layer includes forming BEOL interconnects and bonding a carrier wafer to the substrate on which the plurality of gates have been formed.

16. The method according to claim 15, wherein: forming the gates in the semiconductor wafer further includes forming back-gate-fixing vias at edges of the gates and filling the back-gate-fixing vias with a conductive material while the conductive material of the gates is being formed; the method further includes forming gate via contacts to connect the gates having the back-gate-fixing vias to the front-end-of-line (BEOL) wire layer; and the method further includes connecting the power rail to the back-gate-fixing vias.

17. The method according to claim 15, further comprising connecting one or more source / drain regions of one or more other corresponding gates among the plurality of gates that require power to one or more corresponding front-end BEOL wires, the one or more corresponding front-end BEOL wires being connected to the front-end-of-line (BEOL) wire layer.

18. The method according to claim 15, Wherein: the gate is a first gate, and the power rail is a first power rail; the method further comprises: forming a second power rail formed on the back side of the semiconductor wafer; and forming another front-end BEOL wire layer connected to the second power rail through a second gate, wherein the second gate is of a type that is powered off by a power supply coupled from the second power rail to the another front-end BEOL wire layer through the second gate; the first gate is an n-type gate, and the power supply for the first gate is grounded; and the second gate is a p-type gate, and the power supply for the first gate is powered.

19. The method according to claim 18, wherein, forming the first gate and the second gate includes forming the first gate and the second gate adjacent to each other, and the method includes forming and filling a gate notch between the adjacent first gate and second gate.

20. The method according to claim 15, further comprises: forming source / drain contacts that contact corresponding source / drain regions and extend beyond the source / drain regions to provide access to a signal track in a region between two doped regions of the same type and one of the signal tracks in the doped region.

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