Failure determination circuit, imaging device, and voltage detection circuit

Abstract

A fault determination circuit according to one embodiment of the present disclosure includes: a charge pump circuit including an amplification section having an output section configured to output a first voltage, and a switching section, the charge pump circuit configured to generate a second voltage based on the first voltage; a detection section electrically connected to the output section of the amplification section, and configured to output a first signal corresponding to the first voltage output from the output section; and a determination section configured to perform failure determination based on the first signal.

Description

Technical Field

[0001] The present disclosure relates to a failure determination circuit, an imaging device, and a voltage detection circuit. Background Art

[0002] A circuit for determining whether a boosted voltage obtained by boosting an input voltage is abnormal has been proposed. Citation List Patent Documents

[0003] Patent Document 1: Japanese Patent Application Laid-Open No. 2019-4681 Summary of the Invention

[0004] It is desired to reduce the circuit scale of a circuit for failure determination.

[0005] It is desired to provide a failure determination circuit that can suppress an increase in circuit scale.

[0006] A failure determination circuit according to an embodiment of the present disclosure includes: a charge pump circuit including an amplification unit and a switching unit, the amplification unit including an output unit configured to output a first voltage, the charge pump circuit being configured to generate a second voltage based on the first voltage; a detection unit electrically connected to the output unit of the amplification unit, the detection unit being configured to output a first signal corresponding to the first voltage output from the output unit; and a determination unit configured to perform failure determination based on the first signal. An imaging device according to an embodiment of the present disclosure includes: a photoelectric conversion unit that performs photoelectric conversion of light; a readout circuit configured to output a signal based on charges generated by the conversion at the photoelectric conversion unit; a control unit configured to control the readout circuit; a charge pump circuit including an amplification unit and a switching unit, the amplification unit including an output unit configured to output a first voltage, the charge pump circuit being configured to generate a second voltage to be supplied to the control unit based on the first voltage; and a detection unit electrically connected to the output unit of the amplification unit, the detection unit being configured to output a first signal corresponding to the first voltage output from the output unit. A voltage detection circuit according to an embodiment of the present disclosure includes: a charge pump circuit including an amplification unit and a switching unit, the amplification unit including an output unit configured to output a first voltage; and a detection unit electrically connected to the output unit of the amplification unit, the detection unit being configured to output a first signal corresponding to the first voltage output from the output unit. Brief Description of the Drawings

[0007] Figure 1 is a block diagram showing a schematic configuration example of an imaging device according to an embodiment of the present disclosure. Figure 2It is a diagram showing a configuration example of a pixel of an imaging device according to an embodiment of the present disclosure. Figure 3 It is a diagram showing a configuration example of a failure determination circuit of an imaging device according to an embodiment of the present disclosure. Figure 4 It is a timing chart showing an operation example of a charge pump circuit of an imaging device according to an embodiment of the present disclosure. Figure 5A It is an explanatory diagram showing an operation example of a charge pump circuit of an imaging device according to an embodiment of the present disclosure. Figure 5B It is an explanatory diagram showing an operation example of a charge pump circuit of an imaging device according to an embodiment of the present disclosure. Figure 5C It is an explanatory diagram showing an operation example of a charge pump circuit of an imaging device according to an embodiment of the present disclosure. Figure 6A It is an explanatory diagram showing an operation example of a detection unit of an imaging device according to an embodiment of the present disclosure. Figure 6B It is an explanatory diagram showing an operation example of a detection unit of an imaging device according to an embodiment of the present disclosure. Figure 6C It is an explanatory diagram showing an operation example of a detection unit of an imaging device according to an embodiment of the present disclosure. Figure 7 It is an explanatory diagram showing a configuration example of a determination unit of an imaging device according to an embodiment of the present disclosure. Figure 8A It is an explanatory diagram showing an operation example of a determination unit of an imaging device according to an embodiment of the present disclosure. Figure 8B It is an explanatory diagram showing an operation example of a determination unit of an imaging device according to an embodiment of the present disclosure. Figure 8C It is an explanatory diagram showing an operation example of a determination unit of an imaging device according to an embodiment of the present disclosure. Figure 9 It is a diagram showing a configuration example of a detection unit of an imaging device according to Modification 1 of the present disclosure. Figure 10 It is a diagram showing a configuration example of a failure determination circuit of an imaging device according to Modification 2 of the present disclosure. Figure 11A It is a diagram showing a configuration example of a failure determination circuit according to Modification 3 of the present disclosure. Figure 11B It is a diagram showing another configuration example of a failure determination circuit according to Modification 3 of the present disclosure. Figure 12 It is a diagram showing another configuration example of a failure determination circuit according to Modification 3 of the present disclosure. Figure 13 is a block diagram showing a configuration example of an electronic device including an imaging device. Figure 14 is a block diagram showing a schematic configuration example of a vehicle control system. Figure 15 is a diagram for assisting in explaining an example of the installation positions of an out-of-vehicle information detection unit and an imaging unit. Figure 16 is a diagram showing a schematic configuration example of an endoscopic surgical system. Figure 17 is a block diagram showing a functional configuration example of a camera head and a camera control unit (CCU). Detailed Embodiments

[0008] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the description will be made in the following order. 1. Embodiments 2. Variations 3. Application Examples 4. Usage Examples

[0009] <1. Embodiments> Figure 1 is a block diagram showing a schematic configuration example of an imaging device according to an embodiment of the present disclosure. The imaging device 1 includes a plurality of pixels P each including a photoelectric conversion unit, and is configured to perform photoelectric conversion on incident light to generate a signal. The imaging device 1 can receive light that has passed through an optical system (not shown) including an optical lens to generate a signal.

[0010] The photoelectric conversion unit of each pixel P of the imaging device 1 is, for example, a photodiode, and is configured to perform photoelectric conversion on light. The imaging device 1 includes a region having a plurality of pixels P two-dimensionally arranged in a matrix form as an imaging region. The pixel unit 100 is a pixel array in which a plurality of pixels P are arranged, and it can be said that the pixel unit 100 is a light receiving region.

[0011] The imaging device 1 captures incident light (image light) from a subject via an optical system including an optical lens. The imaging device 1 captures an image of the subject formed by the optical lens. The imaging device 1 performs photoelectric conversion on the received light to generate pixel signals. The imaging device 1 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The imaging device 1 is applicable to electronic devices such as digital cameras, video cameras, or mobile phones.

[0012] [Schematic Configuration of Imaging Device] As in Figure 1In the illustrated example, the imaging device 1 includes, in the area around the pixel section 100 (pixel array), for example, a pixel control section 111, a signal processing section 112, a control section 113, a processing section 114, and the like. In addition, the imaging device 1 includes a plurality of control lines L1 and a plurality of signal lines L2.

[0013] The control line L1 is a signal line capable of transmitting a signal for controlling the pixel P, and is connected to the pixel control section 111 and the pixel P of the pixel section 100. In Figure 1 the illustrated example, in the pixel section 100, each of the plurality of control lines L1 is wired for each pixel row including a plurality of pixels P arranged in the horizontal direction (row direction). The control line L1 is configured to transmit a control signal for reading a signal from the pixel P.

[0014] The plurality of control lines L1 for each pixel row of the imaging device 1 include: a wiring for transmitting a signal for controlling a transfer transistor, a wiring for transmitting a signal for controlling a selection transistor, a wiring for transmitting a signal for controlling a reset transistor, and the like. It can be said that the control line L1 is also a driving line for transmitting a signal for driving the pixel P.

[0015] The signal line L2 is a signal line capable of transmitting a signal from the pixel P, and is connected to the pixel P of the pixel section 100 and the signal processing section 112. In the pixel section 100, the signal line L2 is wired for each pixel column including a plurality of pixels P arranged in the vertical direction (column direction). The signal line L2 is a vertical signal line and is configured to transmit a signal output from the pixel P.

[0016] The pixel control section 111 is configured to control each pixel P of the pixel section 100. The pixel control section 111 includes a buffer, a shift register, an address decoder, and the like. The pixel control section 111 generates a signal for driving the pixel P and outputs the signal to each pixel P of the pixel section 100 via the control line L1. The pixel control section 111 is controlled by the control section 113 to perform control of the pixel P of the pixel section 100.

[0017] The pixel control section 111 includes a signal output section 101 having a plurality of buffer circuits. A plurality of buffers 102 are provided in the signal output section 101 corresponding to the number of signals to be transmitted. As in Figure 1 the illustrated example, the buffer 102 (output section) is provided corresponding to the control line L1. The buffer 102 (output section) transmits a signal for driving the pixel P. The plurality of buffers 102 include: a buffer configured to output a signal for controlling the transfer transistor of the pixel P, a buffer configured to output a signal for controlling the reset transistor, a buffer configured to output a signal for controlling the selection transistor, and the like.

[0018] The pixel control unit 111 generates, for example, signals for controlling the pixel P (such as signals for controlling the transfer transistor of the pixel P or signals for controlling the reset transistor, etc.), and supplies such signals to each pixel P through the signal output unit 101 and the control line L1. The pixel control unit 111 can execute control for reading pixel signals from each pixel P. It can be said that the pixel control unit 111 is a pixel driving unit (or vertical driving unit) configured to drive each pixel P. It should be noted that the pixel control unit 111 and the control unit 113 can be regarded together as the pixel control unit.

[0019] In addition, the imaging device 1 includes a charge pump circuit 120 and a detection unit 130. The charge pump circuit 120 is controlled by the control unit 113 and is configured to supply a predetermined voltage (potential) to the signal output unit 101 of the pixel control unit 111 and the like. The detection unit 130 is configured to generate a signal for failure determination. The detection unit 130 is electrically connected to the charge pump circuit 120 and can output a signal regarding the state of the charge pump circuit 120. Although it will be described later, the imaging device 1 includes a failure determination circuit having the charge pump circuit 120 and the detection unit 130.

[0020] The charge pump circuit 120 is a voltage generation unit (such as a buck circuit or a boost circuit, etc.) and is configured to generate a voltage by boosting or bucking the input voltage. The charge pump circuit 120 (voltage generation unit) is electrically connected to the signal output unit 101 and can supply the boosted or bucked voltage to the signal output unit 101. It can be said that the charge pump circuit 120 is a power supply circuit configured to supply voltage and current.

[0021] For example, the charge pump circuit 120 is configured to output a voltage obtained by bucking the input voltage to the signal output unit 101. The charge pump circuit 120 can generate a voltage VRL as a negative voltage through a buck operation to supply the voltage VRL to the signal output unit 101. For example, the voltage VRL is supplied as a negative power supply voltage from the charge pump circuit 120 to the signal output unit 101.

[0022] As an example, the buffer 102 of the signal output unit 101 is configured to output a control signal that reaches a high level (e.g., the power supply voltage VDD) or a low level (e.g., the ground voltage or the voltage VRL supplied from the charge pump circuit 120) to each pixel P. The buffer 102 of the signal output unit 101 can supply, via the control line L1, a control signal having, for example, the voltage VRL level to a transistor (such as a transfer transistor or a reset transistor, etc.) of each pixel P to make the transistor in an off state (non-conducting state).

[0023] It should be noted that the pixel control unit 111 may include a charge pump circuit 120. In addition, the pixel control unit 111 or the control unit 113 may include a detection unit 130. The charge pump circuit 120 and the detection unit 130 may be integrally formed.

[0024] The signal processing unit 112 is configured to perform signal processing on the signals of the pixels received as input. The signal processing unit 112 includes, for example, a load circuit unit, an AD (analog-to-digital) conversion unit, a horizontal selection switch, etc. It should be noted that the signal processing unit 112 may include an amplification circuit unit configured to amplify the signals read from the pixels P via the signal line L2.

[0025] The signals output from each pixel P selected and scanned by the pixel control unit 111 are input to the signal processing unit 112 via the signal line L2. The signal processing unit 112 can, for example, perform signal processing such as AD conversion or CDS (correlated double sampling) on the signals of the pixels P. The signals of each pixel P transmitted through each signal line L2 are subjected to signal processing by the signal processing unit 112 and then output to the processing unit 114.

[0026] The processing unit 114 is configured to perform signal processing on the input signals. The processing unit 114 includes, for example, a circuit that performs various types of signal processing on the pixel signals. The processing unit 114 may include a processor and a memory. The processing unit 114 performs signal processing on the pixel signals input from the signal processing unit 112 and outputs the processed pixel signals. The processing unit 114 can, for example, perform various types of signal processing such as noise reduction processing or gray scale correction processing.

[0027] The control unit 113 is configured to control each part of the imaging device 1. The control unit 113 can receive a clock, data of commands regarding the operation mode, etc. supplied from the outside, and can output data such as internal information regarding the imaging device 1. The control unit 113 includes a timing generator configured to generate various timing signals. The control unit 113 performs drive control of the pixel control unit 111, the signal processing unit 112, etc. based on various timing signals (such as pulse signals or clock signals) generated by the timing generator. It should be noted that the control unit 113 and the processing unit 114 may be integrally formed.

[0028] It should be noted that the pixel control unit 111, the signal processing unit 112, the control unit 113, the processing unit 114, the charge pump circuit 120, the detection unit 130, etc. may be provided on one semiconductor substrate, or may be provided in a divided manner on multiple semiconductor substrates. The imaging device 1 may have a structure including a plurality of stacked substrates (multi-layer structure).

[0029] [Configuration of Pixels] Figure 2This is a diagram showing a configuration example of a pixel of an imaging device according to this embodiment. The pixel P includes a photoelectric conversion section 12 and a readout circuit 20. The readout circuit 20 is configured to output a signal based on the charge generated by photoelectric conversion. As an example, the readout circuit 20 includes a transfer transistor 13, an FD (floating diffusion) 14, an amplification transistor 15, a selection transistor 16, and a reset transistor 17.

[0030] The transfer transistor 13, the amplification transistor 15, the selection transistor 16, and the reset transistor 17 are MOS transistors (MOSFETs) each including a gate terminal, a source terminal, and a drain terminal. In Figure 2 the example shown, the transfer transistor 13, the amplification transistor 15, the selection transistor 16, and the reset transistor 17 are each constituted by an NMOS transistor. It should be noted that the transistors of the pixel P may be constituted by PMOS transistors.

[0031] The photoelectric conversion section 12 is configured to generate charge by photoelectric conversion. In Figure 2 the example shown, the photoelectric conversion section 12 is a photodiode (PD) and converts incident light into charge. The photoelectric conversion section 12 performs photoelectric conversion to generate charge corresponding to the amount of received light.

[0032] The transfer transistor 13 is configured to transfer the charge generated by photoelectric conversion at the photoelectric conversion section 12 to the FD 14. As Figure 2 shown, the transfer transistor 13 is controlled by a signal TRG to electrically connect the photoelectric conversion section 12 and the FD 14 or to disconnect the electrical connection between the photoelectric conversion section 12 and the FD 14. The transfer transistor 13 may transfer the stored charge generated by photoelectric conversion at the photoelectric conversion section 12 to the FD 14.

[0033] The FD 14 is a storage section and is configured to store the transferred charge. The FD 14 may store the charge generated by photoelectric conversion at the photoelectric conversion section 12. It can be said that the FD 14 is also a holding section configured to hold the transferred charge. The FD 14 stores the transferred charge and converts the charge into a voltage corresponding to the capacitance of the FD 14.

[0034] The amplification transistor 15 is configured to generate and output a signal based on the charge stored in the FD 14. As Figure 2 shown, the gate of the amplification transistor 15 is electrically connected to the FD 14 and receives the voltage generated by conversion at the FD 14 as an input. The drain of the amplification transistor 15 is connected to a power supply line supplied with a power supply voltage VDD, and the source of the amplification transistor 15 is connected to a signal line L2 via the selection transistor 16. The amplification transistor 15 may generate a signal based on the charge stored in the FD 14, that is, a signal based on the voltage of the FD 14, and may output the signal to the signal line L2.

[0035] The selection transistor 16 is configured to control the output of the pixel signal. The selection transistor 16 is controlled by the signal SEL and is configured to output the signal from the amplification transistor 15 to the signal line L2. The selection transistor 16 can control the timing of outputting the pixel signal. It should be noted that the selection transistor 16 can be provided between the power supply line supplied with the power supply voltage VDD and the amplification transistor 15. In addition, the selection transistor 16 can be omitted as needed.

[0036] The reset transistor 17 is configured to reset the voltage of the FD 14. In Figure 2 the example shown, the reset transistor 17 is electrically connected to the power supply line supplied with the power supply voltage VDD and is configured to reset the charge of the pixel P. The reset transistor 17 is controlled by the signal RST and can reset the charge stored in the FD 14 to reset the voltage of the FD 14. It should be noted that the reset transistor 17 can discharge the charge stored in the photoelectric conversion unit 12 via the transfer transistor 13.

[0037] The pixel control unit 111 (refer to Figure 1 ) supplies control signals to the gates of the transfer transistor 13, the selection transistor 16, the reset transistor 17, etc. of each pixel P through the above-described signal output unit 101, the control line L1, etc., so that the transistors are in the on state (conducting state) or the off state (non-conducting state). The plurality of control lines L1 of the imaging device 1 include: a wiring for transmitting the signal TRG for controlling the transfer transistor 13, a wiring for transmitting the signal SEL for controlling the selection transistor 16, a wiring for transmitting the signal RST for controlling the reset transistor 17, etc.

[0038] The pixel control unit 111 controls the conduction or cutoff of the transfer transistor 13, the selection transistor 16, the reset transistor 17, etc. The pixel control unit 111 controls the readout circuit 20 of each pixel P so that each pixel P outputs the pixel signal to the signal line L2. The pixel control unit 111 can perform control to read the pixel signal of each pixel P into the signal line L2.

[0039] Figure 3 FIG. is a diagram showing a configuration example of a failure determination circuit of an imaging device according to an embodiment. The failure determination circuit 200 includes a charge pump circuit 120, a detection unit 130, and a determination unit 140. In addition, the failure determination circuit 200 may include a reference voltage generation unit 30. The reference voltage generation unit 30 is configured to generate a reference voltage and a reference current. As Figure 3 shown, the reference voltage generation unit 30 includes an amplification unit 40, a current source 35, and resistors R1 to R3.

[0040] As Figure 3As shown, the reference voltage generation unit 30 includes: a node N1 connected to one end (a terminal) of the current source 35 and the resistor R1, and a node N2 connected to the other end (the other terminal) of the resistor R1 and one end of the resistor R2. Further, the reference voltage generation unit 30 includes a node N3 connected to the other end of the resistor R2 and one end of the resistor R3. The other end of the resistor R3 is connected to the reference potential line. In Figure 3 the example shown, the reference potential line is a ground line (ground wire).

[0041] The amplification unit 40 includes, for example, an input unit 41a, an input unit 41b, and an output unit 42, and includes an amplifier circuit configured to amplify a signal. In Figure 3 the example shown, the input unit 41a of the amplification unit 40 is a first input terminal and is connected to the node N2. A voltage V1 corresponding to the current flowing through the resistors R2 and R3 is input to the input unit 41a. The input unit 41b of the amplification unit 40 is a second input terminal. A reference voltage REF is input to the input unit 41b of the amplification unit 40.

[0042] It should be noted that in Figure 3 the example shown, the input unit 41a is a positive input terminal, and the input unit 41b is a negative input terminal. The output unit 42 of the amplification unit 40 is an output terminal and is electrically connected to the current source 35. The amplification unit 40 can output a voltage based on the voltage V1 input to the input unit 41a and the reference voltage REF input to the input unit 41b from the output unit 42 to the current source 35.

[0043] The current source 35 is configured to supply a current based on the voltage Vout1 that is the output voltage of the output unit 42 of the amplification unit 40. The current source 35 generates a current corresponding to the voltage Vout1 and supplies the current to the resistors R1 to R3. In Figure 3 the example shown, the current source 35 is constituted by a transistor M1. The transistor M1 is, for example, a PMOS transistor.

[0044] One of the source and drain of the transistor M1 is electrically connected to the resistor R1. The other of the source and drain of the transistor M1 is connected to a power supply line to which the power supply voltage VDDH is supplied. The gate of the transistor M1 is electrically connected to the output unit 42 of the amplification unit 40. The transistor M1 can generate a current based on the voltage Vout1 and output the generated current to the resistors R1 to R3 and the like.

[0045] The reference voltage generation unit 30 adjusts the current of the current source 35 so that the voltage V1 at the node N2 of the input unit 41a input to the amplification unit 40 becomes the same voltage as the reference voltage REF input to the input unit 41b. At the nodes N1 and N3, voltages VREF1 and VREF2 are respectively generated based on the current supplied by the current source 35. The voltage VREF1 at the node N1 and the voltage VREF2 at the node N3 both become voltages having magnitudes corresponding to the voltage value of the reference voltage REF and the resistance values of the resistors R1 to R3. As described above, the reference voltage generation unit 30 can generate the voltages VREF1 and VREF2 to supply the voltages VREF1 and VREF2 to the charge pump circuit 120.

[0046] The charge pump circuit 120 includes an amplification unit 50, a switching unit 60, resistors R4 and R5, and a timing control unit 65. The charge pump circuit 120 is configured to output a boosted or bucked voltage based on the voltage Vout2 that is the output voltage of the amplification unit 50. In Figure 3 the example shown, the charge pump circuit 120 is configured to generate the voltage VRL as a negative voltage through a bucking operation.

[0047] The amplification unit 50 includes, for example, an input unit 51a, an input unit 51b, and an output unit 52, and includes an amplifier circuit configured to amplify a signal. In Figure 3 the example shown, the input unit 51a of the amplification unit 50 is a first input terminal and is connected to the node N3. The voltage VREF2 corresponding to the current flowing through the resistor R3 is input to the input unit 51a.

[0048] The input unit 51b of the amplification unit 50 is a second input terminal and is connected to the node N4 that connects the resistor R4 and the resistor R5 to each other. The voltage V2 based on the voltage VRL that is the output voltage of the charge pump circuit 120 (feedback) is input to the input unit 51b of the amplification unit 50. The voltage V2 becomes a voltage having a magnitude corresponding to the difference between the voltage VRL and the voltage VREF1 and the resistance values of the resistors R4 and R5.

[0049] In Figure 3 the example shown, the input unit 51a is a positive input terminal and the input unit 51b is a negative input terminal. The output unit 52 of the amplification unit 50 is an output terminal and is electrically connected to the switching unit 60. The amplification unit 50 generates the voltage Vout2 based on the voltage VREF2 input to the input unit 51a and the voltage V2 input to the input unit 51b.

[0050] The amplifier section 50 can output a voltage Vout2 from the output section 52 to the switching section 60. The voltage Vout2 is an output voltage corresponding to the difference between the voltage VREF2 and the voltage V2. It can be said that the amplifier section 50 is a comparison section, and compares the voltage VREF2 with the voltage V2 to output an output signal as the comparison result.

[0051] The switching section 60 includes a plurality of switches and capacitors. In Figure 3 the illustrated example, the switching section 60 includes a switch SW1, a switch SW2, a switch SW3, a switch SW4, and a capacitor C1. In addition, the switching section 60 includes: a node N11 connected to one electrode (terminal) of the switch SW1, the switch SW2, and the capacitor C1, and a node N12 connected to the other electrode of the switch SW3, the switch SW4, and the capacitor C1.

[0052] The switch SW1 is provided between the output section 52 of the amplifier section 50 and the capacitor C1, and is configured to electrically connect the output section 52 and the capacitor C1 to each other. The switch SW2 is provided between the capacitor C1 and a power supply line to which the power supply voltage VDDH is supplied, and is configured to electrically connect the capacitor C1 and the power supply line to each other.

[0053] The switch SW3 is provided between the capacitor C1 and a capacitor C2 serving as an external capacitor, and is configured to electrically connect the capacitor C1 and the capacitor C2 to each other. The switch SW4 is provided between the capacitor C1 and a reference potential line, and is configured to electrically connect the capacitor C1 and the reference potential line to each other.

[0054] Each switch (switch SW1, SW2, SW3, and SW4) of the switching section 60 is constituted by a transistor. For example, each of the switches SW1 and SW3 is constituted by an NMOS transistor. Each of the switches SW2 and SW4 is constituted by a PMOS transistor.

[0055] The capacitor C1 has a predetermined capacitance value and is configured to hold a voltage. One electrode of the capacitor C1 is connected to the node N11, and the other electrode of the capacitor C1 is connected to the node N12. The capacitor C1 is constituted by, for example, a MOS capacitor, a MIM (metal-insulator-metal) capacitor, or the like. It should be noted that, similar to the capacitor C2, the capacitor C1 can be provided outside the imaging device 1 as an external capacitor.

[0056] The capacitor C2 has a predetermined capacitance value and is configured to hold a voltage. One electrode (terminal) of the capacitor C2 is connected to the switch SW3, and the other electrode of the capacitor C2 is connected to the reference potential line. The capacitor C2 is an external capacitor and can hold the voltage VRL generated by the charge pump circuit 120. It should be noted that the capacitor C2 can be provided inside the imaging device 1.

[0057] The timing control unit 65 supplies signals to the respective switches of the switch unit 60 to control the conduction and cutoff of the respective switches. The timing control unit 65 supplies signals for controlling the switches to the switches SW1 to SW4 in response to a clock signal to switch the connection states of the respective ones of the switches SW1 to SW4. It can be said that the timing control unit 65 is a pulse signal generation unit.

[0058] Figure 4 is a timing chart showing an operation example of the charge pump circuit of the imaging device according to the embodiment. Refer to Figure 4 , Figures 5A to 5C and other timing charts to describe the operation example of the charge pump circuit 120. Figure 4 shows the control signals (drive signals) supplied to the respective switches of the switch unit 60.

[0059] In Figure 4 the period from time t1 to time t2 shown, in the charge pump circuit 120, the switches SW2 and SW4 become conductive states. As Figure 5A schematically shown, the switch SW2 as a PMOS transistor and the switch SW4 as a PMOS transistor become conductive states (on states). In addition, the switch SW1 as an NMOS transistor and the switch SW3 as an NMOS transistor become cutoff states (non-on states).

[0060] When the switches SW2 and SW4 become conductive states, the node N11 and the power supply line supplied with the power supply voltage VDDH are electrically connected to each other, and the node N12 and the reference potential line are electrically connected to each other. This causes the power supply voltage VDDH to be supplied to the node N11, and causes the ground voltage (GND voltage) to be supplied to the node N12. That is, the power supply voltage VDDH is supplied to one electrode of the capacitor C1, and the ground voltage is supplied to the other electrode of the capacitor C1. This causes the capacitor C1 to be charged, and the charge corresponding to the power supply voltage VDDH is stored in the capacitor C1.

[0061] In the period from time t2 to time t3, in the charge pump circuit 120, the switches SW1 to SW4 become cutoff states. As Figure 5B shown, the switches SW1 to SW4 all become cutoff states. In the capacitor C1, the voltage between the electrodes is maintained.

[0062] In the period from time t3 to time t4, in the charge pump circuit 120, the switches SW1 and SW3 become conductive states. As Figure 5C shown, the switches SW1 and SW3 become conductive states, and the switches SW2 and SW4 become cutoff states.

[0063] When the switches SW1 and SW3 are turned on, the output section 52 of the amplifier section 50 and the node N11 are electrically connected to each other, and the capacitor C2 and the node N12 are electrically connected to each other. In this case, the voltage Vout2 is supplied from the output section 52 of the amplifier section 50 to the node N11.

[0064] The voltage supplied to one electrode of the capacitor C1 changes from the power supply voltage VDDH to the voltage Vout2. In this case, when the voltage Vout2, which is a low voltage, is supplied to one electrode of the capacitor C1 in response to the comparison result between the voltage VREF2 and the voltage V2, the voltage of the other electrode of the capacitor C1 is stepped down. The charge of the capacitor C1 is discharged, and it can be said that the voltage of the node N12 is stepped down. The stepped-down voltage is output to the capacitor C2 as the voltage VRL and then smoothed by the capacitor C2.

[0065] In the period from time t4 to time t5, in the charge pump circuit 120, the switches SW1 to SW4 are turned off. The period from time t2 to time t3 and the period from time t4 to time t5 are also referred to as dead times.

[0066] Even in the period after time t5, similar to the period from time t1 to time t5, the step-down operation is performed. This causes the charge pump circuit 120 to generate the voltage VRL as a negative voltage. The charge pump circuit 120 can output the voltage VRL as a negative voltage to the outside (in Figure 1 this case, the signal output section 101 of the pixel control section 111).

[0067] The charge pump circuit 120 controls the step-down operation so that the voltage V2 input to the input section 51b of the amplifier section 50 becomes the same voltage as the voltage VREF2 input to the input section 51a. For example, when the voltage V2 decreases as the negative voltage VRL is generated, the voltage Vout2 increases according to the voltage difference between the voltage V2 and the voltage VREF2.

[0068] When the voltage Vout2 having a level corresponding to the comparison result between the voltage VREF2 and the voltage V2 is supplied to the capacitor C1, the discharge of the charge from the capacitor C1 is reduced. As described above, the charge pump circuit 120 can perform feedback control so that the voltage VRL becomes the target voltage value.

[0069] Figure 3The detection unit 130 shown is configured to generate a signal regarding the state of the charge pump circuit 120. The detection unit 130 is electrically connected to the output unit 52 of the amplification unit 50 and can output a signal corresponding to the voltage Vout2 output from the output unit 52. The detection unit 130 is electrically connected to the output unit 52 of the amplification unit 50 and the switch SW1 of the switch unit 60. The detection unit 130 is configured to generate, for example, a signal indicating whether the magnitude of the voltage Vout2 is greater than a predetermined threshold value.

[0070] In Figure 3 In the example shown, the detection unit 130 includes a first signal generation unit 71 and a second signal generation unit 72. The first signal generation unit 71 is configured to generate a signal (referred to as the signal Power_OK) indicating whether the voltage Vout2 is greater than a first threshold value. The second signal generation unit 72 is configured to generate a signal (referred to as the signal Power_OVER) indicating whether the voltage Vout2 is greater than a second threshold value. It should be noted that the second threshold value is, for example, a value greater than the first threshold value.

[0071] The first signal generation unit 71 includes a transistor M11, a resistor R11, and an inverter 81. The transistor M11 is an n-type transistor (in Figure 3 this case, an NMOS transistor). The gate of the transistor M11 is electrically connected to the output unit 52 of the amplification unit 50. One of the source and drain of the transistor M11 is electrically connected to the resistor R11 and the inverter 81. The other of the source and drain of the transistor M11 is electrically connected to the reference potential line. The voltage Vout2 is input from the output unit 52 of the amplification unit 50 to the gate of the transistor M11.

[0072] The first signal generation unit 71 can generate the signal Power_OK indicating whether the voltage Vout2 is greater than the first threshold value (in Figure 3 this case, the threshold voltage of the transistor M11). For example, when the voltage Vout2 is lower than the first threshold value, the first signal generation unit 71 outputs a low-level signal Power_OK from the inverter 81. In addition, when the voltage Vout2 is higher than the first threshold value, the first signal generation unit 71 outputs a high-level signal Power_OK from the inverter 81.

[0073] The second signal generation unit 72 includes a transistor M12, a resistor R12, and an inverter 82. The transistor M12 is a p-type transistor (in Figure 3 this case, a PMOS transistor). The gate of the transistor M12 is electrically connected to the output unit 52 of the amplification unit 50. One of the source and drain of the transistor M12 is electrically connected to the resistor R12 and the inverter 82. The other of the source and drain of the transistor M12 is electrically connected to the power supply line supplied with the power supply voltage (for example, the power supply voltage VDDH). The voltage Vout2 is input from the output unit 52 of the amplification unit 50 to the gate of the transistor M12.

[0074] The second signal generation unit 72 can generate a signal Power_OVER indicating whether the voltage Vout2 is greater than a second threshold value (a value obtained by subtracting the threshold voltage of the transistor M12 from the power supply voltage VDDH in Figure 3 . For example, when the voltage Vout2 is lower than the second threshold value, the second signal generation unit 72 outputs a low-level signal Power_OVER from the inverter 82. In addition, when the voltage Vout2 is higher than the second threshold value, the second signal generation unit 72 outputs a high-level signal Power_OVER from the inverter 82.

[0075] Figures 6A to 6C is an explanatory diagram showing an operation example of the detection unit of the imaging device according to the embodiment. Figure 6A An example in which the voltage Vout2 is less than the first threshold value (i.e., the case where the voltage VRL does not reach the target voltage) is shown. In this case, the voltage Vout2 input from the amplifier unit 50 to the first signal generation unit 71 and the second signal generation unit 72 is a voltage lower than the first threshold value. This turns the transistor M11 of the first signal generation unit 71 into an off state and turns the transistor M12 of the second signal generation unit 72 into an on state. The first signal generation unit 71 outputs a low-level signal Power_OK, and the second signal generation unit 72 outputs a low-level signal Power_OVER.

[0076] Figure 6B An example in which the voltage value of the voltage Vout2 is between the first threshold value and the second threshold value (i.e., the case where the voltage value of the voltage VRL is within the target range) is shown. In this case, the voltage value of the voltage Vout2 input from the amplifier unit 50 to the first signal generation unit 71 and the second signal generation unit 72 is a value between the first threshold value and the second threshold value. This turns the transistor M11 of the first signal generation unit 71 into an on state and also turns the transistor M12 of the second signal generation unit 72 into an on state. The first signal generation unit 71 outputs a high-level signal Power_OK, and the second signal generation unit 72 outputs a low-level signal Power_OVER.

[0077] Figure 6CAn example is shown in which the voltage Vout2 is greater than the second threshold (i.e., the case where the voltage VRL is an excessive (surplus) negative voltage outside the target range). In this case, the voltage Vout2 input from the amplifier unit 50 to the first signal generation unit 71 and the second signal generation unit 72 is a voltage higher than the second threshold. This turns the transistor M11 of the first signal generation unit 71 on and the transistor M12 of the second signal generation unit 72 off. The first signal generation unit 71 can output a high-level signal Power_OK, and the second signal generation unit 72 can output a high-level signal Power_OVER.

[0078] The determination unit 140 (refer to Figure 3 etc.) is configured to perform a fault determination based on the signal output from the detection unit 130. The determination unit 140 can grasp whether the output voltage of the charge pump circuit 120 is a value within the target range by using the signal output from the detection unit 130 (e.g., the signal Power_OK and the signal Power_OVER), and thus perform a fault determination on the charge pump circuit 120.

[0079] As described above, the detection unit 130 outputs the signals Power_OK and Power_OVER as signals indicating the state of the charge pump circuit 120. The signals Power_OK and Power_OVER are respectively signals indicating whether the voltage VRL is a value within the target range. This enables the determination unit 140 to estimate the presence or absence of a fault in the charge pump circuit 120 by using the signals Power_OK and Power_OVER.

[0080] Figure 7 is an explanatory diagram showing a configuration example of the determination unit of the imaging device according to the embodiment. In addition, Figures 8A to 8C is an explanatory diagram showing an operation example of the determination unit. For example, the determination unit 140 includes a plurality of logic circuits such as flip-flops and AND circuits. In Figure 7 the example shown, the determination unit 140 includes inverters 91, 92a and 92b, AND circuits 93a and 93b, buffers 94a and 94b, and flip-flops 95a and 95b.

[0081] The signal Power_OK is input from the first signal generation unit 71 to the flip-flop 95a via the AND circuit 93a and the buffer 94a. In addition, the signal RESET as a reset signal is input to the flip-flop 95a via the inverter 92a. The flip-flop 95a can perform sampling in response to the signal Power_OK to output a signal XERR1 indicating the determination result of the presence or absence of a fault.

[0082] As an example, when the signal Power_OK goes high within a frame period, the flip-flop 95a outputs a high-level signal XERR1 indicating "no fault". In addition, when the signal Power_OK never goes high within a certain frame period, the flip-flop 95a outputs a low-level signal XERR1 indicating "fault".

[0083] The signal Power_OVER is input to the flip-flop 95b from the second signal generation unit 72 via the inverter 91, the AND circuit 93b, and the buffer 94b. In addition, the signal RESET is input to the flip-flop 95b via the inverter 92b. The flip-flop 95b can perform sampling in response to the signal Power_OVER to output a signal XERR2 indicating the determination result of the presence or absence of a fault.

[0084] As an example, when the signal Power_OVER goes low within a frame period, the flip-flop 95b outputs a high-level signal XERR2 indicating "no fault". In addition, when the signal Power_OK never goes low within a frame period, the flip-flop 95b outputs a low-level signal XERR2 indicating "fault".

[0085] In Figure 8A In the example shown, within the frame period after the signal RESET transitions from low to high, the voltage VRL is a value within the target range. In this case, the signal Power_OK goes high and the signal Power_OVER goes low. The determination unit 140 outputs a high-level signal XERR1 indicating "no fault" and a high-level signal XERR2.

[0086] In Figure 8B In the example shown, within the frame period, the voltage VRL does not drop to the target voltage and the signal Power_OK goes low. The determination unit 140 outputs a low-level signal XERR1 indicating "fault". In Figure 8C In the example shown, within the frame period, the voltage VRL is a low voltage outside the target range and the signal Power_OVER goes high. The determination unit 140 outputs a low-level signal XERR2 indicating "fault".

[0087] [Function and Effect] The failure determination circuit (failure determination circuit 200) according to the present embodiment includes: a charge pump circuit (charge pump circuit 120), which includes an amplification unit (amplification unit 50) and a switching unit (switching unit 60), the amplification unit (amplifier unit 50) includes an output unit configured to output a first voltage (voltage Vout2), and the charge pump circuit (charge pump circuit 120) is configured to generate a second voltage based on the first voltage; a detection unit (detection unit 130), which is electrically connected to the output unit of the amplification unit, and the detection unit (detection unit 130) is configured to output a first signal (for example, signal Power_OK) corresponding to the first voltage output from the output unit; and a determination unit (determination unit 140), which is configured to perform failure determination based on the first signal.

[0088] In the imaging device 1 according to the present embodiment, the detection unit 130 uses the voltage Vout2, which is the output voltage of the amplification unit 50, to generate a signal (signal Power_OK or signal Power_OVER) to be used in failure determination. Compared with the case where failure determination is performed by measuring the output voltage of the charge pump circuit, this can particularly reduce the number of devices in the analog circuit, and can also reduce the circuit area of the detection unit 130, the determination unit 140, etc. A failure determination circuit capable of suppressing an increase in circuit scale can be realized.

[0089] The imaging device 1 according to the present embodiment performs failure determination by using the signal Power_OK or signal Power_OVER that becomes low level or high level. Since a digital determination method is used, the determination unit 140 can be relatively easily designed by RTL design.

[0090] Next, a modification example of the present disclosure will be described. Hereinafter, components similar to those in the above embodiment are denoted by the same reference numerals, and their descriptions are appropriately omitted.

[0091] <2. Modification Example> (2-1. Modification Example 1) In the above embodiment, a configuration example of the detection unit 130 has been described, but the configuration of the detection unit 130 is not limited thereto. Figure 9 It is a diagram showing a configuration example of the detection unit of the imaging device according to Modification Example 1 of the present disclosure. As in Figure 9 In the example shown, the first signal generation unit 71 and the second signal generation unit 72 of the detection unit 130 may each include an input unit 75a and an input unit 75b connected to different power supply lines.

[0092] The input section 75a (input circuit) of the first signal generation section 71 is connected to the reference potential line supplied with the voltage VSSH and the power supply line supplied with the power supply voltage VDD1. The input section 75b (input circuit) of the second signal generation section 72 is connected to the reference potential line supplied with the power supply voltage VDD2 higher than the power supply voltage VDD1 and the power supply line supplied with the power supply voltage VDDH (>VDD2).

[0093] In Figure 9 the example shown, the first signal generation section 71 includes inverters 83a and 83b connected to the reference potential line supplied with the voltage VSSH and the power supply line supplied with the power supply voltage VDD1 as the input section 75a, and is configured to output a signal indicating whether the voltage Vout2 is greater than the first threshold value. The second signal generation section 72 includes inverters 84a and 84b connected to the reference potential line supplied with the power supply voltage VDD2 and the power supply line supplied with the power supply voltage VDDH as the input section 75b, and is configured to output a signal indicating whether the voltage Vout2 is greater than the second threshold value.

[0094] In this way, different first and second threshold values can be set for the first signal generation section 71 and the second signal generation section 72, respectively, and the signal Power_OK and the signal Power_OVER can be generated. In the case of this modification example, an effect similar to that of the above-described embodiment can also be obtained.

[0095] (2-2. Modification Example 2) Figure 10 FIG. is a diagram showing a configuration example of a failure determination circuit of an imaging device according to Modification Example 2. The reference voltage generation section 30 may have a configuration as Figure 10 shown. In Figure 10 the example shown, the reference voltage generation section 30 is configured to output a current corresponding to the reference current IREF supplied to the current source 35a through the current sources 35b and 35c. It can be said that the reference voltage generation section 30 is a reference current generation section configured to generate a reference current.

[0096] In the imaging device 1, the voltage VREF2 is generated by using the output current of the current source 35b, and the voltage V2 is generated by using the output current of the current source 35c. In the case of this modification example, an effect similar to that of the above-described embodiment can also be obtained.

[0097] (2-3. Modification Example 3) The failure determination circuit including the detection section 130 according to the present disclosure is applicable not only to the charge pump circuit 120 but also to various circuits and devices. Figure 11A 、 Figure 11B and Figure 12It is an explanatory diagram showing a configuration example of a failure determination circuit according to Modification 3. For example, as Figure 11A or Figure 11B shown, the detection unit 130 can be connected to the amplifier circuit 160 (regulator circuit) for failure detection of the amplifier circuit 160.

[0098] As Figure 11A shown, the detection unit 130 can be connected to the output unit 152 of the amplifier unit 150, and the signals Power_OK and Power_OVER for failure detection can be generated by using the voltage output from the output unit 152 of the amplifier unit 150. As Figure 11B shown, the signals Power_OK and Power_OVER for failure detection can be generated by using the voltage REGOUT which is the output voltage of the amplifier unit 150.

[0099] In addition, for example, the detection unit 130 can be used to perform failure detection on a filter circuit (such as a low-pass filter or a high-pass filter). For example, as Figure 12 shown, the detection unit 130 can be connected to the filter circuit 170 which is a low-pass filter connected to the power supply, and can be used for failure detection of the filter circuit 170. The detection unit 130, determination unit 140, failure determination circuit 200, etc. according to the present disclosure are applicable to various circuits and devices.

[0100] <3. Application Examples> For example, the above imaging device 1 etc. are applicable to camera systems such as digital cameras, video cameras, etc., or any type of electronic device including an imaging function such as a mobile phone including an imaging function. Figure 13 A schematic configuration of the electronic device 1000 is shown.

[0101] The electronic device 1000 includes, for example, a lens group 1001, an imaging device 1, a DSP (Digital Signal Processor) circuit 1002, a frame memory 1003, a display unit 1004, a storage unit 1005, an operation unit 1006, and a power supply unit 1007 which are connected to each other via a bus 1008.

[0102] The lens group 1001 captures incident light (image light) from a subject to form an image on the imaging surface of the imaging device 1. The imaging device 1 converts the amount of incident light formed as an image on the imaging surface by the lens group 1001 into an electrical signal in units of pixels, and supplies the electrical signal as a pixel signal to the DSP circuit 1002.

[0103] The DSP circuit 1002 is a signal processing circuit that processes the signals supplied from the imaging device 1. The DSP circuit 1002 outputs the image data obtained by processing the signals from the imaging device 1. The frame memory 1003 temporarily stores the image data processed by the DSP circuit 1002 in units of frames.

[0104] For example, the display unit 1004 includes a panel-type display device such as a liquid crystal panel or an organic EL (electroluminescence) panel, and stores the image data of the moving image or still image captured by the imaging device 1 in a recording medium such as a semiconductor memory or a hard disk.

[0105] The operation unit 1006 outputs operation signals for various functions included in the electronic device 1000 according to the operations performed by the user. The power supply unit 1007 is a power supply that appropriately supplies various types of power that will become the operation power of the DSP circuit 1002, the frame memory 1003, the display unit 1004, the storage unit 1005, and the operation unit 1006 to these supply targets.

[0106] <4. Application Examples> (Application Examples for Mobile Bodies) The technology according to the present disclosure (this technology) can be used for various products. For example, the technology according to the present disclosure can be implemented as a device mounted on any type of mobile body such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility device, an airplane, an unmanned aerial vehicle, a ship, or a robot.

[0107] Figure 14 is a block diagram showing a schematic configuration example of a vehicle control system that is an example of a mobile body control system to which the technology of the embodiments according to the present disclosure can be applied.

[0108] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. In Figure 14 the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside vehicle information detection unit 12030, an inside vehicle information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as the functional configurations of the integrated control unit 12050.

[0109] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for the following devices: a driving force generation device such as an internal combustion engine or a drive motor for generating the driving force of the vehicle; a driving force transmission mechanism for transmitting the driving force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating the braking force of the vehicle, etc.

[0110] The body system control unit 12020 controls the operation of various devices provided on the vehicle according to various programs. For example, the body system control unit 12020 serves as a control device for a keyless entry system, a smart key system, an electric window device, or various lights such as a headlight, a taillight, a brake light, a turn signal light, or a fog light. In this case, radio waves transmitted from a portable device as an alternative to a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door lock device, electric window device, lights, etc.

[0111] The outside information detection unit 12030 detects information about the outside of the vehicle having the vehicle control system 12000. For example, the outside information detection unit 12030 is connected to the imaging unit 12031. The outside information detection unit 12030 causes the imaging unit 12031 to image an image of the outside of the vehicle and receives the captured image. Based on the received image, the outside information detection unit 12030 can perform detection processing on objects such as a person, a vehicle, an obstacle, a marker, or a symbol on the road surface, or detection processing of the distance to these objects.

[0112] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 can be visible light, or can be invisible light such as infrared light.

[0113] The inside information detection unit 12040 detects information about the inside of the vehicle. For example, the inside information detection unit 12040 is connected to the driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that images the driver. Based on the detection information input from the driver state detection unit 12041, the inside information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or can determine whether the driver is dozing off.

[0114] The microcomputer 12051 can calculate control target values for the driving force generating device, the steering mechanism, or the braking device based on information about the inside or outside of the vehicle obtained by the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an advanced driver assistance system (ADAS), which includes: collision avoidance or impact mitigation of the vehicle, following driving based on the inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, or vehicle lane departure warning, etc.

[0115] In addition, the microcomputer 12051 can perform cooperative control for autonomous driving, which makes the vehicle autonomously drive based on information about the inside or outside of the vehicle (the information is obtained by the out-vehicle information detection unit 12030 or the in-vehicle information detection unit 12040) by controlling the driving force generating device, the steering mechanism, the braking device, etc., without relying on the driver's operation, etc.

[0116] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on information about the outside of the vehicle (the information is obtained by the out-vehicle information detection unit 12030). For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlight to change from high beam to low beam according to the positions of the vehicle ahead or the oncoming vehicle detected by the out-vehicle information detection unit 12030.

[0117] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device that can visually or auditorily notify information to the passengers in the vehicle or the outside of the vehicle. In Figure 14 the example, the audio speaker 12061, the display unit 12062, and the instrument panel 12063 are shown as output devices. For example, the display unit 12062 can include at least one of an in-vehicle display and a head-up display.

[0118] Figure 15 is a diagram showing an example of the installation position of the imaging unit 12031.

[0119] In Figure 15 it, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0120] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions on the front nose, side mirrors, rear bumper, and rear door of the vehicle 12100 and at a position on the upper part of the windshield inside the vehicle. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the upper part of the windshield inside the vehicle mainly obtain images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly obtain images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or rear door mainly obtains images of the rear of the vehicle 12100. The imaging unit 12105 provided on the upper part of the windshield inside the vehicle is mainly used to detect a vehicle ahead, pedestrians, obstacles, signals, traffic signs, or lanes, etc.

[0121] Incidentally, Figure 15 An example of the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 represents the imaging range of the imaging unit 12101 provided on the front nose. The imaging ranges 12112 and 12113 represent the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively. The imaging range 12114 represents the imaging range of the imaging unit 12104 provided on the rear bumper or rear door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above is obtained.

[0122] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0123] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the temporal change of the distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and thus extract the nearest three-dimensional object as the vehicle ahead. In particular, this three-dimensional object exists on the driving path of the vehicle 12100 and travels in substantially the same direction as the vehicle 12100 at a predetermined speed (for example, equal to or greater than 0 km / h). In addition, the microcomputer 12051 can set the following distance to be maintained between the vehicle front and the vehicle ahead, and perform automatic braking control (including following stop control) or automatic acceleration control (including following start control), etc. Therefore, cooperative control for autonomous driving can be executed, which enables the vehicle to travel autonomously without relying on the driver's operation, etc.

[0124] For example, the microcomputer 12051 can classify three-dimensional object data regarding a three-dimensional object into three-dimensional object data of a two-wheeled vehicle, a standard-sized vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually recognize and obstacles that the driver of the vehicle 12100 has difficulty visually recognizing. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. When the collision risk is equal to or higher than a set value and thus there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or avoidance steering through the drive system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0125] At least one of the imaging units 12101 to 12104 can be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can identify a pedestrian by determining whether there is a pedestrian in the captured images of the imaging units 12101 to 12104. For example, this identification of a pedestrian is performed through a program of extracting feature points in the captured images of the imaging units 12101 to 12104 that are infrared cameras and a program of performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square contour line for emphasis is displayed in a superimposed manner on the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 so that an icon representing the pedestrian or the like is displayed at a desired position.

[0126] Examples of the mobile body control system to which the technology according to the present disclosure can be applied have been described above. For example, the technology according to the present disclosure can be applied to the imaging unit 12031 among the above configurations. Specifically, for example, the imaging device 1 or the like can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, fault detection can be appropriately performed.

[0127] (Application Example of Endoscopic Surgery System) The technology according to the present disclosure (this technology) can be applied to various products. For example, the technology according to the present disclosure can be applied to an endoscopic surgery system.

[0128] Figure 16 FIG. is a schematic configuration example of an endoscopic surgical system to which the technology according to the embodiments of the present disclosure (the present technology) can be applied.

[0129] In Figure 16 it, a state is shown in which a surgeon (doctor) 11131 is performing surgery on a patient 11132 on a hospital bed 11133 using an endoscopic surgical system 11000. As shown in the figure, the endoscopic surgical system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy device 11112, a support arm device 11120 that supports the endoscope 11100 thereon, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0130] The endoscope 11100 includes a lens barrel 11101 and a camera head 11102. A region of the lens barrel having a predetermined length from its distal end is inserted into the body cavity of the patient 11132, and the camera head is connected to the proximal end of the lens barrel 11101. In the illustrated example, the endoscope 11100 is shown as a rigid endoscope configured to have a rigid lens barrel 11101. However, the endoscope 11100 can also be configured as a flexible endoscope having a flexible lens barrel 11101.

[0131] The lens barrel 11101 has an opening at its distal end in which an objective lens is assembled. A light source device 11203 is connected to the endoscope 11100 so that the light generated by the light source device 11203 is introduced into the distal end of the lens barrel 11101 through an optical fiber extending inside the lens barrel 11101 and irradiated onto an observation target in the body cavity of the patient 11132 through the objective lens. It should be noted that the endoscope 11100 can be a direct-view endoscope or a forward-oblique endoscope or a side-view endoscope.

[0132] An optical system and an imaging element are provided inside the camera head 11102 so that the reflected light (observation light) from the observation target is focused on the imaging element through the optical system. The observation light is photoelectrically converted by the imaging element to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The image signal is transmitted as raw data to the CCU 11201.

[0133] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and centrally controls the operations of the endoscope 11100 and the display device 11202. Further, for example, the CCU 11201 receives the image signal from the camera head 11102 and performs various image processing operations such as developing processing (demosaicing processing) on the image signal to display an image based on the image signal.

[0134] The display device 11202 displays, under the control of the CCU 11201, an image based on an image signal that has been subjected to image processing by the CCU 11201 thereon.

[0135] For example, the light source device 11203 includes a light source such as a light-emitting diode (LED) and supplies illumination light when imaging the surgical area to the endoscope 11100.

[0136] The input device 11204 is an input interface of the endoscopic surgical system 11000. A user can input various information or instructions into the endoscopic surgical system 11000 through the input device 11204. For example, the user inputs instructions to change the imaging conditions (type of illumination light, magnification, focal length, etc.) of the endoscope 11100.

[0137] The treatment tool control device 11205 controls the drive of the energy device 11112 to cauterize or incise tissue, seal blood vessels, etc. The pneumoperitoneum device 11206 supplies gas into the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to expand the body cavity to ensure the field of view of the endoscope 11100 and ensure the working space for the surgeon. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various forms such as text, image, or graph.

[0138] It should be noted that the light source device 11203 that supplies illumination light when imaging the surgical area to the endoscope 11100 may be composed of a white light source. For example, the white light source is composed of an LED, a laser light source, or a combination thereof. When the white light source is composed of a combination of red, green, and blue (RGB) laser light sources, since the output intensity and output timing of each color (each wavelength) can be controlled with high precision, the white balance of the captured image can be adjusted by the light source device 11203. Further, in this case, if the laser beams from the respective RGB laser light sources are irradiated on the observation target in a time-division manner, then the drive of the imaging element of the camera head 11102 is controlled in synchronization with the irradiation timing. Then, images corresponding to the R, G, and B colors can also be captured in a time-division manner. According to this method, a color image can be obtained even without a color filter being arranged for the imaging element.

[0139] Further, the drive of the light source device 11203 can be controlled so as to change the intensity of the light to be output at predetermined intervals. By controlling the drive of the imaging element of the camera head 11102 in synchronization with the change timing of the light intensity to acquire images in a time-division manner and synthesize the images, a high-dynamic-range image can be created, and the image will not have occlusion shadows due to underexposure and highlights due to overexposure.

[0140] Further, the light source device 11203 may be configured to provide light in a predetermined wavelength band corresponding to special light observation. For example, in special light observation, by utilizing the wavelength dependence of light absorption of body tissues, light with a narrower band than the illumination light (i.e., white light) during normal observation is irradiated to perform narrow band observation (narrow band imaging) on predetermined tissues such as blood vessels in the mucosal surface part with high contrast. Alternatively, in special light observation, fluorescence observation for obtaining an image from fluorescence generated by irradiating excitation light may be performed. In fluorescence observation, fluorescence observation of body tissues (autofluorescence observation) may be performed by irradiating excitation light on body tissues, or a fluorescence image may be obtained by locally injecting a reagent such as indocyanine green (ICG) into body tissues and irradiating excitation light corresponding to the fluorescence wavelength of the reagent on the body tissues. The light source device 11203 may be configured to provide such narrow band light and / or excitation light suitable for special light observation as described above.

[0141] Figure 17 is a diagram showing Figure 16 a functional configuration example of the illustrated camera head 11102 and CCU 11201.

[0142] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected by a transmission cable 11400 to communicate with each other.

[0143] The lens unit 11401 is an optical system provided at the connection position with the lens barrel 11101. Observation light entering from the distal end of the lens barrel 11101 is guided to the camera head 11102 and introduced into the lens unit 11401. The lens unit 11401 is composed of a combination of a plurality of lenses including a zoom lens and a focusing lens.

[0144] The number of imaging elements included in the imaging unit 11402 can be one (single-board type) or multiple (multi-board type). For example, when the imaging unit 11402 is configured as a multi-board type, image signals corresponding to each R, G, and B are generated by the imaging elements, and the image signals can be synthesized to obtain a color image. The imaging unit 11402 can also be configured to have a pair of imaging elements for obtaining a right-eye image signal and a left-eye image signal corresponding to three-dimensional (3D) display. If 3D display is performed, then the surgeon 11131 can more accurately grasp the depth of the living tissue in the surgical area. It should be noted that when the imaging unit 11402 is configured in a stereoscopic manner, multiple lens unit 11401 systems are provided corresponding to each imaging element.

[0145] Furthermore, the imaging unit 11402 may not necessarily be provided on the camera head 11102. For example, the imaging unit 11402 can be provided directly behind the objective lens inside the lens barrel 11101.

[0146] The drive unit 11403 is composed of an actuator, and under the control of the camera head control unit 11405, moves the zoom lens and the focusing lens of the lens unit 11401 along the optical axis by a predetermined distance. Therefore, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0147] The communication unit 11404 is composed of a communication device for sending and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 as RAW data to the CCU 11201 through the transmission cable 11400.

[0148] In addition, the communication unit 11404 receives a control signal for controlling the drive of the camera head 11102 from the CCU 11201 and provides the control signal to the camera head control unit 11405. For example, the control signal includes information related to imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value when capturing an image, and / or information specifying the magnification and focus of the captured image.

[0149] It should be noted that imaging conditions such as frame rate, exposure value, magnification, or focus can be specified by the user or can be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, an automatic exposure (AE) function, an automatic focus (AF) function, and an automatic white balance (AWB) function are provided in the endoscope 11100.

[0150] The camera head control unit 11405 controls the driving of the camera head 11102 based on the control signal received from the CCU 11201 through the communication unit 11404.

[0151] The communication unit 11411 is composed of a communication device for transmitting various information to and receiving various information from the camera head 11102. The communication unit 11411 receives the image signal transmitted to it from the camera head 11102 through the transmission cable 11400.

[0152] Furthermore, the communication unit 11411 transmits the control signal for controlling the driving of the camera head 11102 to the camera head 11102. The image signal and the control signal can be transmitted through electrical communication, optical communication, etc.

[0153] The image processing unit 11412 performs various image processes on the image signal in the form of RAW data transmitted from the camera head 11102.

[0154] The control unit 11413 performs various controls related to image capturing of the surgical area, etc. through the endoscope 11100 and display of the captured image obtained by image capturing of the surgical area, etc. For example, the control unit 11413 creates a control signal for controlling the driving of the camera head 11102.

[0155] Furthermore, the control unit 11413 controls the display device 11202 to display the captured image in which the surgical area, etc. has been photographed, based on the image signal that has been processed by the image processing unit 11412. At this time, the control unit 11413 can use various image recognition techniques to recognize various objects in the captured image. For example, the control unit 11413 can recognize surgical tools such as surgical forceps, specific living body areas, bleeding, fog when using the energy device 11112, etc. by detecting the shape, color, etc. of the edges of the objects included in the captured image. When the control unit 11413 controls the display device 11202 to display the captured image, it can use the recognition result to display various surgical support information in an overlapping manner with the image of the surgical area. In the case where the surgical support information is displayed in an overlapping manner and presented to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can perform the surgery reliably.

[0156] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for electrical signal communication, an optical fiber for optical communication, or a composite cable for both electrical communication and optical communication.

[0157] Here, although in the illustrated example, communication is performed through wired communication using the transmission cable 11400, communication between the camera head 11102 and the CCU 11201 can be performed through wireless communication.

[0158] Examples of the endoscopic surgical system to which the technology according to the present disclosure can be applied have been described above. The technology according to the present disclosure can be appropriately applied to, for example, the imaging unit 11402 provided on the camera head 11102 of the endoscope 11100 in the above configuration. By applying the technology according to the present disclosure to the imaging unit 11402, a high-performance endoscope 11100 can be provided.

[0159] The present disclosure has been described through embodiments, modification examples, application examples, and usage examples. However, the present technology is not limited to the above embodiments and other embodiments, and various modifications can be made thereto. For example, although the above modification examples have been described as modification examples of the above embodiments, the configurations of the respective modification examples can be appropriately combined.

[0160] A failure determination circuit according to an embodiment of the present disclosure includes: a charge pump circuit including an amplification unit and a switching unit, the amplification unit including an output unit configured to output a first voltage, the charge pump circuit being configured to generate a second voltage based on the first voltage; a detection unit electrically connected to the output unit of the amplification unit, the detection unit being configured to output a first signal corresponding to the first voltage output from the output unit; and a determination unit configured to perform a failure determination based on the first signal. This enables the realization of a failure determination circuit capable of suppressing an increase in circuit scale.

[0161] An imaging device according to an embodiment of the present disclosure includes: a photoelectric conversion unit that performs photoelectric conversion of light; a readout circuit configured to output a signal based on charges generated by the conversion at the photoelectric conversion unit; a control unit (e.g., pixel control unit 111) configured to control the readout circuit; a charge pump circuit including an amplification unit and a switching unit, the amplification unit including an output unit configured to output a first voltage, the charge pump circuit being configured to generate a second voltage to be supplied to the control unit based on the first voltage; and a detection unit electrically connected to the output unit of the amplification unit, the detection unit being configured to output a first signal corresponding to the first voltage output from the output unit. This enables failure detection to be performed while suppressing an increase in circuit scale.

[0162] A voltage detection circuit according to an embodiment of the present disclosure includes: a charge pump circuit including an amplification unit and a switching unit, the amplification unit including an output unit configured to output a first voltage; and a detection unit electrically connected to the output unit of the amplification unit, the detection unit being configured to output a first signal corresponding to the first voltage output from the output unit. This enables the realization of a voltage detection circuit capable of suppressing an increase in circuit scale.

[0163] It should be noted that the effects described herein are merely examples and are not limited to such descriptions, and may also include other effects. In addition, the present disclosure may adopt the following configurations. (1) A failure determination circuit includes: a charge pump circuit including an amplification unit and a switching unit, the amplification unit including an output unit configured to output a first voltage, the charge pump circuit being configured to generate a second voltage based on the first voltage; a detection unit electrically connected to the output unit of the amplification unit, the detection unit being configured to output a first signal corresponding to the first voltage output from the output unit; and a determination unit configured to perform a failure determination based on the first signal. (2) The failure determination circuit according to (1), wherein the switching unit includes a first switch configured to electrically connect the output unit and a first capacitor to each other; and the detection unit is electrically connected to the output unit and the first switch. (3) The failure determination circuit according to (1) or (2), wherein the amplification unit includes a first input unit to which an input voltage based on the second voltage is input; and a second input unit to which a reference voltage is input, the amplification unit being configured to output the first voltage based on the input voltage and the reference voltage from the output unit. (4) The failure determination circuit according to any one of (1) to (3), wherein the detection unit is configured to output the first signal indicating that the first voltage is greater than a first threshold. (5) The failure determination circuit according to any one of (1) to (4), wherein the detection unit includes a first signal generation unit, and the first signal generation unit includes a first transistor to which the first voltage is input and a first resistor electrically connected to a source or a drain of the first transistor, the first signal generation unit being configured to output the first signal. (6) The failure determination circuit according to any one of (1) to (5), wherein the detection unit is configured to output the first signal indicating that the first voltage is greater than a first threshold value and the second signal indicating that the first voltage is greater than a second threshold value. (7) The failure determination circuit according to (6), wherein the determination unit is configured to perform the failure determination based on the first signal and the second signal. (8) The failure determination circuit according to (6) or (7), wherein the detection unit includes a first signal generation unit and a second signal generation unit, the first signal generation unit includes a first transistor to which the first voltage is input and a first resistor electrically connected to a source or a drain of the first transistor, and the first signal generation unit is configured to output the first signal, and the second signal generation unit includes a second transistor to which the first voltage is input and a second resistor electrically connected to a source or a drain of the second transistor, and the second signal generation unit is configured to output the second signal. (9) The failure determination circuit according to (8), wherein the first transistor includes an n-type transistor, and the second transistor includes a p-type transistor. (10) The failure determination circuit according to any one of (1) to (9), wherein the detection unit includes a first signal generation unit, and the first signal generation unit includes a first inverter electrically connected to a first power supply line, and the first signal generation unit is configured to output the first signal indicating that the first voltage is greater than a first threshold value. (11) The failure determination circuit according to (10), wherein the detection unit includes a second signal generation unit, and the second signal generation unit includes a second inverter electrically connected to a second power supply line, and the second signal generation unit is configured to output the second signal indicating that the first voltage is greater than a second threshold value. (12) The failure determination circuit according to any one of (1) to (11), wherein the switch unit includes: a first switch provided between the output unit and a first electrode of a first capacitor; a second switch provided between the first electrode of the first capacitor and a power supply line; A third switch, which is disposed between the second electrode of the first capacitor and the second capacitor; and A fourth switch, which is disposed between the second electrode of the first capacitor and the reference potential line. (13) The failure determination circuit according to (12), wherein the amplifying unit includes: a first input unit to which an input voltage based on the second voltage held by the second capacitor is input; and a second input unit to which a reference voltage is input, and the amplifying unit is configured to output the first voltage based on the input voltage and the reference voltage from the output unit. (14) The failure determination circuit according to any one of (1) to (13), wherein the amplifying unit is configured to output the first voltage corresponding to a difference between the input voltage based on the second voltage and the reference voltage. (15) The failure determination circuit according to any one of (1) to (14), wherein the charge pump circuit is configured to output the second voltage that is boosted or bucked based on the first voltage. (16) An imaging device, comprising: A photoelectric conversion unit that performs photoelectric conversion on light; A readout circuit that is configured to output a signal based on charges generated by conversion at the photoelectric conversion unit; A control unit that is configured to control the readout circuit; A charge pump circuit that includes an amplifying unit and a switching unit, the amplifying unit includes an output unit configured to output a first voltage, and the charge pump circuit is configured to generate a second voltage to be supplied to the control unit based on the first voltage; and A detection unit that is electrically connected to the output unit of the amplifying unit, and the detection unit is configured to output a first signal corresponding to the first voltage output from the output unit. (17) The imaging device according to (16), further comprising a determination unit configured to perform failure determination based on the first signal. (18) A voltage detection circuit, comprising: A charge pump circuit that includes an amplifying unit and a switching unit, the amplifying unit includes an output unit configured to output a first voltage; and A detection unit that is electrically connected to the output unit of the amplifying unit, and the detection unit is configured to output a first signal corresponding to the first voltage output from the output unit. (19) The voltage detection circuit according to (18), wherein the detection unit is configured to output a first signal indicating that the first voltage is greater than a first threshold value and a second signal indicating that the first voltage is greater than a second threshold value. (20) The voltage detection circuit according to (18) or (19), wherein the detection unit includes: a first signal generation unit and a second signal generation unit, the first signal generation unit includes: a first transistor to which the first voltage is input and a first resistor electrically connected to the source or drain of the first transistor, the first signal generation unit is configured to output the first signal, and the second signal generation unit includes: a second transistor to which the first voltage is input and a second resistor electrically connected to the source or drain of the second transistor, the second signal generation unit is configured to output the second signal.

[0164] This application claims the benefit of Japanese Patent Application No. JP2022-180969, filed with the Japan Patent Office on November 11, 2022, the entire contents of which are incorporated herein by reference.

[0165] Those skilled in the art should understand that various deformations, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors as long as they are within the scope of the appended claims or their equivalents.

Claims

1. A fault determination circuit, comprising: a charge pump circuit including an amplification section and a switching section, the amplification section including an output section configured to output a first voltage, the charge pump circuit being configured to generate a second voltage based on the first voltage; a detection section electrically connected to the output section of the amplification section, the detection section being configured to output a first signal corresponding to the first voltage output from the output section; and a determination section configured to perform a fault determination based on the first signal.

2. The fault determination circuit according to claim 1, wherein the switching section includes a first switch configured to electrically connect the output section and a first capacitor to each other; and the detection section is electrically connected to the output section and the first switch.

3. The fault determination circuit according to claim 1, wherein the amplification section includes a first input section to which an input voltage based on the second voltage is input; and a second input section to which a reference voltage is input, the amplification section being configured to output the first voltage based on the input voltage and the reference voltage from the output section.

4. The fault determination circuit according to claim 1, wherein the detection section is configured to output the first signal indicating that the first voltage is greater than a first threshold.

5. The fault determination circuit according to claim 1, wherein the detection section includes a first signal generation section, and the first signal generation section includes a first transistor to which the first voltage is input and a first resistor electrically connected to the source or drain of the first transistor, the first signal generation section being configured to output the first signal.

6. The fault determination circuit according to claim 1, wherein the detection section is configured to output the first signal indicating that the first voltage is greater than a first threshold and a second signal indicating that the first voltage is greater than a second threshold.

7. The fault determination circuit according to claim 6, wherein the determination section is configured to perform the fault determination based on the first signal and the second signal.

8. The fault determination circuit according to claim 6, wherein the detection section includes a first signal generation section and a second signal generation section, the first signal generation section includes a first transistor to which the first voltage is input and a first resistor electrically connected to the source or drain of the first transistor, the first signal generation section being configured to output the first signal, and the second signal generation section includes a second transistor to which the first voltage is input and a second resistor electrically connected to the source or drain of the second transistor, the second signal generation section being configured to output the second signal.

9. The fault determination circuit according to claim 8, wherein the first transistor includes an n-type transistor, and the second transistor includes a p-type transistor.

10. The fault determination circuit according to claim 1, wherein the detection section includes a first signal generation section, and the first signal generation section includes a first inverter electrically connected to a first power supply line, the first signal generation section being configured to output the first signal indicating that the first voltage is greater than a first threshold.

11. The failure determination circuit according to claim 10, wherein the detection unit includes a second signal generation unit, and the second signal generation unit includes a second inverter electrically connected to a second power supply line, and the second signal generation unit is configured to output a second signal indicating that the first voltage is greater than a second threshold value.

12. The failure determination circuit according to claim 1, wherein the switching unit comprises: a first switch disposed between the output unit and a first electrode of a first capacitor; a second switch disposed between the first electrode of the first capacitor and a power supply line; a third switch disposed between a second electrode of the first capacitor and a second capacitor; and a fourth switch disposed between the second electrode of the first capacitor and a reference potential line.

13. The failure determination circuit according to claim 12, wherein the amplification unit comprises: a first input unit to which an input voltage based on the second voltage held by the second capacitor is input; and a second input unit to which a reference voltage is input, and the amplification unit is configured to output the first voltage based on the input voltage and the reference voltage from the output unit.

14. The failure determination circuit according to claim 1, wherein the amplification unit is configured to output the first voltage corresponding to a difference between the input voltage based on the second voltage and the reference voltage.

15. The failure determination circuit according to claim 1, wherein the charge pump circuit is configured to output the second voltage that is boosted or bucked based on the first voltage.

16. An imaging device, comprising: a photoelectric conversion unit that performs photoelectric conversion on light; a readout circuit configured to output a signal based on charges generated by conversion at the photoelectric conversion unit; a control unit configured to control the readout circuit; a charge pump circuit including an amplification unit and a switching unit, the amplification unit including an output unit configured to output a first voltage, and the charge pump circuit being configured to generate a second voltage to be supplied to the control unit based on the first voltage; and a detection unit electrically connected to the output unit of the amplification unit, the detection unit being configured to output a first signal corresponding to the first voltage output from the output unit.

17. The imaging device according to claim 16, further comprising a determination unit configured to perform failure determination based on the first signal.

18. A voltage detection circuit, comprising: a charge pump circuit including an amplification unit and a switching unit, the amplification unit including an output unit configured to output a first voltage; and a detection unit electrically connected to the output unit of the amplification unit, the detection unit being configured to output a first signal corresponding to the first voltage output from the output unit.

19. The voltage detection circuit according to claim 18, wherein the detection unit is configured to output a first signal indicating that the first voltage is greater than a first threshold value and a second signal indicating that the first voltage is greater than a second threshold value.

20. The voltage detection circuit according to claim 19, wherein the detection unit comprises: a first signal generation unit and a second signal generation unit, The first signal generation unit includes: a first transistor to which the first voltage is input and a first resistor electrically connected to the source or drain of the first transistor, and the first signal generation unit is configured to output the first signal, and The second signal generation unit includes: a second transistor to which the first voltage is input and a second resistor electrically connected to the source or drain of the second transistor, and the second signal generation unit is configured to output the second signal.

Images