Three-dimensional memory device word line with reduced barrier damage

Abstract

A method includes obtaining a substrate structure of a three-dimensional (3D) memory device, forming a barrier layer comprising a high-k dielectric material on the substrate structure, and forming a word line comprising molybdenum for the 3D memory device on the barrier layer using an atomic layer deposition (ALD) process.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the manufacture of electronic devices. In particular, embodiments of the present disclosure relate to three-dimensional (3D) memory device word lines with reduced barrier layer damage. Background Art

[0002] An electronic device manufacturing apparatus may include a plurality of chambers, such as a processing chamber and a load lock chamber. Such an electronic device manufacturing apparatus may employ a robotic device in a transfer chamber, the robotic device being configured to transfer substrates between the plurality of chambers. In some cases, a plurality of substrates are transferred together. The processing chamber may be used in the electronic device manufacturing apparatus to perform one or more processes on a substrate, such as a deposition process and an etching process. For many processes, gases flow into the processing chamber. Electronic devices, such as semiconductor devices, are manufactured by performing a series of operations, which may include deposition, oxidation, photolithography, ion implantation, etching, etc., to form many patterned layers. Summary of the Invention

[0003] According to one embodiment, a method is provided. The method includes obtaining a substrate structure of a three-dimensional (3D) memory device, forming a barrier layer including a high-k dielectric material on the substrate structure, and forming a word line including molybdenum for the 3D memory device on the barrier layer using an atomic layer deposition (ALD) process.

[0004] According to one embodiment, a three-dimensional (3D) memory device is provided. The 3D memory device includes a barrier layer, and a word line including molybdenum disposed on the barrier layer. The barrier layer includes a high-k dielectric material that is not damaged by the atomic layer deposition (ALD) chemistry of the molybdenum used to form the word line. Brief Description of the Drawings

[0005] In some of the drawings, the present disclosure is illustrated by way of example and not limitation, where like reference numerals represent like elements.

[0006] It should be noted that different references to "one" or "an" embodiment in the present disclosure are not necessarily to the same embodiment, and such references mean at least one.

[0007] Figure 1 is a diagram of an example portion of a three-dimensional (3D) memory device according to some embodiments.

[0008] Figure 2 is a diagram of an exemplary deposition process according to some embodiments, which can be used to form at least a portion of a three-dimensional (3D) memory device.

[0009] Figures 3A - 3G is a diagram of an exemplary process flow for forming at least a portion of a three-dimensional (3D) memory device according to some embodiments.

[0010] Figure 4 is a diagram showing the difference in threshold voltage (Vt) shift in volts (V) after 1000 program / erase (P / E) cycles for various combinations of word line materials and barrier layer materials according to some embodiments.

[0011] Figure 5 is a diagram according to some embodiments showing drain current in amperes (A) as a function of equivalent oxide thickness (EOT) in nanometers (nm) for various combinations of word line materials and barrier layer materials.

[0012] Figure 6 is a diagram showing an exemplary portion of a three-dimensional (3D) memory device according to some embodiments.

[0013] Figures 7A - 7D is a flow chart of an exemplary method for fabricating a word line of a three-dimensional (3D) memory device with reduced barrier layer damage according to some embodiments. DETAILED DESCRIPTION

[0014] In some memory devices, such as flash memory devices (e.g., NAND flash memory devices), word lines are components involved in data read, write, and erase operations. NAND memory can be organized into a hierarchical structure including blocks, pages, and cells. Cells that store data as charge are the smallest data storage units in a NAND memory device. These cells are grouped into multiple pages, and the pages are further grouped into blocks. Word lines can be used to address and select specific cell columns in a memory array. In a NAND memory device, each cell is essentially a floating gate transistor or a charge trapping transistor. The cells can be organized into a grid-like structure with rows and columns.

[0015] In 3D NAND memory devices, the basic operating principles including the role of word lines are similar to those in planar (2D) NAND memory devices. However, 3D NAND technology introduces significant changes in the physical architecture of the memory cells. Instead of laying the memory cells flat on a silicon substrate, 3D NAND memory devices include vertically arranged stacks of memory cells, effectively creating a 3D structure.

[0016] A 3D NAND memory device may include a plurality of word lines extending from an initial layer of a stacked layer to a final layer of the stacked layer. Each word line may be connected to a corresponding group of cells ("page"), where each cell in the group of cells is included in a corresponding layer of the stacked layer. More specifically, the word line may be connected to the control gate of the cell. The 3D NAND memory device may also include a plurality of bit lines arranged perpendicular to the word lines, where each bit line is connected to a corresponding group of cells ("string"). More specifically, the bit line may be connected to the drain of the cell. The 3D NAND memory device may include additional components such as a source line, select gates (e.g., source select gate and drain select gate), etc. In some 3D NAND memory devices, the word lines are formed of tungsten (W) and / or titanium nitride (TiN).

[0017] Similar to 2D NAND memory devices, to read data from a group of cells ("page") in a 3D NAND memory device, a read voltage is applied to the word line connected to the group of cells, and the data is read out through the connected bit line. To write or program data onto a group of cells, the data is placed on the bit line, and a program voltage is applied to the word line, which causes electrons to tunnel into the floating gate or charge trap layer of the cell (depending on the specific type of 3D NAND memory device). Erasing data is performed by applying an erase voltage sufficient to release the stored charge to the substrate. Thus, read and program operations are performed at the page level, while erase operations are performed at the block level.

[0018] In some embodiments, the 3D NAND memory device includes a barrier layer. The barrier layer acts as a barrier to prevent electrons stored in the charge storage layer (e.g., floating gate or charge trap layer) of the cell from leaking out. In doing so, the barrier layer acts as an insulator to help maintain the stored charge. For example, the barrier layer may be formed of a dielectric material. An example of a dielectric material used to form the barrier layer is aluminum oxide (Al 2 O 3 ). Al 2 O 3 is a dielectric material with a dielectric constant of approximately 7.8. Thus, the barrier layer can contribute to the overall reliability and performance of the cell by ensuring that the charge stored in the cell remains stable and is not affected by interference from adjacent cells or external factors. The barrier layer can also act as a barrier to prevent impurities such as chlorine and fluorine from diffusing into the charge storage layer.

[0019] As described above, during programming and erasing operations, charges are moved into and out of the charge storage layer through a process called tunneling. The barrier layer, in conjunction with the tunnel layer, can control this tunneling process. The tunnel layer is a thin insulating layer that separates the channel layer from the charge storage layer, where data is stored in the form of charges. The main function of the channel layer is to serve as a conduction path for current to flow through the memory cell during read, programming, and erasing operations. Essentially, the channel layer connects the source and drain regions of the memory cell transistor and allows current to flow through it when an appropriate voltage is applied. For example, during programming, electrons can tunnel through the tunnel layer via the channel layer and be trapped in the charge storage layer. During erasing, electrons can tunnel back through the tunnel layer and exit through the channel layer.

[0020] In some embodiments, the 3D NAND memory device includes a charge barrier layer. The charge barrier layer can be used, for example, in charge trap flash (CTF) memory cells. In traditional floating gate flash memory cells, data is stored by injecting electrons into a conductive floating gate. In contrast, CIF memory cells use a charge trapping layer to store electrons, and this charge trapping is insulated by surrounding dielectric materials, one of which is the charge barrier layer. The charge barrier layer can act as a barrier to prevent electrons stored in the charge trapping layer from leaking into the control gate or other surrounding materials.

[0021] The change from a planar 2D architecture to a 3D vertical stacked architecture can achieve significant advantages, including higher capacity, better performance, and lower power consumption. One benefit of 3D NAND is that it allows significant scaling and increased storage density without the need to shrink the cell size. This is achieved by increasing the number of stacked layers.

[0022] The number of cell layers in the 3D memory device continues to increase to improve storage density. To compensate for the total thickness of the memory cell as the number of memory cell layers increases, the word line pitch (e.g., vertical pitch) and thickness can be reduced in order to lower the aspect ratio of the vertical channel structure of the 3D NAND memory device. Additionally, the word line resistance and / or resistivity increases due to the reduced word line thickness. Therefore, the material used to form the word line can achieve a lower resistance or resistivity at a thinner thickness than W and / or TiN, which may be beneficial for continuing to reduce the word line pitch as the number of memory cell layers increases.

[0023] In some embodiments, one candidate material to replace W and / or TiN as a word line material is molybdenum (Mo). For example, Mo has low resistance or resistivity characteristics and can be formed by depositing with a reduced barrier thickness (e.g., no barrier). Any suitable deposition process can be used to deposit Mo to form the word line. One such deposition process is the atomic layer deposition (ALD) process. However, at least some of the ALD chemistries (e.g., solid Mo precursors) used during the ALD process to deposit Mo can cause barrier layer damage (e.g., Al 2 O 3 barrier layer damage). Barrier layer damage can have a negative impact on the performance of the memory device. For example, barrier layer damage can affect the threshold voltage shift during the program / erase cycle, resulting in a shortened durability of the memory device and can have a negative impact on the erase performance due to electron tunneling, etc.

[0024] Some methods of addressing barrier layer damage may involve using different nucleation layers or liner layers. However, the nucleation layer or liner layer is generally formed of a material having a higher resistance or resistivity than the word line material. Therefore, the method of using a nucleation layer or liner layer can increase the word line resistance or resistivity.

[0025] To address these and other drawbacks, the embodiments described herein relate to the formation of word lines including Mo with reduced barrier layer damage. More specifically, the embodiments described herein can provide an ALD process for depositing low resistivity Mo in the formation of word lines and can utilize a barrier layer formed of a high-k dielectric material that resists damage caused by the ALD chemistries used to form Mo. The high-k dielectric material used to form the barrier layer described herein can have a dielectric constant greater than that of Al 2 O 3 . More specifically, the high-k dielectric material used to form the barrier layer described herein can have a dielectric constant greater than about 7.8. For example, the high-k dielectric material used to form the barrier layer described herein can have a dielectric constant greater than or equal to about 10. Therefore, the embodiments described herein can be used to form 3D memory device word lines with low resistance and reduced barrier layer damage, which can maintain or improve the threshold voltage shift during the program / erase cycle. In addition, forming the word line of Mo and the barrier layer of a high-k dielectric material can reduce electron tunneling from the word line to the charge trapping layer, which can improve the erase performance.

[0026] Figure 1Depicts an example portion of a 3D NAND memory device (“device”) 100 according to some embodiments. Device 100 includes a word line 110, a barrier layer 120, a channel layer 130, a tunnel layer 140, a charge trapping layer 150, and / or a charge barrier layer 160. In this illustrative example, there is no capping layer (i.e., no capping layer). In some embodiments, word line 110 is a replacement word line.

[0027] In some embodiments, word line 110 may include Mo. In some embodiments, word line 110 may be formed using an ALD process, depositing Mo in a manner that reduces damage to barrier layer 120. The ALD process may employ any suitable ALD chemistry. For example, the ALD chemistry may include any suitable ALD Mo precursor and reactant. Examples of suitable ALD chemistries include molybdenum dichloride dioxide (MoO 2 Cl 2 ) precursor or molybdenum pentachloride (MoCl 5 ) precursor and hydrogen gas (H 2 ).

[0028] In this example, device 100 further includes a nucleation layer 170, which may also be referred to as a seed layer. Nucleation layer 170 can be used to form Mo during the ALD process. Nucleation layer 170 can include any suitable material to facilitate the formation of Mo during the ALD process. Examples of materials that can be used to form nucleation layer 170 include molybdenum silicide (MoSi x ), silicon molybdenum oxide (e.g., MoSiO), molybdenum nitride (δ-MoN), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), etc. Nucleation layer 170 can be formed using any suitable deposition process. In some embodiments, nucleation layer 170 is formed using an ALD process. Nucleation layer 170 can be formed to have any suitable thickness. In some embodiments, the thickness of nucleation layer 170 ranges from about 0.25 nanometers to about 5 nanometers. In some embodiments, the thickness of nucleation layer 170 ranges from about 0.5 nanometers to about 3 nanometers.

[0029] Barrier layer 120 can include a high-k dielectric material having a dielectric constant greater than Al 2 O 3 . More specifically, barrier layer 120 can include a high-k dielectric material having a dielectric constant greater than about 7.8. For example, barrier layer 120 can include a high-k dielectric material having a dielectric constant greater than or equal to about 10. In some embodiments, barrier layer 120 includes a zirconia material. Examples of zirconia materials include zirconium dioxide (ZrO 2 ), aluminum zirconium dioxide (A1ZrO 2 ), doped ZrO 2etc. In some embodiments, the barrier layer 120 comprises a lanthanum oxide material. An example of a lanthanum oxide material is lanthanum aluminate (LaAlO 3 ). In some embodiments, the barrier layer 120 comprises a hafnium oxide material. Examples of hafnium oxide materials include hafnia (HfO 2 ), doped HfO 2 , etc. In some embodiments, the barrier layer 120 comprises yttria (Y 2 O 3 ). In some embodiments, the barrier layer 120 comprises a doped Al 2 o 3 material (i.e., Al 2 O 3 doped with a high-k material sufficient to increase the dielectric constant of the doped Al 2 o 3 material to above about 7.8). The barrier layer 120 can be formed using any suitable deposition process. In some embodiments, the barrier layer 120 is formed using an ALD process. The barrier layer 120 can be formed to have any suitable thickness. In some embodiments, the thickness of the barrier layer 120 ranges from about 1 nanometer to about 5 nanometers. In some embodiments, the thickness of the barrier layer 120 ranges from about 2 nanometers to about 3 nanometers.

[0030] In some embodiments, the channel layer 130 comprises silicon (Si). In some embodiments, the tunnel layer 140 comprises an oxide material. For example, the tunnel layer 140 can comprise SiO 2 . In some embodiments, the charge trapping layer 150 comprises a nitride material. For example, the charge trapping layer 150 can comprise a silicon nitride material. In some embodiments, the charge barrier layer 160 comprises an oxide material. For example, the charge barrier layer 160 can comprise SiO 2 . Further details regarding the formation of the device 100 will now be described in more detail below with reference to Figures 2 - 3G .

[0031] Figure 2 FIG. 200 is a diagram of an exemplary deposition process according to some embodiments, which can be used to form at least a portion of a 3D memory device. In some embodiments, the deposition process comprises an ALD process. There are various types of ALD processes, and a particular type can be selected based on several factors, such as the surface to be coated, the coating material, the chemical interaction between the surface and the coating material, etc. The general principle of various ALD methods involves growing a thin film layer by repeatedly exposing the surface to be coated to consecutive alternating pulses of gaseous chemical precursors and reactants, and the gaseous chemical precursors and reactants react with the surface one at a time in a self-limiting manner.

[0032] Figure 2 An article 210 having a surface 205 is shown. The article 210 may represent a partially formed memory cell of a 3D NAND device. In an embodiment, the article 210 and the surface 205 may include a barrier layer (not shown) that has been formed thereon. Each individual chemical reaction between a precursor or reactant and the surface is referred to as a "half reaction". In each half reaction process, the precursor or reactant is pulsed onto the surface for a period of time sufficient for the precursor to fully react with the surface. The reaction is self-limiting because the precursor will only react with a limited number of available reaction sites on the surface, forming a uniform and continuous adsorption layer on the surface. Any location that has reacted with the precursor will become unavailable for further reaction with the same precursor unless and / or until the reaction sites are treated, which will create new reaction sites on the uniform and continuous coating. Exemplary treatments may be plasma treatment, treatment by exposing the uniform and continuous adsorption layer to free radicals, or introducing a different precursor capable of reacting with the most recent uniform and continuous film layer adsorbed on the surface.

[0033] In Figure 2 , the article 210 having the surface 205 may be introduced to a first precursor 260 for a first duration until a first half reaction of the first precursor 260 with the surface 205 partially forms a layer 215 by forming an adsorption layer 214. Thereafter, the article 210 may be introduced to a second precursor 265 (also referred to as a reactant) to cause a second half reaction to react with the adsorption layer 214 and fully form the layer 215. For example, the first precursor 260 may be a precursor of molybdenum. For example, the second precursor 265 may be a hydrogen precursor or reactant. The article 210 may be alternately exposed to the first precursor 260 and the second precursor 265 up to x times to achieve a target thickness of the layer 215. For example, x may be an integer from 1 to 100.

[0034] Depending on the type of ALD process, the ALD process may be performed at different temperatures. The optimal temperature range for a particular ALD process is referred to as the "ALD temperature window". Temperatures below the ALD temperature window may result in poor growth rates and non-ALD type depositions. Temperatures above the ALD temperature window may result in thermal decomposition of the article or rapid desorption of the precursor. The range of the ALD temperature window may be from about 20°C to about 600°C. In some embodiments, the ALD temperature window is between about 150 - 350°C.

[0035] ALD processes allow for conformal film layers with uniform film thickness on articles and surfaces with complex geometries, high aspect ratio holes, and three-dimensional structures. Sufficient exposure time of the precursor to the surface enables the precursor to disperse and react fully with the entire surface, including all its three-dimensional complex features. The exposure time for obtaining conformal ALD in high aspect ratio structures is proportional to the square of the aspect ratio and can be predicted using modeling techniques. Additionally, the ALD technique is superior to other commonly used coating techniques as it allows for in-situ on-demand material synthesis of specific compositions or formulations without the long and difficult fabrication of source materials (such as powder feedstocks and sintered targets).

[0036] Figures 3A - 3G is a diagram of an exemplary process flow for forming at least a portion of a 3D memory device according to some embodiments. Figure 3A Illustrates a schematic diagram 300A of an initial structure 305. The initial structure 305 includes a stack of alternating dielectric layers, which includes dielectric layers 310-1 to 310-3 formed of a first material and dielectric layers 320-1 to 320-2 formed of a second material different from the first material. Although three dielectric layers 310-1 to 310-3 and two dielectric layers 320-1 to 320-2 are shown, the initial structure 305 may include any suitable number of dielectric layers. In some embodiments, the first material includes an oxide material and the second material includes a nitride material. For example, the first material includes silicon oxide (e.g., SiO 2 ), and the second material includes silicon nitride (e.g., Si 3 N 4 ).

[0037] The initial structure 305 further includes a stack of channels 330 disposed within the stack of dielectric layers. For example, the stack of channels 330 may include a channel layer 332, a tunnel layer 334, a charge trapping layer 336, a channel layer 338, and a dielectric layer (e.g., silicon oxide) layer 339. The channel layer 332 may be similar to Figure 1 the channel layer 130 of, the tunnel layer 334 may be similar to Figure 1 the tunnel layer 140 of, the charge trapping layer 336 may be similar to Figure 1 the charge trapping layer 150 of, and the charge barrier layer 338 may be similar to Figure 1 the charge barrier layer 160 of.

[0038] Figure 3B Illustrates a diagram 300B showing an etching process being performed to form an opening 340 within the initial structure 305 to form an intermediate structure 345. The opening 340 is formed to expose the dielectric layers 320-1 and 320-2, and will subsequently be as described below with reference to Figure 3CThe dielectric layers 320-1 and 320-2 are removed. In some embodiments, the opening 340 is a slit, and the etching process is a slit etching process. According to the embodiments described herein, any suitable etching process can be used to form the opening 340. In some embodiments, the etching process is a dry etching process. For example, the etching process can be a reactive-ion etch (RIE) process.

[0039] Figure 3C FIG. 300C illustrates a diagram showing the removal of the dielectric layers 320-1 and 320-2 to form an intermediate structure 350 (also referred to as a substrate structure). The dielectric layers 320-1 and 320-2 can be removed using any suitable process. In some embodiments, the dielectric layers 320-1 and 320-2 are removed using an etching process that can selectively etch a second material relative to a first material (e.g., a selective etching process). For example, the etching process can be a wet etching process using a suitable wet etchant.

[0040] Figure 3D FIG. 300D illustrates a diagram showing the formation of a barrier layer 360 conformal to the exposed surface of the substrate structure 350 to form an intermediate structure 365. The barrier layer 360 can be similar to Figure 1 the barrier layer 120. The barrier layer 360 can be formed using any suitable deposition process. In some embodiments, the barrier layer 360 is formed using an ALD process. The barrier layer 360 can be formed to have any suitable thickness. In some embodiments, the thickness of the barrier layer 360 ranges from about 1 nanometer to about 5 nanometers. In some embodiments, the thickness of the barrier layer 360 ranges from about 2 nanometers to about 3 nanometers.

[0041] Figure 3E FIG. 300E illustrates a diagram showing the formation of a nucleation layer 370 conformal to the barrier layer 360 of the intermediate structure 365 to form an intermediate structure 375. The nucleation layer 370 can be similar to Figure 1 the nucleation layer 170. The nucleation layer 370 can be formed using any suitable deposition process. In some embodiments, the nucleation layer 370 is formed using an ALD process. The nucleation layer 370 can be formed to have any suitable thickness. In some embodiments, the thickness of the nucleation layer 370 ranges from about 0.25 nanometer to about 5 nanometers. In some embodiments, the thickness of the nucleation layer 370 ranges from about 0.5 nanometer to about 3 nanometers.

[0042] Figure 3FFIG. 300F shows the formation of word line material 380 within a gap (e.g., a lateral gap) of an intermediate structure 375 to form an intermediate structure 385. In some embodiments, the word line material 380 includes Mo. The word line material 380 can be formed using any suitable deposition process. In some embodiments, the word line material 380 is formed using an ALD process. The word line material 380 can be formed to have any suitable thickness. In some embodiments, the thickness of the word line material 380 ranges from about 5 nanometers to about 30 nanometers. The thickness of the word line material 380 can be no more than Figure 3B the thickness of the opening 340. In some embodiments, the word line material 380 does not completely fill the lateral gap and leaves a seam or void within the lateral gap. In some embodiments, the word line material 380 completely fills the lateral gap without forming a seam or void. In some embodiments, steps of the process flow as Figures 3E - 3F shown (e.g., the formation of the nucleation layer 370 and the formation of the word line material 380) can be performed without breaking vacuum.

[0043] Figure 3G FIG. 300G shows the formation of word line 390 to form structure 395. More specifically, the word line 390 can be formed by recessing or etching back the word line material 380. The word line 390 can be formed using any suitable process. In some embodiments, the word line 390 is formed using an isotropic etching process. For example, the isotropic etching process can be a dry etching process or a wet etching process. More details regarding the process flow as Figures 3A - 3G shown are described above with reference to Figures 1 - 2 and will be described in further detail below with reference to FIGS. 7-8.

[0044] Figure 4 FIG. 400 is a graph showing the difference in threshold voltage (Vth) shift in volts (V) after 1000 programmed / erased (P / E) cycles for various combinations of word line materials and barrier layer materials. As shown, compared to word lines formed of Mo and barrier layer word lines including Al 2 O 3 , word lines formed of Mo and barrier layer word lines including high-k dielectric materials (e.g., ZrO 2 , AlZrO 2 , and LaAlO 3 ) exhibit improved Vt shift after 1000 P / E cycles.

[0045] Figure 5FIG. 500 is a graph showing leakage current in amperes (A) as a function of equivalent oxide thickness (EOT) in nanometers (nm) for various combinations of word line materials and barrier layer materials. The EOT may refer to the thickness of a silicon dioxide (SiO 2 ) layer that would provide the same electrical properties as the electrical properties of a high-k dielectric material used to form a barrier layer (e.g., Figure 1 barrier layer 120).

[0046] Figure 6 FIG. 600 is a diagram showing an example portion of a 3D memory device according to some embodiments. The 3D memory device may include a plurality of components, including a word line (WL) 610, a blocking layer (BL) 620, a charge blocking layer (CBL) 630, a charge trap layer (CTL) 640, a tunnel layer (TL) 650, and a channel layer (CH) 650. More specifically, the word line 610 may include Mo, and the blocking layer 620 may include the high-k dielectric material as described above. This shows electron energy (eV) and distance in nanometers (nm) relative to the components of the 3D memory device. The arrow with an “X” through it indicates that electron tunneling from the word line 610 to the charge trap layer 640 can be reduced due to the combination of the word line 610 including Mo and the blocking layer 420 including the high-k dielectric material, which can improve erase performance.

[0047] Figure 7A FIG. 700 is a flow chart of a method for manufacturing a three-dimensional (3D) word line with reduced barrier layer damage according to some embodiments. At block 710, a substrate structure of a 3D memory device is obtained. The substrate structure may include a plurality of components. In some embodiments, the substrate structure includes a channel layer, a tunnel layer, a charge trap layer, and a charge blocking layer. In some embodiments, obtaining the substrate structure includes forming at least one component of the substrate structure. For example, obtaining the substrate structure may include forming at least one of a channel layer, a tunnel layer, a charge trap layer, or a charge blocking layer. Further details regarding obtaining the substrate structure are described above with reference to Figure 1 and Figures 3A - 3C and will be described in further detail below with reference to Figure 7B .

[0048] At block 720, a barrier layer is formed on the substrate structure. In some embodiments, the barrier layer is formed directly on the substrate structure. For example, the barrier layer can be a conformal layer. The barrier layer can be formed of a high-k dielectric material that resists damage from the chemicals (e.g., ALD chemicals) used to form at least one word line. In some embodiments, the barrier layer is formed of a high-k dielectric material that resists damage from the chemicals used to form Mo. Further details regarding the formation of the barrier layer are described above with reference to Figure 1 and Figure 3D and will be described in more detail below with reference to Figure 7C

[0049] Figure 1 At block 730, at least one word line for a 3D memory device is formed on the barrier layer. In some embodiments, the at least one word line includes replacement word lines. In some embodiments, the at least one word line is formed of Mo. Further details regarding the formation of at least one word line on the barrier layer are described above with reference to Figure 1 and Figure 3D and will be described in more detail below with reference to Figure 7D

[0050] Figure 7B is a flow chart of a method 710 for obtaining a substrate structure for a 3D memory device according to some embodiments. At block 712, an initial structure of a 3D memory device including an alternating dielectric stack and a channel stack is obtained. More specifically, the stack of alternating dielectric layers can include at least one first dielectric layer formed of a first material and at least one second dielectric layer formed of a second material different from the first material. In some embodiments, the first material includes an oxide material and the second material includes a nitride material. For example, the first material includes silicon oxide (e.g., SiO 2 ) and the second material includes silicon nitride (e.g., Si 3 N 4 ). The channel stack can include a channel layer, a tunnel layer, a charge trapping layer, and a channel layer.

[0051] At block 714, an opening is formed within the stack of alternating dielectric layers to obtain an intermediate structure. Forming the opening can include performing an etching process. The opening is formed to expose at least one second dielectric layer within the stack of alternating dielectric layers. In some embodiments, the opening is a slit and the etching process is a slit etching process. Any suitable etching process can be used to form the opening according to the embodiments described herein. In some embodiments, the etching process is a dry etching process. For example, the etching process can be an RIE process.

[0052] At block 716, the base structure of the 3D memory device is formed from an intermediate structure. Forming the base structure can include removing at least one second dielectric layer. Any suitable process can be used to remove the at least one second dielectric layer. In some embodiments, an etching process that can selectively etch a second material relative to a first material (e.g., a selective etching process) is used to remove the at least one second dielectric layer. For example, the etching process can be a wet etching process using a suitable wet etchant. Further details regarding blocks 712 - 716 are described above with reference to Figure 1 , Figures 3A - 3C and Figure 7A .

[0053] Figure 7C is a flow chart of a method 720 for forming a barrier layer on a base structure of a 3D memory device according to some embodiments. At block 722, a base structure of the 3D memory device is obtained. For example, the base structure can be the base structure obtained at block 710 of Figure 7A . (For example, Figure 7B blocks 710 - 716 of

[0054] ). At block 724, a barrier layer conformal to the exposed surface of the base structure of the 3D memory device is formed. Any suitable deposition process can be used to form the barrier layer. In some embodiments, an ALD process is used to form the barrier layer. The barrier layer can be formed to have any suitable thickness. In some embodiments, the thickness of the barrier layer ranges from about 1 nanometer to about 5 nanometers. In some embodiments, the thickness of the barrier layer ranges from about 2 nanometers to about 3 nanometers.

[0055] The barrier layer can be formed from a high-k dielectric material that resists damage to the ALD chemistry used to form the word line material, which is used to form the word lines of the 3D memory device. In some embodiments, the word line material includes Mo. The barrier layer can include a high-k dielectric material having a dielectric constant greater than that of Al 2 O 3 . More specifically, the barrier layer can include a high-k dielectric material having a dielectric constant greater than about 7.8. For example, the barrier layer can include a high-k dielectric material having a dielectric constant greater than or equal to about 10. In some embodiments, the barrier layer includes zirconia. Examples of zirconia materials include ZrO 2 , A1ZrO 2 , doped ZrO 2 , etc. In some embodiments, the barrier layer includes lanthanum oxide. One example of lanthanum oxide is LaAlO 3 . In some embodiments, the barrier layer includes hafnium oxide. Examples of hafnium oxide include HfO 2 , doped HfO 2 , etc. In some embodiments, the barrier layer includes Y2 O 3 . In some embodiments, the barrier layer comprises doped Al 2 O 3 (i.e., Al doped with a high-k material sufficient to increase the dielectric constant of the doped Al 2 O 3 material to above about 7.8). Further details regarding blocks 722 - 724 are described above with reference to 2 O 3 ). Figure 1 , Figures 3A - 3D and Figure 7A .

[0056] Figure 7D is a flow chart of a method 730 for forming at least one word line on a barrier layer according to some embodiments. For example, the barrier layer can be the barrier layer formed in block 720 of Figure 7A (e.g., blocks 722 - 724 of Figure 7C ).

[0057] In block 732, a nucleation layer is formed on the barrier layer. More specifically, the nucleation layer can be formed conformal to the barrier layer. In block 734, the nucleation layer can be used to facilitate the formation of the word line material. Any suitable deposition process can be used to form the nucleation layer. In some embodiments, the ALD process is used to form the nucleation layer. The nucleation layer can be formed to have any suitable thickness. In some embodiments, the thickness of the nucleation layer ranges from about 0.25 nanometers to about 5 nanometers. In some embodiments, the thickness of the nucleation layer 370 ranges from about 0.5 nanometers to about 3 nanometers.

[0058] In block 734, the word line material is formed using the nucleation layer. More specifically, the word line material can be formed within the gaps (e.g., lateral gaps). In some embodiments, the word line material comprises Mo. Any suitable deposition process can be used to form the word line material. In some embodiments, the ALD process is used to form the word line material. More specifically, forming the word line material can include depositing Mo using a suitable ALD chemistry (e.g., MoO 2 Cl 2 or MoCl 5 precursor and H 2 reactant) ALD process. The word line material can be formed to have any suitable thickness. In some embodiments, the thickness of the word line material ranges from about 5 nanometers to about 30 nanometers. In some embodiments, openings (e.g., seams or voids) are formed within the word line material to form at least one word line. In some embodiments, the word line material completely fills the gap without forming an opening. In some embodiments, the formation of the nucleation layer at block 732 and the formation of the word line material at block 734 can be performed without breaking the vacuum.

[0059] In block 736, at least one word line is formed from the word line material. More specifically, the at least one word line can be formed by recessing or etching away the word line material. Any suitable process can be used to form the at least one word line. In some embodiments, the at least one word line is formed by using an isotropic etching process. For example, the isotropic etching process can be a dry etching process or a wet etching process. Further details regarding blocks 732-736 are described above with reference to Figure 1 、 Figures 3E - 3G and Figure 7A description.

[0060] To provide a good understanding of some embodiments of the present disclosure, the foregoing description sets forth numerous specific details, such as examples of particular systems, components, methods, etc. However, it will be apparent to those skilled in the art that at least some embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known components or methods have not been described in detail, or are presented in a simple block diagram format to avoid unnecessarily obscuring the present disclosure. Accordingly, the specific details set forth are merely exemplary. Specific embodiments may differ from these exemplary details and still be considered within the scope of the present disclosure.

[0061] References to "one embodiment" or "an embodiment" in this specification mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" throughout this specification are not necessarily all referring to the same embodiment. Additionally, the word "or" is intended to mean an inclusive "or" rather than an exclusive "or". When the term "about" or "approximately" is used herein, this is intended to mean that the stated nominal value is accurate within ±10%.

[0062] Although the operations of the methods herein are shown and described in a particular order, the order of operations of each method can be changed such that certain operations can be performed in the reverse order, or such that certain operations can be performed at least partially concurrently with other operations. In another embodiment, the instructions or sub-operations of different operations can be in an intermittent and / or alternating manner.

[0063] It should be understood that the above description is intended to be illustrative and not restrictive. After reading and understanding the above description, many other embodiments will be apparent to those skilled in the art. Accordingly, the scope of the present disclosure should be determined with reference to the appended claims and the full scope of equivalents to which such claims are entitled.

Claims

1. A method, the method comprises: obtaining a substrate structure of a three-dimensional (3D) memory device; forming a barrier layer including a high-k dielectric material on the substrate structure; and forming a word line for the 3D memory device including molybdenum on the barrier layer using an atomic layer deposition (ALD) process.

2. The method according to claim 1, wherein the barrier layer comprises a high-k dielectric material having a dielectric constant greater than about 7.

8.

3. The method according to claim 2, wherein the barrier layer comprises a high-k dielectric material having a dielectric constant greater than or equal to about 10.

4. The method according to claim 1, wherein the barrier layer comprises: at least one of zirconia, lanthanum oxide, hafnium oxide, yttrium oxide, or doped alumina.

5. The method according to claim 4, wherein the barrier layer comprises at least one of zirconium dioxide, aluminum-zirconium dioxide, or doped zirconium dioxide.

6. The method according to claim 4, wherein the barrier layer comprises lanthanum aluminate.

7. The method according to claim 4, wherein the barrier layer comprises doped hafnium oxide.

8. The method according to claim 1, wherein forming the word line comprises: performing the ALD process using a hydrogen reactant and a molybdenum precursor selected from the group consisting of molybdenum dichloride dioxide and molybdenum pentachloride.

9. The method according to claim 1, wherein forming the word line comprises: forming a nucleation layer or a seed layer on the barrier layer by exposing the barrier layer to a precursor.

10. The method according to claim 9, wherein the nucleation layer or the seed layer comprises: at least one of molybdenum silicide, molybdenum silicon oxide, molybdenum nitride, titanium nitride, titanium silicon nitride, tantalum nitride, or tantalum silicon nitride.

11. The method according to claim 1, wherein the high-k dielectric layer resists damage from the ALD chemicals of the molybdenum used to form the word line.

12. A three-dimensional (3D) memory device, the three-dimensional (3D) memory device comprises: a barrier layer; and a word line including molybdenum disposed on the barrier layer, wherein the barrier layer comprises a high-k dielectric material that resists damage from the atomic layer deposition (ALD) chemicals of the molybdenum used to form the word line.

13. The 3D memory device according to claim 12, wherein the barrier layer comprises a high-k dielectric material having a dielectric constant greater than about 7.

8.

14. The 3D memory device according to claim 12, wherein the barrier layer comprises a high-k dielectric material having a dielectric constant greater than or equal to about 10.

15. The 3D memory device according to claim 12, wherein the barrier layer comprises: at least one of zirconia, lanthanum oxide, hafnium oxide, yttrium oxide, or doped alumina.

16. The 3D memory device according to claim 15, wherein the barrier layer comprises: at least one of zirconium dioxide, aluminum-zirconium dioxide, or doped zirconium dioxide.

17. The 3D memory device according to claim 15, wherein the barrier layer comprises lanthanum aluminate.

18. The 3D memory device according to claim 15, wherein the barrier layer comprises doped hafnium oxide.

19. The 3D memory device according to claim 12, wherein the 3D memory device further includes a nucleation layer or a seed layer disposed between the barrier layer and the word line.

20. The 3D memory device according to claim 19, wherein the nucleation layer or the seed layer comprises: at least one of molybdenum silicide, molybdenum silicon oxide, molybdenum nitride, titanium nitride, titanium silicon nitride, tantalum nitride, or tantalum silicon nitride.

Images