Method for manufacturing silicon carbide semiconductor device

Abstract

A method for manufacturing a silicon carbide semiconductor device having a switching element formed on a semiconductor substrate (11) comprising silicon carbide and configured with a built-in diode. The method comprises the following steps: measuring the density of basal plane dislocation, namely BPD density, in a semiconductor substrate; when a semiconductor chip (10) having a switching element is assumed to be manufactured, the initial electrical characteristic of the switching element immediately after the semiconductor chip is manufactured is set as an initial value, and the amount of change in the electrical characteristic with respect to the initial value after the switching element is driven for a time equal to or greater than a predetermined value is set as an energization amount of change. Predicting an energization variation amount on the basis of at least the BPD density; and determining whether to use the semiconductor substrate to continue manufacturing the silicon carbide semiconductor device on the basis of the predicted energization variation amount.

Description

[0001] Cross-reference to related applications

[0002] This application is based on Japanese Patent Application No. 2022-199525 filed on December 14, 2022, the contents of which are incorporated herein by reference. Technical field

[0003] The present disclosure relates to a method for manufacturing a SiC semiconductor device using silicon carbide (hereinafter also referred to as "SiC"). Background art

[0004] Conventionally, as a SiC semiconductor device made of SiC, for example, a SiC semiconductor device having a MOSFET formed thereon has been proposed. In addition, MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. Specifically, such a SiC semiconductor device, for example, has an n + -type buffer layer with an impurity concentration lower than that of the SiC substrate formed on an n - -type SiC substrate, and an n - -type drift layer with an impurity concentration lower than that of the buffer layer formed on the buffer layer. A p-type base layer is disposed on the drift layer. In addition, the buffer layer and the drift layer are composed of an epitaxial layer. An n + -type source region is formed on the surface portion of the base layer. And, a plurality of trenches are formed so as to penetrate the source region and the base layer and reach the drift layer, and a gate insulating film and a gate electrode are sequentially formed in each trench. Thus, a trench-gate structure MOSFET is formed.

[0005] Moreover, the SiC semiconductor device as described above constitutes an internal diode through a pn junction between the base layer and the drift layer.

[0006] In addition, in such a SiC semiconductor device, sometimes basal plane dislocations (hereinafter referred to as "BPD") exist in the SiC substrate. In addition, BPD is an abbreviation for Basal plane dislocation. Moreover, it is known that in such a SiC semiconductor device, through the driving of the internal diode, defects expand in the epitaxial layer starting from BPD, and the amount of current during energization decreases. Hereinafter, for the sake of convenience of explanation, the amount of change in the electrical characteristics of the internal diode after the defect expansion caused by BPD with respect to the initial value of the electrical characteristics of the internal diode at the time of manufacturing the SiC semiconductor device is simply referred to as the "energization change amount".

[0007] In recent years, SiC semiconductor devices that suppress such a current fluctuation amount have been demanded. Therefore, the following method has been proposed: based on the BPD density of the SiC substrate, it is determined whether a composite layer for suppressing the current fluctuation amount should be provided during the formation of the epitaxial layer, and the device structure of the SiC semiconductor device is determined (for example, Patent Document 1).

[0008] Prior Art Documents

[0009] Patent Documents

[0010] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2022-77807 Summary of the Invention

[0011] However, in the formation of the epitaxial layer, if the formation process of the composite layer with an impurity concentration higher than that of the SiC substrate is increased, although an SiC semiconductor device with suppressed current fluctuation amount can be provided, its manufacturing cost increases. And, in order to reduce the manufacturing cost, it is desired to determine whether to continue the manufacturing of the SiC semiconductor device based on the predicted current fluctuation amount during the manufacturing process, or to classify the SiC chips formed with MOSFETs according to the required performance.

[0012] The present disclosure relates to a method for manufacturing an SiC semiconductor device in which the current fluctuation amount is suppressed by predicting the current fluctuation amount and reflecting the predicted current fluctuation amount in the manufacturing process.

[0013] According to one aspect of the present disclosure, a method for manufacturing a silicon carbide semiconductor device, the silicon carbide semiconductor device having a switching element formed on a semiconductor substrate made of silicon carbide and having a built-in diode, the manufacturing method including the following steps: measuring the density of basal plane dislocations in the semiconductor substrate, i.e., the BPD density; assuming that a semiconductor chip having a switching element is manufactured, setting the initial electrical characteristics of the switching element immediately after the semiconductor chip is manufactured as an initial value, and setting the change amount of the electrical characteristics after driving the switching element for a time equal to or longer than a specified value with respect to the initial value as the current fluctuation amount, and predicting the current fluctuation amount based on at least the BPD density; and based on the predicted current fluctuation amount, determining whether to continue the manufacturing of the silicon carbide semiconductor device using the semiconductor substrate.

[0014] Thereby, based on at least the BPD density of the semiconductor substrate, the current fluctuation amount of the semiconductor chip is predicted in the case where it is assumed that a semiconductor chip having a switching element is manufactured using the semiconductor substrate made of SiC. And, based on the predicted current fluctuation amount, it is determined whether to continue the manufacturing of the SiC semiconductor device using the semiconductor substrate, whereby an SiC semiconductor device with suppressed current fluctuation amount can be efficiently manufactured.

[0015] In addition, the reference numerals in parentheses added to each component element etc. represent an example of the correspondence relationship between the component element etc. and the specific component element etc. described in the embodiments described later. Description of the Drawings

[0016] Figure 1 is a perspective cross-sectional view showing a structural example of a SiC semiconductor device.

[0017] Figure 2 is a cross-sectional view showing a cell portion of a semiconductor chip made of SiC.

[0018] Figure 3 is Figure 2 an explanatory diagram of the current path in the semiconductor chip.

[0019] Figure 4 is an explanatory diagram of the growth of defects due to BPD.

[0020] Figure 5 is a flowchart showing a part of the manufacturing process of the SiC semiconductor device of the embodiment.

[0021] Figure 6 is a graph showing the relationship between the BPD density of a SiC semiconductor substrate and the change amount of V of the MOSFET of a semiconductor chip manufactured using the SiC semiconductor substrate ON thereof.

[0022] Figure 7 is a graph showing the result of observing strip-shaped defects and triangular defects growing from BPD by PL imaging method.

[0023] Figure 8A is a graph showing an example of the distribution of the BPD density in a SiC semiconductor substrate.

[0024] Figure 8B is a graph showing another example of the distribution of the BPD density in a SiC semiconductor substrate.

[0025] Figure 9 is showing then Figure 5 a flowchart of the manufacturing process of the SiC semiconductor device.

[0026] Figure 10 is a graph showing an example of the deviation of the initial electrical characteristics of a semiconductor chip.

[0027] Figure 11 is equivalent to Figure 2 a cross-sectional view showing a configuration example of a SiC semiconductor device of another embodiment. Detailed Description of the Invention

[0028] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In addition, in the following embodiments, the same or equivalent parts are denoted by the same reference numerals for description.

[0029] (First Embodiment)

[0030] The first embodiment will be described with reference to the accompanying drawings. In addition, in the present embodiment, for example, as Figure 1 shown, a SiC semiconductor device of a semiconductor chip 10 using an inversion-type MOSFET having a trench gate structure formed as a switching element is taken as a representative example for description. In addition, although not particularly illustrated, the semiconductor chip 10 has a cell region and an outer peripheral region formed so as to surround the cell region. And, Figure 1 the MOSFET shown is formed in the cell region of the semiconductor chip 10.

[0031] In addition, for ease of explanation, as Figure 1 shown, one direction in the plane direction of the semiconductor substrate 11 to be described later is referred to as the "X-axis direction", the direction orthogonal to the X-axis direction in the plane direction is referred to as the "Y-axis direction", and the direction orthogonal to the plane direction, that is, orthogonal to the XY plane is referred to as the "Z-axis direction".

[0032] 〔SiC Semiconductor Device〕

[0033] The SiC semiconductor device is configured using the semiconductor chip 10. Specifically, the semiconductor chip 10 includes, for example, an n + -type semiconductor substrate 11 made of SiC. As the semiconductor substrate 11, for example, a SiC substrate having an off angle of 0° to 8° with respect to the (0001) Si plane and an n-type impurity concentration of nitrogen, phosphorus, etc. of 1.0×10 19 / cm 3 and a thickness of about 300 μm is used, but it is not limited thereto. The semiconductor substrate 11 constitutes a drain region, for example.

[0034] On the surface of the semiconductor substrate 11, an n - -type buffer layer 12 made of SiC is formed, for example. The buffer layer 12 is formed by epitaxial growth on the surface of the semiconductor substrate 11. Regarding the buffer layer 12, for example, the n-type impurity concentration is the impurity concentration between the semiconductor substrate 11 and the low-concentration layer 13 to be described later, and the thickness is about 1 μm.

[0035] On the surface of the buffer layer 12, an n-type impurity concentration of 5.0 to 10.0×10 15 / cm 3 and a thickness of about 10 to 15 μm of an n -a low-concentration layer 13 of a type. Regarding the low-concentration layer 13, for example, the impurity concentration may be fixed in the Z-axis direction, but preferably, the concentration distribution has an inclination, and the concentration on the semiconductor substrate 11 side in the low-concentration layer 13 is higher than that on the side away from the semiconductor substrate 11. For example, regarding the low-concentration layer 13, preferably, the impurity concentration of a portion about 3 to 5 μm from the surface of the semiconductor substrate 11 is 2.0×10 15 / cm 3 or so. By adopting such a structure, the internal resistance of the low-concentration layer 13 can be reduced, and the on-resistance can be reduced. In addition, the low-concentration layer 13 is composed of an epitaxial layer based on epitaxial growth.

[0036] In the surface layer portion of the low-concentration layer 13, for example, at the connection portion of the cell portion and the peripheral portion (not shown), a JFET portion 14 and a first deep layer 15 are formed. The JFET portion 14 and the first deep layer 15, for example, have linear portions that are respectively arranged along the X-axis direction and alternately repeated in the Y-axis direction. That is, the JFET portion 14 and the first deep layer 15 are configured such that, in the normal direction with respect to the surface of the semiconductor substrate 11, they are respectively strip-shaped extending along the X-axis direction, and they are arranged alternately along the Y-axis direction. Hereinafter, for the sake of simplicity of description, the normal direction with respect to the surface of the semiconductor substrate 11 is also simply referred to as the "normal direction".

[0037] The JFET portion 14 is, for example, an n-type with an impurity concentration higher than that of the low-concentration layer 13, and the depth is 0.3 to 1.5 μm. The JFET portion 14, for example, has an n-type impurity concentration of 7.0×10 16 to 5.0×10 17 / cm 3 . The JFET portion 14 is, for example, formed as an ion implantation layer by ion-implanting n-type impurities into the low-concentration layer 13.

[0038] Regarding the first deep layer 15, for example, the p-type impurity concentration of boron or the like is 2.0×10 17 to 2.0×10 18 / cm 3 . The first deep layer 15, for example, extends to the guard ring side of the peripheral portion (not shown) farther than the JFET portion 14. For example, the first deep layer 15 is formed shallower than the JFET portion 14. That is, the first deep layer 15 is formed such that the bottom is located within the JFET portion 14, that is, the JFET portion 14 is located between the first deep layer 15 and the low-concentration layer 13. For example, the width of the first deep layer 15 in the Y-axis direction is 0.9 μm or less. Regarding the first deep layer 15, for example, the distance between adjacent first deep layers 15 in the Y-axis direction is 0.75 to 1.1 μm.

[0039] On the surface portion of the low-concentration layer 13, for example, on the outer peripheral portion (not shown), a plurality of p-type protection rings (not shown) are provided so as to surround the unit portion. For example, the protection ring (not shown) has a shape such as a quadrilateral with rounded corners or a circle when viewed from the normal direction.

[0040] On the JFET portion 14 and the first deep layer 15 in the unit portion, for example, a current dispersion layer 16 and a second deep layer 17 are formed.

[0041] The current dispersion layer 16 is constituted by, for example, an n-type impurity layer and has a thickness of 0.5 to 2 μm. The n-type impurity concentration of the current dispersion layer 16 is, for example, 1.0×10 16 ~5.0×10 17 / cm 3 . The current dispersion layer 16 is connected to the JFET portion 14. Therefore, the low-concentration layer 13, the JFET portion 14, and the current dispersion layer 16 are connected, and they constitute a drift layer 18.

[0042] The second deep layer 17 is formed in the unit portion. For example, the p-type impurity concentration is 2.0×10 17 ~2.0×10 18 / cm 3 , and the thickness is equal to that of the current dispersion layer 16. The second deep layer 17 is formed so as to be connected to the first deep layer 15.

[0043] The current dispersion layer 16 and the second deep layer 17 are extended and provided in a direction intersecting with the strip-shaped portion in the JFET portion 14 and the length direction of the first deep layer 15. In the present embodiment, the current dispersion layer 16 and the second deep layer 17 are provided so as to extend in the Y-axis direction as the length direction and a plurality of them are alternately arranged in the X-axis direction. In addition, the formation pitch of the current dispersion layer 16 and the second deep layer 17 corresponds to, for example, the formation pitch of the trench gate structure described later, and the second deep layer 17 is formed so as to sandwich the trench 22 described later.

[0044] A p-type base layer 19 is formed on the current dispersion layer 16 and the second deep layer 17. Moreover, an n + -type source region 20 and a p + -type contact region 21 are formed on the surface portion of the base layer 19 in the unit portion. The source region 20 is formed so as to be in contact with the side surface of the trench 22 described later, and the contact region 21 is formed on the side opposite to the trench 22 with the source region 20 interposed therebetween. In addition, the source region 20 corresponds to an impurity region.

[0045] The base layer 19 has, for example, a p-type impurity concentration of 3.0×10 17 / cm 3As follows. The base layer 19 is formed, for example, by ion implantation or the like, and the impurity concentration in the cell portion is higher than that in the peripheral portion (not shown). The n-type impurity concentration in the surface layer portion of the source region 20, that is, the surface concentration is, for example, 1.0×10 21 / cm 3 . The p-type impurity concentration in the surface layer portion of the contact region 21, that is, the surface concentration is, for example, 1.0×10 21 / cm 3 .

[0046] The base layer 19 and the source region 20 are adjusted in thickness, for example, so that the channel length is 0.4 μm or less. In addition, the channel length refers to the length of the portion along the side surface of the trench 22 in the base layer 19 in the Z-axis direction.

[0047] For example, as described above, the semiconductor chip 10 has a structure in which a semiconductor substrate 11, a buffer layer 12, a low-concentration layer 13, a JFET portion 14, a first deep layer 15, a current dispersion layer 16, a second deep layer 17, a base layer 19, a source region 20, a contact region 21, etc. are stacked. Hereinafter, for the sake of convenience of explanation, in the semiconductor chip 10, the surface on the source region 20 and contact region 21 side is referred to as the "one surface 10a" of the semiconductor chip 10, and the surface on the semiconductor substrate 11 side is referred to as the "other surface 10b" of the semiconductor chip 10. The source region 20 and the contact region 21 are in a state of being exposed from the one surface 10a of the semiconductor chip 10.

[0048] In the cell portion, the semiconductor chip 10 is formed, for example, with a plurality of trenches 22 having a width of 1.4 to 2.0 μm so as to penetrate the base layer 19 and reach the current dispersion layer 16 and the bottom surface is located within the current dispersion layer 16. The trench 22 is formed such that the depth does not reach the JFET portion 14 and the first deep layer 15, and the JFET portion 14 and the first deep layer 15 are located below the bottom surface of the trench 22.

[0049] The trenches 22 extend, for example, along the Y-axis direction and a plurality of trenches are formed and arranged at equal intervals in the X-axis direction to form a strip shape. That is, the trenches 22 are formed such that the length direction is orthogonal to the length direction of the first deep layer 15. The trenches 22 are formed such that they are sandwiched by the second deep layer 17 in the normal direction. And the trenches 22 are formed such that the distance between the centers of adjacent trenches 22, that is, the trench pitch, is 3.0 μm or less.

[0050] The trench 22 is filled, for example, with a gate insulating film 23 formed on the inner wall surface and a gate electrode 24 made of doped polycrystalline silicon (Poly-Si) formed on the surface of the gate insulating film 23. Thus, a trench gate structure is formed. Although not particularly limited, the gate insulating film 23 is formed, for example, by thermally oxidizing the inner wall surface of the trench 22 or by film formation using CVD. CVD is an abbreviation for chemical vapor deposition. For example, the thickness of the gate insulating film 23 is about 100 nm on both the side surface and the bottom surface sides of the trench 22.

[0051] The gate insulating film 23 is also formed on the surface other than the inner wall surface of the trench 22. Specifically, the gate insulating film 23 is formed, for example, so as to also cover a part of the surface of the source region 20 in one surface 10a of the semiconductor chip 10. In other words, the gate insulating film 23 is formed with contact holes 23a that expose the contact region 21 and the remaining part of the source region 20 in a part different from the part where the gate electrode 24 is disposed.

[0052] The gate insulating film 23 is also formed on the surface of the base layer 19 in the unillustrated outer peripheral portion. The gate electrode 24 also extends, in the same manner as the gate insulating film 23, onto the surface of the gate insulating film 23 in the unillustrated outer peripheral portion. The trench gate structure of the present embodiment is configured as described above.

[0053] The semiconductor chip 10 is formed, for example, with a mesa structure in an unillustrated outer peripheral portion, and this mesa structure is a structure in which a recess is formed so as to penetrate the base layer 19 and reach the current dispersion layer 16. And, in a region adjacent to the unit portion in the unillustrated outer peripheral portion, contact regions 21 are formed in the surface layer portion of the base layer 19 in the same manner as the unit portion.

[0054] An interlayer insulating film 25 is formed on one surface 10a of the semiconductor chip 10 so as to cover the gate electrode 24, the gate insulating film 23, etc. The interlayer insulating film 25 is made of, for example, BPSG or the like. BPSG is an abbreviation for Borophosphosilicate Glass.

[0055] An interlayer insulating film 25 is formed with a contact hole 25a that communicates with the contact hole 23a to expose the source region 20 and the contact region 21. The contact hole 25a formed in the interlayer insulating film 25 is formed in a manner that communicates with the contact hole 23a formed in the gate insulating film 23, and functions as a single contact hole together with the contact hole 23a. Hereinafter, the contact hole 23a and the contact hole 25a are also collectively referred to as "contact hole 23b". The pattern of the contact hole 23b is arbitrary, and examples thereof include a pattern in which a plurality of square contact holes are arranged, a pattern in which rectangular linear contact holes are arranged, or a pattern in which linear contact holes are arranged. The contact hole 23b is, for example, linear along the length direction of the trench 22.

[0056] A source electrode 26 is formed on the interlayer insulating film 25 and is electrically connected to the source region 20 and the contact region 21 via the contact hole 23b. The source electrode 26 is also connected to the contact region 21 of the base layer 19 formed in an outer peripheral portion (not shown). In addition, an unillustrated gate wiring is formed on the interlayer insulating film 25 and is electrically connected to the gate electrode 24 via the contact hole 23b.

[0057] The source electrode 26 is composed of, for example, multiple metals such as Ni / Al. The portion of the multiple metals that contacts the n-type SiC, that is, the portion constituting the source region 20, is composed of a metal capable of making an ohmic contact with the n-type SiC. In addition, at least the portion of the multiple metals that contacts the p-type SiC, that is, the contact region 21, is composed of a metal capable of making an ohmic contact with the p-type SiC.

[0058] On the other side 10b side of the semiconductor chip 10, a drain electrode 27 is formed and is electrically connected to the semiconductor substrate 11. The semiconductor chip 10 constitutes, for example, an n-channel type inversion-type trench gate structure MOSFET through the above-described structure. In addition, the semiconductor chip 10 constitutes a built-in diode through the pn junction between the drift layer 18 and the base layer 19 and the like.

[0059] The above is a basic structure example of the semiconductor chip 10 for a SiC semiconductor device. The SiC semiconductor device is used, for example, as a device that constitutes an inverter circuit or the like for driving a three-phase motor or the like using the MOSFET of the semiconductor chip 10, but is not limited to this use, and can of course be applied to other uses.

[0060] 〔Defect growth caused by basal plane dislocations〕

[0061] The SiC semiconductor device, for example, as Figure 2 shown, has a MOSFET with a trench gate structure in the cell portion and a built-in diode BD formed of a pn junction. In addition, in the SiC semiconductor device, for example, BPDs exist in the semiconductor substrate 11, the buffer layer 12, the drift layer, etc., and defects caused by the BPDs may occur.

[0062] As shown Figure 3 in the figure, the SiC semiconductor device has a circuit structure including a MOSFET and a built-in diode BD. When the MOSFET is turned on, a conduction current I flows from the drain electrode 27 to the source electrode 26 ON . In addition Figure 3 the "S", "D", and "G" in the figure respectively correspond to the source electrode 26, the drain electrode 27, and the gate electrode 24. Specifically, when a specified voltage such as 20 V is applied to the gate electrode 24, a channel is formed on the surface of the base layer 19 that is in contact with the trench 22, and a conduction current I flows between the source electrode 26 and the drain electrode 27 ON .

[0063] After that, when the SiC semiconductor device is in the off state, it is applied with a reverse bias and becomes in the reverse conduction state. Therefore, the built-in diode BD functions as a freewheeling diode, and a freewheeling current I flows through the built-in diode OFF . At this time, as shown Figure 4 in the figure, holes diffused from the p-type layer side to the n-type layer side of the pn junction constituting the built-in diode BD recombine with electrons in the n-type layer. Since the recombination energy of these holes and electrons is large, the BPD of the SiC semiconductor device expands and a stacking fault D is generated. Hereinafter, such a stacking fault D will be simply referred to as "defect D". This defect D becomes an obstacle to the conduction current I ON and the freewheeling current I OFF . As described above, since the semiconductor chip 10 generates defect D when driven for a time longer than a specified value, the electrical characteristics after driving are degraded compared to the electrical characteristics in the stage immediately after manufacturing, that is, before the generation of defect D

[0064] In recent years, for SiC semiconductor devices, it has been required to reduce the "power-on variation amount", which is the variation amount of the electrical characteristics after driving for a time longer than a specified value with respect to the initial electrical characteristics of the semiconductor chip 10 before the generation of defect D. In addition, as the electrical characteristics mentioned here, for example, the forward voltage Vf of the built-in diode BD, the voltage V when the MOSFET is turned on, etc. can be cited DS . Since the manufacturing cost of SiC semiconductor devices is higher than that of semiconductor devices mainly composed of Si (silicon), it is important to predict the power-on variation amount in the manufacturing process in order to manufacture SiC semiconductor devices that suppress the increase in manufacturing cost and reduce the power-on variation amount

[0065] 〔Manufacturing method of SiC semiconductor device〕

[0066] Next, a manufacturing method of the SiC semiconductor device according to the present embodiment and prediction of the amount of current change will be described. In addition, regarding the growth of an epitaxial layer made of SiC, the formation of a trench-gate structure MOSFET, etc., they can be achieved by known SiC semiconductor manufacturing processes, and thus their details are omitted in this specification.

[0067] For example, the SiC semiconductor device of the present embodiment is manufactured through Figure 5 the processes shown. In step S110, a plurality of semiconductor substrates 11 are cut out from an ingot made of SiC.

[0068] In the next step S120, for example, for one representative of the plurality of cut semiconductor substrates 11, at least the density of BPD is measured. The density of BPD is obtained, for example, by wet etching the surface of the semiconductor substrate 11 with potassium hydroxide (KOH), confirming the number of depressions, i.e., etch pits, on the etched surface, and calculating the number per unit area. Specifically, for example, the BPD density is obtained by photographing the surface of the semiconductor substrate 11 after KOH etching and analyzing the photographed image using known image analysis techniques.

[0069] In step S130, based at least on the BPD density, prediction of the amount of current change when assuming that a semiconductor chip 10 is manufactured using the semiconductor substrate 11 cut out in step S110 is performed. For example, in step S130, a prescribed calculation formula or a discrimination model composed of a machine learning model is used to predict the amount of current change based at least on the BPD density. Specifically, for example, the BPD density of the semiconductor substrate 11 is measured, and the initial V ON of the MOSFET of the semiconductor chip 10 manufactured using the semiconductor substrate 11 with this BPD density is obtained, and the change amount ΔV ON after driving for a prescribed time is obtained. Data on the ratio of the change amount ΔV ON of the semiconductor chip 10 to the initial V ON is obtained. The relationship between the previously obtained BPD density and the ratio of the change amount ΔV ON of the semiconductor chip 10 to the initial V Figure 6 is as shown, for example. Figure 6 The results shown imply that there is a relationship between the BPD density of the semiconductor substrate 11 and ΔV ON / initial V ONThere is a prescribed correlation therebetween, and it is possible to predict the amount of current variation based on the BPD density. Then, using a discrimination model constructed based on the relational data between the BPD density and the amount of current variation, during the manufacturing of the semiconductor chip 10, the amount of current variation of the semiconductor chip 10 is predicted. As the discrimination model, for example, it is possible to use a calculation formula of multiple regression analysis method that is derived from the above-mentioned relational data obtained in advance and takes the BPD density as at least one variable, or any machine learning model with the relational data as learning data. As the machine learning model, for example, it is possible to use known methods such as support vector machine, neural network, random forest, k-nearest neighbor method, etc.

[0070] In addition, the discrimination model is, for example, stored in a recording medium of an electronic control unit in which various electronic components such as ROM, RAM, and I / O are mounted on a circuit board (not shown), and is read from the recording medium and executed as needed. In addition, regarding the driving conditions such as the prescribed current application time, voltage, temperature, etc. in the data of the amount of current variation (for example, ΔV ON / Initial V ON ) that is obtained in advance before step S130, they are appropriately set according to the use, usage environment, and required performance of the SiC semiconductor device, etc. In addition, in the above, an example where the data of the amount of current variation obtained in advance for predicting the amount of current variation is ΔV ON / Initial V ON has been described, but it is not limited thereto, and other electrical characteristics such as ΔVf / Initial Vf of the built-in diode may also be used.

[0071] In step S140, it is determined whether the amount of current variation predicted in step S130 is below a prescribed value. This determination is executed, for example, by a determination program recorded in the electronic control unit that stores the discrimination model used in step S130. In the case of an affirmative determination in step S140, that is, when the amount of current variation after driving for a prescribed time or more is small and the reliability of the electrical characteristics is estimated to be high, the manufacturing of the SiC semiconductor device using the semiconductor substrate 11 cut out in step S110 is continued. On the other hand, in the case of a negative determination in step S140, that is, when the amount of current variation after driving for a prescribed time or more is large and the reliability of the electrical characteristics is estimated to be low, the manufacturing of the SiC semiconductor device using the semiconductor substrate 11 cut out in step S110 is aborted. In addition, regarding the threshold value used in the determination in step S140, it is appropriately set, for example, according to the required performance of the manufactured SiC semiconductor device, etc. Thereby, the manufacturing of the SiC semiconductor device can be suppressed to the minimum, its manufacturing cost can be reduced, and a SiC semiconductor device with an amount of current variation below a prescribed value can be manufactured.

[0072] In the above, an example was described in which the BPD density is measured in step S120 and the amount of current change is predicted based at least on the BPD density in step S130, but it is not limited thereto. In order to further improve the prediction accuracy of the amount of current change, other parameters are also measured, and in addition to the BPD density, the amount of current change can be predicted using these other parameters.

[0073] For example, by considering the type of BPD in addition to the BPD density, the prediction accuracy of the amount of current change can be further improved. BPD is classified into a total of 72 types according to 12 orientations and 6 Burgers vectors b in hexagonal SiC. Specifically, the orientations are 12 axial directions: [11-20], [-12-10], [-2110], [-1-120], [1-210], [2-1-10], [10-10], [01-10], [1-100], [-1010], [0-110], [-1100]. The Burgers vector b has 3 types: (1 / 3)[11-20], (1 / 3)[-2110], (1 / 3)[1-210], and there are further 2 types based on the dislocation loop direction for each of these 3 types. That is, there are a total of 6 axial directions for the Burgers vector b.

[0074] In addition, the notations such as [11-20] with parentheses above refer to Miller indices. In addition, the "-" (dash) in the notation of the Miller indices should originally be added above the desired number, but due to limitations in the expression based on electronic applications, it is added before the desired number in this specification.

[0075] Regarding the orientation of BPD, for example, it can be obtained by observing the surface after etching with KOH. Regarding the Burgers vector b, for example, it can be measured by non-destructive testing such as X-ray topography and PL (photoluminescence) imaging. The discrimination of the BPD type can be performed, for example, by using an image after KOH etching or an image obtained by X-ray topography or PL imaging and analyzing it through a known image authentication technique. In addition, using the above-mentioned images and analysis results obtained by various methods as teacher data and using a deep learning model such as deep learning can further improve the discrimination accuracy of the BPD type.

[0076] BPD is classified into BPDs in which triangular defect D1 grows, BPDs in which band-shaped defect D2 grows, and BPDs in which defect D does not grow according to the above types. In particular, for example, as Figure 7As shown, the area of the strip-shaped defect D2 is larger than that of the triangular defect D1, so it has a greater impact on the change in the amount of energization. For example, regarding the BPD with the Burgers vector b being (1 / 3)[-2110], it grows as the strip-shaped defect D2 in the orientations of [11-20], [-12-10], [2-1-10], [10-10], [01-10], [1-100], [-1100]. In addition, regarding the BPD with the Burgers vector b being (1 / 3)[1-210], it grows as the strip-shaped defect D2 in the orientations of [-2110], [-1-120], [1-210], [1-100], [-1010], [0-110], [-1100]. That is, 28 out of 72 types of BPDs grow as the strip-shaped defect D2. Therefore, by predicting the change in the amount of energization based on these two parameters, namely the BPD density and the BPD type, the prediction accuracy can be further improved.

[0077] For example, in advance, obtain the relationship data between the 28 types out of 72 types of BPDs that grow as the strip-shaped defect D2 and the change in the amount of energization (ΔV ON / initial V ON etc.). In addition, as a discrimination model, for example, use the calculation formula for the change in the amount of energization calculated by the multiple regression analysis method with the BPD density and the BPD type as variables, and the relationship data between the density / type of BPDs and the change in the amount of energization as the teacher data to construct a machine learning model for predicting the change in the amount of energization. And in step S130, it is sufficient to predict the change in the amount of energization based on the BPD density and the BPD type of the semiconductor substrate 11 measured in step S120.

[0078] In addition, in this case, as the BPD density, for example, the result calculated only based on the 28 types of strip-shaped defects D2 growing in the BPDs can be used, but the result calculated without distinguishing the types of BPDs can also be used together. In addition, the types of BPDs in which the triangular defect D1 grows can also be used for predicting the change in the amount of energization.

[0079] In addition, for example, as Figure 8A 、 Figure 8B shown, the BPD density has a distribution in the plane of the semiconductor substrate 11. In Figure 8A 、 Figure 8B , it is the distribution of the BPD density in the plane of the semiconductor substrate 11. The region with a lower BPD density is represented by a color closer to white, and the region with a higher BPD density is represented by a color closer to black. Figure 8A 、 Figure 8BThe distributions of the BPD density shown are the distributions of the semiconductor substrate 11 cut from different SiC ingots. Thus, in the case where there is a distribution in the BPD density, only a part of the semiconductor substrate 11 may be in a state where the predicted amount of current variation is below a specified threshold. For example, in such a case, a positive determination is made in step S140, the manufacturing of the SiC semiconductor device is continued, and the semiconductor chip 10 manufactured by picking up the part where the predicted amount of current variation is below the specified threshold may be used. In addition, in the case where the predicted amount of current variation in a region of the semiconductor substrate 11 above a specified value (not limited, for example, 80% or more) exceeds the specified threshold, a negative determination is made in step S140, and the manufacturing of the SiC semiconductor device using the semiconductor substrate 11 may be aborted.

[0080] Furthermore, in step S130, the impurity concentration of the semiconductor substrate 11 may also be used as one of the parameters in the prediction of the amount of current variation. In this case, the relationship data between the impurity concentration of the semiconductor substrate 11 and the amount of current variation of the semiconductor chip 10 manufactured using it is obtained in advance, and a discrimination model using the relationship data is constructed. And in step S130, the impurity concentration of the semiconductor substrate 11 may be used as one of the parameters in the prediction of the amount of current variation.

[0081] Next, refer to Figure 9 For the subsequent Figure 5 manufacturing process of the SiC semiconductor device shown in the flowchart will be described.

[0082] In step S210, an epitaxial layer is grown on the semiconductor substrate 11 in which the predicted amount of current variation in step S140 is below the threshold or the ratio of the region below the threshold is above a specified value, to form a buffer layer 12 and a low-concentration layer 13. Hereinafter, for the sake of convenience of explanation, the structure in which an epitaxial layer is formed on the semiconductor substrate 11 is referred to as a "SiC wafer". The SiC wafer may also be referred to as a SiC epitaxial wafer.

[0083] In the next step S220, a prediction of the amount of current change when it is assumed that the semiconductor chip 10 is manufactured using the SiC wafer is made. For example, data on the amount of current change of the semiconductor chip 10 is obtained in advance for each parameter of the impurity concentration and film thickness of the buffer layer 12 and the impurity concentration and film thickness of the low-concentration layer 13 that constitutes the drift layer 18. In addition, data on the impurity concentration and film thickness of each of the buffer layer 12 and the low-concentration layer 13 in the SiC wafer formed in step S210 is recorded, for example, in a recording medium (not shown). And the discrimination model for predicting the amount of current change in step S220 has the following structure: in addition to the BPD density, at least one of the impurity concentration and film thickness of each of the buffer layer 12 and the low-concentration layer 13 is used as a parameter in the prediction of the amount of current change. Further, the discrimination model used in step S220 is, for example, the same as the discrimination model used in step S130, and is set as a discrimination model using the multiple regression analysis method or any machine learning model.

[0084] In the next step S230, a determination is made as to whether the amount of current change predicted in step S220 is below a specified value. This determination is performed, for example, by a determination program recorded in an electronic control unit that stores the discrimination model used in step S220. When the determination in step S230 is affirmative, that is, when it is estimated that the reliability is high, the process proceeds to step S240, and the manufacturing of the SiC semiconductor device that continues to use the SiC wafer formed in step S210 is carried out. On the other hand, when the determination in step S230 is negative, that is, when it is estimated that the reliability is low, the manufacturing of the SiC semiconductor device that uses the SiC wafer formed in step S210 is aborted. Further, regarding the threshold value used in the determination in step S230, for example, it is also appropriately set according to the required performance of the manufactured SiC semiconductor device, etc., in the same way as the threshold value in the determination in step S140.

[0085] In step S240, for example, a JFET section 14, a first deep layer 15, a current dispersion layer 16, a second deep layer 17, a base layer 19, a source region 20, and a contact region 21 are formed on a SiC wafer. Additionally, in step S240, for example, a trench gate structure, a source electrode 26, a drain electrode 27, and a guard ring (not shown) for the outer peripheral section are formed to form a plurality of semiconductor chips 10 having MOSFETs. Further, the parameters of each layer formed in step S240 are recorded, for example, in a recording medium (not shown) for predicting the amount of change in energization in step S260 described later. As the parameters of each layer mentioned here, for example, the impurity concentration and width of the JFET section 14, the pitch between the trench gate structures in the cell section, the impurity concentration and film thickness of the first deep layer 15 and the second deep layer 17, etc. can be cited. Additionally, as the parameters of each layer, the impurity concentration and width of the source region 20 and the contact region 21, etc. can also be cited.

[0086] In step S250, regarding the plurality of semiconductor chips 10 formed in step S240, various electrical characteristics such as V f 、V ON 、I-V characteristics, etc. are measured. The initial electrical characteristics of the plurality of semiconductor chips 10 obtained in step S250 are recorded, for example, in a recording medium (not shown) and used as one of the parameters in the prediction of the amount of change in energization in step S260.

[0087] In step S260, for example, by a discrimination model, in addition to the BPD density, at least one of the various parameters obtained in steps S240 and S250 is used to predict the amount of change in energization for the plurality of semiconductor chips 10. Specifically, relationship data between the various parameters such as the impurity concentration, film thickness, width, and pitch of the trench gate structure of each layer of the MOSFET formed in step S240 and the actual amount of change in energization is obtained in advance. Additionally, relationship data between the initial values of the various electrical characteristics of the semiconductor chips 10 manufactured in step S250 and the actual amount of change in energization is obtained in advance. And, in addition to the BPD density, based on this relationship data, a discrimination model for predicting the amount of change in energization using at least one of the various parameters such as the impurity concentration of each layer on the epitaxial wafer layer and the initial electrical characteristics of the semiconductor chips 10 is constructed. In step S260, such a discrimination model is used to predict the amount of change in energization.

[0088] In step S270, based on the amount of change in energization predicted in step S260, the semiconductor chips 10 are classified. This classification process is executed, for example, by a program recorded in an electronic control unit storing the discrimination model used in step S260. The plurality of semiconductor chips 10 formed on one wafer are, for example, as Figure 10 shown, in the V between the source electrode 26 / drain electrode 27 which is one of the initial electrical characteristicsON Deviations can be seen therein. In addition, Figure 10 The horizontal axis of the graph shown is the initial V ON (unit: V), and the vertical axis is the number of sheets. Also, as the semiconductor chip 10 is driven, defects D grow inside, and V ON shifts to the high voltage side. In step S270, for example, based on the initial V ON and the predicted amount of current variation (ΔV ON ), the changed V ON , that is, "changed V ON " and the V ON required for the SiC semiconductor device, that is, "required V ON ", the difference is used to classify multiple semiconductor chips 10. For example, the group with the lowest changed V ON relative to the required V ON , that is, the group with the highest performance, is set as grade 1, and the group with a low voltage second only to grade 1 for changed V ON is set as grade 2, and grading corresponding to the predicted performance after the change is performed in this way. In addition, for the group that does not meet the required performance in step S270, that is, the semiconductor chips 10 classified as the NG grade, they are removed without entering step S280.

[0089] In step S280, for example, the semiconductor chips 10 classified in step S270 are mounted on a lead frame or the like, and resin sealing or the like is performed to manufacture the SiC semiconductor device. At this time, the semiconductor chip 10 is used for, for example, the SiC semiconductor device for uses corresponding to the grade classified in step S270. For example, as an example of step S270, applying the highest performance grade to in-vehicle uses can be cited, but it is not limited thereto.

[0090] The above is the basic manufacturing process of the SiC semiconductor device of this embodiment. In addition, in step S270, an example of using V ON as the amount of current variation in the classification of the semiconductor chip 10 has been described, but it is not limited thereto, and the amount of current variation of other electrical characteristics can also be used as an index according to the required performance.

[0091] According to this embodiment, in each stage of slicing the semiconductor substrate 11 from the SiC ingot, growing the epitaxial layer, and forming the MOSFET with a trench gate structure, the amount of current variation of the finally manufactured semiconductor chip 10 is predicted at least based on the BPD density. And when the predicted amount of current variation is below a specified value, the manufacturing of the SiC semiconductor device is continued. Thus, it becomes a manufacturing method of a SiC semiconductor device that predicts the amount of current variation, reflects the predicted amount of current variation in the manufacturing process to determine whether to continue, thereby suppressing the manufacturing cost and suppressing the amount of current variation.

[0092] In addition, in the present embodiment, the following effects can also be obtained.

[0093] (1) By discriminating the types of BPDs in the semiconductor substrate 11 and predicting the amount of current variation based on the BPD density and the types of BPDs, the prediction of the amount of current variation can be made with higher accuracy.

[0094] (2) When discriminating the types of BPDs, it is performed by using image authentication of the image obtained by photographing the semiconductor substrate 11, thereby improving the discrimination accuracy of the types of BPDs.

[0095] (3) By using at least one or more of the type of BPD, the impurity concentration of the semiconductor substrate 11, the impurity concentration and film thickness of the buffer layer 12, and the impurity concentration and film thickness of the drift layer 18, and the BPD density as parameters, the prediction accuracy of the amount of current variation is improved. In addition, even if the impurity concentration and film thickness of the base layer 19, the impurity concentration and width of the source region 20 and the contact region 21, and at least one of the initial electrical characteristics of the semiconductor chip 10 are used as parameters of the discrimination model, the prediction accuracy of the amount of current variation is further improved. That is, by predicting the amount of current variation based on two or more parameters including the BPD density, compared with the case of making this prediction only based on the BPD density, the amount of current variation can be predicted with high accuracy.

[0096] (4) In the prediction of the amount of current variation, by using a discrimination model based on the multiple regression analysis method or a machine learning model, the prediction accuracy of the amount of current variation is improved.

[0097] (5) For the manufactured semiconductor chip 10, it is classified according to the predicted amount of current variation, and the classified semiconductor chip 10 is used for a SiC semiconductor device corresponding to the classification. Thus, the manufacture of the SiC semiconductor device is not carried out more than necessary, and a SiC semiconductor device that suppresses the amount of current variation while reducing the manufacturing cost can be manufactured.

[0098] (Other Embodiments)

[0099] This disclosure has been described based on the embodiments, but it should be understood that this disclosure is not limited to these embodiments and structures. This disclosure also includes various modifications and variations within the equivalent scope. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one, or less than one of them, also fall within the scope and spirit of this disclosure.

[0100] In the above embodiment, as the SiC semiconductor device, an example of using the semiconductor chip 10 having the structure with the JFET portion 14 and the deep layers 15 and 17 has been described, but it is not limited thereto. For example, as Figure 11As shown, when the semiconductor chip 10 does not have a structure such as a JFET section 14, deep layers 15, 17, etc., it is sufficient to limit the parameters used in predicting the amount of power-on change to the components of the semiconductor chip 10. For example, in addition to the BPD density of the semiconductor substrate 11, at least one or more of the BPD type, the impurity concentration of the semiconductor substrate 11, the impurity concentration and film thickness or width of the drift layer 28, the base layer 19, and the source region 20 may be used as the prediction parameters. In this way, the parameters used in predicting the amount of power-on change can also be appropriately changed according to the structure of the semiconductor chip 10. In addition, the drift layer 28 mentioned here has at least a structure without a JFET section 14.

[0101] The control unit (e.g., an electronic control unit recording a discrimination model) and its method described in the present disclosure can also be implemented by a dedicated computer provided by a processor and a memory configured to execute one or more functions embodied by a computer program. Alternatively, the control unit and its method described in the present disclosure can also be implemented by a dedicated computer provided by a processor composed of one or more dedicated hardware logic circuits. Alternatively, the control unit and its method described in the present disclosure can also be implemented by one or more dedicated computers provided by a combination of a processor configured to execute one or more functions and a memory and a processor composed of one or more hardware logic circuits. In addition, the computer program can also be stored as instructions executed by a computer in a computer-readable non-removable tangible recording medium.

[0102] In addition, in each of the above embodiments, the elements constituting the embodiments are not necessarily essential except in cases where they are specifically indicated as essential and cases where they are clearly considered essential in principle. In addition, in each of the above embodiments, when referring to numerical values such as the number, value, quantity, range, etc. of the elements constituting the embodiments, they are not limited to the specific number except in cases where they are specifically indicated as essential and cases where they are clearly limited to a specific number in principle. In addition, in each of the above embodiments, when referring to the shape, positional relationship, etc. of the elements, etc., they are not limited to the shape, positional relationship, etc. except in cases where they are specifically indicated and cases where they are clearly limited to a specific shape, positional relationship, etc. in principle.

[0103] (Viewpoint of the present disclosure)

[0104] Regarding the above-presented present disclosure, for example, it can be grasped as the viewpoints shown below.

[0105] [First viewpoint]

[0106] A method for manufacturing a silicon carbide semiconductor device, the silicon carbide semiconductor device having a switching element formed on a semiconductor substrate (11) made of silicon carbide and having a built-in diode, the manufacturing method including the following steps: measuring the density of basal plane dislocations in the semiconductor substrate, i.e., the BPD density; assuming that a semiconductor chip (10) having the switching element is manufactured, setting the initial electrical characteristics of the switching element immediately after the semiconductor chip is manufactured as the initial value, setting the change amount of the electrical characteristics after driving the switching element for a time equal to or greater than a specified value with respect to the initial value as the energization change amount, and predicting the energization change amount based at least on the BPD density; and based on the predicted energization change amount, making a determination as to whether to continue manufacturing the silicon carbide semiconductor device using the semiconductor substrate.

[0107] [Second Viewpoint]

[0108] The method for manufacturing a silicon carbide semiconductor device according to the first viewpoint further includes a step of discriminating the type of the basal plane dislocations, i.e., the BPD type, and the step of predicting the energization change amount is performed based on the BPD density and the BPD type.

[0109] [Third Viewpoint]

[0110] The method for manufacturing a silicon carbide semiconductor device according to the second viewpoint, the step of discriminating the BPD type is performed by image authentication, and the image authentication uses an image obtained by photographing the semiconductor substrate.

[0111] [Fourth Viewpoint]

[0112] The method for manufacturing a silicon carbide semiconductor device according to any one of the first to third viewpoints further includes a step of laminating a buffer layer (12) and a drift layer (18, 28) on the semiconductor substrate to form a silicon carbide wafer. In the step of predicting the energization change amount, based on at least one or more of the type of the basal plane dislocations, i.e., the BPD type, the impurity concentration of the semiconductor substrate, the impurity concentration and film thickness of the buffer layer, the impurity concentration and film thickness of the drift layer, and the BPD density, the energization change amount is predicted. In the step of making a determination as to whether to continue manufacturing the silicon carbide semiconductor device, it is determined whether to continue manufacturing the silicon carbide semiconductor device using the silicon carbide wafer.

[0113] [Fifth Viewpoint]

[0114] The method for manufacturing a silicon carbide semiconductor device according to any one of the first to fourth viewpoints, in the step of predicting the energization change amount, a determination model learned through prior machine learning is used.

[0115] [Sixth Aspect]

[0116] In the method for manufacturing a silicon carbide semiconductor device according to any one of the first to fourth aspects, in the step of predicting the amount of change in energization, a determination model based on multiple regression analysis having at least the BPD density as one of the variables is used.

[0117] [Seventh Aspect]

[0118] In the method for manufacturing a silicon carbide semiconductor device according to the fifth or sixth aspect, the method further includes a step of manufacturing a plurality of the semiconductor chips by forming a base layer (19), a source region (20), and a contact region (21) in the silicon carbide wafer. In the step of predicting the amount of change in energization, the determination model is used to predict the amount of change in energization based on at least three or more of the BPD density, the BPD type, the impurity concentration of the semiconductor substrate, the impurity concentration and film thickness of the buffer layer, the impurity concentration and film thickness of the drift layer, the impurity concentration and width of the source region, the impurity concentration and width of the contact region, and the initial electrical characteristics of the switching element.

[0119] [Eighth Aspect]

[0120] In the method for manufacturing a silicon carbide semiconductor device according to the seventh aspect, in the step of manufacturing a plurality of the semiconductor chips, a JFET portion (14) and deep layers (15, 17) are further formed in the silicon carbide wafer. In the step of predicting the amount of change in energization, the determination model is used to predict the amount of change in energization based on at least three or more of the BPD density, the BPD type, the impurity concentration of the semiconductor substrate, the impurity concentration and film thickness of the buffer layer, the impurity concentration and film thickness of the drift layer, the impurity concentration and width of the JFET portion, the impurity concentration of the deep layers, the impurity concentration and width of the source region, the impurity concentration and width of the contact region, and the initial electrical characteristics of the switching element.

[0121] [Ninth Aspect]

[0122] In the method for manufacturing a silicon carbide semiconductor device according to the seventh or eighth aspect, the method further includes a step of classifying the plurality of manufactured semiconductor chips into categories corresponding to the predicted values of the amount of change in energization.

Claims

1. A manufacturing method of a silicon carbide semiconductor device, the silicon carbide semiconductor device having a switching element formed on a semiconductor substrate (11) made of silicon carbide and including a built-in diode, the manufacturing method being characterized in that, it includes the following steps: measuring the density of basal plane dislocations, i.e., BPD density, in the semiconductor substrate; assuming that a semiconductor chip (10) having the switching element is manufactured, setting the initial electrical characteristics of the switching element immediately after the semiconductor chip is manufactured as the initial value, and setting the change amount of the electrical characteristics after driving the switching element for a time equal to or greater than a specified value with respect to the initial value as the energization change amount, and predicting the energization change amount based at least on the BPD density; and based on the predicted energization change amount, making a determination as to whether to continue manufacturing the silicon carbide semiconductor device using the semiconductor substrate.

2. The manufacturing method of a silicon carbide semiconductor device according to claim 1, characterized in that, it further includes a step of discriminating the type of the basal plane dislocations, i.e., BPD type, and the step of predicting the energization change amount is performed based on the BPD density and the BPD type.

3. The manufacturing method of a silicon carbide semiconductor device according to claim 2, characterized in that, the step of discriminating the BPD type is performed by image authentication, and the image authentication uses an image obtained by photographing the semiconductor substrate.

4. The manufacturing method of a silicon carbide semiconductor device according to claim 1, characterized in that, it further includes a step of laminating a buffer layer (12) and a drift layer (18, 28) on the semiconductor substrate to form a silicon carbide wafer, in the step of predicting the energization change amount, based on at least one or more of the type of the basal plane dislocations, i.e., BPD type, the impurity concentration of the semiconductor substrate, the impurity concentration and film thickness of the buffer layer, the impurity concentration and film thickness of the drift layer, and the BPD density, predicting the energization change amount, in the step of making a determination as to whether to continue manufacturing the silicon carbide semiconductor device, determining whether to continue manufacturing the silicon carbide semiconductor device using the silicon carbide wafer.

5. The manufacturing method of a silicon carbide semiconductor device according to claim 4, characterized in that, in the step of predicting the energization change amount, a determination model learned by prior machine learning is used.

6. The manufacturing method of a silicon carbide semiconductor device according to claim 4, characterized in that, in the step of predicting the energization change amount, a determination model based on multiple regression analysis having at least the BPD density as one of the variables is used.

7. The manufacturing method of a silicon carbide semiconductor device according to claim 5 or 6, characterized in that, it further includes a step of forming a base layer (19), a source region (20), and a contact region (21) in the silicon carbide wafer to manufacture a plurality of the semiconductor chips. In the step of predicting the amount of current conduction change, using the determination model, based on at least three or more of the BPD density and the BPD type, the impurity concentration of the semiconductor substrate, the impurity concentration and film thickness of the buffer layer, the impurity concentration and film thickness of the drift layer, the impurity concentration and width of the source region, the impurity concentration and width of the contact region, and the initial electrical characteristics of the switching element, the amount of current conduction change is predicted.

8. The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein, in the step of manufacturing a plurality of the semiconductor chips, a JFET portion (14) and deep layers (15, 17) are further formed in the silicon carbide wafer, In the step of predicting the amount of current conduction change, using the determination model, based on at least three or more of the BPD density and the BPD type, the impurity concentration of the semiconductor substrate, the impurity concentration and film thickness of the buffer layer, the impurity concentration and film thickness of the drift layer, the impurity concentration and width of the JFET portion, the impurity concentration of the deep layer, the impurity concentration and width of the source region, the impurity concentration and width of the contact region, and the initial electrical characteristics of the switching element, the amount of current conduction change is predicted.

9. The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein, it further includes a step of classifying the plurality of manufactured semiconductor chips into categories corresponding to the predicted values of the amount of current conduction change.

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