Semiconductor device

Abstract

The invention relates to a semiconductor device. According to one embodiment, a semiconductor device includes: a first transistor and a second transistor on a substrate; a first terminal; and a composite body including a second terminal and a first insulator partially covering the second terminal. The first end of the first transistor and the second end of the second transistor are connected to each other. The first terminal includes: a first portion in contact with a first conductor connected to a third terminal of the first transistor; a second portion connected to the first portion; and a third portion connected to the second portion. The second terminal includes a fourth portion, a fifth portion, and a sixth portion. The fourth portion is in contact with a second conductor connected to a fourth terminal of the second transistor. The fifth portion is connected to the fourth portion and is arranged side by side with the second portion of the first terminal. And the sixth part is connected with the fifth part. The first insulator covers the fifth portion.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device. Background Art

[0002] A semiconductor device includes a power module that processes high voltage. The power module can be configured as one package including a plurality of power semiconductor elements.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2020-155501 Summary of the Invention

[0006] Problems to be Solved by the Invention

[0007] To provide a semiconductor device that can be easily manufactured.

[0008] Means for Solving the Problems

[0009] A semiconductor device according to one embodiment includes: a first transistor and a second transistor on a substrate; a first terminal; and a composite body including a second terminal and a first insulator that locally covers the second terminal. The first end of the first transistor is connected to the second end of the second transistor. The first terminal includes: a first portion that contacts a first conductor connected to the third end of the first transistor; a second portion connected to the first portion; and a third portion connected to the second portion. The second terminal includes a fourth portion, a fifth portion, and a sixth portion. The fourth portion contacts a second conductor connected to the fourth end of the second transistor. The fifth portion is connected to the fourth portion and is arranged side by side with the second portion of the first terminal. The sixth portion is connected to the fifth portion. The first insulator covers the fifth portion. Brief Description of the Drawings

[0010] Figure 1 A perspective view showing an example of the appearance of the semiconductor device according to the first embodiment.

[0011] Figure 2 A diagram showing an example of the circuit of the semiconductor device according to the first embodiment.

[0012] Figure 3 A diagram schematically showing an example of the internal structure of the semiconductor device according to the first embodiment.

[0013] Figure 4 A diagram showing an example of the terminal structure of the semiconductor device according to the first embodiment.

[0014] Figure 5It is a perspective view showing the structure of the terminals and related components of the semiconductor device according to the first embodiment.

[0015] Figure 6 They are perspective views respectively showing the structure of the terminals and related components of the semiconductor device according to the first embodiment.

[0016] Figure 7 It shows the cross-sectional structure of the terminal of the semiconductor device according to the first embodiment.

[0017] Figure 8 It shows the cross-sectional structure of the terminal complex of the semiconductor device according to the first embodiment.

[0018] Figure 9 It is a perspective view showing a part of the manufacturing process of the terminal complex of the semiconductor device according to the first embodiment.

[0019] Figure 10 It shows the cross-sectional structure of the terminal of the semiconductor device according to the first embodiment.

[0020] Figure 11 It is a perspective view showing a part of the semiconductor device according to the first embodiment.

[0021] Figure 12 It is a perspective view showing the insulator of the semiconductor device according to a modification of the first embodiment.

[0022] Figure 13 It shows the cross-sectional structure of the terminal of the semiconductor device according to a modification of the first embodiment.

[0023] Figure 14 It shows a part of the manufacturing process of the terminal complex of the semiconductor device according to a modification of the first embodiment. Detailed Embodiments

[0024] Hereinafter, the embodiments will be described with reference to the drawings.

[0025] The drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thicknesses of the respective layers, etc. may be different from the actual situation. In addition, there may also be parts with different relationships and ratios of the dimensions between the drawings.

[0026] Hereinafter, the embodiments will be described using the XYZ orthogonal coordinate system. Sometimes the positive direction of the vertical axis of the drawing is referred to as the upper side, and the negative direction as the lower side. Sometimes the positive direction of the horizontal axis of the drawing is referred to as the right side, and the negative direction as the left side. That is, in the top view showing the XY plane (the XY plane view (hereinafter, the same)), the upper side refers to the +Y direction, the lower side refers to the -Y direction, the right side refers to the +X direction, and the left side refers to the -X direction.

[0027] 1. First Embodiment

[0028] The semiconductor device of the first embodiment is a power module. Examples of application modes of the semiconductor device of the first embodiment include a power conversion device for a railway vehicle and industrial equipment for a renewable energy power generation system.

[0029] Figure 1 It is a perspective view showing an example of the appearance of the semiconductor device of the first embodiment. The semiconductor device 1 includes a base substrate 10, a housing 11, covers 12 and 13, one or more terminals 14, one or more terminals 15, one or more terminals 16, and one or more terminals 17. The base substrate 10, the housing 11, and the covers 12 and 13 constitute a container of the semiconductor device 1. The internal space of the container of the semiconductor device 1 houses semiconductor elements and conductors that implement a circuit.

[0030] The base substrate 10 is a support of the semiconductor device 1. The base substrate 10 has a flat plate shape, for example, a quadrilateral shape. The base substrate 10 constitutes the lower part of the container of the semiconductor device 1. The base substrate 10 has threaded holes at its four corners, for example. The base substrate 10 includes copper (Cu) or ceramic, for example.

[0031] The housing 11 is an insulator having a cylindrical shape. The housing 11 is located on the upper surface of the base substrate 10. The housing 11 constitutes the side part of the container of the semiconductor device 1. The housing 11 is fixed to the base substrate 10. The housing 11 includes polyphenylene sulfide (PPS: Poly-Phenylene Sulfide), for example.

[0032] In the following description, the plane on which the base substrate 10 extends is referred to as the XY plane. The length direction of the base substrate 10 is referred to as the X direction, and the direction orthogonal to the X direction is referred to as the Y direction. The direction from the base substrate 10 toward the housing 11 is referred to as the Z direction. The Z direction is also the upward direction.

[0033] The covers 12 and 13 are insulators having a flat plate shape. The covers 12 and 13 are located on the upper surface of the housing 11. The covers 12 and 13 constitute the upper part of the container of the semiconductor device 1. The covers 12 and 13 are fixed to the housing 11. The covers 12 and 13 include PPC, for example.

[0034] The terminals 14, 15, 16, and 17 are the ends of bus bars (not shown) that electrically connect devices outside the semiconductor device 1 to the inside of the semiconductor device 1, respectively. Figure 1 And the following description is based on an example of two terminals 14, two terminals 15, three terminals 16, and eight terminals 17.

[0035] Terminal 14 is an input terminal. Terminal 14 has a P (Positive) polarity during the operation of the semiconductor device 1. Terminals 14 are electrically connected to each other. The upper surface of terminals 14 is exposed from the upper surface of the lid 13. Terminals 14 are arranged, for example, in the Y direction.

[0036] Terminal 15 is an input terminal. Terminal 15 has an N (Negative) polarity during the operation of the semiconductor device 1. Terminals 15 are electrically connected to each other. The upper surface of terminals 15 is exposed from the upper surface of the lid 13. Terminals 15 are arranged, for example, in the Y direction. The group of terminals 15 is located at a position in the -Y direction with respect to the group of terminals 14. The -Y direction is the opposite direction to the Y direction.

[0037] Terminal 16 is an output terminal. Terminal 16 is also referred to as an AC (Alternating Current) terminal. Terminals 16 are electrically connected to each other. The upper surface of terminals 16 is exposed from the upper surface of the lid 13. The group of terminals 16 is located at a position in the -Y direction with respect to the group of terminals 15.

[0038] Terminal 17 is a control terminal or a monitoring terminal. The control terminal is, for example, a terminal that receives a voltage for controlling the semiconductor elements included in the semiconductor device 1. The monitoring terminal is, for example, a terminal that outputs a voltage for monitoring the electrical characteristics of the semiconductor device 1. Terminals 17 are arranged along two opposite sides of the lid 12 in the X direction.

[0039] Figure 2 An example of the circuit of the semiconductor device according to the first embodiment is shown. Figure 2 The example shows a case where the semiconductor device 1 includes the transistors Tup and Tlow.

[0040] The transistors Tup and Tlow are n-type MOS (Metal-Oxide-Semiconductor) transistors. The transistors Tup and Tlow are connected in series.

[0041] The transistor Tup has a drain terminal connected to the node P, a source terminal, and a gate terminal connected to the node G1. The transistor Tlow has a drain terminal, a source terminal connected to the node N, and a gate terminal connected to the node G2.

[0042] The source terminal of the transistor Tup is connected to the drain terminal of the transistor Tlow. The source terminal of the transistor Tup and the drain terminal of the transistor Tlow are connected to the node AC and the node M.

[0043] The nodes P, N, and AC correspond to terminals 14, 15, and 16, respectively. The nodes G1 and G2 correspond to one of the terminals 17, respectively. The nodes M1 and M2 correspond to one of the terminals 17, respectively.

[0044] The circuit implemented by the semiconductor device 1 is not limited to Figure 2 the example. For example, the transistors Tup and Tlow can also be IGBTs (Insulated-Gate Bipolar Transistors). Multiple transistors Tup and / or multiple Tlows can also be provided. In this case, the multiple transistors Tup are connected in parallel, and the multiple transistors Tlow are connected in parallel.

[0045] Figure 3 An example of the internal structure of the semiconductor device according to the first embodiment is schematically shown. Figure 3 Only the base substrate 10, and the terminals 14 and 15 among the Figure 1 constituent elements shown are illustrated. The semiconductor device 1 further includes one or more circuit boards 20, multiple conductors 21, multiple semiconductor chips 22, multiple conductors 23, and multiple insulators 24. Figure 3 And the following description is based on an example of four circuit boards 20.

[0046] The circuit board 20 is an insulating substrate that supports the constituent elements of the circuit (refer to Figure 2 ) implemented by the semiconductor device 1. The circuit board 20 is located on the upper surface of the base substrate 10. The circuit board 20 contains, for example, silicon nitride (SiN). The circuit boards 20 are distributed on the upper surface of the base substrate 10. In one example, the circuit boards 20 are arranged in the X direction and the Y direction, and the following description and Figure 3 are based on such an example. The circuit board 20 includes a circuit board 20a located at a position closer to the -X direction and a circuit board 20b located at a position closer to the X direction. One circuit board 20a and one circuit board 20b are arranged in the X direction.

[0047] The conductor 21 is a wiring pattern having a flat plate shape. The conductor 21 is located on the upper surface of each circuit board 20. The conductor 21 forms a part of the circuit of the semiconductor device 1. Figure 3 Taking the shape along the XY plane (sometimes referred to as the planar shape) of the conductor 21 shown as an example, it can have any planar shape as long as it can implement Figure 2 the circuit shown.

[0048] The semiconductor chip 22 is a chip including semiconductor elements. The semiconductor chip 22 is located on the upper surface of one conductor 21 and is distributed on the upper surface of the conductor 21. The semiconductor chip 22 includes a semiconductor chip 22a above the circuit board 20a and a semiconductor chip 22b above the circuit board 20b. The semiconductor chip 22a functions as the transistor Tlow. The semiconductor chip 22b functions as the transistor Tup. Each semiconductor chip 22 includes a terminal 221.

[0049] The conductor 23 is a bonding wire. Each conductor 23 is connected to one terminal 221 and one conductor 21.

[0050] The terminal 14 is a conductor having a flat plate shape. The terminal 14 is bent or folded and extended at several locations. The terminal 14 is connected to at least one conductor 21 on one circuit board 20b on the side opposite to the side including the surface exposed from the cover 13 (hereinafter sometimes referred to as the upper surface). Regarding the further shape of the terminal 14, reference will be made to Figure 10 which will be described later.

[0051] The terminal 15 is a conductor having a flat plate shape. The terminal 15 is bent or folded and extended at several locations. The terminal 15 is connected to at least one conductor 21 on one circuit board 20a on the side opposite to the side including the surface exposed from the cover 13 (hereinafter sometimes referred to as the upper surface). Regarding the further shape of the terminal 15, reference will be made to Figure 6 and Figure 7 which will be described later.

[0052] The insulator 24 contains resin, for example. The insulator 24 locally covers the terminal 15. The insulator 24 covers the portions other than the upper surface and its vicinity and the surface in contact with the conductor 21 and its vicinity in the terminal 15. The insulator 24 extends along the shape of the terminal 15. Regarding the further shape of the insulator 24, reference will be made to Figure 6 and Figure 8 which will be described later.

[0053] Figure 4 An example of the structure of the terminals of the semiconductor device according to the first embodiment is shown. Figure 4 The state of observing the terminal 16 from a plane along the XY plane is shown.

[0054] The terminal 16 has a flat plate shape, and the flat plate has a shape bent or folded at several locations. The terminal 16 includes an upper surface portion 16a and a lower surface portion 16b. The upper surface portion 16a and the lower surface portion 16b are connected to each other via other portions.

[0055] The upper surface portion 16a occupies the uppermost part of the terminal 16. The upper surface portion 16a extends along the XY plane. The upper surface of the upper surface portion 16a is exposed on the upper surface of the cover 13.

[0056] The lower surface portion 16b occupies the lowermost part of the terminal 16. The lower surface portion 16b extends along the XY plane. The lower surface portion 16b is in contact with the lower surface and the upper surface of the conductor 21 corresponding to the node AC of the circuit (refer to Figure 2 ) implemented by the semiconductor device 1.

[0057] Regarding the structure of the portion of the terminal 16 other than the upper surface portion 16a and the lower surface portion 16b, it may have any structure as long as it has a structure in which the upper surface portion 16a is connected to the lower surface portion 16b and the lower surface portion 16b can be located above the conductor 21 to which the lower surface portion 16b should be connected. An example is described below.

[0058] In one example, the terminal 16 further includes a first intermediate portion 16c, a second intermediate portion 16d, and a third intermediate portion 16e. The first intermediate portion 16c extends along the YZ plane and is connected to one side of the upper surface portion 16a. The second intermediate portion 16d extends along the XY plane and is connected to the side of the first intermediate portion 16c that is opposite to the side connected to the upper surface portion 16a. The third intermediate portion 16e extends along the YZ plane and is connected to the side of the second intermediate portion 16d that is opposite to the side connected to the first intermediate portion 16c. The third intermediate portion 16e is also connected to the lower surface portion 16b at the side opposite to the side connected to the second intermediate portion 16d. Generally speaking, the terminal 16 has a shape formed by connecting multiple L-shapes.

[0059] Multiple upper surface portions 16a may also be connected to one first intermediate portion 16c.

[0060] Figure 5 It is a perspective view showing the structure of the terminal of the semiconductor device according to the first embodiment and related components. Figure 6 It is a perspective view respectively showing the structure of the terminal of the semiconductor device according to the first embodiment and related components. Figure 7 It shows the cross-sectional structure of the terminal of the semiconductor device according to the first embodiment. Figure 8 It shows the cross-sectional structure of the terminal complex of the semiconductor device according to the first embodiment.

[0061] As Figure 5 shown, the terminal 15 is partially located inside the insulator 24 and is covered by the insulator 24. The terminal 15 and the insulator 24 are integrated. Hereinafter, the structure of the group including the terminal 15 and the insulator 24 is sometimes referred to as the terminal complex 31. The terminal complex 31 can be formed by insert molding.

[0062] The terminal complex 31 may further include multiple insulators 26. The insulator 24 has a depression along the outer shape of the insulator 26 in the portion including the lower surface, and the insulator 26 is partially located in the depression. The insulator 26 is, for example, resin.

[0063] As Figure 6 and Figure 7 shown, the terminal 15 includes an upper surface portion 15a, at least one lower surface portion 15b, and a first intermediate portion 15c. Figure 5 and Figure 7The following description is based on an example of two lower surface portions 15b.

[0064] The upper surface portion 15a occupies the uppermost part of the terminal 15. The upper surface portion 15a extends along the XY plane. The upper surface of the upper surface portion 15a is exposed on the upper surface of the lid 13.

[0065] The lower surface portion 15b occupies the lowermost part of the terminal 15. The lower surface portion 15b extends along the XY plane. The lower surface portion 15b is in contact with the lower surface and the upper surface of the conductor 21 corresponding to the node N of the circuit (see Figure 2 ) implemented by the semiconductor device 1.

[0066] The first intermediate portion 15c extends along the XY plane. In one example, the first intermediate portion 15c extends in the X direction. The first intermediate portion 15c is connected to the upper surface portion 15a and the lower surface portion 15b respectively via other parts of the terminal 15 at opposite sides. The first intermediate portion 15c is partially located in the region directly below the upper surface portion 15a and is partially opposed to the upper surface portion 15a. In one example, the first intermediate portion 15c is not located in the region directly above the lower surface portion 15b and is not opposed to the lower surface portion 15b.

[0067] Regarding the structure of the parts of the terminal 15 other than the upper surface portion 15a, the lower surface portion 15b, and the first intermediate portion 15c, as long as the first intermediate portion 15c is connected to the upper surface portion 15a and the lower surface portion 15b and the lower surface portion 15b can be located above the conductor 21 to which the lower surface portion 15b should be connected, it can have any structure. An example is described below.

[0068] In one example, the terminal 15 further includes a second intermediate portion 15d and a third intermediate portion 15e. The second intermediate portion 15d extends along the YZ plane and is connected to one side of the upper surface portion 15a and one side of the first intermediate portion 15c at opposite sides.

[0069] The third intermediate portion 15e extends along the YZ plane and is connected to the lower surface portion 15b at the side of the first intermediate portion 15c opposite to the side connected to the second intermediate portion 15d. In one example, the third intermediate portion 15e branches into two on the lower surface portion 15b side. The branched portions each have a shape formed by connecting a plurality of L - shaped portions along the YZ plane.

[0070] As Figure 6 and Figure 8 shown, the insulator 24 locally surrounds the terminal 15 and at least does not surround the upper surface portion 15a and the lower surface portion 15b of the terminal 15. The insulator 24 has a shape along the shape of the portion of the terminal 15 surrounded by the insulator 24 in the surrounded portion. Specifically, it is as follows.

[0071] The insulator 24 includes a first part 24a, a second part 24b, and a third part 24c. The first part 24a occupies the middle part of the insulator 24. The first part 24a extends along the XY plane and extends in the X direction. The first part 24a surrounds the first intermediate part 15c of the terminal 15, includes the first intermediate part 15c therein, and is in contact with the first intermediate part 15c. The first part 24a has a plurality of holes (openings) 241. Each hole 241 extends from the upper surface of the first part 24a to the upper surface of the terminal 15. The first part 24a includes a portion having a shape along the outer contour of the insulator 26.

[0072] The second part 24b occupies the uppermost part of the insulator 24. The second part 24b extends along the YZ plane. The second part 24b is connected to the first part 24a at the lower end. The second part 24b surrounds a part of the second intermediate part 15d of the terminal 15, surrounds the lower part of the second intermediate part 15d, and includes the lower part of the second intermediate part 15d therein. The second part 24b is in contact with the second intermediate part 15d of the terminal 15. The position of the upper end (upper surface) of the second part 24b depends at least partially on the shape of the terminal 14. Regarding the upper end position of the second part 24b, reference will be made to Figure 10 which will be described later.

[0073] The third part 24c occupies the lowermost part of the insulator 24. The third part 24c extends along the YZ plane. The third part 24c is connected to the end of the first part 24a that is opposite to the end connected to the second part 24b at the upper end. The third part 24c surrounds a part of the third intermediate part 15e of the terminal 15, surrounds the upper part of the third intermediate part 15e, and includes the upper part of the third intermediate part 15e therein. The third part 24c is in contact with the third intermediate part 15e of the terminal 15.

[0074] Generally speaking, the insulator 24 has a shape formed by connecting a plurality of L-shaped shapes along the XZ plane.

[0075] As Figure 5 and Figure 6 shown, the insulator 26 includes a first part 26a and a protrusion 26b. The first part 26a has a shape obtained by cutting a rectangular parallelepiped extending in the X direction from a rectangular parallelepiped extending in the X direction, and has a column shape with a curved U shape extending along the Z direction along the XY plane. The protrusion 26b is connected to the first part 26a and extends in the Z direction, and has a rectangular parallelepiped shape. The first part 26a is located inside the insulator 24, and for example, has a lower surface (XY plane at the position closest to the -Z direction) that is flush with the lower surface of the insulator 24 (XY plane at the position closest to the -Z direction). The protrusion 26b protrudes locally from the lower surface of the insulator 24.

[0076] Figure 9It is a perspective view showing a part of the manufacturing process of the terminal complex of the semiconductor device according to the first embodiment. Using a device for forming the insulator 24, the terminal complex 31 is formed by insert molding. The device has a mold inside that encloses a space along the shape of the insulator 24.

[0077] As Figure 8 shown, the insulator 26 is set in the mold with the protruding portion 26b facing the -Z direction. The mold has a hole, and the protruding portion 26b is inserted into the hole. The terminal 15 is arranged on the upper surface of the insulator 24 in the inner space of the mold with the first intermediate portion 15c along the XY plane. Figure 8 It shows the state where the terminal 15 and the insulator 26 are arranged in the mold at the lower part. The terminal 15 is fixed by further applying pressure from the Z - direction side with a rod. Thus, in the state where the terminal 15 and the insulator 26 are arranged, the material of the insulator 24 is injected into the inner space of the mold. During the formation of the insulator 24 by injecting the insulator 24, the protruding portion 26b fixes the position of the terminal 15, suppressing the movement and / or rotation of the terminal 15. By the insert molding of injecting the insulator 24, as Figure 5 shown, the terminal complex 31 is formed. By not forming the insulator 24 in the region where the rod fixing the terminal 15 is located during the insert molding, the hole 241 of the insulator 24 is formed.

[0078] Figure 10 It shows the cross - sectional structure of the terminal of the semiconductor device according to the first embodiment. Figure 10 It also shows the terminal complex 31 (the group of the terminal 15 and the insulator 24), and also shows the arrangement of the terminal complex 31 and the insulator 24 in the semiconductor device 1.

[0079] As Figure 10 shown, the terminal 14 includes an upper surface portion 14a, at least one lower surface portion 14b, a first intermediate portion 14c, and a second intermediate portion 14d. The terminal 14 locally has a shape along the outer shape of the terminal complex 31, especially its insulator 24. The terminal 14 is locally in contact with or close to the lower surface of the insulator 24 on the upper surface.

[0080] The upper surface portion 14a occupies the uppermost part of the terminal 14. The upper surface portion 14a extends along the XY plane. The upper surface of the upper surface portion 14a is exposed on the upper surface of the cover 13.

[0081] The lower surface portion 14b occupies the lowermost part of the terminal 14. The lower surface portion 14b extends along the XY plane. The lower surface portion 14b is in contact with the upper surface of the conductor 21 corresponding to the node P of the circuit (refer to Figure 2 ) implemented by the semiconductor device 1 on the lower surface.

[0082] The first intermediate portion 14c extends along the XY plane. The first intermediate portion 14c is connected to the lower surface portion 14b via other portions of the terminal 14. The first intermediate portion 14c is located in a region directly above the lower surface portion 14b and faces the lower surface portion 14b. The first intermediate portion 14c faces the first intermediate portion 15c of the terminal 15. The first intermediate portion 14c is not located in a region directly below the upper surface portion 14a and does not face the upper surface portion 14a.

[0083] The second intermediate portion 14d extends along the YZ plane. The second intermediate portion 14d is connected to an end of the upper surface portion 14a via other portions of the terminal 14. The second intermediate portion 14d faces the second intermediate portion 15d of the terminal 15. There is a distance D1 between the second intermediate portion 14d and the second intermediate portion 15d of the terminal 15. The distance D1 is greater than the distance between the first intermediate portion 14c and the first intermediate portion 15c of the terminal 15. The second intermediate portion 14d faces the insulator 24. In one example, the position of the upper end of the insulator 24 in the Z direction is located below the upper end of the second intermediate portion 14d and above the lower end.

[0084] Regarding the structure of portions of the terminal 14 other than the upper surface portion 14a, the lower surface portion 14b, the first intermediate portion 14c, and the second intermediate portion 14d, any structure may be adopted as long as the first intermediate portion 14c is connected to the lower surface portion 14b and the second intermediate portion 14d and the lower surface portion 14b can be located above the conductor 21 to which the lower surface portion 14b is to be connected. An example is described below.

[0085] In one example, the terminal 14 further includes a third intermediate portion 14e, a fourth intermediate portion 14f, and a fifth intermediate portion 14g. The third intermediate portion 14e extends along the YZ plane and is connected to an end of the first intermediate portion 14c. The third intermediate portion 14e faces the second intermediate portion 15d of the terminal 15. The distance between the third intermediate portion 14e and the second intermediate portion 15d of the terminal 15 is less than the distance D1.

[0086] The fourth intermediate portion 14f is connected to the end of the second intermediate portion 14d and the end of the third intermediate portion 14e. The shape of the fourth intermediate portion 14f along the XY plane is curved. The upper end of the fourth intermediate portion 14f, that is, the end connected to the second intermediate portion 14d, is located below (-z direction side) the upper end of the insulator 24.

[0087] The fifth intermediate portion 14g extends along the YZ plane. The fifth intermediate portion 14g is connected to the end of the first intermediate portion 14c and the end of the lower surface portion 14b. In one example, as described later Figure 11As shown, the fifth intermediate portion 14g is divided into two branches on the lower surface portion 14b side. The divided portions each have a shape formed by connecting a plurality of L-shaped portions along the YZ plane. In this example, the divided portions of the fifth intermediate portion 14g each have the same shape as the divided portions of the third intermediate portion 15e of the terminal 15, and face each other.

[0088] Figure 11 FIG. is a perspective view showing a part of the semiconductor device according to the first embodiment. Figure 10 The positional relationship between the terminal complex 31 (the group of the terminal 15, the insulators 24 and 26) and the terminal 14 in the semiconductor device 1 is also shown. As Figure 10 shown and as described with reference to Figure 9 the terminal 14 is in contact with the terminal complex 31, particularly the insulator 24. The terminal 14 is arranged such that the first intermediate portion 14c of the terminal 14 is located in the region between the protruding portions 26b of the insulator 26. That is, when the terminal complex 31 is arranged on the terminal 14, the protruding portions 26b of the insulator 26 can function as a guide for aligning the terminal complex 31 and the terminal 14.

[0089] According to the semiconductor device of the first embodiment, as described below, there is provided a semiconductor device capable of suppressing inductance and being manufactured by a simplified process.

[0090] To achieve Figure 2 the circuit configuration shown, by including two terminals such as the terminal 14 and the terminal 15 having portions facing each other at a short distance, inductance can be suppressed. That is, when one of the transistors Tup and Tlow, both of which are off, is turned on, a current flows between the terminal 14 and the terminal 15. Generally, when the state of the current flowing through a conductor changes, inductance is generated in the conductor, and the inductance functions as a resistance against the current. During the period when a current flows between the terminal 14 and the terminal 15, the direction of the current flowing through the terminal 14 ( Figure 9 in the -X direction in ) is opposite to the direction of the current flowing through the terminal 15 ( Figure 9 in the X direction in ). Therefore, the inductance generated by the current flowing through the terminal 14 and the inductance generated by the current flowing through the terminal 15 have opposite polarities to each other. Therefore, by arranging the terminal 14 and the terminal 15 at a short distance, the inductance generated by the current flowing through the terminal 14 and the inductance generated by the current flowing through the terminal 15 cancel each other out. Therefore, the semiconductor device 1 can suppress inductance.

[0091] To suppress inductance, the distance between terminal 14 and terminal 15 is preferably short. On the other hand, insulation between terminal 14 and terminal 15 needs to be ensured. For this purpose, it is conceivable to dispose an insulator between terminal 14 and terminal 15. However, in this case, during the manufacturing process of the semiconductor device 1, terminal 14, terminal 15, and the insulator need to be disposed separately. Such a manufacturing process makes alignment of terminal 14, terminal 15, and the insulator difficult.

[0092] To facilitate alignment, it is conceivable to form terminal 15 and the insulator covering terminal 15 by insert molding. Generally, during insert molding, the pressure of the resin supplied to the internal space of the mold is high. Therefore, the position of terminal 15 needs to be fixed. For this purpose, it is conceivable to clamp terminal 15 using a bar in contact with the upper surface of terminal 15 and a bar in contact with the lower surface of terminal 15. In this case, by the same mechanism as described with reference to Figure 8 In addition to forming hole 241 in insulator 24, a hole reaching terminal 15 from the lower surface is formed in the first portion 24a of insulator 24. Through this hole, terminal 14 and terminal 15 face each other with air therebetween inside the hole. Since the distance between terminal 14 and terminal 15 is short, insulation between terminal 14 and terminal 15 cannot be ensured in the portion of the hole due to the presence of the hole.

[0093] According to the first embodiment, insulator 24 and terminal 15 are formed by insert molding. Therefore, insulator 24 and terminal 15 have an integral structure as terminal complex 31. Therefore, the arrangement of terminal 15 (terminal complex 31) and terminal 14 is easier.

[0094] Furthermore, the semiconductor device 1 of the first embodiment includes insulator 26. During the formation of insulator 24 by insert molding, insulator 26 fixes terminal 14. Therefore, a structure (e.g., a bar) located in the -Z direction of terminal 15 and fixing terminal 15 during insert molding is not required. Therefore, it is possible to suppress the region where insulator 24 cannot be formed due to the presence of the structure, and further suppress the space in the -Z direction of terminal 15 where insulator 24 is formed. Therefore, insulation between terminal 14 and terminal 15 can be ensured.

[0095] Instead of providing two insulators 26, one insulator 26A may be provided as shown in Figure 12 In this case, insulator 26A has a structure formed by combining the two insulators 26 shown in Figure 5 and Figure 6

[0096] As shown in Figure 13As shown, the insulator 26 may also include a protrusion 26b on the Z-direction side. In this case, the terminal 15 includes a hole (opening) 151 in the first intermediate portion 15c. The hole 151 extends through the upper and lower surfaces of the first intermediate portion 15c. The protrusion 26b is located within the hole 151. During insert molding, the protrusion 26b is inserted into the hole 151. Even though there is the hole 151, the region directly below the hole 151 is occupied by the insulator 26. Therefore, even with the presence of the hole 151, insulation between the terminals 14 and 15 can be ensured.

[0097] As Figure 14 shown, during insert molding, the bar for fixing the terminal 15 may not be used. In this case, the outlet 45 for injecting the material of the insulator 24 is located above the first intermediate portion 15c of the terminal 15 and the insulator 26. The injected material of the insulator 24 applies pressure to the first intermediate portion 15c, thereby fixing the position of the terminal 15. In this case, the insulator 24 does not have the hole 241.

[0098] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the scope equivalent thereto.

Claims

1. A semiconductor device comprising: A first transistor and a second transistor are located on the substrate, and a first terminal of the first transistor and a second terminal of the second transistor are connected to each other; a first terminal including a first portion connected to a first conductor connected to a third end of the first transistor, a second portion connected to the first portion, and a third portion connected to the second portion; and A complex includes a second terminal and a first insulator partially covering the second terminal, wherein the second terminal includes a fourth part, a fifth part and a sixth part, the fourth part is connected to the second conductor connected to the fourth end of the second transistor, the fifth part is connected to the fourth part and is parallel to the second part of the first terminal, the sixth part is connected to the fifth part, and the first insulator covers the fifth part.

2. The semiconductor device according to claim 1, wherein The above-mentioned portion 4 includes a first sub-portion, and the first sub-portion includes a region connected to the above-mentioned portion 5, The above-mentioned section 6 includes a second subsection, and the second subsection includes a region connected to the above-mentioned section 5, The first insulator further covers the first sub-portion and the second sub-portion.

3. The semiconductor device according to claim 2, wherein: The first insulator is continuous over a region around the fifth portion, a region around the first sub-portion, and a region around the second sub-portion.

4. The semiconductor device according to claim 3, wherein: The fifth portion is located closer to the first direction than the second portion. The first insulator covers the surface of the fifth portion facing the first direction and the surface of the fifth portion facing the second direction. The second direction is opposite to the first direction.

5. The semiconductor device according to claim 4, wherein: The fourth portion is located closer to the third direction than the first portion. The sixth portion is located closer to the third direction than the third portion. The first insulator covers the surface of the fourth portion facing the third direction, the surface of the fourth portion facing the fourth direction, the surface of the sixth portion facing the third direction, and the surface of the sixth portion facing the fourth direction. The fourth direction is opposite to the third direction.

6. The semiconductor device according to claim 1, wherein The above-mentioned complex further includes a second insulator, The first insulator has a recess along the shape of the second insulator at a portion covering the fifth portion. The second insulator is located in the recess of the first insulator.

7. The semiconductor device according to claim 6, wherein: The second insulator includes: Section 7; and One or more eighth portions are connected to the seventh portion and protrude from the first insulator.

8. The semiconductor device according to claim 6, wherein: The above-mentioned section 5 includes an opening, The second insulator includes: Section 7; and One or more 8th parts are connected to the above-mentioned 7th part and are located in the above-mentioned opening.

9. The semiconductor device according to claim 1, wherein: The first insulator and the second terminal are integrated.

10. The semiconductor device according to claim 1, wherein The first insulator and the second terminal are formed by insert molding.

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