Multi-color light-emitting micro LED display and manufacturing method thereof

Abstract

One method includes fabricating a semiconductor light emitting structure configured to emit different colors of radiation (e.g., visible light of blue, green, and red) on the same growth substrate using selective region growth. The light-emitting structure can form each sub-pixel of a multi-color pixel array. An array of multicolor pixels may be transferred from a growth substrate to a backplane using a single transfer process to provide a high resolution multicolor display.

Description

[0001] Related Applications This application claims the benefit of priority from U.S. Provisional Patent Application No. 63 / 380,683, filed Oct. 24, 2022, the entire content of which is hereby incorporated by reference for all purposes. Technical Field

[0002] The present invention relates to light-emitting devices, and more particularly, to displays including multi-color light-emitting device sub-pixels derived from a common growth substrate and methods of manufacturing the same. Background Art

[0003] Light-emitting devices, such as light-emitting diodes (LEDs), are used in electronic displays, such as backlights in liquid crystal displays in laptop computers or televisions. Light-emitting devices include light-emitting diodes (LEDs) and various other types of electronic devices configured to emit light. Summary of the Invention

[0004] According to one aspect of the present disclosure, a display includes: a backplane having a flat mounting surface; and a multi-color pixel bonded to the flat mounting surface of the backplane, the multi-color pixel including a plurality of sub-pixels, wherein each sub-pixel is configured to emit light having a different peak wavelength. Each sub-pixel of the multi-color pixel includes a front surface and a back surface, the front surface being configured to emit light therethrough, and the back surface facing the backplane. Each sub-pixel of the multi-color pixel includes a front portion, a back portion, and a semiconductor connection portion, the front portion being adjacent to the front surface of the sub-pixel and a first conductivity type semiconductor material layer, the back portion being adjacent to the back surface of the sub-pixel and including a first flat surface and a second flat surface extending parallel to the flat mounting surface of the backplane and a sidewall extending between the first flat surface and the second flat surface, the back portion including an active region and a second conductivity type semiconductor material layer, and the semiconductor connection portion being between the front portion and the back portion of the sub-pixel. A dielectric material layer extends over at least a portion of the first flat surface and the second flat surface and the sidewall of the back portion and laterally surrounds the semiconductor connection portion of each of the sub-pixels of the multi-color pixel.

[0005] According to another aspect of the present disclosure, a method of manufacturing a light-emitting device includes: forming a first-conductive-type semiconductor material layer over an initial growth substrate; forming a first dielectric material layer over the first-conductive-type semiconductor material layer; lithographically patterning the first dielectric material layer to form an opening through the first dielectric material layer; forming a first semiconductor material pedestal structure within the opening and laterally surrounded by the first dielectric material layer; forming a first light-emitting device structure via selective growth from the first semiconductor material pedestal structure, the first light-emitting device structure including a first active region and a second-conductive-type semiconductor material layer over the first active region, wherein the first active region is configured to emit light having a first peak wavelength; performing an etching process to remove the first dielectric material layer; forming a second dielectric material layer using a conformal deposition process, the second dielectric material layer being over the first-conductive-type semiconductor layer and the first light-emitting device structure and laterally surrounding and contacting the first semiconductor material pedestal structure; lithographically patterning the second dielectric material layer to form an opening through the second dielectric material layer; forming a second semiconductor material pedestal structure within the opening and laterally surrounded by the second dielectric material layer; forming a second light-emitting device structure via selective growth from the second semiconductor material pedestal structure, the second light-emitting device structure including a second active region and a second-conductive-type semiconductor material layer over the second active region, wherein the second active region is configured to emit light having a second peak wavelength different from the first peak wavelength; and performing an etching process to remove the second dielectric material layer.

[0006] According to another aspect of the present disclosure, a multicolor pixel includes: a common semiconductor material layer having a first conductivity type; a first sub-pixel located on the common semiconductor material layer and including a first mesa, the first mesa including a first active region and a first semiconductor material layer having a second conductivity type; a second sub-pixel located on the common semiconductor material layer and including a second mesa, the second mesa including a second active region and a second semiconductor material layer having a second conductivity type; and a third sub-pixel located on the common semiconductor material layer and including a third mesa, the third mesa including a third active region and a third semiconductor material layer having a second conductivity type. Each sub-pixel is configured to emit light having a different peak wavelength. The first mesa, the second mesa, and the third mesa are laterally spaced apart from each other. The size of the opening and thus the top surface area of the three mesas can be customized according to the emission wavelength and the external quantum efficiency (EQE) of each of the emission wavelength mesas. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a plan view of a substrate of a light-emitting diode having multiple colors according to an embodiment of the present disclosure.

[0008] Figure 2is a vertical cross - sectional view of a first exemplary structure of a pixel region including an initial growth substrate on which multi - color light - emitting pixels can be formed subsequently according to various embodiments of the present disclosure.

[0009] Figure 3 is a vertical cross - sectional view of a first exemplary structure of a continuous doped semiconductor material layer formed on an initial growth substrate according to various embodiments of the present disclosure.

[0010] Figure 4 is a vertical cross - sectional view of a first exemplary structure of a continuous superlattice structure formed on a continuous doped semiconductor material layer according to various embodiments of the present disclosure.

[0011] Figure 5 is a vertical cross - sectional view of a first exemplary structure of a continuous lower spacer layer formed on a continuous superlattice structure according to various embodiments of the present disclosure.

[0012] Figure 6 is a vertical cross - sectional view of a first exemplary structure of a continuous first dielectric material layer formed on a continuous lower spacer layer according to various embodiments of the present disclosure.

[0013] Figure 7 is a vertical cross - sectional view of a first exemplary structure of a patterned mask formed on a continuous first dielectric material layer according to various embodiments of the present disclosure.

[0014] Figure 8 is a vertical cross - sectional view of a first exemplary structure of an opening formed through the first dielectric material layer in a first sub - pixel region according to various embodiments of the present disclosure.

[0015] Figure 9 is a vertical cross - sectional view of a first exemplary structure of an upper spacer layer formed on a continuous lower spacer layer in a first sub - pixel region according to various embodiments of the present disclosure.

[0016] Figure 10 is a vertical cross - sectional view of a first exemplary structure of an active region formed on an upper spacer layer in a first sub - pixel region according to various embodiments of the present disclosure.

[0017] Figure 11 is a vertical cross - sectional view of a first exemplary structure of an optional electron - blocking layer formed on an active region in a first sub - pixel region according to various embodiments of the present disclosure.

[0018] Figure 12 is a vertical cross - sectional view of a first exemplary structure of a doped semiconductor material layer formed on an electron - blocking layer in a first sub - pixel region according to various embodiments of the present disclosure.

[0019] Figure 13 is a vertical cross-sectional view of a first exemplary structure after an etching process for removing a first dielectric material layer according to various embodiments of the present disclosure.

[0020] Figure 14 is a vertical cross-sectional view of a first exemplary structure including a continuous second dielectric material layer formed over a lower portion of a spacer layer and over side and top surfaces of a mesa portion of a first light-emitting epitaxial semiconductor structure according to various embodiments of the present disclosure.

[0021] Figure 15 is a vertical cross-sectional view of a first exemplary structure including a patterned mask formed over a continuous second dielectric material layer according to various embodiments of the present disclosure.

[0022] Figure 16 is a vertical cross-sectional view of a first exemplary structure including an opening formed through a second dielectric material layer in a second sub-pixel region according to various embodiments of the present disclosure.

[0023] Figure 17 is a vertical cross-sectional view of a first exemplary structure including an upper portion of a spacer layer formed in a second sub-pixel region according to various embodiments of the present disclosure.

[0024] Figure 18 is a vertical cross-sectional view of a first exemplary structure including an active region formed over an upper portion of a spacer layer and over a second dielectric material layer in a second sub-pixel region according to various embodiments of the present disclosure.

[0025] Figure 19 is a vertical cross-sectional view of a first exemplary structure including a second light-emitting epitaxial semiconductor structure in a pixel region according to various embodiments of the present disclosure.

[0026] Figure 20 is a vertical cross-sectional view of a first exemplary structure after an etching process for removing a second dielectric material layer according to various embodiments of the present disclosure.

[0027] Figure 21 is a vertical cross-sectional view of a first exemplary structure including a continuous third dielectric material layer formed over a lower portion of a spacer layer, over side and top surfaces of a mesa portion of a first light-emitting epitaxial semiconductor structure, and over side and top surfaces of a mesa portion of a second light-emitting epitaxial semiconductor structure according to various embodiments of the present disclosure.

[0028] Figure 22 is a vertical cross-sectional view of a first exemplary structure including a patterned mask formed over a continuous third dielectric material layer according to various embodiments of the present disclosure.

[0029] Figure 23is a vertical cross - sectional view of a first exemplary structure according to various embodiments of the present disclosure, including an opening formed through a third dielectric material layer in a third sub - pixel region.

[0030] Figure 24 is a vertical cross - sectional view of a first exemplary structure according to various embodiments of the present disclosure, including an upper portion of a spacer layer formed in a third sub - pixel region.

[0031] Figure 25 is a vertical cross - sectional view of a first exemplary structure according to various embodiments of the present disclosure, including an upper portion of a spacer layer formed in a third sub - pixel region and an active region above a third dielectric material layer.

[0032] Figure 26 is a vertical cross - sectional view of a first exemplary structure according to various embodiments of the present disclosure, including a third light - emitting epitaxial semiconductor structure in a pixel region.

[0033] Figure 27 is a vertical cross - sectional view of a first exemplary structure according to various embodiments of the present disclosure after an etching process for removing a third dielectric material layer.

[0034] Figure 28 is a vertical cross - sectional view of a first exemplary structure according to various embodiments of the present disclosure, including a continuous fourth dielectric material layer formed above a lower portion of a spacer layer, above side surfaces and upper surfaces of mesa portions of a first light - emitting epitaxial semiconductor structure, above side surfaces and upper surfaces of mesa portions of a second light - emitting epitaxial semiconductor structure, and above side surfaces and upper surfaces of mesa portions of a third light - emitting epitaxial semiconductor structure.

[0035] Figure 29 is a vertical cross - sectional view of a first exemplary structure according to various embodiments of the present disclosure, including a contact electrode above an upper surface of a mesa portion of each sub - pixel of a multicolor pixel.

[0036] Figure 30 is a vertical cross - sectional view of an alternative structure according to various embodiments of the present disclosure, including a reflector layer above a fourth dielectric material layer.

[0037] Figure 31 is a vertical cross - sectional view of a first exemplary structure according to various embodiments of the present disclosure, including an isolation trench surrounding a multicolor light - emitting device pixel.

[0038] Figure 32 is a vertical cross - sectional view of an alternative structure according to various embodiments of the present disclosure, including an isolation trench surrounding each sub - pixel.

[0039] Figure 33A vertical cross - sectional view of a second exemplary structure according to various embodiments of the present disclosure, including a continuous first - conductivity - type doped semiconductor material layer formed on an initial growth substrate.

[0040] Figure 34 A vertical cross - sectional view of a second exemplary structure according to various embodiments of the present disclosure, including a continuous first dielectric material layer formed on the continuous first - conductivity - type doped semiconductor material layer.

[0041] Figure 35 A vertical cross - sectional view of a second exemplary structure according to various embodiments of the present disclosure, including an opening formed through the first dielectric material layer in a sub - pixel region.

[0042] Figure 36 A vertical cross - sectional view of a second exemplary structure according to various embodiments of the present disclosure, including a discontinuous first - conductivity - type semiconductor material layer formed within an opening in the first dielectric material layer in a first sub - pixel region.

[0043] Figure 37 A vertical cross - sectional view of a second exemplary structure according to various embodiments of the present disclosure, including a superlattice structure and a spacer layer formed on an upper portion of the first - conductivity - type semiconductor material layer in a first sub - pixel region.

[0044] Figure 38 A vertical cross - sectional view of a second exemplary structure according to various embodiments of the present disclosure, including a first light - emitting epitaxial semiconductor structure in a pixel region.

[0045] Figure 39 A vertical cross - sectional view of a second exemplary structure according to various embodiments of the present disclosure, including a multi - color light - emitting pixel including a first light - emitting epitaxial semiconductor structure, a second light - emitting epitaxial semiconductor structure, and a third light - emitting epitaxial semiconductor structure.

[0046] Figure 40 A vertical cross - sectional view showing a backplane and an initial growth substrate on which multi - color light - emitting sub - pixels are formed.

[0047] Figure 41 A vertical cross - sectional view showing that the initial growth substrate is vertically moved relative to the backplane according to an embodiment of the present disclosure such that each of the "diode - side bonding material portion and backplane - side bonding material portion" faces and contacts each other.

[0048] Figure 42 A vertical cross - sectional view showing a laser irradiation process using a detachment laser beam according to various embodiments of the present disclosure.

[0049] Figure 43is a vertical cross - sectional view of an initial growth substrate and a backplane after applying a compressive force that causes deformation of a bonding material portion according to an embodiment of the present disclosure.

[0050] Figure 44 is a vertical cross - sectional view of a bonding laser irradiation process that causes reflow and subsequent bonding of a pair that matches the "diode - side bonding material portion and the backplane - side bonding material portion" according to an embodiment of the present disclosure.

[0051] Figure 45 is a vertical cross - sectional view of a multi - color light - emitting device pixel transferred from an initial growth substrate to a backplane according to an embodiment of the present disclosure.

[0052] Figure 46 is a vertical cross - sectional view of a part of a display including a multi - color light - emitting device pixel mounted on a backplane according to an embodiment of the present disclosure.

[0053] Figure 47 is a vertical cross - sectional view of a part of a display including a multi - color light - emitting device pixel mounted on a backplane according to another embodiment of the present disclosure.

[0054] Figure 48 is a vertical cross - sectional view of a part of a display including a multi - color light - emitting device pixel mounted on a backplane according to another embodiment of the present disclosure. Detailed Description

[0055] As stated above, the present disclosure relates to light - emitting devices, and more particularly to displays including multi - color light - emitting device sub - pixels derived from a common growth substrate and methods of manufacturing the same. Various aspects thereof are described below. Throughout the drawings, like elements are described with the same reference numerals. Unless otherwise explicitly stated, elements with the same reference numerals are assumed to have the same material composition. The drawings are not drawn to scale. Multiple examples of an element may be replicated where a single example of the element is shown, unless it is explicitly described or otherwise clearly indicated that there is no replication of the element. Ordinal numbers such as "first", "second", and "third" are only used to identify similar elements, and different ordinal numbers may be employed in the specification and claims of the present disclosure.

[0056] As used herein, "light-emitting device" refers to any device configured to emit light, and includes, but is not limited to, light-emitting diodes (LEDs), lasers such as vertical-cavity surface-emitting lasers (VCSELs), and any other electronic device configured to emit light when a suitable electrical bias is applied. The light-emitting device can be a vertical structure (e.g., vertical LED) (wherein the p-side contact and the n-side contact are located on opposite sides of the structure), or can be a lateral structure (wherein the p-side contact and the n-side contact are located on the same side of the structure). As used herein, "light-emitting device assembly" refers to an assembly in which at least one light-emitting device is structurally fixed relative to a carrier structure, which can include, for example, a substrate, a matrix, or any other structure configured to provide stable mechanical support for the at least one light-emitting device.

[0057] Display devices according to various embodiments of the present disclosure can be formed by transferring an array of light-emitting devices from an initial growth substrate to a target substrate. The target substrate can be any substrate on which it is desired to form various types of devices in any configuration. In an illustrative example, the target substrate can be a backplane substrate (such as an active or passive matrix backplane substrate for driving light-emitting devices). As used herein, "backplane" or "backplane substrate" refers to any substrate configured to have a plurality of devices fixed thereon. In one embodiment, the center-to-center spacing of adjacent light-emitting devices on the backplane substrate can be the same as the center-to-center spacing of adjacent light-emitting devices on the growth substrate. The light-emitting devices can include a plurality of light-emitting devices (such as a set of two light-emitting devices, one configured to emit blue light and one configured to emit green light). The light-emitting devices can include a set of three light-emitting devices, one configured to emit blue light, one configured to emit green light, and one configured to emit red light. As used herein, "adjacent light-emitting devices" refers to a plurality (two or more) of light-emitting devices that are located in a closer position compared to at least another light-emitting device.

[0058] A plurality of light-emitting devices configured to emit different colors of light can be fabricated on the initial growth substrate. As used herein, "initial growth substrate" refers to a substrate that is processed to form devices thereon or therein. The devices can include light-emitting devices and / or sensor devices (e.g., photodetectors) and / or any other electronic device. The light-emitting device can be any type of light-emitting device (i.e., vertical light-emitting diode, lateral light-emitting diode, or any combination thereof). The light-emitting devices can be formed as an array on the initial growth substrate.

[0059] A display device, such as a direct-view display, can be formed by an ordered array of pixels located on a target substrate, such as a backplane. Each pixel can include a set of sub-pixels that emit light of a corresponding peak wavelength. For example, a pixel can include a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Each sub-pixel can include one or more light-emitting devices (e.g., LEDs) that emit light of a specific wavelength. Each pixel is driven by a backplane circuit such that any combination of colors within a color gamut can be displayed for each pixel on the display. A display panel can be formed by a process of soldering, or otherwise electrically attaching, the LED sub-pixels to bonding pads located on the backplane. The bonding pads are electrically driven by the backplane circuit and other driving electronics.

[0060] In an embodiment of the present disclosure, a method for manufacturing a multi-color (e.g., three-color or more) direct-view display can be performed by using light-emitting devices that emit different colors of light in each pixel. In one embodiment, bulk (e.g., planar) LEDs can be used. Each LED can have a corresponding blue light-emitting active region, a green light-emitting active region, and a red light-emitting active region to form a blue sub-pixel, a green sub-pixel, and a red sub-pixel in each pixel.

[0061] A display device, such as a direct-view display device, can be manufactured by epitaxially growing various material layers (such as III-V semiconductor material layers including group III nitrides) over a suitable initial growth substrate (e.g., a wafer). Standard semiconductor manufacturing techniques can be used to process the material layers to provide a plurality of light-emitting devices (e.g., LEDs) on the initial growth substrate, where each light-emitting device can include semiconductor material regions of opposite conductive types (i.e., n-type and p-type) surrounding an active region, and the active region can include one or more quantum wells. The quantum wells are designed to emit light of a specific peak wavelength, which can range from ultraviolet to visible red light. Subsequently, the light-emitting devices are transferred from the initial growth substrate to the backplane to form a display panel.

[0062] In the case of a multicolor display panel, typically, light-emitting devices of the same type are grown on respective initial growth substrates, and each initial growth substrate is processed under conditions optimized to provide light emission at a specific peak wavelength (e.g., red, green, or blue). Then, using separate transfer steps, the individual light-emitting devices from each initial growth substrate are transferred to a backplane to provide a display panel having multicolor (e.g., red, green, and blue) light-emitting device subpixels. This process can lead to many complexities (including the need to perform multiple separate transfer steps with strict alignment tolerances). In the case of lower-resolution displays where the pixel pitch is relatively large (e.g., 40 - 50 μm or greater), the alignment tolerance may be on the order of 2 μm, which does not pose a particularly significant challenge. However, for higher-resolution displays where the pixel pitch is 20 μm or less and the size of the light-emitting device subpixels is 5 μm or less, an alignment tolerance of 2 μm becomes unacceptable.

[0063] Another approach to manufacturing a multicolor light-emitting device (e.g., a micro-LED) display includes providing multiple monochromatic light-emitting panels having different peak wavelengths (e.g., red, green, and blue) and using an optical engine to combine the light from the respective monochromatic light-emitting panels to create a multicolor display. However, the incorporation of multiple light-emitting panels and the associated optical engine can increase the complexity and size of the final product, which may make it unsuitable for some applications (such as in displays for wearable devices).

[0064] Various embodiments include multicolor (e.g., red, green, and blue) direct-view display devices in which light-emitting structures configured to emit respective different wavelengths of light can be fabricated on the same initial growth substrate using selective area growth. This can enable the manufacture of a display via a single transfer process for transferring the light-emitting structures emitting different colors from the initial growth substrate to a single backplane, thus avoiding the alignment tolerances of multiple transfer steps or the issues associated with using three different monochromatic light-emitting panels. Accordingly, a high-resolution multicolor LED display device can be provided that can include a pixel density of 1100 pixels per inch (PPI) or greater on a single display panel.

[0065] Figure 1A substrate 101 is shown on which an array of pixels 25 is fabricated. Each pixel 25 may include a plurality of sub-pixels (10B, 10G, 10R), and each of the plurality of sub-pixels (10B, 10G, 10R) includes a light-emitting epitaxial semiconductor structure configured to emit light of a corresponding wavelength. Each pixel 25 may include light-emitting diodes that emit light of different wavelengths. For example, each pixel 25 may include at least one first-type light-emitting diode 10B (such as at least one blue light-emitting diode) that emits light having a first peak wavelength (such as a peak wavelength in the range of 400 nm to 495 nm), at least one second-type light-emitting diode 10G (such as at least one green light-emitting diode) that emits light having a second peak wavelength (such as a peak wavelength in the range of 495 nm to 570 nm), and at least one third-type light-emitting diode 10R (such as at least one red light-emitting diode 10R) that emits light having a third peak wavelength (such as a peak wavelength in the range of 600 nm to 700 nm). The number of each type of light-emitting diode within the pixel 25 may be selected to provide a suitable level of illumination for each pixel. For example, a plurality of epitaxial semiconductor structure LEDs that emit green light, blue light, and red light are formed in each corresponding green light-emitting region, blue light-emitting region, and red light-emitting region of the pixel 25. Optionally, a portion of the pixel 25 may be left empty as a repair site for later attaching a repair LED device to compensate for a defective or non-functional LED device 10G, 10B, or 10R in a particular pixel 25. The empty space may be used for one or more additional functions of the display device (such as touch recognition using an infrared photodiode sensor).

[0066] In some embodiments, a dense array of pixels 25 may be formed on the substrate 101, and each pixel 25 has the same structure. Each pixel 25 may include a plurality of sub-pixels (10B, 10G, 10R) configured to emit light of different peak wavelengths. As described in more detail below, each pixel 25 may be electrically isolated from adjacent pixels 25 in the array. In some embodiments, the spacing separating adjacent pixels 25 in the array may be less than about 10 μm (such as less than about 5 μm (e.g., ≤2 μm), including less than about 1 μm) (such as 500 nm to 2 μm).

[0067] In some embodiments, the size and / or shape of the respective sub-pixels (10B, 10G, 10R) within each pixel 25 may be customized to compensate for differences in the light output efficiency of the different sub-pixels. For example, in Figure 1In the embodiment shown, the red-emitting sub-pixel 10R has a size along a horizontal direction that is greater than the corresponding sizes of the blue-emitting sub-pixel 10B and the green-emitting sub-pixel 10G. This larger red-emitting LED area relative to each of the blue-emitting LED area and the green-emitting LED area can help compensate for the relatively low light output efficiency of the red-emitting LED. Other suitable configurations for the sub-pixels (10B, 10G, 10R) are within the scope of the present disclosure. In some embodiments, the space separating adjacent sub-pixels (10B, 10G, 10R) within the pixel 25 can be less than about 10 μm (such as, less than about 5 μm (e.g., ≤2 μm), including less than about 1 μm). Each sub-pixel (i.e., LED) can have a corresponding length and width of 20 μm or less (such as, 500 nm to 10 μm, including 1 μm to 5 μm). In one embodiment, the corresponding lengths and widths of the blue sub-pixel and the green sub-pixel can be equal to each other (i.e., providing square blue sub-pixels and green sub-pixels having the same horizontal area), and the length of the red sub-pixel can be greater than its width and greater than the lengths of the green sub-pixel and the blue sub-pixel (i.e., providing a rectangular red sub-pixel having a larger horizontal area than the blue sub-pixel and the green sub-pixel).

[0068] As will be described in more detail below, at least a portion of the pixel 25 including the sub-pixels (10B, 10G, 10R) can subsequently be transferred from the substrate 101 to a backplane to provide a display device (such as, a direct-view display device). As used herein, a direct-view display device is a display device in which each pixel 25 includes at least one light source that generates light from within that can be seen by an observer when a suitable electrical bias is applied. Thus, a direct-view display device does not require a backlight unit or liquid crystal material. As used herein, a "multi-color" pixel is a pixel that can emit light of different peak wavelengths depending on the application of an electrical bias and is thus inherently capable of displaying multiple colors.

[0069] Referring to Figure 2 , a first exemplary structure is shown, which is a structure in the process for manufacturing the monolithic multi-color light-emitting device pixel 25 as shown in Figure 1 . As used herein, a "structure in the process" is a structure that is subsequently modified to fabricate the final structure. Figure 2 is a vertical cross-section of the pixel region 250 of the substrate 101 on which the multi-color light-emitting pixel 25 can be subsequently formed. The pixel region 250 can include sub-pixel regions 110B, 110G, and 110B, and the corresponding blue-emitting sub-pixel 10B, green-emitting sub-pixel 10G, and red-emitting sub-pixel 10R can be subsequently formed in the sub-pixel regions 110B, 110G, and 110B. Thus, Figure 2The vertical cross-sectional view shows a portion of the substrate 101 taken along line A-A' in Figure 1 before forming the array of multi-color light-emitting device pixels 25.

[0070] Referring again to Figure 2 , the substrate 101 (which may also be referred to as the initial growth substrate 101) may include a single-crystal material layer that serves as a template for subsequent epitaxial growth of a semiconductor material layer on the substrate 101. Any single-crystal material layer can be used for the initial growth substrate 101 as long as a compound semiconductor material (such as a group III-V compound semiconductor material) can be epitaxially grown from the flat surface of the single-crystal material layer. As used herein, a "flat" surface refers to a two-dimensional Euclidean surface without curvature. The initial growth substrate 101 may include a single-crystal material (such as Al 2 O 3 (sapphire), diamond, Si, Ge, GaN, AlN, SiC, InN, GaP, GaAsP, GaAs, InP, ZnO, ZnS, and ZnSe). For example, the growth substrate 101 may include sapphire (i.e., single-crystal aluminum oxide) having a suitable surface orientation.

[0071] In some embodiments, the initial growth substrate 101 may include a single-side polished (SSP) sapphire substrate or a patterned sapphire substrate (PSS) having a patterned (e.g., rough) growth surface. Optionally, a patterned silicon or silicon carbide substrate may be used. Bumps, pits, and / or angled cuts may or may not be provided on the flat surface of the growth substrate 101 to facilitate epitaxial growth of the semiconductor material layer on the growth substrate 101 and / or to facilitate separation of the semiconductor device structure (e.g., an LED) from the growth substrate 101 in a subsequent separation process.

[0072] In an alternative embodiment, the growth substrate 101 may include an undoped semiconductor buffer layer 101B on the top surface of the sapphire base 101S. The undoped semiconductor buffer layer 101B may include an undoped (e.g., intrinsic) group III-V compound semiconductor material epitaxially grown on the sapphire base 101S, and the undoped (e.g., intrinsic) group III-V compound semiconductor material may include a group III nitride semiconductor material. In one non-limiting example, the buffer layer 101B may be composed of GaN. Other suitable group III-V compound semiconductor material buffer layers 101B that can be epitaxially grown on the sapphire base 101S are within the scope of this disclosure.

[0073] Figure 3FIG. 0 is a vertical cross-sectional view of a first exemplary structure according to various embodiments of the present disclosure, including a continuous doped semiconductor material layer 103 formed over an initial growth substrate 101. As used herein, a "continuous" layer refers to an unpatterned material layer that is not divided into multiple parts. Thus, each point in the continuous layer can be completely connected to a point located within the continuous layer. The continuous doped semiconductor material layer 103 may include a group III-V compound semiconductor material epitaxially grown on the initial growth substrate 101 (e.g., on an undoped semiconductor buffer layer 101B if present, or on a sapphire base 101S if the buffer layer 101B is omitted), and the group III-V compound semiconductor material may include a group III nitride semiconductor material. In one non-limiting example, the continuous doped semiconductor material layer 103 may be composed of GaN. Other suitable group III-V compound semiconductor materials that can be epitaxially grown on the initial growth substrate 101 are within the scope of the present disclosure. The continuous doped semiconductor material layer 103 may have a doping of a first conductivity type, which may be n-type or p-type. The continuous doped semiconductor material layer 103 may also be referred to as a first conductivity type doped semiconductor layer 103. The continuous doped semiconductor material layer 103 may be formed over the initial growth substrate 101 using a suitable deposition process, such as metalorganic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy (LPE), metalorganic molecular beam epitaxy (MOMBE), and / or atomic layer deposition (ALD). Other suitable deposition processes are within the scope of the present disclosure.

[0074] In some embodiments, the continuous doped semiconductor material layer 103 may be formed over the surface of the initial growth substrate 101 via initial nucleation growth of a group III-V compound semiconductor material (e.g., GaN), and the initial growth substrate 101 may be undoped or lightly doped with a dopant of the first conductivity type. Then, a group III-V compound semiconductor material having a relatively high concentration of a dopant of the first conductivity type may be epitaxially grown during the initial nucleation growth. The continuous doped semiconductor material layer 103 may be formed of a single crystal group III-V compound semiconductor material (e.g., single crystal GaN). In some embodiments, the thickness of the continuous doped semiconductor material layer 103 may be between about 2 μm and about 5 μm, but larger and smaller thicknesses of the continuous doped semiconductor material layer 103 may be utilized.

[0075] Figure 41 is a vertical cross-sectional view of a first exemplary structure including a continuous superlattice structure 105 formed on a continuous doped semiconductor material layer 103 according to various embodiments of the present disclosure. The continuous superlattice structure 105 may be formed of alternating layers of a first III-V compound semiconductor material and a second III-V compound semiconductor material having a different composition than the first III-V compound semiconductor material. In one non-limiting embodiment, the first III-V compound semiconductor material may be In x Ga 1-x N, wherein 0.01≤x≤0.1 (eg, x≈0.03), and the second III-V compound semiconductor material may be GaN. Figure 4 In the embodiment shown in FIG. 1 , a first example of a continuous superlattice structure 105 may include a continuous InGaN layer 104 formed on a continuous doped semiconductor material layer 103. 1 , and formed on the continuous InGaN layer 104 1 The continuous GaN layer 106 1 . Additional instances of the continuous superlattice structure 105 may be subsequently formed such that the continuous superlattice structure 105 may include a layer stack comprising n instances of “a continuous InGaN layer 104 and a continuous GaN layer on top of the continuous InGaN layer”, where n may be an integer in the range between 20 and 50.

[0076] Each of the alternating layers 104, 106 of the first III-V compound semiconductor material and the second III-V compound semiconductor material forming the continuous superlattice structure 105 may be formed using a suitable deposition process as described above. In some embodiments, each layer 104 of the first III-V compound semiconductor material (e.g., InGaN) may have a thickness in the range of 1-2 nm, and each layer 106 of the second III-V compound semiconductor material (e.g., GaN) may have a thickness in the range of 4-6 nm, but it will be understood that greater or lesser thicknesses may be utilized. In various embodiments, the continuous superlattice structure 105 may be used to suppress dislocation density in epitaxial semiconductor material layers subsequently formed above the continuous superlattice structure 105.

[0077] Figure 5is a vertical cross-sectional view of a first exemplary structure according to various embodiments of the present disclosure, including an optional continuous lower spacer layer 107a formed on a continuous superlattice structure 105. The continuous lower spacer layer 107a may include a III-V compound semiconductor material (such as, GaN) epitaxially grown on the continuous superlattice structure 105. The continuous lower spacer layer 107a may be formed using a suitable deposition process as described above. In some embodiments, the continuous lower spacer layer 107a may be formed of the same III-V compound semiconductor material (e.g., GaN) as the continuous doped semiconductor material layer 103. The continuous lower spacer layer 107a may be lightly doped with a dopant of a first conductivity type. In some embodiments, the average concentration of the dopant of the first conductivity type present in the continuous lower spacer layer 107a may be less than the average concentration of the dopant of the first conductivity type present in the continuous doped semiconductor material layer 103. The continuous lower spacer layer 107a may have a thickness in the range of about 5-25 nm, but larger and smaller thicknesses may be utilized. Optionally, the continuous lower spacer layer 107a may be omitted.

[0078] Figure 6 is a vertical cross-sectional view of a first exemplary structure according to various embodiments of the present disclosure, including a continuous first dielectric material layer 109 formed on the continuous lower spacer layer 107a (if the continuous lower spacer layer 107a exists, or directly on the superlattice 105 due to the omission of the continuous lower spacer layer 107a). The continuous first dielectric material layer 109 may be composed of a suitable dielectric material, such as alumina, silica, silicon nitride, etc., including combinations thereof. The continuous first dielectric material layer 109 may be deposited using a suitable deposition process, such as plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDPCVD), atomic layer deposition (ALD), and combinations thereof. Other suitable deposition processes are within the scope of the present disclosure. The continuous first dielectric material layer 109 may have a thickness in the range of about 10-100 nm, but larger and smaller thicknesses may also be utilized. In various embodiments, the upper surface of the continuous first dielectric material layer 109 may be composed of a dielectric material that minimizes or prevents the epitaxial growth of a III-V compound semiconductor material on the continuous first dielectric material layer 109.

[0079] Figure 7is a vertical cross - sectional view of a first exemplary structure including a patterned mask 108 formed over a continuous first dielectric material layer 109 according to various embodiments of the present disclosure. The patterned mask 108 can be formed by the following steps: applying a layer of photoresist over the continuous first dielectric material layer 109 and lithographically patterning the layer of photoresist to form one or more openings therethrough by photolithographic exposure and development. Each opening through the patterned mask 108 can be located in a sub - pixel region 110B of the first exemplary structure, and the sub - pixel region 110B corresponds to a position where the same type of sub - pixel 10B (i.e., a sub - pixel that emits the same color of light) can be formed subsequently. In Figure 7 embodiments, the one or more openings are located in the sub - pixel region 110B where a blue - emitting sub - pixel 10B can be formed subsequently, but it will be understood that the one or more openings can alternatively be located in the sub - pixel region 110G or 110R. Thus, although Figure 7 a single opening through the patterned mask 108 is shown, it will be understood that each pixel region 250 of the first exemplary structure can include an opening through the patterned mask 108, and the opening can be located in the sub - pixel region 110B where the same type of sub - pixel 10B is to be formed subsequently.

[0080] The size and shape of each opening through the patterned mask 108 can be selected to optimize the shape and size of the epitaxial semiconductor structure to be formed subsequently in the sub - pixel region 110B. For example, the opening through the patterned mask 108 can have a polygonal shape (such as, triangle, rectangle (including square), pentagon, hexagon, heptagon, etc.), a circular shape, an oval shape, and / or any other generally curved closed two - dimensional shape. In an illustrative example, the openings in the patterned mask 108 can have a rectangular shape, a triangular shape, a hexagonal shape, or a circular shape arranged as a two - dimensional periodic array.

[0081] Figure 8 is a vertical cross - sectional view of a first exemplary structure including an opening 111 formed through a first dielectric material layer 109 according to various embodiments of the present disclosure. Referring to Figure 7 and Figure 8 , an etching process (such as, a wet etching process and / or a dry etching process) can be performed to remove the portions of the continuous first dielectric material layer 109 exposed through the openings in the patterned mask 108, thereby transferring the pattern of the openings in the patterned mask 108 to the first dielectric material layer 109. The upper surface of the lower spacer layer 107a can be exposed at the bottom of each opening 111 in the first dielectric material layer 109. Thus, the first dielectric material layer 109 can be used as a patterned growth mask, and the patterned growth mask can be in each sub - pixel region 110B of the same type (e.g.,Figure 8 In the embodiment of, selective epitaxial growth of a semiconductor structure is achieved over the exposed upper surface of the lower spacer layer 107a within the sub-pixel region 110B corresponding to the position of the blue-emitting sub-pixel 10B. After the etching process, the patterned mask 108 can be removed using a suitable process (such as by ashing and / or dissolving in a solvent).

[0082] Figure 9 is a vertical cross-sectional view of a first exemplary structure according to various embodiments of the present disclosure, including an optional upper spacer layer 107b formed over a continuous lower spacer layer 107a. The upper spacer layer 107b can include a III-V compound semiconductor material. In various embodiments, the upper spacer layer 107b can be composed of the same material as the material of the continuous lower spacer layer 107a (such as GaN lightly doped with a dopant of a first conductivity type). The upper spacer layer 107b can be formed using a selective semiconductor deposition process that grows semiconductor material from a semiconductor surface and does not grow semiconductor material from a dielectric surface. Thus, the semiconductor material of the upper spacer layer 107b can be selectively grown over the exposed surface of the continuous lower spacer layer 107a within the opening 111 in the first dielectric material layer 109, but there may be minimal growth or no growth of the semiconductor material of the upper spacer layer 107b over the upper surface of the first dielectric material layer 109. The upper spacer layer 107b can fill at least a portion of the opening 111 in the first dielectric material layer 109. In some embodiments, the upper spacer layer 107b can completely fill the opening 111 in the first dielectric material layer 109 such that the upper surface of the upper spacer layer 107b can be substantially coplanar with the upper surface of the first dielectric material layer 109. The upper spacer layer 107b can be a discontinuous layer of semiconductor material that contacts the continuous lower spacer layer 107a and is laterally surrounded by the first dielectric material layer 109. Although Figure 9 a single discontinuous upper spacer layer 107b is shown, it will be understood that each pixel region 250 of the first exemplary structure can include a discontinuous upper spacer layer 107b located within the sub-pixel region 110B where the same type of sub-pixel 10B is subsequently formed. The lower spacer layer 107b and each upper spacer layer 107a can be considered to form a single spacer layer 107 that includes a continuous lower spacer layer portion 107a and one or more discontinuous upper spacer layer portions 107b having pedestal-like structures located within each sub-pixel region 110B of the first exemplary structure.

[0083] The upper spacer layer 107b may have a thickness in the range of about 5 - 25 nm, although greater and smaller thicknesses may be utilized. In some embodiments, the combined thickness of the continuous lower spacer layer 107a and upper spacer layer 107b may be between about 10 nm and about 50 nm, although greater and smaller thicknesses may be employed. Optionally, the upper spacer layer 107b may be omitted.

[0084] Figure 10 is a vertical cross - sectional view of a first exemplary structure in accordance with various embodiments of the present disclosure that includes an active region 116 formed over the upper spacer layer 107b (if present). The active region 116 may be formed using a selective semiconductor deposition process that grows semiconductor material from a semiconductor surface and does not grow semiconductor material from a dielectric surface. Thus, the active region 116 may be selectively grown over the upper surface of the upper spacer layer 107b within the sub - pixel region 110B.

[0085] The active region 116 may include at least one semiconductor material that emits radiation (e.g., visible or ultraviolet radiation) when a suitable electrical bias is applied. In one embodiment, the active region 116 includes an optically active compound semiconductor layer stack configured to emit light. For example, the active region 116 may include at least one quantum well (QW) structure (112, 114) that emits light when an electrical bias is applied across it. Each quantum well structure (112, 114) of the active region 116 may include at least one example of a first bandgap semiconductor layer 112 having a first bandgap and a second bandgap semiconductor layer 114 having a second bandgap greater than the first bandgap located over the first bandgap semiconductor layer 112. In some embodiments, the active region 116 may include a layer stack that includes multiple examples of quantum well structures that include a first bandgap semiconductor layer 112 and a second bandgap semiconductor layer 114 over the first bandgap semiconductor layer 112 (such as between 2 and 10 repeated examples of "first bandgap semiconductor layer 112 and second bandgap semiconductor layer 114"). Optionally, the active region 116 may include any other suitable semiconductor layer or stack of layers for light - emitting diode applications as long as it can be selectively grown over the upper spacer layer 107b. The collection of all layers within the active region 116 is referred to herein as the active layer.

[0086] In various embodiments, each of the respective layers 112, 114 forming the active region 116 may include a mesa structure that includes a horizontally flat upper surface and tapered sidewalls 113, 115 extending from the horizontally flat upper surface toward the upper surface of the first dielectric material layer 109. As used herein, a "tapered" element refers to an element that is neither horizontal nor vertical. The width dimension of the mesa structure (i.e., the dimension of the mesa structure in the horizontal plane) may increase between the horizontally flat upper surface of the mesa structure and the upper surface of the first dielectric material layer 109. Each of the respective layers 112, 114 forming the active region 116 may also include a bottom surface. The bottom surfaces of the layers 112, 114 of the active region may be coplanar with each other and may each contact the upper surface of the first dielectric material layer 109. The bottom surface of the lowermost layer of the active region 116 (i.e., Figure 10 layer 112 in

[0087] In Figure 10 the embodiment shown in z Ga 1-z N, where 0.18 ≤ z ≤ 0.22 (e.g., z ≈ 0.2), and the second bandgap semiconductor layer 114 may be composed of GaN. The first bandgap semiconductor layer 112 may have a thickness in the range of about 2.5 - 5 nm (i.e., between the horizontally flat upper surface of layer 112 and the upper surface of the material layer immediately below), and the second bandgap semiconductor layer 114 may have a thickness in the range of about 15 - 20 nm (i.e., between the horizontally flat upper surface of layer 114 and the upper surface of the material layer immediately below), although greater and smaller thicknesses may be employed.

[0088] Although Figure 10 a single blue - emitting active region 116 is shown in

[0089] Figure 11is a vertical cross - sectional view of a first exemplary structure according to various embodiments of the present disclosure, including an optional electron - blocking layer 117 formed over an active region 116. The electron - blocking layer 117 may be composed of a doped semiconductor material having a doping of a second conductivity type, which is opposite to the first conductivity type. For example, if the first conductivity type is n - type, the second conductivity type is p - type. If the first conductivity type is p - type, the second conductivity type is n - type. In some embodiments, the electron - blocking layer 117 may include a doped AlGaN material having a doping of the second conductivity type. The electron - blocking layer 117 may be formed using a selective semiconductor deposition process that grows semiconductor material from a semiconductor surface and does not grow semiconductor material from a dielectric surface. Thus, the electron - blocking layer 117 may be selectively grown over the upper surface and the exposed sidewalls 115 of the active region 116 within the sub - pixel region 110B.

[0090] The electron - blocking layer 117 may include a mesa structure that includes a horizontally flat upper surface and tapered sidewalls 118 extending from the horizontally flat upper surface toward the upper surface of the first dielectric material layer 109. The tapered sidewalls 118 of the electron - blocking layer 117 may laterally surround the active region 116. The width dimension of the mesa structure may increase between the horizontally flat upper surface of the mesa structure and the upper surface of the first dielectric material layer 109. The electron - blocking layer 117 may also include a bottom surface that contacts the upper surface of the first dielectric material layer 109 and may be coplanar with the bottom surface of each of the layers 112, 114 of the active region 116. The electron - blocking layer 117 may have a thickness in the range of about 15 - 30 nm (i.e., between the horizontally flat upper surface of the electron - blocking layer 117 and the horizontally flat upper surface of the active region 116), but larger and smaller thicknesses may be employed.

[0091] The electron - blocking layer 117 may serve as a current - blocking layer for the angled facets (i.e., sidewalls 113, 115) of the active region 116, thereby reducing leakage current through the angled facets of the active region 116. This may enable uniform emission of light with a narrow full - width at half - maximum (FWHM) from a flat c - plane region within the active region 116 and may also facilitate parallel emission of light along the vertical direction from a plurality of light - emitting sub - pixels 10B, 10G, 10R of the display device.

[0092] Although a single electron - blocking layer 117 is shown in Figure 11 it will be understood that each pixel region 250 of the first exemplary structure may include an electron - blocking layer 117 over the blue - emitting active region 116 within the sub - pixel region 110B of the pixel region 250.

[0093] Figure 12is a vertical cross-sectional view of a first exemplary structure according to various embodiments of the present disclosure, including a doped semiconductor material layer 119 formed over an electron blocking layer 117. The doped semiconductor material layer 119 may be composed of a doped semiconductor material having a doping of a second conductivity type. In some embodiments, the doped semiconductor material layer 119 may include a doped group III-V compound semiconductor material (such as, GaN) having a doping of a second conductivity type. The doped semiconductor material layer 119 may also be referred to as a second conductivity type doped semiconductor material layer 119. The doped semiconductor material layer 119 may be formed using a selective semiconductor deposition process that grows semiconductor material from a semiconductor surface and does not grow semiconductor material from a dielectric surface. Thus, the doped semiconductor material layer 119 may selectively epitaxially grow over the upper surface and exposed sidewalls 118 of the electron blocking layer 117 within the sub-pixel region 110B. In embodiments where the electron blocking layer 117 is omitted, the doped semiconductor material layer 119 may selectively epitaxially grow over the upper surface and exposed sidewalls 115 of the active region 116 within the sub-pixel region 110B.

[0094] The doped semiconductor material layer 119 may include a mesa structure that includes a horizontally flat upper surface 122 and tapered sidewalls 120 extending from the horizontally flat upper surface toward the upper surface of the first dielectric material layer 109. The tapered sidewalls 120 of the doped semiconductor material layer 119 may laterally surround the electron blocking layer 117 and the active region 116. The width dimension of the mesa structure may increase between the horizontally flat upper surface of the mesa structure and the upper surface of the first dielectric material layer 109. The doped semiconductor material layer 119 may also include a bottom surface that contacts the upper surface of the first dielectric material layer 109 and may be coplanar with the bottom surfaces of each of the layers 112, 114 of the active region 116 and the bottom surface of the electron blocking layer 117. The doped semiconductor material layer 119 may have a thickness in the range of about 50 - 200 nm (i.e., between the horizontally flat upper surface 122 of the doped semiconductor material layer 119 and the horizontally flat upper surface of the electron blocking layer 117, or in embodiments where the electron blocking layer 117 is not included, between the horizontally flat upper surface 122 of the doped semiconductor material layer 119 and the horizontally flat upper surface of the active region 116). Larger and smaller thicknesses of the doped semiconductor material layer 119 are within the scope contemplated by the present disclosure.

[0095] Although in Figure 12A doped semiconductor material layer 119 is shown above the electron blocking layer 117, but it will be understood that in embodiments where the electron blocking layer 117 is not included within the sub-pixel region 110B of the pixel region 250, each pixel region 250 of the first exemplary structure may include a doped semiconductor material layer 119 directly on the active region 116.

[0096] Referring again to Figure 12 , a first light-emitting epitaxial semiconductor structure 10B (i.e., a sub-pixel structure) is shown in the pixel region 250 of the first exemplary structure. The first light-emitting epitaxial semiconductor structure 10B can be capable of emitting light of a first color (e.g., blue) when an appropriate electrical bias is applied. The first light-emitting epitaxial structure 10B includes an optional first conductivity type doped semiconductor layer 103 above an initial growth substrate 101, an optional superlattice structure 105 above the first conductivity type doped semiconductor layer 103, and a spacer layer 107 above the superlattice structure 105. The spacer layer 107 includes a lower portion 107a and an upper portion 107b that forms a pedestal-like structure above the lower portion 107a of the spacer layer 107. A first dielectric material layer 109 is located above the upper surface of the lower portion 107a of the spacer layer 107 and laterally surrounds the upper portion 107b of the spacer layer 107.

[0097] The first light-emitting epitaxial semiconductor structure 10B further includes a mesa portion 121 above a portion of the dielectric material layer 109 and the upper portion 107b of the spacer layer 107. The mesa portion 121 includes a flat horizontal lower surface in contact with the upper portion 107b of the spacer layer 107 and the upper surface of the first dielectric material layer 109, a flat horizontal upper surface 122, and a tapered outer sidewall 120 extending between the flat horizontal upper surface 122 and the flat horizontal lower surface of the mesa portion 121. Figure 12 The mesa portion 121 in the embodiment of Figure 12 includes an active region 116, an optional electron blocking layer 117 above the upper surface of the active region 116 and laterally surrounding the active region 116, and a second conductivity type doped semiconductor material layer 119 above the upper surface of the electron blocking layer 117 and laterally surrounding the electron blocking layer 117. A plurality of mesa portions 121 as shown in

[0098] Figure 13 is a vertical cross-sectional view of the first exemplary structure after an etching process to remove the first dielectric material layer 109 according to various embodiments of the present disclosure. Referring to Figure 13, a selective etching process can be used to selectively remove the first dielectric material layer 109 and expose the upper surface of the lower portion 107a of the spacer layer 107. The etching process can also provide a recess 123 between the mesa portion 123 of the first light-emitting epitaxial semiconductor structure 10B and the upper surface of the lower portion 107a of the spacer layer 107. The recess 123 can surround the upper portion 107b of the spacer layer 107. The recess 123 can be vertically defined by the upper surface of the lower portion 107a of the spacer layer 107 and the lower surface of the mesa portion 121 (e.g., the bottom surfaces of the active region 116, the electron blocking layer 117, and the second conductivity type doped semiconductor material layer 119). The upper portion 107b of the spacer layer 107 can form the sidewall of the recess 123.

[0099] In various embodiments, a suitable etching process (such as a wet chemical etching process) can be used to remove the first dielectric material layer 109. In some embodiments, the etching process can include multiple etching steps using different etching chemistries optimized to selectively remove materials from the first exemplary structure. For example, an initial etching can be performed to remove residual semiconductor material from above the upper surface of the first dielectric material layer 109. The initial etching can be a wet chemical etching (such as KOH-based etching). The mesa portion 121 of the first light-emitting epitaxial semiconductor structure 10B can optionally be covered by a mask during the etching process to protect the mesa portion 121 from being etched. Then, subsequent anisotropic etching steps can be used to remove the first dielectric material layer 109. The subsequent etching steps can utilize different etching chemistries (such as HF-based etching and / or hot phosphoric acid-based etching) optimized to selectively remove the dielectric material of the first dielectric material layer 109 (e.g., silicon oxide and / or silicon nitride, respectively).

[0100] Figure 14is a vertical cross - sectional view of a first exemplary structure according to various embodiments of the present disclosure, including a continuous second dielectric material layer 209 formed over a lower portion 107a of the spacer layer 107 and over side surfaces 120 and upper surfaces 122 of a mesa portion 121 of the first light - emitting epitaxial semiconductor structure 10B. The continuous second dielectric material layer 209 may be composed of a suitable dielectric material, such as alumina, silicon oxide, silicon nitride, etc., including combinations thereof. The material of the continuous second dielectric material layer 209 may be the same or different from the material of the first dielectric material layer 109. A suitable deposition process may be used to deposit the continuous second dielectric material layer 209, such as plasma - enhanced chemical vapor deposition (PECVD), high - density plasma chemical vapor deposition (HDPCVD), atomic layer deposition (ALD), and combinations thereof. Other suitable deposition processes are within the scope of the present disclosure. In various embodiments, a conformal deposition process (such as ALD) may be used to deposit the continuous second dielectric material layer 209. Thus, the continuous second dielectric material layer 209 may have a relatively uniform thickness over the upper surface of the lower portion 107a of the spacer layer 107, over the side surfaces of the upper portion 107a of the spacer layer 107 and the bottom surface of the mesa portion 121 exposed in the recess 121, and over the tapered outer sidewalls 120 and the horizontal flat upper surface 122 of the mesa portion 121. In some embodiments, the continuous second dielectric material layer 209 may completely fill the recess 123 between the bottom surface of the mesa portion 123 and the spacer layer 107. The continuous second dielectric material layer 209 may have a thickness in the range of about 10 - 100 nm, but larger and smaller thicknesses may also be utilized. In various embodiments, the upper surface of the continuous second dielectric material layer 209 may be composed of a dielectric material that minimizes or prevents epitaxial growth of III - V compound semiconductor materials over the continuous second dielectric material layer 209 in subsequent deposition processes.

[0101] Figure 15 is a vertical cross - sectional view of a first exemplary structure according to various embodiments of the present disclosure, including a patterned mask 208 formed over the continuous second dielectric material layer 209. The patterned mask 208 may be formed as described above with reference to Figure 7 formation. The patterned mask 208 may include openings therethrough in each sub - pixel region 110G of the first exemplary structure, where each sub - pixel region 110G corresponds to a location where the same type of sub - pixel 10G may be subsequently formed therein. In Figure 15In an embodiment, one or more openings are located in a sub-pixel region 110G where a green-emitting sub-pixel 10G may be formed subsequently. However, it will be understood that the one or more openings may alternatively be located in a sub-pixel region 110R where a red-emitting sub-pixel 10R may be formed subsequently, or in a sub-pixel region 110B where a blue-emitting sub-pixel 10E may be formed subsequently. Although Figure 15 shows a single opening through the patterned mask 208, it will be understood that each pixel region 250 of the first exemplary structure may include an opening through the patterned mask 208, where the opening may be located in a sub-pixel region 110G where the same type of sub-pixel 10G is to be formed subsequently. As previously referenced Figure 7 It is described that the size and shape of each opening through the patterned mask 208 can be selected to optimize the shape and size of the epitaxial semiconductor structure to be formed subsequently in the sub-pixel region 110G.

[0102] Figure 16 is a vertical cross-sectional view of a first exemplary structure including an opening 211 formed through a second dielectric material layer 209 according to various embodiments of the present disclosure. Referring to Figure 15 and Figure 16 , as described above with reference to Figure 7 and Figure 8 The etching process can remove the portion of the continuous second dielectric material layer 209 exposed through the opening in the patterned mask 208 and form one or more openings 211 through the second dielectric material layer 209. The lower portion 107a of the spacer layer 107 can be exposed at the bottom of each opening 211. The remaining portion of the second dielectric material layer 209 can be used as a patterned growth mask, and the patterned growth mask can achieve selective epitaxial growth of a semiconductor structure above the exposed upper surface of the lower spacer layer 107a in each sub-pixel region 110G (e.g., the sub-pixel region 110G corresponding to the position of the green-emitting sub-pixel 10G). After the etching process, the patterned mask 208 can be removed using a suitable process (such as by ashing and / or dissolving with a solvent).

[0103] Figure 17 is a vertical cross-sectional view of a first exemplary structure including an upper portion 107b of a spacer layer 107 formed in a sub-pixel region 110G according to various embodiments of the present disclosure. In various embodiments, the upper portion 107b of the spacer layer 107 formed in the sub-pixel region 110G can be composed of the same material as the lower portion 107a and / or the upper portion 107a of the spacer layer 107 located in the sub-pixel 10B. In some embodiments, the upper portion 107b of the spacer layer 107 formed in the sub-pixel region 110G can include GaN lightly doped with a dopant of a first conductivity type. As described above with reference to Figure 9As described above, the upper portion 107b of the spacer layer 107 within the sub-pixel region 110G can be selectively grown over the exposed surface of the continuous lower spacer layer 107a within the opening 211 in the second dielectric material layer 209, but there may be minimal or no growth of the semiconductor material over the upper surface of the second dielectric material layer 209. The upper portion 107b of the spacer layer 107 within the sub-pixel region 110G can fill at least a portion of the opening 211 in the second dielectric material layer 209 and can completely fill the opening 211 such that the upper surface of the upper spacer layer 107b can be substantially coplanar with the upper surface of the second dielectric material layer 209. Although Figure 17 a single discontinuous upper portion 107b of the spacer layer 107 is shown in the sub-pixel region 110G in

[0104] Figure 18 FIG. [FIG. number not provided in the original], it will be understood that each pixel region 250 of the first exemplary structure can include a discontinuous upper portion 107b of the spacer layer 107 within the sub-pixel region 110G where the green light-emitting sub-pixel 10G is subsequently formed therein. Optionally, the lower and / or upper portions of the spacer layer 107 can be omitted.

[0105] FIG. [FIG. number not provided in the original] is a vertical cross-sectional view of a first exemplary structure including an active region 216 formed over an upper portion 107b of a spacer layer 107 and a second dielectric material layer 209 within a sub-pixel region 110G. Similar to the active region 116 of the blue light-emitting sub-pixel 10B described above, the active region 216 can be formed using a selective semiconductor deposition process capable of achieving selective growth of the active region 216 over the upper portion 107b of the spacer layer 107 within the sub-pixel region 110G. The active region 216 within the sub-pixel region 110G can have a structure similar or identical to the active region 116 of the sub-pixel 10B. For example, the active region 216 can include an optically active compound semiconductor layer stack configured to emit light (such as at least one of the above-described quantum well (QW) structures (212, 214) that emits light when an electrical bias is applied across it). In some embodiments, the active region 216 can include a layer stack including multiple examples of quantum well structures including a first bandgap semiconductor layer 212 and a second bandgap semiconductor layer 214 over the first bandgap semiconductor layer 212 (such as between 2 and 10 repeats of "first bandgap semiconductor layer 212 and second bandgap semiconductor layer 214"). Optionally, the active region 216 can include any other suitable semiconductor layer or stack of layers for light-emitting diode applications as long as it can be selectively grown over the upper portion 107b of the spacer layer 107. The collection of all layers within the active region 216 can also be referred to as the active layer.In various embodiments, each of the respective layers 212, 214 forming the active region 216 may include a mesa structure that includes a horizontally flat upper surface and tapered sidewalls 213, 215 extending from the horizontally flat upper surface toward the upper surface of the second dielectric material layer 209. The width dimension of the mesa structure (i.e., the dimension of the mesa structure in the horizontal plane) may increase between the horizontally flat upper surface of the mesa structure and the upper surface of the second dielectric material layer 209. Each of the respective layers 212, 214 forming the active region 216 may also include a bottom surface, wherein the bottom surfaces of the layers 212, 214 may be coplanar with each other and may each contact the upper surface of the second dielectric material layer 209. The bottom surface of the lowermost layer of the active region 216 (i.e., Figure 18 layer 212 in

[0106] In Figure 18 the embodiment shown in z Ga 1-z N, where 0.22 ≤ z ≤ 0.24 (e.g., x ≈ 0.23), and the second bandgap semiconductor layer 214 may be composed of GaN. In various embodiments, the first bandgap semiconductor layer 212 within the active region 216 formed in the sub-pixel region 110G may have a higher indium concentration than the first bandgap semiconductor layer 112 within the blue light emitting sub-pixel 10B. The first bandgap semiconductor layer 212 may have a thickness in the range of about 2.5 - 5 nm (i.e., between the horizontally flat upper surface of the layer 212 and the upper surface of the material layer immediately below), and the second bandgap semiconductor layer 214 may have a thickness in the range of about 15 - 20 nm (i.e., between the horizontally flat upper surface of the layer 214 and the upper surface of the material layer immediately below), although larger and smaller thicknesses may be employed.

[0107] Although Figure 18 a single green light emitting active region 216 is shown in

[0108] Figure 19is a vertical cross-sectional view of a first exemplary structure including a second light-emitting epitaxial semiconductor structure 10G in a pixel region 250 according to various embodiments of the present disclosure. The second light-emitting epitaxial semiconductor structure 10G may form a green light-emitting sub-pixel 10G within the pixel region 250. The green light-emitting sub-pixel 10G may be formed by depositing an optional electron blocking layer 217 over an upper surface and sidewalls 215 of the active region 216, and depositing a second conductivity type doped semiconductor material layer 219 over an upper surface and sidewalls 218 of the electron blocking layer 217. The electron blocking layer 217 may include a doped semiconductor material (such as, AlGaN) having a doping of the second conductivity type. The second conductivity type doped semiconductor material layer 219 may include a doped III-V compound semiconductor material (such as, GaN) having a doping of the second conductivity type.

[0109] The electron blocking layer 217 and the second conductivity type doped semiconductor material layer 219 may have a structure and / or dimensions similar to or the same as those of the electron blocking layer 117 and the second conductivity type doped semiconductor material layer 119 of the first light-emitting epitaxial semiconductor structure 10B (i.e., the blue light-emitting sub-pixel 10B). Specifically, the electron blocking layer 217 may form a mesa structure including a horizontal flat upper surface over the active region 216 and a tapered sidewall 218 extending from the horizontal flat upper surface of the electron blocking layer 217 toward the upper surface of the second dielectric material layer 209 and laterally surrounding the active region 216. The second conductivity type doped semiconductor material layer 219 may form a mesa structure including a horizontal flat upper surface 222 over the electron blocking layer 217 and a tapered sidewall 220 extending from the horizontal flat upper surface 222 of the second conductivity type doped semiconductor material layer 219 toward the upper surface of the second dielectric material layer 209 and laterally surrounding the electron blocking layer 217.

[0110] Accordingly, the second light-emitting epitaxial semiconductor structure 10G (i.e., the green light-emitting sub-pixel 10G) includes an optional first conductivity type doped semiconductor layer 103 over an initial growth substrate 101, an optional superlattice structure 105 over the first conductivity type doped semiconductor layer 103, and a spacer layer 107 over the superlattice structure 105. The spacer layer 107 includes a lower portion 107a and a discontinuous upper portion 107b forming a pedestal-like structure over the lower portion 107a of the spacer layer 107. The second dielectric material layer 209 is located over the upper surface of the lower portion 107a of the spacer layer 107 and laterally surrounds the upper portion 107b of the spacer layer 107.

[0111] The second light-emitting epitaxial semiconductor structure 10G further includes a mesa portion 221 over a portion of the second dielectric material layer 209 and an upper portion 107b of the spacer layer 107. The mesa portion 221 includes a flat horizontal lower surface in contact with the upper portion 107b of the spacer layer 107 and the upper surface of the second dielectric material layer 209, a flat horizontal upper surface 222, and a tapered outer sidewall 220 extending between the flat horizontal upper surface 222 and the flat horizontal lower surface of the mesa portion 221. Figure 19 In the embodiment of Figure 19 , the mesa portion 221 includes an active region 216 configured to emit green light when a suitable electrical bias is applied, an optional electron blocking layer 217 over the upper surface of the active region 216 and laterally surrounding the active region 216, and a second conductivity type doped semiconductor material layer 219 over the upper surface of the electron blocking layer 217 and laterally surrounding the electron blocking layer 217. The mesa portion 221 of the second light-emitting epitaxial semiconductor structure 10G may be laterally spaced apart from the mesa portion 121 of the first light-emitting semiconductor structure 10B. A plurality of mesa portions 221 as shown in Figure 19 may be formed over corresponding upper portions 107b of the spacer layer 107, wherein each mesa portion 221 may form a part of the second light-emitting epitaxial semiconductor structure 10G located within the pixel region 250 of the first exemplary structure.

[0112] Figure 20 is a vertical cross-sectional view of the first exemplary structure after an etching process for removing the second dielectric material layer 209, in accordance with various embodiments of the present disclosure. Referring to Figure 20 , an etching process may be used to selectively remove the second dielectric material layer 209 from the upper surface of the lower portion 107a of the spacer layer 107 and over the mesa portion 121 of the first light-emitting epitaxial semiconductor structure 10B. As shown in Figure 20 , the etching process may also expose recesses 123 and 223 between the lower portion 107a of the spacer layer 107 and the corresponding mesa portions 121 and 221 of the first light-emitting epitaxial semiconductor structure 10B and the second light-emitting epitaxial semiconductor structure 10G. As described above with reference to Figure 13 , a suitable etching process (such as a wet chemical etching process) may be used to remove the second dielectric material layer 209. For example, an initial etching (such as a potassium hydroxide (KOH)-based etching) may be performed to remove residual semiconductor material from above the upper surface of the second dielectric material layer 209. The mesa portion 221 of the second light-emitting epitaxial semiconductor structure 10G may optionally be covered with a mask to protect the mesa portion 221 from being etched. Then, subsequent anisotropic etching steps (such as a hydrofluoric acid (HF)-based etching and / or a hot phosphoric acid-based etching) may be used to remove the second dielectric material layer 209.

[0113] Figure 21is a vertical cross - sectional view of a first exemplary structure according to various embodiments of the present disclosure, including a continuous third dielectric material layer 309 formed over a lower portion 107a of the spacer layer 107, over side surfaces 120 and upper surface 122 of a mesa portion 121 of the first light - emitting epitaxial semiconductor structure 10B, and over side surfaces 220 and upper surface 222 of a mesa portion 221 of the second light - emitting epitaxial semiconductor structure 10G. The continuous third dielectric material layer 309 may be composed of a suitable dielectric material, such as alumina, silicon oxide, silicon nitride, etc., including combinations thereof. The material of the continuous third dielectric material layer 309 may be the same or different from the material of the first dielectric material layer 109 and / or the second dielectric material layer 209. The continuous third dielectric material layer 309 may be deposited using the above - mentioned suitable deposition processes. In various embodiments, a conformal deposition process (such as ALD) may be used to deposit the continuous third dielectric material layer 309. Thus, the continuous third dielectric material layer 309 may have a relatively uniform thickness over the upper surface of the lower portion 107a of the spacer layer 107 and over the surfaces of the mesa portions 121 and 221. In some embodiments, the continuous third dielectric material layer 309 may completely fill the recesses 123 and 223 between the bottom surfaces of the mesa portions 121 and 221 and the spacer layer 107. The continuous third dielectric material layer 309 may have a thickness in the range of about 10 - 100 nm, but larger and smaller thicknesses may also be utilized. In various embodiments, the upper surface of the continuous third dielectric material layer 309 may be composed of a dielectric material that minimizes or prevents epitaxial growth of III - V compound semiconductor materials over the continuous third dielectric material layer 309 in subsequent deposition processes.

[0114] Figure 22 is a vertical cross - sectional view of a first exemplary structure according to various embodiments of the present disclosure, including a patterned mask 308 formed over the continuous third dielectric material layer 309. The patterned mask 308 may be formed as described above with reference to Figure 7 formation. The patterned mask 308 may include openings through the patterned mask 308 in each sub - pixel region 110R of the first exemplary structure, and each sub - pixel region 110R corresponds to a position where the same type of sub - pixel 10R may be formed subsequently. In Figure 22 embodiments, one or more openings are in a sub - pixel region 110RG where a red - emitting sub - pixel 10G may be formed subsequently. Although Figure 22 shows a single opening through the patterned mask 308, it will be understood that each pixel region 250 of the first exemplary structure may include an opening through the patterned mask 208, and the opening may be located in a sub - pixel region 110R where the same type of sub - pixel 10R is formed subsequently. As previously referred to Figure 7As described above, the size and shape of each opening passing through the patterned mask 308 can be selected to optimize the shape and size of the epitaxial semiconductor structure to be formed in the sub-pixel region 110R subsequently.

[0115] Figure 23 is a vertical cross-sectional view of a first exemplary structure including an opening 311 formed through a third dielectric material layer 309 according to various embodiments of the present disclosure. Referring to Figure 22 and Figure 23 , as described above with reference to Figure 7 and Figure 8 The etching process can remove the portions of the continuous third dielectric material layer 309 exposed through the openings in the patterned mask 308 and form one or more openings 311 through the second dielectric material layer 309. The lower portion 107a of the spacer layer 107 can be exposed at the bottom of each opening 311. The remaining portion of the second dielectric material layer 309 can be used as a patterned growth mask, which can enable selective epitaxial growth of a semiconductor structure over the exposed upper surface of the lower spacer layer 107a within each sub-pixel region 110R (e.g., the sub-pixel region 110R corresponding to the position of the red-emitting sub-pixel 10R). After the etching process, the patterned mask 308 can be removed using a suitable process (such as by ashing and / or dissolving with a solvent).

[0116] Figure 24 is a vertical cross-sectional view of a first exemplary structure including an upper portion 107b of a spacer layer 107 formed within a sub-pixel region 110R according to various embodiments of the present disclosure. In various embodiments, the upper portion 107b of the spacer layer 107 formed in the sub-pixel region 110R can be composed of the same material as the lower portion 107a and / or the upper portion 107a of the spacer layer 107 located in the sub-pixel 10B and / or the sub-pixel 10G. In some embodiments, the upper portion 107b of the spacer layer 107 formed in the sub-pixel region 110R can include GaN lightly doped with a dopant of a first conductivity type. As described above with reference to Figure 9 The upper portion 107b of the spacer layer 107 within the sub-pixel region 110R can be selectively grown over the exposed surface of the continuous lower spacer layer 107a within the opening 311 in the third dielectric material layer 309, but there may be minimal growth or no growth of semiconductor material over the upper surface of the third dielectric material layer 309. The upper portion 107b of the spacer layer 107 within the sub-pixel region 110R can fill at least a portion of the opening 311 in the third dielectric material layer 309 and can completely fill the opening 311 such that the upper surface of the upper spacer layer 107b can be substantially coplanar with the upper surface of the third dielectric material layer 309. Although Figure 24A single discontinuous upper portion 107b of the spacer layer 107 is shown in the sub-pixel region 110R in [reference], but it will be understood that each pixel region 250 of the first exemplary structure may include a discontinuous upper portion 107b of the spacer layer 107 located in the sub-pixel region 110R where a red light-emitting sub-pixel 10R is subsequently formed therein.

[0117] Figure 25 is a vertical cross-sectional view of a first exemplary structure according to various embodiments of the present disclosure, including an upper portion 107b of a spacer layer 107 formed within a sub-pixel region 110R and an active region 316 over a third dielectric material layer 309. As in the case of the active regions 116 and 216 of the blue light-emitting sub-pixel 10B and the green light-emitting sub-pixel 10G, respectively, the active region 316 in the sub-pixel region 110R can be formed using a selective semiconductor deposition process that enables selective growth of the active region 316 over the upper portion 107b of the spacer layer 107 within the sub-pixel region 110R. The active region 316 in the sub-pixel region 110R can have a structure similar to or the same as the active region 116 of the sub-pixel 10B and / or the active region 216 in the sub-pixel 10G. For example, the active region 316 can include an optically active compound semiconductor layer stack configured to emit light (such as at least one of the above-described quantum well (QW) structures (312, 314) that emits light when an electrical bias is applied across it). In some embodiments, the active region 316 can include a layer stack that includes multiple examples of quantum well structures, the quantum well structures including a first bandgap semiconductor layer 312 and a second bandgap semiconductor layer 314 over the first bandgap semiconductor layer 312 (such as between 2 and 10 repeating examples of "the first bandgap semiconductor layer 312 and the second bandgap semiconductor layer 314"). Optionally, the active region 316 can include any other suitable semiconductor layer or stack of layers for light-emitting diode applications as long as it can be selectively grown over the upper portion 107b of the spacer layer 107. The collection of all layers within the active region 316 can also be referred to as the active layer.

[0118] In various embodiments, each of the corresponding layers 312, 314 forming the active region 316 can form a mesa structure that includes a horizontally flat upper surface and tapered sidewalls 313, 315 extending from the horizontally flat upper surface toward the upper surface of the third dielectric material layer 309. The width dimension of the mesa structure (i.e., the dimension of the mesa structure in the horizontal plane) can increase between the horizontally flat upper surface of the mesa structure and the upper surface of the third dielectric material layer 309. Each of the corresponding layers 312, 314 forming the active region 316 can also include a bottom surface, wherein the bottom surfaces of the layers 312, 314 can be coplanar with each other and can each contact the upper surface of the third dielectric material layer 309. The lowermost layer of the active region 316 (i.e., Figure 25The bottom surface of the layer 312) therein may additionally contact the upper portion 107b of the spacer layer 107.

[0119] In Figure 25 the embodiment shown, the active region 316 formed in the sub-pixel region 110R may be configured to emit red light having a peak wavelength in the range of 600 nm to 700 nm when an appropriate electrical bias is applied across it. In a non-limiting illustrative example of a red light-emitting active region 316 composed of a quantum well structure, the first bandgap semiconductor layer 312 may be composed of In z Ga 1-z N, where 0.24 ≤ z ≤ 0.27 (e.g., x ≈ 0.25), and the second bandgap semiconductor layer 314 may be composed of GaN. In various embodiments, the first bandgap semiconductor layer 312 within the active region 316 formed in the sub-pixel region 110R may have a higher indium concentration than the first bandgap semiconductor layer 112 within the blue light-emitting sub-pixel 10B and the first bandgap semiconductor layer 212 within the green light-emitting sub-pixel 10G. The first bandgap semiconductor layer 312 may (i.e., between the horizontal flat upper surface of the layer 312 and the upper surface of the material layer immediately below) have a thickness in the range of about 2.5 - 5 nm, and the second bandgap semiconductor layer 314 may (i.e., between the horizontal flat upper surface of the layer 314 and the upper surface of the material layer immediately below) have a thickness in the range of about 15 - 20 nm, but larger and smaller thicknesses may be employed.

[0120] Figure 26 is a vertical cross-sectional view of a first exemplary structure of a third light-emitting epitaxial semiconductor structure 10R included in the pixel region 250 according to various embodiments of the present disclosure. The third light-emitting epitaxial semiconductor structure 10R may form a red light-emitting sub-pixel 10R within the pixel region 250. Thus, the first light-emitting epitaxial semiconductor structure 10B, the second light-emitting epitaxial semiconductor structure 10G, and the third light-emitting epitaxial semiconductor structure 10R may together form a multi-color pixel 25. A plurality of such as Figure 26The multicolor pixel 25 shown in [the figure] can be located above the initial growth substrate 101. The third light-emitting epitaxial semiconductor structure 10R can be formed by forming an optional electron blocking layer 317 over the upper surface and sidewalls 315 of the active region 316, and forming a second-conductivity-type doped semiconductor material layer 319 over the upper surface and sidewalls 318 of the electron blocking layer 317. The electron blocking layer 317 can include a doped semiconductor material (such as, AlGaN), which has a doping of the second conductivity type. The second-conductivity-type doped semiconductor material layer 319 can include a doped group III-V compound semiconductor material (such as, GaN), which has a doping of the second conductivity type. The electron blocking layer 317 and the second-conductivity-type doped semiconductor material layer 319 can have structures and / or dimensions similar to or the same as those of the electron blocking layer 117 and the second-conductivity-type doped semiconductor material layer 119 of the first light-emitting epitaxial semiconductor structure 10B (i.e., the blue light-emitting sub-pixel 10B) and / or the electron blocking layer 217 and the second-conductivity-type doped semiconductor material layer 219 of the second light-emitting epitaxial semiconductor structure 10G (i.e., the green light-emitting sub-pixel 10B). Specifically, the electron blocking layer 317 can form a mesa structure, which includes a horizontal flat upper surface over the active region 316 and a tapered sidewall 318 that extends from the horizontal flat upper surface of the electron blocking layer 317 toward the upper surface of the third dielectric material layer 309 and laterally surrounds the active region 316. The second-conductivity-type doped semiconductor material layer 319 can form a mesa structure, which includes a horizontal flat upper surface 322 over the electron blocking layer 317 and a tapered sidewall 320 that extends from the horizontal flat upper surface 322 of the second-conductivity-type doped semiconductor material layer 319 toward the upper surface of the third dielectric material layer 309 and laterally surrounds the electron blocking layer 317.

[0121] Therefore, the third light-emitting epitaxial semiconductor structure 10R (i.e., the red light-emitting sub-pixel 10R) includes an optional first-conductivity-type doped semiconductor layer 103 above the initial growth substrate 101, an optional superlattice structure 105 above the first-conductivity-type doped semiconductor layer 103, and a spacer layer 107 above the superlattice structure 105. The spacer layer 107 includes a lower portion 107a and a discontinuous upper portion 107b that forms a pedestal-like structure above the lower portion 107a of the spacer layer 107. The third dielectric material layer 309 is located above the upper surface of the lower portion 107a of the spacer layer 107 and laterally surrounds the upper portion 107b of the spacer layer 107.

[0122] The third light-emitting epitaxial semiconductor structure 10R further includes a mesa portion 321 over a part of the third dielectric material layer 309 and an upper portion 107b of the spacer layer 107. The mesa portion 321 includes a flat horizontal lower surface in contact with the upper portion 107b of the spacer layer 107 and the upper surface of the third dielectric material layer 309, a flat horizontal upper surface 322, and a tapered outer sidewall 320 extending between the flat horizontal upper surface 322 and the flat horizontal lower surface of the mesa portion 321. Figure 25 In the embodiment of Figure 25 , the mesa portion 321 includes an active region 316 configured to emit red light when a suitable electrical bias is applied, an optional electron blocking layer 317 over the upper surface of the active region 316 and laterally surrounding the active region 316, and a second conductivity type doped semiconductor material layer 319 over the upper surface of the electron blocking layer 317 and laterally surrounding the electron blocking layer 317. The mesa portion 321 of the third light-emitting epitaxial semiconductor structure 10R may be laterally spaced apart from the mesa portion 221 of the second light-emitting semiconductor structure 10G and the mesa portion 121 of the first light-emitting semiconductor structure 10B. A plurality of mesa portions 321 as shown in Figure 26 may be formed over corresponding upper portions 107b of the spacer layer 107, wherein each mesa portion 321 may form a part of the third light-emitting epitaxial semiconductor structure 10G of the multicolor pixel 25 of the first exemplary structure.

[0123] In the above manufacturing method, the first (i.e., blue) light-emitting epitaxial semiconductor structure 10B is formed before forming the second (i.e., green) light-emitting epitaxial semiconductor structure 10G, and the first (i.e., blue) light-emitting epitaxial semiconductor structure 10B and the second (i.e., green) light-emitting epitaxial semiconductor structure 10G are formed before forming the third (i.e., red) light-emitting epitaxial semiconductor structure 10R. Due to the differences in the compositions of the corresponding light-emitting epitaxial semiconductor structures 10B, 10G, and 10R, this manufacturing sequence may be advantageous. Specifically, the first (i.e., blue) light-emitting epitaxial semiconductor structure 10B typically includes the lowest indium concentration in the active region 116 of the structure 10B. The second (i.e., green) light-emitting epitaxial semiconductor structure 10G typically has a relatively high indium concentration in the active region 216, and the third (i.e., red) light-emitting epitaxial semiconductor structure 10R typically has the highest indium concentration in the active region 316. By forming the semiconductor structures with relatively high indium concentrations after forming the semiconductor structures with relatively low indium concentrations, the high-temperature processes for the structures with relatively high indium concentrations can be minimized. It is believed that the high-temperature processes for indium-containing semiconductor structures may result in indium loss in the structures. Therefore, by minimizing the high-temperature processes for the red light-emitting semiconductor structure and the green light-emitting semiconductor structure, the indium loss in these structures can be minimized and the performance of the multicolor light-emitting device can be improved.

[0124] Figure 27is a vertical cross-sectional view of a first exemplary structure after an etching process for removing the third dielectric material layer 309, according to various embodiments of the present disclosure. Referring to Figure 27 , the third dielectric material layer 209 can be selectively removed from above the upper surface of the lower portion 107a of the spacer layer 107, the mesa portion 121 of the first light-emitting epitaxial semiconductor structure 10B, and the mesa portion 221 of the second light-emitting epitaxial semiconductor structure 10G using an etching process. The etching process can also expose the recesses 123, 223, and 323 between the lower portion 107a of the spacer layer 107 and the corresponding mesa portions 121, 221, and 331 of the first light-emitting epitaxial semiconductor structure 10B, the second light-emitting epitaxial semiconductor structure 10G, and the third light-emitting epitaxial semiconductor structure 10R, respectively. As referred to above with respect to Figure 13 , the third dielectric material layer 309 can be removed using a suitable etching process (such as, a wet chemical etching process). For example, an initial etching (such as, a potassium hydroxide (KOH)-based etching) can be performed to remove residual semiconductor material from above the upper surface of the second dielectric material layer 309. The mesa portion 321 of the third light-emitting epitaxial semiconductor structure 10R can optionally be covered with a mask to protect the mesa portion 321 from being etched. Then, a subsequent anisotropic etching step (such as, a hydrofluoric acid (HF)-based etching and / or a hot phosphoric acid-based etching) can be used to remove the third dielectric material layer 309.

[0125] Figure 28is a vertical cross-sectional view of a first exemplary structure including a continuous fourth dielectric material layer 350 formed over a lower portion 107a of the spacer layer 107, over side surfaces 120 and upper surfaces 122 of mesa portions 121 of the first light-emitting epitaxial semiconductor structure 10B, over side surfaces 220 and upper surfaces 222 of mesa portions 221 of the second light-emitting epitaxial semiconductor structure 10G, and over side surfaces 320 and upper surfaces 322 of mesa portions 321 of the third light-emitting epitaxial semiconductor structure 10R. The continuous fourth dielectric material layer 350 may be composed of a suitable dielectric material such as alumina, silica, silicon nitride, etc., including combinations thereof. The material of the continuous fourth dielectric material layer 350 may be the same as or different from the materials of the first dielectric material layer 109, the second dielectric material layer 209, and / or the third dielectric material layer 309. The continuous fourth dielectric material layer 350 may be deposited using a suitable deposition process as described above. In various embodiments, a conformal deposition process (such as, ALD) may be used to deposit the continuous fourth dielectric material layer 350. Thus, the continuous fourth dielectric material layer 350 may have a relatively uniform thickness over the upper surface of the lower portion 107a of the spacer layer 107 and over the surfaces of the mesa portions 121, 221, and 321. In some embodiments, the continuous fourth dielectric material layer 350 may completely fill the recesses 123, 223, and 323 between the bottom surfaces of the mesa portions 121, 221, and 321 and the spacer layer 107. The continuous fourth dielectric material layer 350 may have a thickness in the range of about 10 - 100 nm, but larger and smaller thicknesses may also be utilized. In one embodiment, the heights (i.e., thicknesses) of the three mesa portions 121, 221, and 321 may be the same. In another embodiment, the heights (i.e., thicknesses) of the three mesa portions 121, 221, and 321 may be different from each other. For example, the mesa portion 321 of the red sub-pixel 10R may be thicker than the mesa portions 121 and / or 221 of the blue sub-pixel 10B and / or the green sub-pixel 10G, respectively.

[0126] Figure 29 is a vertical cross-sectional view of a first exemplary structure including contact electrodes 351 over upper surfaces 122, 222, and 322 of mesa portions 121, 221, and 321 of each of the sub-pixels 10B, 10G, and 10R in a multicolor pixel 25 according to various embodiments of the present disclosure. Referring to Figure 29 , a photoresist layer ( Figure 29(not shown in the figure) can be applied over the fourth dielectric material layer 350 and can be lithographically patterned to provide openings over the upper surfaces 122, 222, and 322 of the mesa portions 121, 221, and 321 in each of the sub-pixels 10B, 10G, and 10R. In some embodiments, the openings through the photoresist layer can overlie the central portions of the upper surfaces 122, 222, and 322 of the mesa portions 121, 221, and 321 and can not overlie the peripheral portions of the upper surfaces 122, 222, and 322 adjacent to the respective sidewalls 120, 220, and 320 of the mesa portions 121, 221, and 321. An etching process can be performed to remove the unmasked portions of the fourth dielectric material layer 350 using the photoresist layer as an etching mask, thereby forming openings through the fourth dielectric material layer 350 that expose portions of the upper surfaces 122, 222, and 322 of the mesa portions 121, 221, and 321 in each of the sub-pixels 10B, 10G, and 10R. The photoresist layer can then be removed, for example, by ashing.

[0127] Then, a conductive material can be deposited over the fourth dielectric material layer 350 and over the exposed upper surfaces 122, 222, and 322 of the mesa portions 121, 221, and 321 in each of the sub-pixels 10B, 10G, and 10R. In some embodiments, the conductive material can include a reflective metal (such as, aluminum, silver, copper, and / or gold). Other suitable conductive materials (such as, conductive transparent oxides (e.g., indium tin oxide or aluminum zinc oxide)) are within the scope of the present disclosure. The conductive material can be deposited, for example, by sputtering. Other suitable deposition processes are within the scope of the present disclosure. The conductive material can fill each of the openings through the fourth dielectric material layer 350 located over the upper surfaces 122, 222, and 322 of the mesa portions 121, 221, and 321 of the sub-pixels 10B, 10G, and 10R. An excess of the conductive material can be removed from the upper surface of the fourth dielectric material layer 350 using a planarization process (such as, chemical mechanical polishing (CMP)), leaving discontinuous contact electrodes 351 in contact with the upper surfaces 122, 222, and 322 of the mesa portions 121, 221, and 321 in each of the sub-pixels 10B, 10G, and 10R. As Figure 29 shown, each contact electrode 351 can be laterally surrounded by the fourth dielectric material layer 350 and can have an upper surface that is substantially coplanar with the upper surface of the fourth dielectric material layer 350. In an alternative embodiment, the fourth dielectric material layer 350 can be omitted, and the contact electrodes 351 can be formed on the upper surfaces 122, 222, and 322 of the mesa portions 121, 221, and 321 in each of the sub-pixels 10B, 10G, and 10R by conductive layer deposition followed by lithography and etching.

[0128] Each of the contact electrodes 351 can be in electrical contact with the second-conductive-type semiconductor material layers 119, 219, and 319 of the corresponding sub-pixels 10B, 10G, and 10R of the first exemplary structure. In embodiments where the second-conductive-type semiconductor material layers 119, 219, and 319 comprise a p-type semiconductor material, the contact electrodes 351 can provide anode contact electrodes 351 for the corresponding sub-pixels 10B, 10G, and 10R of the multi-color pixel 25. As discussed above, in various embodiments, the contact electrodes 351 can contact the second-conductive-type semiconductor material layers 119, 219, and 319 in the central regions of the horizontally flat upper surfaces 122, 222, and 322 of the second-conductive-type semiconductor material layers 119, 219, and 319, and can not contact the second-conductive-type semiconductor material layers 119, 219, and 319 in the peripheral regions of the horizontally flat upper surfaces 122, 222, 322 adjacent to the sidewalls 120, 220, and 320 of the second-conductive-type semiconductor material layers 119, 219, and 310. This can facilitate current injection from the tops of the mesa faces 121, 221, and 321 through the active regions 116, 216, and 316 rather than through the faceted sidewalls of the mesa faces 121, 221, and 321, which can provide improved light extraction efficiency.

[0129] Optionally, at least one metal (i.e., conductive) barrier layer (not shown) can be formed as a component of the contact electrode 351. In this case, the at least one metal barrier layer can be located at the flat surface of the contact electrode 351 and can be used to assist in subsequent bonding of solder material over the corresponding sub-pixels 10B, 10G, and 10R. The at least one metal barrier layer can comprise a metal or metal alloy (i.e., metallization) material layer (i.e., a set of metal layers disposed between the conductive bonding structure and the die) that can be used for under-bump metallurgy (UBM). In one embodiment, the at least one metal barrier layer can comprise a diffusion barrier layer and an adhesion promoter layer. Exemplary materials for the diffusion barrier layer include titanium, titanium-tungsten, titanium-platinum, or tantalum. Exemplary materials for the adhesion promoter layer include tungsten, platinum, or a stack of tungsten and platinum. Any other known under-bump metallurgy in the art can also be employed.

[0130] Figure 30is a vertical cross - sectional view of an alternative structure including a reflector layer 353 over a fourth dielectric material layer 350 according to various embodiments of the present disclosure. The reflector layer 353 may be composed of a suitable optical reflective material, such as one or more reflective conductive materials (e.g., silver, aluminum, copper, gold, etc.). In some embodiments, the reflector layer 353 may include a thin - film distributed Bragg reflector (DBR) with a small refractive index change to provide enhanced reflectivity. A suitable deposition method (such as sputtering and / or vacuum evaporation) may be used to deposit the reflector layer 353. Other suitable deposition methods are within the scope of the present disclosure. The reflector layer 353 may be configured to reflect light emitted from the active regions 116, 216, 316 of the sub - pixels 10B, 10G, 10R in a downward direction (i.e., toward the growth substrate 101). In some embodiments, the reflector layer 353 may be configured to direct light at a controlled viewing angle (e.g., within a range between 30 - 150° (such as between 60 - 120°)).

[0131] In various embodiments, the reflector layer 353 may be deposited as a continuous layer over the fourth dielectric material layer 350. Then, a photoresist layer may be applied over the reflector layer 353, and the process steps described above with reference to Figure 29 may be performed to form an opening through the reflector layer 353 and the fourth dielectric layer 350, and to form discontinuous contact electrodes 351 that are within the opening and contact the upper surfaces 122, 222, 322 of the mesa portions 121, 221, 321 in each of the sub - pixels 10B, 10G, and 10R. As Figure 30 shown, each contact electrode 351 may be laterally surrounded by both the reflector layer 353 and the fourth dielectric material layer 350. In embodiments where the reflector layer 353 is composed of a conductive material, the contact electrode 351 may be electrically connected to the reflector layer 353.

[0132] Various alternative configurations of the reflector layer 353 and the contact electrodes 351 are within the scope of the present disclosure. For example, in embodiments where the reflector layer 353 is composed of a conductive material, a continuous reflector layer 353 may be formed over the structure as Figure 29 shown, such that a portion of the reflector layer 353 overlays and contacts the upper surface of each contact electrode 351. Thus, the portion of the reflector layer 353 that overlays the contact electrode 351 may provide an electrical conduction path between each contact electrode 351 and a corresponding bonding structure (e.g., a solder material portion) that may be subsequently disposed over the reflector layer 353. In yet a further embodiment, as described above with reference to Figure 29As described above, an opening may be formed through the fourth dielectric material layer 350 to expose the upper surfaces 122, 222, and 322 of the mesa portions 121, 221, and 321 in each of the sub-pixels 10B, 10G, and 10R. Then, a continuous reflector layer 353 may be formed over the fourth dielectric material layer 350 and within the opening in the fourth dielectric material layer 350. The portions of the continuous reflector layer 353 that are located within the opening and that contact the upper surfaces 122, 222, and 322 of the mesa portions 121, 221, and 321 in each of the sub-pixels 10B, 10G, and 10R may serve as contact electrodes 351 (e.g., anode contact electrodes 351) for each of the sub-pixels 10B, 10G, and 10R.

[0133] Figure 31 is a vertical cross-sectional view of a first exemplary structure including isolation trenches 360 surrounding a multi-color light-emitting device pixel 25 in accordance with various embodiments of the present disclosure. Referring to Figure 31 , a photoresist layer (not shown in Figure 30 ) may be applied over the fourth dielectric material layer 350 (or over the reflector layer 353 in the embodiments of Figure 31 ), and the photoresist layer may be lithographically patterned to provide an opening extending around the periphery of the multi-color light-emitting device pixel 25. An etching process may be performed to remove the portions of the fourth dielectric material layer 350 (and the reflector layer 353, if present), the spacer layer 107, the superlattice structure 105, and the first conductivity type doped semiconductor layer 103 that are exposed through the photoresist layer. The etching process may stop at the initial growth substrate 101. Subsequently, the photoresist layer may be removed, for example, by ashing.

[0134] Thus, trenches 360 may be formed around the periphery of the multi-color light-emitting device pixel 25. In some embodiments, a network of trenches 360 may be formed around each multi-color light-emitting device pixel 25 formed on the initial growth substrate 101. The trenches 360 may electrically isolate the corresponding pixels 25 and may thus be referred to as isolation trenches 360. In the embodiment shown in Figure 31 , each of the sub-pixels 10B, 10G, and 10R within a given pixel 25 may share a common first conductivity type doped semiconductor layer 103, a common superlattice structure 107, and a common lower portion 107a of the spacer layer 107. In embodiments including a reflector layer 353 made of a conductive material, a separate etching process may be performed to remove portions of the reflector layer 353 between the corresponding sub-pixels 10B, 10G, and 10R to electrically isolate the contact electrodes 351 of the corresponding sub-pixels 10B, 10G, and 10R.

[0135] Figure 32is a vertical cross - sectional view of an alternative structure including isolation trenches 360 surrounding each of the sub - pixels 10B, 10G, 10R according to various embodiments of the present disclosure. The isolation trenches 360 can be formed as described above with reference to Figure 31 The network of isolation trenches 360 can be formed around each of the sub - pixels 10B, 10G, and 10R formed on the initial growth substrate 101 to electrically isolate the corresponding sub - pixels 10B, 10G, and 10R. Thus, in the embodiment shown in Figure 32 each of the sub - pixels 10B, 10G, 10R can include a discontinuous first - conductivity - type doped semiconductor layer 103, a discontinuous superlattice structure 107, and a discontinuous lower portion 107a of the spacer layer 107.

[0136] In various embodiments, Figure 31 and Figure 32 the mesa faces 121, 221, 321 of each of the sub - pixels 10B, 10G, 10R in the structures shown in

[0137] can include unetched faceted sidewall surfaces, meaning that the tapered sidewall surfaces (e.g., surfaces 113, 213, 313, 115, 215, 315, 118, 218, 318, 120, 220, and 321) of the corresponding material layers 116, 216, 316, 118, 217, 317, 119, 219, 319 forming the mesa faces 121, 221, 321 may not undergo a re - etching process. Due to the lack of dangling bonds along the faceted sidewall surfaces of the mesa faces 121, 221, and 321, this can provide light - emitting device sub - pixels 10B, 10G, and 10R with high quantum efficiency.

[0137] In an alternative embodiment, the isolation trenches 360 can be omitted. This results in a display device with a higher PPI.

[0138] Figures 33 to 39 is a sequential vertical cross - sectional view of a second exemplary structure of a structure in a process for manufacturing a monolithic multicolor light - emitting device pixel 25 according to an alternative embodiment of the present disclosure. Figure 33 is a vertical cross - sectional view of a second exemplary structure including a continuous doped semiconductor material layer 103a formed on top of the initial growth substrate 101 according to various embodiments of the present disclosure. Figure 33 The second exemplary structure shown in Figure 3 can be derived from the first exemplary structure described above with reference to Figure 33 For the sake of brevity, the repeated discussion of similar elements is omitted. Figure 33 The difference between the second exemplary structure of Figure 3 and the first exemplary structure of Figure 33 can be that the thickness of the continuous doped semiconductor material layer 103a in the second exemplary structure of Figure 3The thickness of the continuous doped semiconductor material layer 103 in the first exemplary structure. In various embodiments, Figure 33 The thickness of the continuous doped semiconductor material layer 103a in the second exemplary structure may be between about 1 μm and about 4 μm (such as in the range of about 2 - 3 μm (e.g., ≈2.5 μm)). Figure 33 The continuous doped semiconductor material layer 103a in the second exemplary structure may include a group III - V compound semiconductor material (e.g., GaN), and the group III - V compound semiconductor material may be doped with a dopant of a first conductivity type. Thus, the continuous doped semiconductor material layer 103a may be referred to as a first conductivity type doped semiconductor material layer 103a.

[0139] Figure 34 is a vertical cross - sectional view of a second exemplary structure according to various embodiments of the present disclosure, including a continuous first dielectric material layer 109 formed over the continuous first conductivity type doped semiconductor material layer 103a. The continuous first dielectric material layer 109 may be equivalent to the continuous first dielectric material layer 109 described above with reference to Figure 6 For the sake of brevity, the repeated discussion of the continuous first dielectric material layer 109 is omitted.

[0140] Figure 35 is a vertical cross - sectional view of a second exemplary structure according to various embodiments of the present disclosure, including an opening 111 formed through the first dielectric material layer 109 in the sub - pixel region 10B. Referring to Figure 35 , as described above with reference to Figure 7 and Figure 8 A patterned mask may be formed over the first dielectric material layer 109 including the opening in the sub - pixel region 110B. An etching process as described above with reference to Figure 9 may be performed to provide an opening 111 through the first dielectric material layer 109 in the sub - pixel region 110B. The upper surface of the continuous first conductivity type doped semiconductor material layer 103a may be exposed at the bottom of the opening 111. After the etching process, the patterned mask may be removed using a suitable technique (such as by ashing or dissolving with a solvent).

[0141] Figure 36is a vertical cross-sectional view of a second exemplary structure including a discontinuous first-conductivity-type semiconductor material layer 103b within an opening 111 in a first dielectric material layer 109 formed in a sub-pixel region 110B, according to various embodiments of the present disclosure. The discontinuous first-conductivity-type semiconductor material layer 103b may include a III-V compound semiconductor material doped with a dopant of the first conductivity type. In various embodiments, the discontinuous first-conductivity-type semiconductor material layer 103b may be composed of the same material as that of the continuous first-conductivity-type semiconductor material layer 103b (e.g., doped GaN). A selective semiconductor deposition process may be used to form the discontinuous first-conductivity-type semiconductor material layer 103b, which grows semiconductor material from a semiconductor surface and does not grow semiconductor material from a dielectric surface. Thus, the semiconductor material of the discontinuous first-conductivity-type semiconductor material layer 103b may selectively grow over the exposed surface of the continuous first-conductivity-type semiconductor material layer 103a within the opening 111 in the first dielectric material layer 109. In some embodiments, the discontinuous first-conductivity-type semiconductor material layer 103b may completely fill the opening 111 in the first dielectric material layer 109 such that the upper surface of the discontinuous first-conductivity-type semiconductor material layer 103b may be substantially coplanar with the upper surface of the first dielectric material layer 109. Although Figure 36 shows a single discontinuous first-conductivity-type semiconductor material layer 103b, it will be understood that each pixel region 250 of the second exemplary structure may include a discontinuous first-conductivity-type semiconductor material layer 103b located in the sub-pixel region 110B. The continuous first-conductivity-type semiconductor material layer 103a and each discontinuous first-conductivity-type semiconductor material layer 103b may be considered to form a single first-conductivity-type semiconductor material layer 103, which includes a continuous lower portion 103a and one or more discontinuous upper portions 103b laterally surrounded by the first dielectric material layer 109.

[0142] Figure 37 is a vertical cross-sectional view of a second exemplary structure including a superlattice structure 105 and a spacer layer 107 formed over an upper portion 103b of a first-conductivity-type semiconductor material layer 103 in a sub-pixel region 110B, according to various embodiments of the present disclosure. The superlattice structure 105 and the spacer layer 107 may have the same as those referred to above Figure 4 , Figure 5 and Figure 9The superlattice structure 105 and the spacer layer 107 of the first exemplary embodiment described have equivalent compositions and thicknesses. The superlattice structure 105 and the spacer layer 107 of the second exemplary embodiment may differ from the superlattice structure 105 and the spacer layer 107 of the first exemplary embodiment in that: the superlattice structure 105 and the spacer layer 107 of the second exemplary embodiment may include discontinuous layers formed using a selective semiconductor deposition process that grows semiconductor material from a semiconductor surface and does not grow semiconductor material from a dielectric surface. Thus, the superlattice structure 105 may be selectively grown above the upper portion 103b of the first-conductive-type semiconductor material layer 103, and the spacer layer 107 may be selectively grown above the superlattice structure 105 in the sub-pixel region 110B.

[0143] In various embodiments, the superlattice structure 105 may include a mesa structure that includes a horizontally flat upper surface and tapered sidewalls extending from the horizontally flat upper surface toward the upper surface of the first dielectric material layer 109. The width dimension of the mesa structure may increase between the horizontally flat upper surface of the mesa structure and the upper surface of the first dielectric material layer 109. The spacer layer 107 may include a mesa structure that includes a horizontally flat upper surface above the horizontally flat upper surface of the superlattice structure 105 and tapered sidewalls that extend between the horizontally flat upper surface and toward the upper surface of the first dielectric material layer 109 and laterally surround the superlattice structure 105. The superlattice structure 105 and the spacer layer 107 may also include bottom surfaces that may be coplanar with each other and may each contact the upper surface of the first dielectric material layer 109. The bottom surface of the superlattice structure 105 may additionally contact the upper portion 103b of the first-conductive-type semiconductor material layer 103.

[0144] Figure 38 is a vertical cross-sectional view of a second exemplary structure including the first light-emitting epitaxial semiconductor structure 10B in the pixel region 250 according to various embodiments of the present disclosure. The first light-emitting epitaxial semiconductor structure 10B may be formed using the process steps described above with reference to Figures 10 to 13 described. Specifically, the above-described blue light-emitting active region 116 may be selectively grown above the spacer layer 107, the above-described optional electron blocking layer 117 may be selectively grown above the blue light-emitting active region 116, and the above-described second-conductive-type doped semiconductor material layer 119 may be selectively grown above the optional electron blocking layer 117 to provide the first light-emitting epitaxial semiconductor structure 10B. Then, the above-described etching process may be performed to remove the first dielectric material layer 109 from the second exemplary structure.

[0145] Figure 38The first light-emitting epitaxial structure 10B in the embodiment includes a first-conductivity-type doped semiconductor material layer 103 on an initial growth substrate 101. Among them, the first-conductivity-type doped semiconductor material layer 103 includes a continuous lower part 103a and an upper part 103b that forms a pedestal-like structure on the continuous lower part 103a. The first light-emitting epitaxial semiconductor structure 10B further includes a mesa portion 121 on the upper part 103b of the first-conductivity-type doped semiconductor material layer 103. The mesa portion 121 includes a flat horizontal lower surface that contacts the upper part 103a of the first-conductivity-type doped semiconductor material layer 103 and the upper surface of the first dielectric material layer 109, a flat horizontal upper surface 122, and a tapered outer sidewall 120 that extends between the flat horizontal upper surface 122 and the flat horizontal lower surface of the mesa portion 121. Figure 38 The mesa portion 121 in the embodiment includes a superlattice structure 105, a spacer layer 107 on the upper surface of the superlattice structure 105 and laterally surrounding the superlattice structure 105, a blue light-emitting active region 116 on the upper surface of the spacer layer 107 and laterally surrounding the spacer layer 107, an optional electron blocking layer 117 on the upper surface of the active region 116 and laterally surrounding the active region 116, and a second-conductivity-type doped semiconductor material layer 119 on the upper surface of the electron blocking layer 117 and laterally surrounding the electron blocking layer 117. A recess 123 can be located between the lower surface of the mesa portion 121 and the lower part 103a of the first-conductivity-type doped semiconductor material layer 103, and laterally surround the upper part 103b of the first-conductivity-type doped semiconductor material layer 103. A plurality of Figure 38 The mesa portions 121 as shown in can be located on the upper part 103b of the first-conductivity-type doped semiconductor material layer 103. Among them, each mesa portion 121 can form a part of the first light-emitting epitaxial semiconductor structure 10B located in the pixel region 250 of the second exemplary structure.

[0146] Figure 39 is a vertical cross-sectional view of a second exemplary structure including multicolor light-emitting pixels 25 according to various embodiments of the present disclosure. The multicolor light-emitting pixels 25 include a first light-emitting epitaxial semiconductor structure 10B (i.e., a blue light-emitting sub-pixel 10B), a second light-emitting epitaxial semiconductor structure 10G (i.e., a green light-emitting sub-pixel 10G), and a third light-emitting epitaxial semiconductor structure 10R (i.e., a red light-emitting sub-pixel 10R). Referring to Figure 39 , the above process steps described regarding Figures 34 to 38 can be repeated to form the second light-emitting epitaxial semiconductor structure 10G in the sub-pixel region 110G, and the above can be repeated again regarding Figures 34 to 38The described process steps form a third light-emitting epitaxial structure 10R in the sub-pixel region 110R. The second light-emitting epitaxial semiconductor structure 10G and the third light-emitting epitaxial structure 10R may have the same structure as the above-described first light-emitting epitaxial semiconductor structure 10B. Specifically, the second light-emitting epitaxial semiconductor structure 10G and the third light-emitting epitaxial structure 10R may each include a mesa portion 221, 321 on a respective upper portion 103b of the first-conductivity-type doped semiconductor material layer 103. Each of the mesa portions 221, 321 may include a superlattice structure 205, 305, a spacer layer 207, 307 on the upper surface of and laterally surrounding the superlattice structure 205, 305, an active region 216, 316 on the upper surface of and laterally surrounding the spacer layer 207, 307, an electron blocking layer 217, 317 on the upper surface of and laterally surrounding the active region 216, 316, and a second-conductivity-type doped semiconductor material layer 219, 319 on the upper surface of and laterally surrounding the electron blocking layer 117. In the second light-emitting epitaxial semiconductor structure 10G, the active region 216 may be a green light-emitting active region, and in the third light-emitting epitaxial semiconductor structure 10R, the active region 316 may be a red light-emitting active region. The recesses 223, 323 may be located between the lower surface of the respective mesa portions 221, 321 and the lower portion 103a of the first-conductivity-type doped semiconductor material layer 103, and laterally surround the upper portion 103b of the first-conductivity-type doped semiconductor material layer 103. Then, one or more of the process steps shown in Figures 28 to 32 may be performed on the second exemplary structure to form a dielectric material layer 350 above and between the mesa structures 121, 221, 321, a contact electrode 351 contacting each of the mesa structures 121, 221, 321, an optional reflector layer 353 above the dielectric material layer 350, and an isolation trench 360 surrounding each pixel 25 and / or sub-pixels 10B, 10G, and 10R.

[0147] In the above embodiment, the first connection portions, second connection portions, and third connection portions (i.e., 107b or 103b) of different sub-pixels 10B, 10G, and 10R in the same pixel 25 contact the first-conductivity-type common semiconductor material layer (i.e., 107a or 103a) in the same horizontal plane. Therefore, the connection portions of different sub-pixels 10B, 10G, and 10R in the same pixel 25 are laterally coplanar. Similarly, the active regions 116, 216, and 316 of different sub-pixels 10B, 10G, and 10R in the same pixel 25 are laterally coplanar and have bottom surfaces equidistant from the horizontal plane including the top surface of the first-conductivity-type common semiconductor material layer (i.e., 107a or 103a).

[0148] In various embodiments, one or more of the above-described multicolor light-emitting pixels 25 may be transferred from an initial growth substrate 101 to a target substrate (such as a backplane) to provide a multicolor display. Figures 40 to 45 is a sequential vertical cross-sectional view of an exemplary process for transferring multicolor light-emitting pixel 25 from an initial growth substrate 101 to a backplane 400 in accordance with an embodiment of the present disclosure. Although Figures 40 to 45 illustrates a transfer process in which a single multicolor light-emitting pixel 25 is transferred from an initial growth substrate 101 to a backplane 400, in other embodiments, multiple multicolor light-emitting pixels 25 (such as a continuous array of multicolor light-emitting pixels 25, including all multicolor light-emitting pixels 25 formed on the initial growth substrate 101) may be transferred from the initial growth substrate 101 to the backplane 400 during a single transfer process. Additionally, although Figures 40 to 45 illustrates one example of a suitable transfer process, it will be understood that other suitable processes for transferring one or more multicolor light-emitting pixels 25 from an initial growth substrate to a target substrate may also be utilized.

[0149] Figure 40 is a vertical cross-sectional view showing the backplane 400 and the initial growth substrate 101 on which one or more multicolor light-emitting pixels 25 are formed. Figure 40 The exemplary multicolor light-emitting pixel 25 shown in Figure 31 corresponds to the first exemplary structure shown in Figure 30 , Figure 32 and / or Figure 39 described multicolor light-emitting pixel 25 structures). In the embodiment shown in Figure 40 , the orientation of the structure is reversed (i.e., flipped) relative to the orientation shown in Figure 31 such that the initial growth substrate 101 is located on the top side of the structure and the mesa structures 121, 221, 321 of the sub-pixels 10B, 10G, and 10R are located on the bottom side of the structure. The diode-side bonding material portion 365 may be attached to the contact electrode 351 of each of the sub-pixels 10B, 10G, and 10R. In one embodiment, the diode-side bonding material portion 365 may be a soldering material portion (such as pure tin or an alloy of tin and indium).

[0150] The backplane 400 (which may also be referred to as the "backplane substrate" 400) may include any suitable substrate configured to have a plurality of devices (such as, light-emitting devices) fixed thereon. In one embodiment, the backplane 400 may include a substrate of silicon, glass, plastic, and / or at least other materials that can provide structural support for the devices to be subsequently transferred thereon. In one embodiment, the backplane 400 may be a passive backplane, and a metal interconnect structure 403 including metallized lines exists, for example, in a cross-cross grid in the passive backplane. In some embodiments, active device circuits (such as, field effect transistors) may not exist in the backplane 400. In another embodiment, the backplane 400 may be an active backplane, which includes a metal interconnect structure 403 that is a cross-cross grid of conductive lines and also includes device circuits at one or more intersections of the cross-cross grid of conductive lines. The device circuits may include one or more transistors. The backplane 400 may also include bonding pads 405 located on the first (i.e., upper) surface of the backplane 400. The bonding pads 405 may be electrically coupled to the metal interconnect structure 403. The bonding pads 405 may be made of a suitable conductive material, such as gold, copper, nickel, titanium, titanium nitride, tungsten, or tungsten nitride, including their combinations (such as, stacks) and / or their alloys. The arrangement of the bonding pads 405 on the backplane 400 may correspond to the arrangement of the light-emitting device sub-pixels 10B, 10G, and 10R of the pixels 25 formed on the initial growth substrate 101. A backplane-side bonding material portion 407 may be attached to the bonding pads 405. In one embodiment, the backplane-side bonding material portion 407 may be a soldering material portion (such as, pure tin or an alloy of tin and indium).

[0151] The initial growth substrate 101 and the backplane 400 may be arranged such that the lower surfaces of the sub-pixels 10B, 10G, 10R of the multicolor light-emitting device pixel 25 face the upper surface of the backplane 400, and each of the diode-side bonding material portions 365 attached to the contact electrodes 351 of the sub-pixels 10B, 10G, and 10R is aligned above the backplane-side bonding material portion 407 located above the bonding pads 405 of the backplane 400.

[0152] Figure 41 is a vertical cross-sectional view showing the initial growth substrate 101 relative to the backplane 400 moving vertically according to an embodiment of the present disclosure such that each of the "diode-side bonding structure 365 and the backplane-side bonding material portion 407" faces and contacts each other. Generally, at least one bonding material portion 365, 407 may be disposed between each vertically adjacent pair of "the corresponding one of the bonding pads 405 and the corresponding one of the contact electrodes 351 of the sub-pixels 10B, 10G, 10R". In some embodiments, as Figure 41As shown, a pair of "diode-side bonding material portions 365 and backplane-side bonding material portions 407" can be disposed between each vertically adjacent pair of "a corresponding one of the bonding pads 405 and the contact electrodes 351 of a corresponding one of the sub-pixels 10B, 10G, 10R". Optionally, either the diode-side bonding material portion 407 or the backplane-side bonding material portion 407 can be omitted. In some embodiments, a soldering flux 409 can be applied between the plurality of sub-pixels 10B, 10G, 10R and the backplane 400 such that the soldering flux 409 laterally surrounds each of the bonding material portions 365, 407. The soldering flux 409 can be any suitable liquid flux that reacts with tin oxide to leave conductive tin bonding material portions 365, 407.

[0153] In some embodiments, the combination of the backplane 400 and the initial growth substrate 101 can be disposed within a fixture (not shown), which can hold the combination in place without lateral sliding. The fixture can include, for example, a clamping combination that can be configured to apply a compressive force against the back side of the initial growth substrate 101 and / or the backplane 400. The clamping combination can hold the combination of the backplane 400 and the initial growth substrate 101 in such a way that light irradiation can be allowed to pass through the clamping combination and at least a portion of the initial growth substrate 101 during one or more subsequent optical irradiation steps described in further detail below.

[0154] Referring again to Figure 41 , as indicated by the arrows in Figure 41 , a compressive force can be applied along the vertical direction to the combination of the backplane 400, the bonding material portions 365, 407, and the initial growth substrate 101. In some embodiments, the compressive force can be applied by the above-described clamping combination. The magnitude of the compressive force can be selected such that the bonding material portions 365, 407 are not deformed in a significant manner (i.e., the bonding material portions 365, 407 can maintain the shape provided before clamping), and the corresponding bonding material portions 365 and 407 are not joined to each other.

[0155] Figure 42 is a vertical cross-sectional view showing a laser irradiation process using a lift-off laser beam LD according to various embodiments of the present disclosure. Referring to Figure 42 , the set of all light-emitting device structures (e.g., which can be the respective sub-pixels 10B, 10G, and 10R and / or the respective pixels 25 located on the initial growth substrate 101) that are subsequently transferred from the initial growth substrate 101 to the backplane 400 can be referred to as a first subset of the light-emitting device structures. In various embodiments, a lift-off laser beam LD can be used to perform a laser lift-off process to lift off the first subset of the light-emitting device structures, which can be referred to as a lift-off laser irradiation process.

[0156] Referring toFigure 42 , a laser irradiation process can be performed to irradiate the first-conductive-type doped semiconductor material layer 103 of each light-emitting device structure to be subsequently transferred to the backplane 400 using the lift-off laser beam LD. Thus, in Figure 42 the embodiment shown in Figure 42 the embodiment shown in each of the sub-pixels 10B, 10G, and 10R of the multi-color pixel 25 shares a common first-conductive-type doped semiconductor material layer 103. Thus, the first-conductive-type doped semiconductor material layer 103 can be irradiated over the entire region of the first-conductive-type doped semiconductor material layer 103 within the pixel 25 (i.e., the continuous region of the first-conductive-type doped semiconductor material layer 103 in the pixel 25 surrounded by the isolation trenches 360 can be irradiated). In an embodiment where the lateral dimension (e.g., diameter) of the lift-off laser beam LD is greater than the corresponding lateral dimension of the multi-color pixel 25, the entire region of the first-conductive-type doped semiconductor material layer 103 within the pixel 25 can be irradiated simultaneously by the lift-off laser beam LD. Optionally, the region of the first-conductive-type doped semiconductor material layer 103 within the pixel 25 can be irradiated sequentially (such as by scanning the lift-off laser beam LD across different portions of the first-conductive-type doped semiconductor material layer 103 located within the pixel 25).

[0157] In other embodiments where the respective sub-pixels 10B, 10G, and 10R of the pixel 25 are surrounded by the isolation trenches 360 (such as Figure 32 shown in ), the lift-off laser beam LD can irradiate the discontinuous first-conductive-type doped semiconductor material layers 103 within each of the sub-pixels 10B, 10G, and 10R of the pixel 25 simultaneously or sequentially.

[0158] In some embodiments, the lift-off laser beam LD can have a peak wavelength in the ultraviolet range or in the visible light range, and can have a peak wavelength that is preferentially absorbed by the constituent atoms (e.g., gallium atoms and / or nitrogen atoms) of the first-conductive-type doped semiconductor material layer 103. Without wishing to be bound by a specific theory, it is believed that irradiating the lift-off laser beam LD onto the first-conductive-type doped semiconductor material layer 103 can cause the evaporation of nitrogen atoms, while producing minimal evaporation of gallium atoms or no evaporation of gallium atoms. Thus, the irradiation reduces the atomic percentage of nitrogen in the remaining material.

[0159] In one embodiment, and without being bound by specific theory, it is believed that: after being irradiated by the detached laser beam LD, at least a portion of the first-conductivity-type doped semiconductor material layer 103 can be transformed into gallium-rich droplets. The gallium-rich droplets can consist of pure liquid gallium-rich droplets or can include an alloy of gallium and nitrogen, the alloy of gallium and nitrogen containing gallium with an atomic concentration greater than 55% (such as 60% to 99%). If the temperature of the assembly is maintained below the melting temperature of gallium or its alloy (e.g., 29.76 °C), the liquid gallium-rich droplets can solidify into solid gallium-rich material portions 411 (e.g., pure gallium or gallium-rich alloy particles or regions) after irradiation. In one embodiment, as Figure 42 shown, within each first-conductivity-type doped semiconductor material layer 103 in a first subset of the light-emitting device structures irradiated by the detached laser beam LD, the portion of the first-conductivity-type doped semiconductor material layer 103 near the interface between the first-conductivity-type doped semiconductor material layer 103 and the initial growth substrate 101 can include gallium-rich material portions 411 (i.e., solid pure gallium or gallium-rich alloy particles or regions). In some embodiments, the gallium-rich material portions 411 can include gallium atoms with an atomic concentration greater than 55% (such as 60% to 100%). The gallium-rich material portions 411 can have an average thickness in the range of 5 nm to 100 nm (such as 10 nm to 50 nm), but smaller and larger thicknesses are within the scope of the present disclosure. Each gallium-rich material portion 411 can include a continuous material layer or can include a cluster of spherical material portions. In various embodiments, the first-conductivity-type doped semiconductor material layer 103 or portions thereof that are not located in the light-emitting device structures to be subsequently transferred to the backplane 400 and thus not irradiated by the detached laser beam LD may not include any gallium-rich material portions 411. In some embodiments, the gallium-rich material portions 411 within the first-conductivity-type doped semiconductor material layer 103 irradiated by the detached laser beam LD can include gallium atoms with an atomic concentration of at least 55% and can have a lower melting point than the first-conductivity-type doped semiconductor material layer 103 that is not irradiated by the detached laser beam LD and can include gallium atoms with an atomic concentration less than 55% (such as about 50%).

[0160] Figure 43 is a vertical cross-sectional view of the initial growth substrate 101 and the backplane 400 after applying a compressive force that causes deformation of the bonding material portions 365 and 407 according to an embodiment of the present disclosure. Referring to Figure 43 , as shown by Figure 43As indicated by the arrow in [description], an additional compressive force can be applied vertically to the combination of the backplane 400, the bonding material portions 365, 407, and the initial growth substrate 101. In some embodiments, the compressive force can be applied by the above-mentioned clamping combination. The magnitude of the compressive force can be selected to cause deformation of the bonding material portions 365 and 407 (i.e., die-cast the bonding material portions to smooth any rough bonding surfaces). Thus, after converting a subset of the first-conductive-type doped semiconductor material layer 103 into the gallium-rich material portion 411, each matching pair of "the corresponding diode-side bonding material portion 165 and the corresponding backplane-side bonding material portion 407" can be pressed against each other under a second pressure greater than the first pressure. The second pressure is sufficient to cause deformation of the diode-side bonding material portion 365 and the backplane-side bonding material portion 407.

[0161] Figure 44 is a vertical cross-sectional view showing a bonding laser irradiation process that causes reflow and subsequent bonding of a matching pair of "the diode-side bonding material portion 365 and the backplane-side bonding material portion 407" according to an embodiment of the present disclosure. Referring to Figure 44 , a laser beam LB can be used to irradiate each matching pair of "the diode-side bonding material portion 365 and the backplane-side bonding material portion 407" below each light-emitting device (e.g., the multicolor pixel 25) in the first subset of the light-emitting devices to be transferred to the backplane 400. The laser beam LB can have a photon energy less than the bandgap of the III-V compound semiconductor material in the light-emitting device (e.g., a material containing gallium and nitrogen), and thus can pass through the light-emitting device to reach the bonding material portions 365, 407. For example, the laser beam LB employed during the bonding laser irradiation process can be an infrared laser beam (such as a carbon dioxide laser beam having a peak wavelength of 9.4 micrometers or 10.6 micrometers).

[0162] Each matching pair of "the diode-side bonding material portion 365 and the backplane-side bonding material portion 407" irradiated by the laser beam LB can be heated to the reflow temperature, and the bonding material of the pair of "the diode-side bonding material portion 365 and the backplane-side bonding material portion 407" (which can be a soldering material) reflows at the reflow temperature. When the irradiation of the laser beam LB is terminated, the reflowed material can be re-cured to provide a re-cured bonding material portion 413. Each re-cured bonding material portion 413 is bonded to the bonding pad 405 of the backplane 400 and the contact electrodes 351 of the sub-pixels 10B, 10G, and 10R of the multicolor pixel 25 to be subsequently transferred to the backplane 400.

[0163] Figure 45 is a vertical cross-sectional view showing a multicolor light-emitting device pixel 25 transferred from the initial growth substrate 101 to the backplane 400 according to an embodiment of the present disclosure. Referring to Figure 44 and Figure 45, after the above-described bonding laser irradiation process, the assembly including the initial growth substrate 101, the light-emitting device 25, and the backplane 400 can be heated to a temperature above the melting temperature of the gallium-rich material portion 411 of the first conductivity type doped semiconductor layer 103 but below the melting temperature of the remaining portion of the first conductivity type doped semiconductor layer 103 (e.g., below the melting temperature of gallium nitride). For example, if the gallium-rich material portion 411 is composed of pure gallium, the temperature can be raised to at least 30 degrees Celsius (such as 35 to 50 degrees Celsius) to melt the gallium-rich material portion 411 into gallium-rich droplets. As indicated by the arrow in Figure 45 , this can enable each light-emitting device (e.g., the multicolor pixel 25) below the gallium-rich portion 411 to be easily separated from the initial growth substrate 101. For example, the initial growth substrate 101 and any light-emitting device attached to the initial growth substrate 101 can be separated from the backplane 400 and the first subset of the light-emitting devices 25 bonded to the backplane 400 through the re-cured bonding material portion 413 by applying a force less than 100N.

[0164] Although a single multicolor light-emitting device pixel 25 is shown bonded to the backplane 400 in Figure 45 , it will be understood that multiple multicolor light-emitting device pixels 25 can be similarly bonded to the backplane 400 to form a direct-view multicolor display. In some embodiments, as described above with reference to Figures 40 to 45 , a continuous region of the multicolor light-emitting pixels 25 (including all the multicolor light-emitting pixels 400 forming the display) can be transferred from a common initial growth substrate 101 to the backplane 400 in a single transfer process. In some embodiments, the center-to-center spacing of adjacent multicolor light-emitting device pixels 25 of the display can be the same as the center-to-center spacing of adjacent multicolor light-emitting device pixels 25 on the initial growth substrate 101 from which the pixels 25 are transferred. In some embodiments, the density of the pixels 25 on the display can be at least about 1100 PPI. In some embodiments, the space separating adjacent pixels 25 of the display can be less than about 10 μm (such as less than about 5 μm (e.g., ≤2 μm), including less than about 1 μm). In some embodiments, the space separating adjacent sub-pixels (10B, 10G, 10R) in each pixel 25 of the display can be less than about 10 μm (such as less than about 5 μm (e.g., ≤2 μm), including less than about 1 μm) (such as taking 500 nm to 2 μm as an example).

[0165] Figure 46 is a vertical cross-sectional view of a part of a display 500 including multicolor light-emitting device pixels 25 mounted on a backplane 400 according to an embodiment of the present disclosure. Referring to Figure 46, after transferring a plurality of multi-color light-emitting device pixels 25 to the backplane, a dielectric matrix 415 can be disposed in the space between adjacent pixels 25 and in the space between the light-emitting device sub-pixels 10B, 10G, 10R bonded to the backplane 400. The dielectric matrix 415 can include a self-planarizing dielectric material, such as spin-on glass (SOG) or a polymer, or the dielectric matrix 415 can be planarized by recess etching polishing or chemical mechanical polishing. The planar surface of the planarized dielectric matrix 415 can be in a horizontal plane including the planar upper surface of each pixel 25 of the display 500, or can be vertically recessed below the horizontal plane including the planar upper surface of the pixel 25.

[0166] Referring again to Figure 46 , a front-side transparent conductive layer 417 can be formed over the upper surface of each multi-color light-emitting device pixel 25 of the display 500. The front-side transparent conductive layer 417 can include a transparent conductive oxide material (e.g., indium tin oxide, aluminum-doped zinc oxide, or another suitable material). The front-side transparent conductive layer 417 can be deposited over the first conductive type doped semiconductor material layer 103. The front-side transparent conductive layer 417 can be used as a common ground electrode (e.g., an n-side electrode) for the sub-pixels 10B, 10G, 10R of the multi-color pixel 25. An optional transparent passivation dielectric layer 419 can be formed over the front-side transparent conductive layer 417. The transparent passivation dielectric layer 419 can include silicon nitride or silicon oxide. Other suitable dielectric materials are within the scope of this disclosure.

[0167] Referring again to Figure 46, A direct-view display device 500 according to one embodiment includes at least one multicolor light-emitting device pixel 25 bonded to a backplane 400. The multicolor light-emitting device pixel 25 may include a plurality of semiconductor material sub-pixels (10B, 10G, 10R), wherein each semiconductor material sub-pixel (10B, 10G, 10R) is configured to emit light having a different peak wavelength. Each semiconductor material sub-pixel (10B, 10G, 10R) may include a front surface 501 and a rear surface 503, the front surface 501 being configured to emit light passing therethrough, and the rear surface 503 facing the backplane 400. Each semiconductor material sub-pixel (10B, 10G, 10R) may include a front portion (103, 105, 107a) adjacent to the front surface 501 of the semiconductor material sub-pixel (10B, 10G, 10R), a rear portion (121, 221, 321) adjacent to the rear surface 503 of the semiconductor material sub-pixel (10B, 10G, 10R), and a semiconductor connection portion 107b between the front portion (103, 105, 107a) and the rear portion (121, 221, 321). The front portion (103, 105, 107a) of each semiconductor material sub-pixel (10R, 10G, 10R) may include a first-conductive-type doped semiconductor material layer 103, and may optionally further include a superlattice structure 105 and / or a part of a spacer layer 107a. The rear portion (121, 221, 321) of each semiconductor material sub-pixel (10B, 10G, 10R) may include an active region (116, 216, 316) and a second-conductive-type doped semiconductor material layer (119, 219, 319), and may optionally further include an electron blocking layer 117. The rear portion (121, 221, 321) of each semiconductor material sub-pixel (10R, 10G, 10R) may include a first flat surface and a second flat surface extending parallel to the main surface of the backplane 400 (i.e., the surface of the backplane 400 to which the corresponding semiconductor material sub-pixel (10B, 10G, 10R) is bonded) and a tapered sidewall (120, 220, 320) extending between the first flat surface and the second flat surface. The lateral dimension of the rear portion (121, 221, 321) of each semiconductor material sub-pixel (10B, 10G, 10R) may decrease between the first flat surface and the second flat surface along the direction extending toward the backplane 400.

[0168] The dielectric material layer 350 may extend over at least a portion of the first and second flat surfaces and the tapered sidewalls (120, 220, 320) of the rear side portions (121, 221, 321) of each semiconductor material sub-pixel (10B, 10G, 10R), and may laterally surround the semiconductor connection portion 107b. The dielectric material layer 350 may continuously extend over each semiconductor material sub-pixel (10B, 10G, 10R). The semiconductor connection portion 107b in each semiconductor material sub-pixel (10B, 10G, 10R) may have a lateral dimension in a direction parallel to the main surface of the backplane 400, and the lateral dimension is smaller than the lateral dimensions of the front side portions (103, 105, 107a) and the rear side portions (121, 221, 321) of the corresponding semiconductor material sub-pixels (10B, 10G, 10R).

[0169] In an embodiment Figure 46 the semiconductor connection portion 107b between the front side portion (103, 105, 107a) and the rear side portion (121, 221, 321) of each of the semiconductor material sub-pixels (10B, 10G, 10R) includes a portion of the spacer layer 107b. Further, in Figure 46 the embodiment, the front side portions (103, 105, 107a) are continuous between each of the semiconductor material sub-pixels (10R, 10G, 10R) of the multi-color pixel 25.

[0170] Figure 47 is a vertical cross-sectional view of a portion of a display 500 including a multi-color light-emitting device pixel 25 mounted to a backplane 400 according to another embodiment of the present disclosure. Figure 47 The embodiment of Figure 32 may be derived from the exemplary multi-color light-emitting device pixel 25 shown in Figure 47 including isolation trenches 160 formed around each of the sub-pixels 10B, 10G, 10R. Thus Figure 46 the display 500 shown in Figure 47 may differ from the display shown in

[0171] Figure 46 in that the front side portions (103, 105, 107a) of each of the semiconductor material sub-pixels (10R, 10G, 10R) are not continuous between the corresponding semiconductor material sub-pixels (10R, 10G, 10R). Additionally, the dielectric material layer 350 over each of the semiconductor material sub-pixels (10B, 10G, 10R) does not continuously extend between the sub-pixels (10B, 10G, 10R) within the pixel 25. In the embodiment shown in Figure 47 the dielectric matrix 415 may extend between the front side portions (103, 105, 107a) of each of the semiconductor material sub-pixels (10R, 10G, 10R) within the pixel 25.

[0171] Figure 48 is a vertical cross - sectional view of a portion of a display 500 including a multicolor light - emitting device pixel 25 mounted to a backplane 400, according to another embodiment of the present disclosure. Figure 48 Embodiments of Figure 39 may be derived from the exemplary multicolor light - emitting device pixel 25 shown in Figure 48 In the embodiment shown in , the front - side portion (103a) of each of the semiconductor - material sub - pixels (10R, 10G, 10R) includes a portion 103a of a first - conductivity - type doped semiconductor - material layer 103. Another portion 103b of the first - conductivity - type doped semiconductor - material layer may form a semiconductor connection portion 103b. The rear - side portion (121, 221, 321) of each of the semiconductor - material sub - pixels (10B, 10G, 10R) includes a superlattice structure 105, a spacer layer 107, an active region (116, 216, 316), and a second - conductivity - type doped semiconductor - material layer (119, 219, 319), and may optionally further include an electron - blocking layer 117.

[0172] In yet a further embodiment, as shown in Figure 30 a reflector layer 353 may be located above a dielectric material layer 360 and may extend over at least a portion of the flat surface and the tapered sidewalls (120, 220, 320) of the rear - side portion (121, 221, 321) of each of the semiconductor - material sub - pixels (10B, 10G, 10R).

[0173] The foregoing description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the appended claims and the principles and novel features disclosed herein.

Claims

1. A method of manufacturing a multi-color light-emitting device, comprising: forming a first-conductive-type semiconductor material layer over an initial growth substrate; forming a first dielectric material layer over the first-conductive-type semiconductor material layer; lithographically patterning the first dielectric material layer to form an opening through the first dielectric material layer; forming a first semiconductor material pedestal structure within the opening and laterally surrounded by the first dielectric material layer; forming a first light-emitting device structure via selective growth from the first semiconductor material pedestal structure, the first light-emitting device structure including a first active region and a second-conductive-type semiconductor material layer over the first active region, wherein the first active region is configured to emit light having a first peak wavelength; performing an etching process to remove the first dielectric material layer; forming a second dielectric material layer using a conformal deposition process, the second dielectric material layer being over the first-conductive-type semiconductor layer and the first light-emitting device structure and laterally surrounding and contacting the first semiconductor material pedestal structure; lithographically patterning the second dielectric material layer to form an opening through the second dielectric material layer; forming a second semiconductor material pedestal structure within the opening and laterally surrounded by the second dielectric material layer; forming a second light-emitting device structure via selective growth from the second semiconductor material pedestal structure, the second light-emitting device structure including a second active region and a second-conductive-type semiconductor material layer over the second active region, wherein the second active region is configured to emit light having a second peak wavelength different from the first peak wavelength; and performing an etching process to remove the second dielectric material layer.

2. The method according to claim 1, further comprising: forming a third dielectric material layer using a conformal deposition process, the third dielectric material layer being over the first-conductive-type semiconductor layer, the first light-emitting device structure, and the second light-emitting device structure and laterally surrounding and contacting each of the first semiconductor material pedestal structure and the second semiconductor material pedestal; lithographically patterning the third dielectric material layer to form an opening through the third dielectric material layer; forming a third semiconductor material pedestal structure within the opening and laterally surrounded by the third dielectric material layer; forming a third light-emitting device structure via selective growth from the third semiconductor material pedestal structure, the third light-emitting device structure including a third active region and a second-conductive-type semiconductor material layer over the third active region, wherein the third active region is configured to emit light having a third peak wavelength different from the first peak wavelength and the second peak wavelength; and performing an etching process to remove the third dielectric material layer.

3. The method according to claim 2, further comprising: forming a fourth dielectric material layer over the first-conductive-type semiconductor layer, the first light-emitting device structure, the second light-emitting device structure, and the third light-emitting device structure and laterally surrounding and contacting each of the first semiconductor material pedestal structure, the second semiconductor material pedestal structure, and the third semiconductor material pedestal structure.

4. The method according to claim 3, wherein, The first peak wavelength is in the range of 400 nm to 495 nm, the second peak wavelength is in the range of 495 nm to 570 nm, and the third peak wavelength is in the range of 600 nm to 700 nm.

5. The method according to claim 3, wherein, each of the first dielectric material layer, the second dielectric material layer, the third dielectric material layer, and the fourth dielectric material layer has a thickness in the range of 10 nm to 100 nm.

6. The method according to claim 3, wherein, each of the first dielectric material layer, the second dielectric material layer, the third dielectric material layer, and the fourth dielectric material layer includes at least one of alumina, silica, and silicon nitride.

7. The method according to claim 2, wherein, each of the first light-emitting device structure, the second light-emitting device structure, and the third light-emitting device structure includes a mesa structure having a horizontally flat upper surface, a horizontally flat lower surface, and tapered sidewalls, wherein the width dimension of the mesa structure increases between the horizontally flat upper surface and the horizontally flat lower surface; and the second-conductive-type semiconductor material layer forms a part of the horizontally flat lower surface, the horizontally flat upper surface, and the tapered sidewalls in each of the mesa structures.

8. The method according to claim 2, further comprising: performing an etching process to form a trench continuously extending around the first light-emitting device structure, the second light-emitting device structure, and the third light-emitting device structure, wherein the trench extends through the first-conductive-type semiconductor material layer to the initial growth substrate.

9. The method according to claim 2, wherein, the first-conductive-type semiconductor material layer, the first semiconductor material pedestal structure, and the first light-emitting device structure form a first sub-pixel of a multi-color light-emitting device pixel; the first-conductive-type semiconductor material layer, the second semiconductor material pedestal structure, and the second light-emitting device structure form a second sub-pixel of a multi-color light-emitting device pixel; and the first-conductive-type semiconductor material layer, the third semiconductor material pedestal structure, and the third light-emitting device structure form a third sub-pixel of a multi-color light-emitting device pixel, and wherein the method further comprises: transferring the first sub-pixel, the second sub-pixel, and the third sub-pixel from the initial growth substrate to the second substrate using a single transfer process.

10. The method according to claim 9, wherein, transferring the first sub-pixel, the second sub-pixel, and the third sub-pixel from the initial growth substrate to the second substrate using a laser lift-off process.

11. A display, comprising: a backplane having a flat mounting surface; and multi-color pixels bonded to the flat mounting surface of the backplane, the multi-color pixels including a plurality of sub-pixels, wherein each sub-pixel is configured to emit light having different peak wavelengths, and wherein each sub-pixel of the multi-color pixels includes a front surface and a back surface, the front surface is configured to emit light passing through it, the back surface faces the backplane, and each sub-pixel of the multi-color pixels includes: a front portion adjacent to the front surface of the sub-pixel and including a first-conductive-type semiconductor material layer; The rear portion, adjacent to the rear surface of the sub-pixel and having a first flat surface, a second flat surface, and sidewalls, the first flat surface and the second flat surface extending parallel to the flat mounting surface of the backplane, the sidewalls extending between the first flat surface and the second flat surface, the rear portion including an active region and a semiconductor material layer of a second conductivity type; and A semiconductor connection portion, between the front portion and the rear portion of the sub-pixel, and wherein a dielectric material layer extends over at least a portion of the first flat surface, the second flat surface, and the sidewalls of the rear portion, and laterally surrounds the semiconductor connection portion of each of the sub-pixels of the multi-color pixel.

12. The display according to claim 11, wherein, The multi-color pixel includes a blue light-emitting sub-pixel, a green light-emitting sub-pixel, and a red light-emitting sub-pixel; and The spacing between adjacent sub-pixels of the multi-color pixel is less than 5 μm.

13. The display according to claim 11, wherein, The front portion of each of the sub-pixels of the multi-color pixel further includes: A superlattice structure; and A first portion of a semiconductor spacer layer, wherein a second portion of the semiconductor spacer layer forms the semiconductor connection portion of the sub-pixel.

14. The display according to claim 11, wherein, The sidewalls extending between the first flat surface and the second flat surface of the rear portion of each of the sub-pixels of the multi-color pixel include tapered sidewalls, and the lateral dimension of the rear portion of each sub-pixel decreases between the first flat surface and the second flat surface along the direction extending toward the backplane; The semiconductor material layer of the second conductivity type forms a part of the first flat surface, the second flat surface, and the tapered sidewalls of the rear portion of each sub-pixel, and the semiconductor material layer of the second conductivity type laterally surrounds the active region in each sub-pixel; and The rear portion of each of the sub-pixels of the multi-color pixel further includes a semiconductor electron blocking layer located between the active region and the semiconductor material layer of the second conductivity type.

15. The display according to claim 11, wherein: The dielectric material layer has a thickness in the range of 10 nm to 100 nm; The dielectric material layer includes at least one of alumina, silica, and silicon nitride; and The dielectric material layer extends continuously over and between each of the sub-pixels of the multi-color pixel.

16. The display of claim 11, wherein, The front portions of each of the sub-pixels of the multi-color pixel are continuous with each other.

17. The display according to claim 11, wherein, A transparent conductive electrode extends over the front surface of each sub-pixel of the multi-color pixel; A contact electrode contacts the rear surface of each sub-pixel of the multi-color pixel, wherein each of the contact electrodes is laterally surrounded by a dielectric material layer; and A bonding material portion is located between each of the contact electrodes and a bonding pad on the flat mounting surface of the backplane.

18. The display according to claim 11, wherein, The lateral dimension of the semiconductor connection portion is smaller than the lateral dimensions of the first flat surface and the second flat surface of the rear portion in each of the sub-pixels.

19. The display according to claim 11, wherein, The first-conductivity-type semiconductor material layer, the second-conductivity-type semiconductor material layer, and the semiconductor connection portion in each sub-pixel include GaN, and the active region in each sub-pixel includes a quantum well structure, and the quantum well structure includes at least one GaN layer and at least one InGaN layer.

20. The display device according to claim 11, wherein, The front side portion of each of the sub-pixels of the multi-color pixel includes a first portion of the first-conductivity-type semiconductor material layer, and the second portion of the first-conductivity-type semiconductor material layer forms the semiconductor connection portion of each of the sub-pixels.

21. A multi-color pixel, comprising: A common semiconductor material layer having a first conductivity type; A first sub-pixel located on the common semiconductor material layer and including a first mesa, the first mesa including a first active region and a first semiconductor material layer having a second conductivity type; A second sub-pixel located on the common semiconductor material layer and including a second mesa, the second mesa including a second active region and a second semiconductor material layer having a second conductivity type; and A third sub-pixel located on the common semiconductor material layer and including a third mesa, the third mesa including a third active region and a third semiconductor material layer having a second conductivity type, wherein each sub-pixel is configured to emit light having different peak wavelengths; and The first mesa, the second mesa, and the third mesa are laterally spaced apart from each other.

22. The multi-color pixel according to claim 21, further comprising: A first semiconductor connection portion having a lateral dimension smaller than that of the first mesa and located between the first mesa and the common semiconductor material layer; A second semiconductor connection portion having a lateral dimension smaller than that of the second mesa and located between the second mesa and the common semiconductor material layer; and A third semiconductor connection portion having a lateral dimension smaller than that of the third mesa and located between the third mesa and the common semiconductor material layer, wherein the first connection portion, the second connection portion, and the third connection portion contact the common semiconductor material layer in the same horizontal plane.

23. The multi-color pixel according to claim 22, further comprising: A dielectric material layer laterally surrounding the first semiconductor connection portion, the second semiconductor connection portion, and the third semiconductor connection portion.

24. The multi-color pixel according to claim 22, wherein, The first sub-pixel includes a blue light-emitting sub-pixel, the second sub-pixel includes a green light-emitting sub-pixel, and the third sub-pixel includes a red light-emitting sub-pixel; and The spacing between adjacent sub-pixels of the multi-color pixel is less than 5 μm.

25. A display device, comprising: A backplane having a flat mounting surface; and The multi-color pixel according to claim 21, bonded to the flat mounting surface of the backplane.

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