A circuit board intelligent test management system and method

Abstract

The present invention relates to the technical field of circuit board performance testing, and in particular to a circuit board intelligent test management system and method. The method comprises the following steps: continuously monitoring the current conduction of the circuit board hole position; when the current conduction is detected to be lower than a preset current conduction threshold, determining that the hole position current conduction is abnormal, and recording the abnormal state time and the coordinates of the abnormal initial position; obtaining a circuit board hole position image based on the abnormal initial position coordinates; identifying the hole position internal features of the circuit board hole position image, extracting the defective area of the hole position internal features, and marking it as a potential defective area of the hole position. The present invention uses data processing technology, laser scanning technology, and image detection technology to realize abnormal current conduction judgment of the circuit board hole position, identify the defective area image of the abnormal circuit board hole position, determine the circuit board defect optimization plan, and thus improve the accuracy of circuit board testing.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board performance detection, and in particular to an intelligent test management system and method for circuit boards. Background Art

[0002] A printed circuit board (PCB) is a support for electronic components and the hardware carrier for their electrical connections. In the early days, PCB testing relied primarily on manual inspection and simple electrical testing equipment, which was inefficient and prone to errors. With the development of electronic technology, bed-of-nails online testing technology has emerged. This technology uses a specialized bed of nails to contact components on the PCB for testing, enabling rapid detection of missing or incorrect components, as well as parameter deviations. Traditional PCB testing methods are typically unable to continuously monitor the current conduction through the PCB holes in real time and can only perform static or periodic testing. Once a current conduction anomaly occurs in a PCB hole, it is difficult to quickly and accurately locate the initial site of the anomaly, resulting in inefficient troubleshooting. While existing PCB testing uses automated optical inspection (AOI) technology to detect external defects on PCBs, its ability to identify internal features of the hole is limited, making it difficult to accurately extract defective areas within the hole, leading to missed detections or misjudgments. Summary of the Invention

[0003] Based on this, it is necessary to provide a system and method for intelligent testing management of circuit boards to solve at least one of the above technical problems.

[0004] To achieve the above object, a method for intelligent test management of a circuit board is provided, the method comprising the following steps:

[0005] Step S1: Continuously monitor the current conduction of the circuit board hole position; when the current conduction is detected to be lower than the preset current conduction threshold, it is determined that the hole current conduction state is abnormal, and the abnormal state time and abnormal initial position coordinates are recorded;

[0006] Step S2: obtaining a circuit board hole image according to the coordinates of the abnormal initial site; identifying the hole internal features of the circuit board hole image, extracting the defective area of the hole internal features, and marking it as a potential defective area of the hole;

[0007] Step S3: If the abnormal state time is greater than the preset abnormal state duration, laser detection is performed on the potential defect area of the hole to generate defect laser detection data; structural topology recognition is performed on the defect laser detection data to obtain defect structural topology data; and a circuit board defect optimization solution is determined based on the defect structural topology data;

[0008] Step S4: Real-time monitoring of the circuit board hole current value. When the circuit board hole current value is lower than the preset current conduction threshold again, the real-time abnormal site coordinates are obtained; when the real-time abnormal site coordinates match the abnormal initial site coordinates, the circuit board is optimized and repaired according to the circuit board defect optimization plan.

[0009] The present invention continuously monitors the current conduction of the circuit board holes. When the current conduction falls below a preset current conduction threshold, it can accurately determine the abnormal current conduction state of the hole and record the abnormal state time and the coordinates of the abnormal initial location. This precise positioning and recording function ensures the timely discovery and detailed recording of abnormal conditions in the circuit board holes, providing an accurate basis for subsequent detection and repair. The circuit board hole image is acquired based on the coordinates of the abnormal initial location, and the internal features of the hole are identified and the defective area is extracted, marking it as a potential defect area of the hole. This process enables the rapid identification and positioning of potential defects within the circuit board hole, improves detection efficiency, avoids misjudgment of normal areas, and ensures detection accuracy. When the abnormal state time is greater than the preset abnormal state duration, the potential defect area of the hole is laser detected to generate defect laser detection data. By performing structural topology identification on the defect laser detection data, defect structural topology data is obtained, and based on this data, a circuit board defect optimization solution is determined. This solution can formulate targeted repair measures based on the actual defect situation to ensure the scientific nature and effectiveness of the repair; it monitors the current value of the circuit board hole position in real time, and when the current value of the circuit board hole position is again lower than the preset current conduction threshold, obtains the real-time abnormal site coordinates. If the real-time abnormal site coordinates match the abnormal initial site coordinates, the circuit board is optimized and repaired according to the circuit board defect optimization plan. This real-time monitoring and repair management mechanism can effectively prevent the further deterioration of the circuit board hole position defects, extend the service life of the circuit board, and improve the reliability and stability of the circuit board. Therefore, the present invention uses data processing technology, laser scanning technology and image detection technology to realize abnormal current conduction judgment of the circuit board hole position, identify the defect area image of the abnormal hole position of the circuit board, determine the circuit board defect optimization plan, and thus improve the accuracy of the circuit board test.

[0010] Preferably, step S1 includes the following steps:

[0011] Step S11: Current sensors are respectively installed at the power input terminal hole and the power distribution node hole of the circuit board, and the current conduction is continuously sampled with a sampling period of 1 millisecond to 100 milliseconds, and each sampling lasts for 10 microseconds to 100 microseconds to obtain current monitoring data;

[0012] Step S12: The current monitoring data is segmented in chronological order, with each segment containing 50 to 200 sampling points, and the average value, maximum value, and minimum value of each segment are calculated as the current conduction value;

[0013] Step S13: when it is detected that the current conduction amount is lower than the preset current conduction amount threshold, it is determined that the hole current conduction state is abnormal;

[0014] Step S14: Record the abnormality detection time, data collection time, and abnormality confirmation time when the abnormal state occurs to obtain the abnormal state time;

[0015] Step S15: marking abnormal conduction locations on the circuit board according to the abnormal conduction status of the hole current to obtain the coordinates of the abnormal initial location.

[0016] The present invention respectively sets current sensors at the power input terminal hole and the power distribution node hole of the circuit board, which can specifically monitor the key current transmission nodes of the circuit board and ensure comprehensive monitoring of the current conduction state; the current conduction is continuously sampled according to a sampling period of 1 millisecond to 100 milliseconds and a sampling duration of 10 microseconds to 100 microseconds, which can capture the transient changes of the current with high time resolution, ensure the integrity and accuracy of the current monitoring data, and provide a reliable basis for subsequent analysis; the current monitoring data is segmented and processed in chronological order, each segment contains 50 to 200 sampling points, and the average value, maximum value and minimum value of each segment data are calculated as the current conduction value, which can effectively simplify the data processing process, extract key features, reduce data complexity, and retain key information of current changes, thereby improving data processing efficiency; by comparing the calculated current conduction value with a preset current conduction threshold, when it is detected that the current conduction value is lower than the threshold, it is determined to be an abnormal current conduction state of the hole. This threshold-based judgment method can quickly and accurately identify abnormal current conduction conditions at the circuit board holes, avoid missed detections and misjudgments, and ensure timely discovery of abnormal conditions; recording the abnormal detection time, data acquisition time, and abnormal confirmation time when the abnormal condition occurs can accurately determine the time point and duration of the abnormality, providing an accurate time reference for subsequent fault analysis and location, and helping to quickly assess the severity and impact range of the abnormality; marking the abnormal conduction site of the circuit board according to the abnormal current conduction state of the hole, obtaining the coordinates of the initial abnormal site, can accurately determine the specific location of the abnormality, and provide precise spatial positioning for subsequent defect detection and repair, making it easier to quickly find the root cause of the problem and take targeted measures.

[0017] Preferably, the step S2 of acquiring the circuit board hole position image according to the abnormal initial position coordinates includes:

[0018] Place the circuit board on the inspection platform and align the optical imaging device lens with the area where the abnormal initial location of the circuit board is located according to the coordinates of the abnormal initial location;

[0019] Start the optical imaging device and photograph the area where the initial abnormality of the circuit board is located from the front, 45-degree angles, and 90-degree angles in sequence. When photographing from the front, set the lens aperture size to F4.1-F5.6; when photographing from a 45-degree angle, set the lens aperture size to F5.6-F8; and when photographing from a 90-degree angle, set the lens aperture size to F8-F11.

[0020] An initial image of the circuit board hole position is collected; the initial image of the circuit board hole position is converted into a grayscale image, and the image hole position noise is removed to obtain a circuit board hole position image.

[0021] The present invention places a circuit board on a testing platform and aligns the optical imaging device lens with the area of the circuit board where the initial abnormality occurs based on the coordinates of the initial abnormality location. This allows for precise positioning and focusing of the abnormal area on the circuit board, ensuring accurate and targeted imaging and providing a clear image foundation for subsequent image analysis. The optical imaging device is then activated to sequentially capture the area where the initial abnormality occurs from the front, at a 45-degree angle, and at a 90-degree angle. The lens aperture is set accordingly based on the different shooting angles (the aperture for frontal shooting is F4.1-F5.6, the aperture for 45-degree shooting is F5.6-F8, and the aperture for 90-degree shooting is F8-F11). This multi-angle shooting method, combined with optimized aperture settings, can fully capture the detailed features of the abnormal area on the circuit board while ensuring that images captured at different angles have an appropriate depth of field and clarity, avoiding image blur or loss of detail caused by improper aperture settings. After capturing the initial image of the circuit board hole position, it is converted into a grayscale image and image hole noise is removed to obtain the circuit board hole position image. Grayscale conversion can simplify image data and reduce the complexity of subsequent processing; noise removal further improves image quality and enhances the recognizability of hole features in the image, providing high-quality image input for subsequent defect detection and analysis.

[0022] Preferably, the step S2 of identifying the internal features of the hole positions of the circuit board hole position image and extracting the defective areas of the internal features of the hole positions includes:

[0023] Traverse the pixel points of the circuit board hole image and extract the pixel values of the pixel points;

[0024] Binarize the hole image of the circuit board according to the pixel value. If the pixel value is 0-125, it is divided into the hole area; if the pixel value is 126-255, it is divided into the non-hole area;

[0025] Determine the flatness and thickness of the circuit board in the non-hole area; identify the hole contour boundary of the hole area based on the flatness of the circuit board;

[0026] Calculate the circuit board hole depth based on the circuit board thickness; calculate the maximum inscribed circle diameter of the hole contour boundary to obtain the circuit board hole diameter; identify the hole wall texture degree at the hole contour boundary to obtain the hole wall roughness;

[0027] Combine the circuit board hole depth, circuit board hole diameter and hole wall roughness into the hole internal features;

[0028] The defective area where the internal features of the hole are located is extracted and marked as the potential defective area of the hole.

[0029] This method traverses the pixel points of a circuit board hole image and extracts pixel values. Binarization is performed based on the pixel value range (0-125 for the hole area, 126-255 for the non-hole area), accurately dividing the image into hole and non-hole areas. This processing method effectively simplifies the complexity of image analysis and provides a clear regional division basis for subsequent feature extraction. Determining the circuit board flatness and thickness in the non-hole area allows for a comprehensive assessment of the physical condition of the non-hole area. Flatness and thickness information are important parameters for analyzing the overall quality of a circuit board and provide accurate background information for subsequent hole feature extraction. The hole contour boundaries of the hole area are identified based on the circuit board's flatness, and the hole depth is calculated based on the circuit board's thickness, enabling precise extraction of the hole's geometric features. At the same time, the maximum inscribed circle diameter of the hole contour boundary is measured to obtain the PCB hole diameter, and the hole wall texture is identified to obtain the hole wall roughness. These operations provide important data for a comprehensive assessment of hole quality. The PCB hole depth, PCB hole diameter, and hole wall roughness are combined into internal hole features, and the defect areas where the internal hole features are located are extracted and marked as potential defect areas of the hole. This integration and marking method can effectively identify potential defects in the hole and provide a clear target area for subsequent defect analysis and repair.

[0030] Preferably, if the abnormal state time in step S3 is greater than a preset abnormal state duration, performing laser detection on the potential defect area of the hole position includes:

[0031] If the abnormal state time is longer than the preset abnormal state duration, aim the laser camera of the laser detection equipment at the potential defect area of the hole;

[0032] Start the laser detection equipment and set the emission wavelength parameter to 532 nm to 1064 nm, the power range parameter to 10 mW to 100 mW, the laser beam emission time parameter to 10 msec to 100 msec, and the emission frequency to 1 Hz to 10 Hz;

[0033] Receive the laser signal reflected from the potential defect area of the hole, and extract the signal intensity and reflection time of the laser signal;

[0034] The laser signal is fitted into defect laser detection data based on signal intensity and reflection time.

[0035] When the abnormal state lasts longer than a preset abnormal state duration, the present invention aligns the laser camera of the laser detection device with the potential defect area of the hole, ensuring that the laser detection can accurately focus on the area where the defect may exist, thereby improving detection efficiency and accuracy. The laser detection device is activated and the emission wavelength parameters are set to 532 nanometers to 1064 nanometers, the power range parameters are set to 10 milliwatts to 100 milliwatts, the laser beam emission time parameters are set to 10 milliseconds to 100 milliseconds, and the emission frequency parameters are set to 1 Hz to 10 Hz. The optimized configuration of these parameters ensures that the laser beam has sufficient energy and an appropriate wavelength during the penetration and reflection process to meet the needs of hole detection of different materials and depths, while avoiding unnecessary damage to the circuit board. The laser signal reflected from the potential defect area of the hole is received and the signal intensity and reflection time of the laser signal are extracted. Signal intensity and reflection time are key characteristic parameters in laser detection, which can reflect the physical state and defect characteristics of the hole, providing an important basis for subsequent data analysis. The laser signal is fitted into defect laser detection data based on the signal intensity and reflection time, which can convert the collected raw signal into detection data with clear physical meaning, facilitating further analysis and processing. This data fitting method can effectively extract defect features and provide accurate data support for subsequent structural topology identification and defect assessment.

[0036] Preferably, the structural topology identification of the defect laser detection data in step S3 includes:

[0037] Determine the coordinates of defect holes based on defect laser detection data;

[0038] Measure the distance between the hole and the adjacent component pins according to the coordinates of the defective hole to obtain the distance between the hole and the component pins;

[0039] Measure the distance between the hole and the edge of the circuit board according to the coordinates of the defective hole to obtain the hole edge spacing;

[0040] Measure the hole verticality deviation and hole wall concentricity deviation according to the defect hole coordinates;

[0041] Detect the conductive connection relationship of the hole based on the hole component pin spacing and the hole edge spacing; detect the hole stacking misalignment structure based on the hole verticality deviation and hole wall concentricity deviation;

[0042] The defect laser detection data is subjected to structural topology recognition through the hole conductive connection relationship and the hole stacking dislocation structure to obtain the defect structural topology data.

[0043] The present invention determines the coordinates of defective hole positions based on defect laser detection data, and can accurately locate the specific position of the defect in the hole position, providing an accurate spatial reference for subsequent measurement and analysis; measures the spacing between the hole position and the pins of adjacent components according to the coordinates of the defective hole position, and obtains the spacing between the pins of the hole position components, which can evaluate the relative position relationship between the hole position and the surrounding components, ensure a reasonable spacing between the component pins and the hole position, and avoid short circuits or poor contact problems caused by insufficient spacing; measures the distance between the hole position and the edge of the circuit board according to the coordinates of the defective hole position, and obtains the spacing between the edges of the hole position, which can evaluate the relative position of the hole position and the edge of the circuit board, ensure the accuracy of the hole position in the design and manufacturing process, and avoid circuit board structural problems caused by position deviation; measures the verticality deviation of the hole position and the concentricity deviation of the hole wall according to the coordinates of the defective hole position, which can accurately evaluate the geometric accuracy of the hole position, and detect the hole position in the manufacturing process. The verticality and concentricity problems that may arise during the process provide an important basis for subsequent defect analysis; the conductive connection relationship of the hole is detected based on the hole component pin spacing and the hole edge spacing, which can accurately determine the conductive connection status of the hole and the surrounding components, ensuring that the electrical performance of the circuit board meets the design requirements; the hole stacking dislocation structure is detected based on the hole verticality deviation and the hole wall concentricity deviation, which can identify the stacking dislocation of the hole in the multi-layer circuit board, ensure the accuracy of the hole connection between layers, and avoid electrical failures caused by stacking dislocation; the defect laser detection data is subjected to structural topology recognition through the hole conductive connection relationship and the hole stacking dislocation structure to obtain the defect structure topology data, which can comprehensively analyze the structural characteristics and topological relationship of the defect, improve the description of the defect data, and provide an accurate and comprehensive basis for the subsequent defect assessment and repair plan formulation.

[0044] Preferably, determining the circuit board defect optimization solution based on the defect structure topology data in step S3 includes:

[0045] The defect structure topology data is divided into structural short circuit data and structural dislocation data;

[0046] Marking the short circuit position of the circuit board on the structural short circuit data, and determining the short circuit impact range of the short circuit position on the circuit board to generate short circuit impact range data; detecting the affected components on the short circuit impact range data to obtain short circuit impact component data;

[0047] The structural dislocation data is used to mark the circuit board dislocation area, and the wiring path of the circuit board dislocation area is identified to generate the dislocation wiring path data.

[0048] The present invention divides the defect structure topology data into structural short circuit data and structural dislocation data, realizes the classification management of different types of defect data, facilitates the subsequent targeted analysis and processing of different defect types, and improves the efficiency and accuracy of defect processing; marks the short circuit position of the circuit board on the structural short circuit data, can accurately locate the specific location of the short circuit, and provide a clear target for the repair of the short circuit problem; determines the short circuit impact range of the circuit board short circuit position and generates short circuit impact range data, which can comprehensively evaluate the potential impact range of the short circuit on the circuit board, ensuring that all potentially affected areas are considered during the repair process; and affects the short circuit impact range data. Component detection obtains data on components affected by short circuits, which can clearly identify components that may be damaged or affected by short circuits, providing an important basis for subsequent component detection and repair, and avoiding further damage caused by short circuits; marking the dislocation area of the circuit board based on the structural dislocation data can clearly identify the area with dislocation problems in the circuit board, providing a clear positioning for the repair of the dislocation problem; wiring path identification is performed on the dislocation area of the circuit board, and dislocation wiring path data is generated, which can accurately identify the wiring path in the dislocation area, provide detailed wiring information for repairing the dislocation problem, and ensure that the wiring path can be correctly adjusted during the repair process to restore the normal function of the circuit board.

[0049] Preferably, the step S3 of determining the circuit board defect optimization solution based on the defect structure topology data further includes:

[0050] Determine the type and quantity of components affected by the short circuit based on the short-circuit affected component data, and repair the short-circuit points of the components on the circuit board to obtain component short-circuit repair data;

[0051] Determine the area affected by the misaligned wiring based on the misaligned wiring path data, and rearrange the wiring paths of the misaligned wiring area of the circuit board to obtain wiring path optimization data;

[0052] Integrate component short-circuit repair data and wiring path optimization data to obtain a circuit board defect optimization solution.

[0053] The present invention determines the types and quantities of components affected by a short circuit based on short-circuit-affected component data, can clearly identify the specific impact range of the short circuit on components on a circuit board, and provide an accurate target for repair work; repairs component short-circuit points on the circuit board to obtain component short-circuit repair data, can specifically solve the short-circuit problem, restore the normal electrical connection of the components, and ensure the functional recovery of the circuit board; determines the area affected by the misaligned wiring based on the misaligned wiring path data, can accurately identify the wiring area affected by the misalignment in the circuit board; rearranges the wiring path of the misaligned wiring area on the circuit board to obtain wiring path optimization data, can effectively adjust the wiring path, solve the electrical connection problem caused by the misalignment, optimize the wiring structure of the circuit board, and improve the reliability and performance of the circuit board; integrates the component short-circuit repair data and the wiring path optimization data to obtain a circuit board defect optimization plan, can comprehensively consider the results of short-circuit repair and wiring optimization, and form a comprehensive repair plan. This integrated plan can ensure that after the circuit board is repaired, not only the current defect problem is solved, but also the overall structure is optimized, and the reliability and service life of the circuit board are improved.

[0054] Preferably, step S4 includes the following steps:

[0055] Step S41: monitoring the current value of the circuit board hole position in real time, and triggering the circuit board positioning and acquisition device switch when the current value of the circuit board hole position is lower than the preset current conduction threshold again;

[0056] Step S42: performing real-time detection of the circuit board edge by the circuit board positioning and acquisition equipment to extract the real-time edge of the circuit board;

[0057] Step S43: Calculating the X-coordinate value and the Y-coordinate value of the abnormal hole position on the circuit board in the X-axis and Y-axis directions parallel to the real-time edge of the circuit board; and calculating the Z-coordinate value of the abnormal hole position on the circuit board in the Z-axis direction perpendicular to the real-time edge of the circuit board;

[0058] Step S44: obtaining the real-time abnormal site coordinates based on the X coordinate value, the Y coordinate value, and the Z coordinate value;

[0059] Step S45: When the real-time abnormal site coordinates match the abnormal initial site coordinates, the circuit board is optimized and repaired according to the circuit board defect optimization solution.

[0060] The present invention monitors the current value of the circuit board hole position in real time. When the current value again falls below the preset current conduction threshold, the circuit board positioning and acquisition device is triggered. This real-time monitoring and triggering mechanism can promptly detect abnormal conditions of the circuit board hole position, ensuring that the subsequent detection process is quickly initiated when the abnormal situation occurs again, thereby improving detection efficiency and response speed. The circuit board positioning and acquisition device performs real-time detection of the circuit board edge, extracts the real-time edge of the circuit board, and provides an accurate reference for subsequent coordinate measurement. The X-axis and Y-axis directions parallel to the real-time edge of the circuit board are used to measure the X-coordinate value and Y-coordinate value of the abnormal circuit board hole position, and the Z-axis direction perpendicular to the real-time edge of the circuit board is used to measure the Z-coordinate value of the abnormal circuit board hole position. This coordinate measurement method can accurately determine the three-dimensional spatial position of the abnormal hole position, ensuring positioning accuracy. Based on the X-coordinate value, Y-coordinate value, and Z-coordinate value, the real-time coordinates of the abnormal position are obtained. This method accurately and in real time captures the coordinates of abnormal hole locations, providing a precise positioning basis for subsequent repair management. When the real-time abnormal site coordinates match the initial abnormal site coordinates, optimized repair management for the circuit board is performed according to the circuit board defect optimization plan. This coordinate-matching-based repair management method ensures that repair measures are precisely applied to the initially detected abnormal area, avoiding misoperation, improving the accuracy and reliability of repairs, and effectively resolving circuit board defects.

[0061] This specification also provides a circuit board intelligent test management system for executing the circuit board intelligent test management method described above. The circuit board intelligent test management system includes:

[0062] The initial abnormality monitoring module is used to continuously monitor the current conduction of the circuit board hole position; when the current conduction is detected to be lower than the preset current conduction threshold, it is determined to be an abnormal current conduction state of the hole position, and the abnormal state time and the coordinates of the abnormal initial position are recorded;

[0063] The hole image recognition module is used to obtain the hole image of the circuit board based on the coordinates of the abnormal initial site; identify the internal features of the hole in the hole image of the circuit board, extract the defect area of the hole internal features, and mark it as the potential defect area of the hole;

[0064] The defect structure topology detection module is used to perform laser detection on the potential defect area of the hole position if the abnormal state time is greater than the preset abnormal state duration, generate defect laser detection data; perform structural topology recognition on the defect laser detection data to obtain defect structure topology data; and determine the circuit board defect optimization plan based on the defect structure topology data;

[0065] The circuit board optimization and repair module is used to monitor the current value of the circuit board hole position in real time. When the current value of the circuit board hole position is lower than the preset current conduction threshold again, the real-time abnormal site coordinates are obtained; when the real-time abnormal site coordinates match the abnormal initial site coordinates, the circuit board is optimized and repaired according to the circuit board defect optimization plan.

[0066] Through the collaborative work of an initial anomaly monitoring module, a hole image recognition module, a defective structural topology detection module, and a circuit board optimization and repair module, the present invention achieves automated management of the entire process, from circuit board hole anomaly monitoring, defect identification, structural topology detection, to optimized repair. The initial anomaly monitoring module continuously monitors the current conduction of circuit board holes, accurately determines the abnormal state, and records the abnormal time and initial site coordinates, providing accurate information for subsequent processing. The hole image recognition module acquires hole images based on the abnormal initial site coordinates, efficiently identifies and extracts defective areas with internal hole features, and marks them as potential defect areas. The defective structural topology detection module performs laser detection and structural topology recognition on potential defect areas, generates defect laser detection data, and determines an optimized repair plan, ensuring the scientific and effective nature of defect treatment. The circuit board optimization and repair module monitors the hole current value in real time. When the current value falls below the threshold again, it obtains the real-time abnormal site coordinates and matches them with the initial site coordinates. Repair management is then carried out according to the optimized plan, effectively preventing the problem from worsening and extending the service life of the circuit board. The system significantly improves the efficiency and accuracy of circuit board test management, reduces manual intervention, and reduces the risk of operational errors. At the same time, it improves production efficiency and quality control levels and reduces production delays caused by defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 A schematic diagram of a process flow for a circuit board intelligent test management method;

[0068] Figure 2 for Figure 1 Detailed implementation steps of step S1 in FIG.

[0069] Figure 3 for Figure 1 Detailed implementation steps of step S4 in FIG.

[0070] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0071] The following is a clear and complete description of the technical method of the present invention in conjunction with the accompanying drawings. It is obvious that the embodiments described are part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts are within the scope of protection of the present invention.

[0072] In addition, the accompanying drawings are merely schematic illustrations of the present invention and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor and / or microcontroller approaches.

[0073] It should be understood that although the terms "first," "second," and the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the exemplary embodiments. The term "and / or" as used herein includes any and all combinations of one or more of the listed associated items.

[0074] To achieve this, please refer to Figures 1 to 3 , a method for intelligent test management of a circuit board, the method comprising the following steps:

[0075] Step S1: Continuously monitor the current conduction of the circuit board hole position; when the current conduction is detected to be lower than the preset current conduction threshold, it is determined that the hole current conduction state is abnormal, and the abnormal state time and abnormal initial position coordinates are recorded;

[0076] Step S2: obtaining a circuit board hole image according to the coordinates of the abnormal initial site; identifying the hole internal features of the circuit board hole image, extracting the defective area of the hole internal features, and marking it as a potential defective area of the hole;

[0077] Step S3: If the abnormal state time is greater than the preset abnormal state duration, laser detection is performed on the potential defect area of the hole to generate defect laser detection data; structural topology recognition is performed on the defect laser detection data to obtain defect structural topology data; and a circuit board defect optimization solution is determined based on the defect structural topology data;

[0078] Step S4: Real-time monitoring of the circuit board hole current value. When the circuit board hole current value is lower than the preset current conduction threshold again, the real-time abnormal site coordinates are obtained; when the real-time abnormal site coordinates match the abnormal initial site coordinates, the circuit board is optimized and repaired according to the circuit board defect optimization plan.

[0079] The present invention continuously monitors the current conduction of the circuit board holes. When the current conduction falls below a preset current conduction threshold, it can accurately determine the abnormal current conduction state of the hole and record the abnormal state time and the coordinates of the abnormal initial location. This precise positioning and recording function ensures the timely discovery and detailed recording of abnormal conditions in the circuit board holes, providing an accurate basis for subsequent detection and repair. The circuit board hole image is acquired based on the coordinates of the abnormal initial location, and the internal features of the hole are identified and the defective area is extracted, marking it as a potential defect area of the hole. This process enables the rapid identification and positioning of potential defects within the circuit board hole, improves detection efficiency, avoids misjudgment of normal areas, and ensures detection accuracy. When the abnormal state time is greater than the preset abnormal state duration, the potential defect area of the hole is laser detected to generate defect laser detection data. By performing structural topology identification on the defect laser detection data, defect structural topology data is obtained, and based on this data, a circuit board defect optimization solution is determined. This solution can formulate targeted repair measures based on the actual defect situation to ensure the scientific nature and effectiveness of the repair; it monitors the current value of the circuit board hole position in real time, and when the current value of the circuit board hole position is again lower than the preset current conduction threshold, obtains the real-time abnormal site coordinates. If the real-time abnormal site coordinates match the abnormal initial site coordinates, the circuit board is optimized and repaired according to the circuit board defect optimization plan. This real-time monitoring and repair management mechanism can effectively prevent the further deterioration of the circuit board hole position defects, extend the service life of the circuit board, and improve the reliability and stability of the circuit board. Therefore, the present invention uses data processing technology, laser scanning technology and image detection technology to realize abnormal current conduction judgment of the circuit board hole position, identify the defect area image of the abnormal hole position of the circuit board, determine the circuit board defect optimization plan, and thus improve the accuracy of the circuit board test.

[0080] In the embodiment of the present invention, reference Figure 1 FIG. 1 is a flow chart of a method for intelligent test management of a circuit board according to the present invention. In this example, the method for intelligent test management of a circuit board includes the following steps:

[0081] Step S1: Continuously monitor the current conduction of the circuit board hole position; when the current conduction is detected to be lower than the preset current conduction threshold, it is determined that the hole current conduction state is abnormal, and the abnormal state time and abnormal initial position coordinates are recorded;

[0082] In this embodiment of the present invention, a current detection chip, connected in series with the circuit, can directly measure the current flowing through a circuit board via. This chip features high precision and low noise, enabling accurate detection of minute current changes. First, the current detection chip is connected in series with the circuit board via circuit to ensure accurate measurement of the current flowing through the chip. The output of the current detection chip is connected to an analog-to-digital converter (ADC) to convert the analog current signal into a digital signal. The ADC's sampling rate is set to 1000 times per second to ensure real-time capture of current changes. During system initialization, a preset current conduction threshold, denoted as I_threshold, is set. This threshold is calibrated based on the current range of the via during normal circuit board operation, for example, to 10 mA. The system uses simple comparison logic to compare the real-time collected current value, I_measured, with I_threshold. When I_measured falls below I_threshold, the system determines that the via is in an abnormal current conduction state. At this point, the system starts a timer to record the duration of the abnormal state, T_abnormal. At the same time, a built-in coordinate positioning module obtains the initial coordinate position (X_abnormal, Y_abnormal) of the hole. Using a pre-set PCB hole layout diagram and the position information of the current detection chip, the coordinate positioning module accurately calculates the coordinates of the abnormal hole. The system stores the duration of the abnormal state, T_abnormal, and the coordinates of the initial abnormal location (X_abnormal, Y_abnormal) in local memory for subsequent analysis and processing. The entire monitoring process is implemented through a simple loop control logic, ensuring continuous monitoring of the current conduction of the PCB hole and timely recording of relevant information when an abnormality occurs.

[0083] Step S2: obtaining a circuit board hole image according to the coordinates of the abnormal initial site; identifying the hole internal features of the circuit board hole image, extracting the defective area of the hole internal features, and marking it as a potential defective area of the hole;

[0084] In this embodiment of the present invention, a high-resolution industrial camera is used to capture images of circuit board holes. The pixel resolution of the industrial camera is set to 4000×4000 to ensure clear capture of hole details. The camera's aperture is adjusted to F8, and the shutter speed is set to 1 / 200 second to balance lighting conditions and image clarity. The camera lens focal length is selected to be 50 mm to ensure moderate magnification of the hole image, fully covering the hole area without excessive magnification that would cause distortion. The captured circuit board hole image is transmitted to an image processing system. The system first grayscales the image, converting the RGB color image to a grayscale image to reduce data volume and simplify subsequent processing. After grayscaling, the image is binarized with a threshold of 128. Pixels with grayscale values above 128 are set to white (value 255), and pixels with grayscale values below or equal to 128 are set to black (value 0), thereby highlighting the characteristic areas within the hole. The system then uses an edge detection algorithm, such as the Canny algorithm, to perform edge detection on the binarized image. The low threshold of the Canny algorithm is set to 50 and the high threshold is set to 150 to accurately identify the contours and defect edges inside the hole. Through edge detection, the characteristic contours inside the hole are extracted, including structures such as the hole wall and the hole bottom. Subsequently, the system analyzes the extracted internal features of the hole and identifies the defective areas therein. By calculating the area, shape and texture features of the characteristic area, they are compared with the pre-defined normal hole feature template. If the area deviation of a certain area exceeds 10%, or the shape irregularity exceeds 20%, or the similarity of the texture features with the normal template is less than 80%, the area is marked as a potential defect area of the hole. The marking process is achieved by drawing a red rectangular box on the image. The coordinates and size information of the rectangular box are recorded in the data file for subsequent further analysis and processing.

[0085] Step S3: If the abnormal state time is greater than the preset abnormal state duration, laser detection is performed on the potential defect area of the hole to generate defect laser detection data; structural topology recognition is performed on the defect laser detection data to obtain defect structural topology data; and a circuit board defect optimization solution is determined based on the defect structural topology data;

[0086] In this embodiment of the present invention, the abnormal state duration T_abnormal is first compared with a preset abnormal state duration T_threshold. When T_abnormal exceeds T_threshold, a laser inspection device is activated to inspect the potential defect area at the hole. The laser inspection device uses a laser source with a wavelength of 1064 nanometers, a laser power of 50 milliwatts, and a scanning speed of 100 millimeters per second to ensure accurate coverage of the potential defect area at the hole. The laser inspection device focuses the laser beam on the potential defect area at the hole, collecting defect information through laser reflection and scattering signals. During the inspection process, the laser inspection device scans the potential defect area point by point at a 0.1 mm step size, simultaneously recording the laser reflection intensity value I_laser at each scan point. The generated defect laser detection data includes the coordinates (X_laser, Y_laser) of each scan point and the corresponding reflection intensity value I_laser, which is stored in a data file. Subsequently, the defect laser detection data is used for structural topology recognition. A threshold-based recognition algorithm is used, with the reflection intensity threshold I_threshold set to 200. For scanning points where the reflection intensity I_laser is lower than I_threshold, they are identified as defect points and their coordinates are recorded. By analyzing the spatial distribution relationship of the defect points, the defect structure topology data is constructed, including the connection relationship between the defect points and the boundary information of the defect area. Based on the defect structure topology data, the circuit board defect optimization plan is determined. According to the shape, size and distribution of the defect area, the hole area that needs to be repaired or adjusted is calculated. If the area of the defect area is less than 1 square millimeter, laser repair technology is used to remove excess material or fill missing material through laser ablation; if the area of the defect area is larger than 1 square millimeter, it is recommended to adopt an optimization plan of local replacement of the hole position. The specific parameters of the optimization plan, such as the power of the laser repair, the scanning path and the size range of the local replacement, are accurately calculated and recorded based on the defect structure topology data.

[0087] Step S4: Real-time monitoring of the circuit board hole current value. When the circuit board hole current value is lower than the preset current conduction threshold again, the real-time abnormal site coordinates are obtained; when the real-time abnormal site coordinates match the abnormal initial site coordinates, the circuit board is optimized and repaired according to the circuit board defect optimization plan.

[0088] In this embodiment of the present invention, a current detection device continuously monitors the current value at a circuit board hole. This current detection device utilizes a high-precision Hall-effect sensor with a sensitivity of 100 mV / A. This sensor can detect current changes at the circuit board hole in real time and output the current value in milliamperes. The preset current conduction threshold, I_threshold, is set to 10 mA. When the current value, I_current, at the circuit board hole falls below I_threshold again, the abnormality detection process is triggered. After detecting an abnormality, the real-time coordinates of the abnormal location are obtained through a positioning system. The positioning system utilizes high-precision optical positioning technology, achieving a positioning accuracy of ±0.05 mm. Based on the abnormality signal fed back by the current detection device, the positioning system quickly locates the abnormal hole and obtains the real-time coordinates of the abnormal location (X_realtime, Y_realtime). These real-time coordinates (X_realtime, Y_realtime) are then compared with the initial coordinates (X_abnormal, Y_abnormal) of the abnormal location recorded in step S1. The comparison process is achieved by calculating the Euclidean distance between the two coordinate points. If the distance is less than the set matching threshold D_threshold (for example, 0.1 mm), the real-time abnormal location is determined to match the initial abnormal location. If a match is determined, the circuit board is optimized and repaired according to the circuit board defect optimization plan determined in step S3. If the optimization plan is laser repair, the laser repair equipment is activated with the laser wavelength set to 532 nanometers, the power to 30 milliwatts, and the scanning speed to 50 mm per second. The defective area is repaired according to the scanning path planned in the optimization plan. During the repair process, the laser equipment precisely controls the emission and movement of the laser according to the shape and size of the defective area to ensure the accuracy and completeness of the repair. After the repair is completed, the current detection equipment is used to test the current of the repaired hole again to verify whether the repair effect meets the preset current conduction threshold requirements.

[0089] As an example of the present invention, refer to Figure 2 As shown, in this example, step S1 includes:

[0090] Step S11: Current sensors are respectively installed at the power input terminal hole and the power distribution node hole of the circuit board, and the current conduction is continuously sampled with a sampling period of 1 millisecond to 100 milliseconds, and each sampling lasts for 10 microseconds to 100 microseconds to obtain current monitoring data;

[0091] Step S12: The current monitoring data is segmented in chronological order, with each segment containing 50 to 200 sampling points, and the average value, maximum value, and minimum value of each segment are calculated as the current conduction value;

[0092] Step S13: when it is detected that the current conduction amount is lower than the preset current conduction amount threshold, it is determined that the hole current conduction state is abnormal;

[0093] Step S14: Record the abnormality detection time, data collection time, and abnormality confirmation time when the abnormal state occurs to obtain the abnormal state time;

[0094] Step S15: marking abnormal conduction locations on the circuit board according to the abnormal conduction status of the hole current to obtain the coordinates of the abnormal initial location.

[0095] In this embodiment of the present invention, high-precision current sensors are first installed in the power input and power distribution node holes of the circuit board. These current sensors utilize the Hall effect principle, with a sensitivity of 100 mV / mA, and are capable of converting current signals into voltage output signals. The sampling period of the current sensor is set to 10 milliseconds, with each sampling duration of 50 microseconds. The sampling period and duration are set using the current sensor's built-in timer and trigger, ensuring accurate current signal acquisition within each sampling period. The output of the current sensor is connected to an analog-to-digital converter (ADC) with a sampling rate of 100,000 times per second. The ADC converts the analog voltage signal output by the current sensor into a digital signal, generating current monitoring data. The current monitoring data is recorded in milliamperes, with each sampling point including a sampling timestamp and the corresponding current. The collected current monitoring data is segmented and processed in chronological order. Each segment contains 100 sampling points, and statistical analysis is performed on each segment by a data processing unit. The data processing unit first reads all current values in each segment and then calculates the average value μ_segment, the maximum value I_max, and the minimum value I_min for each segment. The average value, μ_segment, is calculated by summing all current values in each data segment and dividing it by the number of sampling points (100). The maximum value, I_max, is obtained by scanning all current values in each data segment and finding the maximum value. The minimum value, I_min, is obtained by scanning all current values in each data segment and finding the minimum value. These three parameters serve as the current conduction characteristics for that time period and are used for subsequent analysis and judgment. The system presets a current conduction threshold, I_threshold, set to 15 mA. The data processing unit compares the average value, μ_segment, of each data segment with I_threshold. When μ_segment falls below I_threshold, the system determines that the hole is in a current conduction abnormality state and triggers subsequent abnormality handling procedures. When a current conduction abnormality is detected, the data processing unit records the abnormality detection time, T_detect, which is the time when the system first detects the abnormality; the data acquisition time, T_acquire, which is the time when data acquisition begins for that segment; and the abnormality confirmation time, T_confirm, which is the time when the system finally confirms the abnormality. The anomaly detection time T_detect is obtained through the internal clock of the data processing unit, accurate to the millisecond level; the data acquisition time T_acquire is obtained by reading the timestamp of the first sampling point of the data segment; the anomaly confirmation time T_confirm is obtained by the current time after the data processing unit confirms the anomaly.By calculating the time difference between T_confirm and T_acquire, the abnormal state time, T_abnormal, is calculated in milliseconds to represent the duration of the abnormal state. Based on the abnormal current conduction state at the hole position, the abnormal conduction location on the circuit board is marked, combined with the circuit board layout information and the sensor location information. The positioning system obtains the initial coordinates of the abnormal location, recorded as the abnormal initial location coordinates (X_initial, Y_initial). The positioning system determines the precise coordinates of the abnormal location through geometric calculations based on the installation position of the current sensor and the circuit board layout. The abnormal initial location coordinates (X_initial, Y_initial) are recorded in millimeters, and the data processing unit stores this coordinate information in the system database for further analysis and processing.

[0096] Preferably, the step S2 of acquiring the circuit board hole position image according to the abnormal initial position coordinates includes:

[0097] Place the circuit board on the inspection platform and align the optical imaging device lens with the area where the abnormal initial location of the circuit board is located according to the coordinates of the abnormal initial location;

[0098] Start the optical imaging device and photograph the area where the initial abnormality of the circuit board is located from the front, 45-degree angles, and 90-degree angles in sequence. When photographing from the front, set the lens aperture size to F4.1-F5.6; when photographing from a 45-degree angle, set the lens aperture size to F5.6-F8; and when photographing from a 90-degree angle, set the lens aperture size to F8-F11.

[0099] An initial image of the circuit board hole position is collected; the initial image of the circuit board hole position is converted into a grayscale image, and the image hole position noise is removed to obtain a circuit board hole position image.

[0100] In an embodiment of the present invention, the circuit board is placed on a fixture of the detection platform to ensure that its position is stable and flat. The detection platform is equipped with a high-precision positioning system that can accurately adjust the position of the optical imaging device according to the input coordinate information. According to the coordinates of the initial abnormality point (X_initial, Y_initial) recorded in step S15, the positioning system drives the lens of the optical imaging device to move to the area above the coordinates, so that the center of the lens is aligned with the area where the initial abnormality point of the circuit board is located. The optical imaging device is started and the area where the initial abnormality point of the circuit board is located is photographed from different angles in turn. First, shoot from the front, set the lens aperture size to F5, the shutter speed to 1 / 125 second, and the ISO sensitivity to 200 to ensure that the image is clear and the exposure is moderate. After the shooting is completed, adjust the lens angle to 45 degrees, adjust the lens aperture size to F6.3, keep the shutter speed unchanged, and the ISO sensitivity still at 200, and take a second shot. Finally, the lens angle was adjusted to 90 degrees, the lens aperture was set to F9, the shutter speed was adjusted to 1 / 60 second, and the ISO sensitivity remained at 200, completing the third shot. After each shot, the optical imaging device transmitted the image data to the image processing system. After receiving the three images taken from the front, at a 45-degree angle, and at a 90-degree angle, the image processing system first processed the front image. This image was converted from RGB color format to grayscale using a weighted average method, with the weights for the red, green, and blue channels being 0.299, 0.587, and 0.114, respectively. After the conversion, the grayscale image was denoised using a median filter algorithm with a filter window size of 3×3 pixels to remove noise from the image holes, resulting in a clear image of the circuit board holes.

[0101] Preferably, the step S2 of identifying the internal features of the hole positions of the circuit board hole position image and extracting the defective areas of the internal features of the hole positions includes:

[0102] Traverse the pixel points of the circuit board hole image and extract the pixel values of the pixel points;

[0103] Binarize the hole image of the circuit board according to the pixel value. If the pixel value is 0-125, it is divided into the hole area; if the pixel value is 126-255, it is divided into the non-hole area;

[0104] Determine the flatness and thickness of the circuit board in the non-hole area; identify the hole contour boundary of the hole area based on the flatness of the circuit board;

[0105] Calculate the circuit board hole depth based on the circuit board thickness; calculate the maximum inscribed circle diameter of the hole contour boundary to obtain the circuit board hole diameter; identify the hole wall texture degree at the hole contour boundary to obtain the hole wall roughness;

[0106] Combine the circuit board hole depth, circuit board hole diameter and hole wall roughness into the hole internal features;

[0107] The defective area where the internal features of the hole are located is extracted and marked as the potential defective area of the hole.

[0108] In an embodiment of the present invention, during the analysis of a circuit board hole image, the grayscale circuit board hole image is first pixel-wise traversed. The image processing system reads the grayscale value of each pixel in the image row by row and column by column, storing the grayscale value as a pixel value P(x, y), where (x, y) represents the coordinate position of the pixel. Subsequently, the circuit board hole image is binarized based on the pixel value. A binarization threshold range is set. When the pixel value P(x, y) is between 0 and 125, the pixel is classified as a hole area and its pixel value is set to 0; when the pixel value P(x, y) is between 126 and 255, the pixel is classified as a non-hole area and its pixel value is set to 255. After binarization, the image is divided into a hole area and a non-hole area. For the non-hole area, an image processing algorithm is used to determine the flatness and thickness of the circuit board. Flatness is assessed by calculating the standard deviation (σ_flatness) of the grayscale values of pixels in the non-hole area. The smaller the standard deviation, the better the flatness. The circuit board thickness is calculated by analyzing the grayscale distribution in the non-hole area and combining it with a pre-calibrated grayscale-thickness relationship model to obtain the circuit board thickness value (T_board). Based on the circuit board flatness, the hole outlines of the hole area are identified. Edge detection algorithms, such as the Canny algorithm, are used to detect the edges of the binarized hole area. The Canny algorithm sets the low threshold to 50 and the high threshold to 150 to detect the hole outlines and represent them as a series of coordinate points (C(x, y)). Based on the circuit board thickness (T_board), the hole depth (D_hole) is calculated. The hole depth is calculated by analyzing the grayscale distribution of pixels in the hole area and combining it with the circuit board thickness using linear interpolation. Assuming that the lowest grayscale value in the hole area corresponds to the circuit board thickness (T_board), and the highest grayscale value corresponds to a depth of 0, the corresponding depth value is calculated based on the grayscale value ratio of the pixels to obtain the hole depth (D_hole). Calculate the maximum inscribed circle diameter D_inner within the hole contour boundary. Using geometric calculation methods, find the largest circle that can completely inscribe the hole contour within the hole contour boundary C(x, y). Calculate the diameter of this circle, D_inner, as the PCB hole diameter. Identify the hole wall texture within the hole contour boundary to obtain the hole wall roughness R_roughness. Use texture analysis algorithms, such as the gray-level co-occurrence matrix (GLCM) method, to analyze the pixels near the hole contour boundary. Calculate the contrast eigenvalue of the GLCM matrix; the larger the contrast eigenvalue, the higher the hole wall roughness. Based on the correspondence between the contrast eigenvalue and the hole wall roughness, calculate the hole wall roughness R_roughness. Combine the PCB hole depth D_hole, the PCB hole diameter D_inner, and the hole wall roughness R_roughness into internal hole features.By analyzing the distribution of the internal features of the hole, the areas that do not conform to the normal range are extracted, that is, the areas where the internal feature values of the hole deviate from the normal threshold range, and marked as potential defect areas of the hole.

[0109] Preferably, if the abnormal state time in step S3 is greater than a preset abnormal state duration, performing laser detection on the potential defect area of the hole position includes:

[0110] If the abnormal state time is longer than the preset abnormal state duration, aim the laser camera of the laser detection equipment at the potential defect area of the hole;

[0111] Start the laser detection equipment and set the emission wavelength parameter to 532 nm to 1064 nm, the power range parameter to 10 mW to 100 mW, the laser beam emission time parameter to 10 msec to 100 msec, and the emission frequency to 1 Hz to 10 Hz;

[0112] Receive the laser signal reflected from the potential defect area of the hole, and extract the signal intensity and reflection time of the laser signal;

[0113] The laser signal is fitted into defect laser detection data based on signal intensity and reflection time.

[0114] In an embodiment of the present invention, during the implementation of the intelligent test management method for circuit boards, when the abnormal state duration T_abnormal exceeds the preset abnormal state duration T_threshold, the laser camera of a laser inspection device is first aligned with the potential hole defect area. The laser inspection device is mounted on a robotic arm of the inspection platform. The robotic arm's high-precision positioning system adjusts the position and angle of the laser camera based on the coordinates of the initial abnormal location (X_initial, Y_initial) recorded in step S15 and the boundary information of the potential hole defect area, so that the center of the laser camera is precisely aligned with the potential hole defect area. The laser inspection device is activated, and the emission wavelength parameters are set to 1064 nanometers, the power range parameter to 50 milliwatts, the laser beam emission time parameter to 50 milliseconds, and the emission frequency to 5 Hz. These parameters are selected based on a comprehensive consideration of the circuit board material properties and the requirements for potential hole defect detection, ensuring effective stimulation of the reflected signal from the potential hole defect area while avoiding damage to the circuit board. The laser inspection device emits a laser beam according to the set parameters. After the laser beam irradiates the potential hole defect area, a portion of the laser energy is reflected back to the receiving device of the laser inspection device. The receiving device receives laser signals reflected from potential defect areas at the hole in real time and converts the optical signals into electrical signals using a built-in photoelectric converter. The system analyzes each reflected laser signal, extracting its signal intensity (I_reflected) and reflection time (T_reflection). The signal intensity (I_reflected) is measured using the output voltage of the photoelectric converter, while the reflection time (T_reflection) is calculated from the time difference between the laser emission and signal reception. Based on these values, the system performs data fitting on the laser signal. Using a least-squares fitting algorithm, the system fits the collected signal intensity and reflection time data points of the reflected laser signals into a curve, generating defect laser detection data. During the fitting process, the system considers the relationship between reflection time and signal intensity, as well as the physical properties of the potential defect area at the hole, to ensure that the fitting results accurately reflect the laser reflection characteristics of the potential defect area. The defect laser detection data includes the mathematical expression of the fitted curve, key parameters (such as slope and intercept), and the corresponding reflection time range. This data is stored and used for subsequent defect analysis and processing.

[0115] Preferably, the structural topology identification of the defect laser detection data in step S3 includes:

[0116] Determine the coordinates of defect holes based on defect laser detection data;

[0117] Measure the distance between the hole and the adjacent component pins according to the coordinates of the defective hole to obtain the distance between the hole and the component pins;

[0118] Measure the distance between the hole and the edge of the circuit board according to the coordinates of the defective hole to obtain the hole edge spacing;

[0119] Measure the hole verticality deviation and hole wall concentricity deviation according to the defect hole coordinates;

[0120] Detect the conductive connection relationship of the hole based on the hole component pin spacing and the hole edge spacing; detect the hole stacking misalignment structure based on the hole verticality deviation and hole wall concentricity deviation;

[0121] The defect laser detection data is subjected to structural topology recognition through the hole conductive connection relationship and the hole stacking dislocation structure to obtain the defect structural topology data.

[0122] In an embodiment of the present invention, during intelligent testing and management of a circuit board, the coordinates of a defective hole are first determined from defect laser detection data. By analyzing the reflection time T_reflection and signal intensity I_reflected in the defect laser detection data, combined with the emission parameters of the laser detection equipment and the geometric information of the potential defect area at the hole, the precise coordinates (X_defect, Y_defect) of the defective hole are calculated using triangulation. Specifically, the coordinate position of the defective hole on a two-dimensional plane is calculated based on the positional relationship between the laser emission point and the receiving point, as well as the optical path corresponding to the reflection time T_reflection. Next, based on the determined defective hole coordinates (X_defect, Y_defect), the spacing between the hole and the adjacent component pins is measured. High-precision optical measurement equipment is used, achieving a measurement accuracy of ±0.01 mm. The optical measurement equipment's lens is aligned with the defective hole and the adjacent component pins, and an image recognition algorithm is used to identify the edge contours of the hole and the pins. The straight-line distance between their center points is calculated to obtain the component pin spacing D_pin at the hole in millimeters. Simultaneously, the distance between the hole and the edge of the circuit board is measured. The optical measurement device's lens is aligned with the defective hole and the edge of the circuit board. The positions of the hole edge and the circuit board edge are determined using an image recognition algorithm. The shortest straight-line distance between the two is calculated to obtain the hole edge spacing D_edge in millimeters. Furthermore, based on the defective hole coordinates (X_defect, Y_defect), the hole's perpendicularity deviation and hole wall concentricity deviation are measured. For perpendicularity deviation, the angle θ between the hole axis and the circuit board plane is measured using a laser beam emitted by a laser inspection device. The perpendicularity deviation Δθ is defined as the difference between θ and 90 degrees. For hole wall concentricity deviation, the circularity characteristics of the hole wall contour are extracted by analyzing the laser reflection signal from the hole wall in the defect laser inspection data. The center offset Δr between the minimum circumscribed circle and the maximum inscribed circle of the hole wall contour is calculated as the hole wall concentricity deviation. The conductive connection relationship of the hole is inspected based on the hole component pin spacing D_pin and the hole edge spacing D_edge. By setting the thresholds D_pin_threshold and D_edge_threshold, when D_pin is less than D_pin_threshold or D_edge is less than D_edge_threshold, the hole is determined to have a risk of conductive connection with the component pin or circuit board edge. Furthermore, based on the hole perpendicularity deviation Δθ and the hole wall concentricity deviation Δr, the hole stacking misalignment structure is detected. By setting the perpendicularity deviation threshold Δθ_threshold and the concentricity deviation threshold Δr_threshold, when Δθ is greater than Δθ_threshold or Δr is greater than Δr_threshold, the hole is determined to have a stacking misalignment structure.Finally, the defect laser inspection data is used to identify structural topology based on the hole's conductive connection relationship and the hole's stacking misalignment structure. Using image processing and geometric analysis algorithms, combined with the inspection results of the conductive connection relationship and stacking misalignment structure, structural topology data of the defective hole is constructed. This topology data includes the hole's geometry, dimensional parameters, relative position to surrounding components and the circuit board edge, and the type and location of potential defects. This data is stored and used for subsequent defect analysis and the development of optimized repair plans.

[0123] Preferably, determining the circuit board defect optimization solution based on the defect structure topology data in step S3 includes:

[0124] The defect structure topology data is divided into structural short circuit data and structural dislocation data;

[0125] Marking the short circuit position of the circuit board on the structural short circuit data, and determining the short circuit impact range of the short circuit position on the circuit board to generate short circuit impact range data; detecting the affected components on the short circuit impact range data to obtain short circuit impact component data;

[0126] The structural dislocation data is used to mark the circuit board dislocation area, and the wiring path of the circuit board dislocation area is identified to generate the dislocation wiring path data.

[0127] In an embodiment of the present invention, during intelligent testing and management of a circuit board, defective structural topology data is first classified and processed. By analyzing the geometric shape, dimensional parameters, and defect type within the defective structural topology data, the data is divided into structural short-circuit data and structural misalignment data. Structural short-circuit data refers to defects that pose a risk of conductive connection, while structural misalignment data refers to defects that involve misaligned stacking structures. For the structural short-circuit data, an image processing algorithm is used to mark the short-circuit location on the circuit board. By identifying the geometric features of the short-circuit location, such as an abnormal connection point between a hole and a component pin, the coordinates (X_short, Y_short) of the short-circuit location are marked. Subsequently, the short-circuit impact range of the short-circuit location on the circuit board is determined. Using an algorithm based on a current diffusion model, the short-circuit current diffusion path and impact range are calculated based on the circuit board's circuit layout and the short-circuit location. The short-circuit impact range threshold is set to an area between 1 mm and 5 mm around the short-circuit location, generating short-circuit impact range data including the boundary coordinates and area of the affected area. The short-circuit impact range data is then used to detect affected components. By comparing and analyzing the short-circuit impact range with the circuit board's component layout, the components within the short-circuit impact range are identified. Using an image recognition algorithm, combined with component shape and position information, short-circuit-affected component data is obtained, including the type, coordinate location, and quantity of affected components. For structural misalignment data, an image processing algorithm is used to mark the misaligned areas of the circuit board. By identifying the geometric features of the misaligned area, such as the deviation between the hole position and the wiring path, the coordinate range of the misaligned area (X_misalign, Y_misalign) is marked. Subsequently, the wiring path of the misaligned area of the circuit board is identified. Using image analysis technology based on a path tracing algorithm, combined with the circuit board's wiring diagram, the original wiring path within the misaligned area and the wiring path changed due to the misalignment are identified. Misaligned wiring path data is generated, including the coordinates of the wiring path's start and end points, as well as the path's shape and length information. Through the above steps, the defective structure topology data is divided into structural short-circuit data and structural dislocation data. The short-circuit location and dislocation area are marked and analyzed in detail, and the short-circuit impact range data and dislocation wiring path data are generated, providing an accurate basis for the subsequent circuit board optimization and repair plan.

[0128] Preferably, the step S3 of determining the circuit board defect optimization solution based on the defect structure topology data further includes:

[0129] Determine the type and quantity of components affected by the short circuit based on the short-circuit affected component data, and repair the short-circuit points of the components on the circuit board to obtain component short-circuit repair data;

[0130] Determine the area affected by the misaligned wiring based on the misaligned wiring path data, and rearrange the wiring paths of the misaligned wiring area of the circuit board to obtain wiring path optimization data;

[0131] Integrate component short-circuit repair data and wiring path optimization data to obtain a circuit board defect optimization solution.

[0132] In an embodiment of the present invention, during the implementation of the intelligent test management method for a circuit board, the type and number of components affected by a short circuit are first determined based on the short-circuit-affecting component data. By analyzing the component type and coordinate location information in the short-circuit-affecting component data, the number of components of different types affected by the short circuit is calculated. For example, if the short-circuit-affecting component data includes three types of components: resistors, capacitors, and chips, the number of each type of component is calculated to obtain component short-circuit impact statistics, including the component type (Type_short) and the corresponding number (Count_short). Subsequently, the circuit board component short-circuit points are repaired. Based on the component short-circuit impact statistics, laser repair technology is used to repair the affected components. The laser repair equipment is set to a wavelength of 532 nanometers, a power of 30 milliwatts, and a scanning speed of 50 millimeters per second. For each short-circuit-affected component, the laser repair equipment operates according to a preset repair path to remove abnormal conductive connection points. After the repair is completed, detailed repair operation information, including the type, coordinate location, and repair parameters of the repaired component, is recorded to generate component short-circuit repair data. Next, the area affected by misaligned wiring is determined based on the misaligned wiring path data. By analyzing the starting and ending coordinates and path shape information in the misaligned wiring path data, the routing area affected by the misalignment is identified. Using an image processing algorithm and the circuit board wiring diagram, the boundaries of the area affected by the misaligned wiring are marked (X_misroute, Y_misroute). The wiring paths in the misaligned wiring area are then rearranged. An automatic routing algorithm is used to replan the routing paths within the area affected by the misaligned wiring based on the circuit board's electrical connection requirements and wiring rules. The automatic routing algorithm considers factors such as the circuit board's electrical performance, wiring spacing, and wiring length to generate a new routing path. The new routing path meets the circuit board's electrical connection requirements and avoids the effects of misalignment. The re-arranged routing path information, including the new starting and ending coordinates, path shape, and length, is recorded to generate routing path optimization data. Finally, the component short circuit repair data and the routing path optimization data are integrated to obtain a circuit board defect optimization solution. The repair operation information from the component short-circuit repair data and the rearrangement path information from the wiring path optimization data are combined to form a complete PCB defect optimization plan. The optimization plan details the specific repair and rearrangement operation steps, parameters, and areas involved, providing clear guidance for subsequent PCB repair and optimization.

[0133] As an example of the present invention, refer to Figure 3 As shown, in this example, step S4 includes:

[0134] Step S41: monitoring the current value of the circuit board hole position in real time, and triggering the circuit board positioning and acquisition device switch when the current value of the circuit board hole position is lower than the preset current conduction threshold again;

[0135] Step S42: performing real-time detection of the circuit board edge by the circuit board positioning and acquisition equipment to extract the real-time edge of the circuit board;

[0136] Step S43: Calculating the X-coordinate value and the Y-coordinate value of the abnormal hole position on the circuit board in the X-axis and Y-axis directions parallel to the real-time edge of the circuit board; and calculating the Z-coordinate value of the abnormal hole position on the circuit board in the Z-axis direction perpendicular to the real-time edge of the circuit board;

[0137] Step S44: obtaining the real-time abnormal site coordinates based on the X coordinate value, the Y coordinate value, and the Z coordinate value;

[0138] Step S45: When the real-time abnormal site coordinates match the abnormal initial site coordinates, the circuit board is optimized and repaired according to the circuit board defect optimization solution.

[0139] In this embodiment of the present invention, during the implementation of the intelligent test management method for circuit boards, step S41 is first performed, where a high-precision current sensor monitors the current value of the circuit board holes in real time. The current sensor has a sampling rate of 1000 times per second, enabling accurate measurement of current changes in the circuit board holes. When the current value of the circuit board hole is detected to fall below the preset current conduction threshold I_threshold again, the circuit board positioning and acquisition device is triggered. The preset current conduction threshold I_threshold is set to 10 mA. When the current value I_current falls below this threshold, the positioning and acquisition device is activated. Step S42 is then initiated, where the circuit board positioning and acquisition device performs real-time edge detection on the circuit board. The positioning and acquisition device utilizes laser scanning technology. A laser transmitter moves along the circuit board surface at a scanning frequency of 2000 times per second, emitting a laser beam and receiving reflected signals. Real-time edge information of the circuit board is extracted by analyzing the intensity and time delay of the reflected signals. This real-time edge information includes the edge's contour coordinates and shape characteristics, recorded in millimeters. In step S43, the X- and Y-coordinate values (X_realtime and Y_realtime) of the abnormal hole on the circuit board are measured along the X and Y axes, parallel to the real-time edge of the circuit board. The edge profile information obtained by the positioning acquisition device through laser scanning is combined with a pre-set coordinate system to calculate the position of the abnormal hole on the X and Y axes. Simultaneously, the Z-coordinate value (Z_realtime) of the abnormal hole on the circuit board is measured along the Z axis, perpendicular to the real-time edge of the circuit board. The Z coordinate value (Z_realtime) is measured using a laser ranging module with an accuracy of 0.01 mm, accurately reflecting the vertical positional deviation of the hole. Based on the X-, Y-, and Z-coordinate values (X_realtime, Y_realtime, and Z_realtime) obtained in step S43, step S44 is executed to obtain the real-time coordinates of the abnormal location (X_realtime, Y_realtime, and Z_realtime). The real-time coordinates of the abnormal location are calculated by the data processing unit by integrating the coordinate values in the X, Y, and Z directions and stored as three-dimensional coordinates. Finally, in step S45, the real-time abnormal location coordinates (X_realtime, Y_realtime, Z_realtime) are matched with the initial abnormal location coordinates (X_initial, Y_initial, Z_initial) recorded in step S15. The Euclidean distance between the two coordinate points is calculated. If the distance is less than the set matching threshold D_threshold (for example, 0.1 mm), the real-time abnormal location is determined to match the initial abnormal location. At this point, optimized repair management of the circuit board is performed according to the circuit board defect optimization plan.Optimization repair management includes repairing components affected by short circuits and rearranging wiring paths in misaligned wiring areas. Specific operating parameters are executed according to the records in the optimization plan to ensure that the performance of the circuit board returns to normal levels.

[0140] This specification also provides a circuit board intelligent test management system for executing the circuit board intelligent test management method described above. The circuit board intelligent test management system includes:

[0141] The initial abnormality monitoring module is used to continuously monitor the current conduction of the circuit board hole position; when the current conduction is detected to be lower than the preset current conduction threshold, it is determined to be an abnormal current conduction state of the hole position, and the abnormal state time and the coordinates of the abnormal initial position are recorded;

[0142] The hole image recognition module is used to obtain the hole image of the circuit board based on the coordinates of the abnormal initial site; identify the internal features of the hole in the hole image of the circuit board, extract the defect area of the hole internal features, and mark it as the potential defect area of the hole;

[0143] The defect structure topology detection module is used to perform laser detection on the potential defect area of the hole position if the abnormal state time is greater than the preset abnormal state duration, generate defect laser detection data; perform structural topology recognition on the defect laser detection data to obtain defect structure topology data; and determine the circuit board defect optimization plan based on the defect structure topology data;

[0144] The circuit board optimization and repair module is used to monitor the current value of the circuit board hole position in real time. When the current value of the circuit board hole position is lower than the preset current conduction threshold again, the real-time abnormal site coordinates are obtained; when the real-time abnormal site coordinates match the abnormal initial site coordinates, the circuit board is optimized and repaired according to the circuit board defect optimization plan.

[0145] Through the collaborative work of an initial anomaly monitoring module, a hole image recognition module, a defective structural topology detection module, and a circuit board optimization and repair module, the present invention achieves automated management of the entire process, from circuit board hole anomaly monitoring, defect identification, structural topology detection, to optimized repair. The initial anomaly monitoring module continuously monitors the current conduction of circuit board holes, accurately determines the abnormal state, and records the abnormal time and initial site coordinates, providing accurate information for subsequent processing. The hole image recognition module acquires hole images based on the abnormal initial site coordinates, efficiently identifies and extracts defective areas with internal hole features, and marks them as potential defect areas. The defective structural topology detection module performs laser detection and structural topology recognition on potential defect areas, generates defect laser detection data, and determines an optimized repair plan, ensuring the scientific and effective nature of defect treatment. The circuit board optimization and repair module monitors the hole current value in real time. When the current value falls below the threshold again, it obtains the real-time abnormal site coordinates and matches them with the initial site coordinates. Repair management is then carried out according to the optimized plan, effectively preventing the problem from worsening and extending the service life of the circuit board. The system significantly improves the efficiency and accuracy of circuit board test management, reduces manual intervention, and reduces the risk of operational errors. At the same time, it improves production efficiency and quality control levels and reduces production delays caused by defects.

[0146] The present invention is therefore intended to be illustrative and non-restrictive in all respects, with the scope of the invention being defined by the appended claims rather than the foregoing description, and all changes that come within the meaning and range of equivalents of the application documents are intended to be embraced therein.

[0147] The foregoing description is intended only to provide specific embodiments of the present invention, which will enable those skilled in the art to understand and implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but is to be construed in the widest possible manner consistent with the principles and novel features disclosed herein.

Claims

1. A method for intelligent test management of circuit boards, characterized in that: The following steps are involved: Step S1: Continuously monitor the current conduction of the circuit board hole position; when the current conduction is detected to be lower than the preset current conduction threshold, it is determined that the hole current conduction state is abnormal, and the abnormal state time and abnormal initial position coordinates are recorded; Step S2: obtaining a circuit board hole image according to the coordinates of the abnormal initial site; identifying the hole internal features of the circuit board hole image, extracting the defective area of the hole internal features, and marking it as a potential defective area of the hole; Step S3: If the abnormal state time is greater than the preset abnormal state duration, laser detection is performed on the potential defect area of the hole to generate defect laser detection data; structural topology recognition is performed on the defect laser detection data to obtain defect structural topology data; and a circuit board defect optimization solution is determined based on the defect structural topology data; Step S4: Real-time monitoring of the circuit board hole current value. When the circuit board hole current value is lower than the preset current conduction threshold again, the real-time abnormal site coordinates are obtained; when the real-time abnormal site coordinates match the abnormal initial site coordinates, the circuit board is optimized and repaired according to the circuit board defect optimization plan.

2. The method for intelligent test management of circuit boards according to claim 1, characterized in that: Step S1 includes the following steps: Step S11: Current sensors are respectively installed at the power input terminal hole and the power distribution node hole of the circuit board, and the current conduction is continuously sampled with a sampling period of 1 millisecond to 100 milliseconds, and each sampling lasts for 10 microseconds to 100 microseconds to obtain current monitoring data; Step S12: The current monitoring data is segmented in chronological order, with each segment containing 50 to 200 sampling points, and the average value of each segment is calculated as the current conduction value; Step S13: when it is detected that the current conduction amount is lower than the preset current conduction amount threshold, it is determined that the hole current conduction state is abnormal; Step S14: Record the abnormality detection time, data collection time, and abnormality confirmation time when the abnormal state occurs to obtain the abnormal state time; Step S15: marking abnormal conduction locations on the circuit board according to the abnormal conduction status of the hole current to obtain the coordinates of the abnormal initial location.

3. The method for intelligent test management of circuit boards according to claim 1, characterized in that: Acquiring the circuit board hole position image according to the abnormal initial position coordinates in step S2 includes: Place the circuit board on the inspection platform and align the optical imaging device lens with the area where the abnormal initial location of the circuit board is located according to the coordinates of the abnormal initial location; Start the optical imaging device and photograph the area where the initial abnormality of the circuit board is located from the front, 45-degree angles, and 90-degree angles in sequence. When photographing from the front, set the lens aperture size to F4.1-F5.6; when photographing from a 45-degree angle, set the lens aperture size to F5.6-F8; and when photographing from a 90-degree angle, set the lens aperture size to F8-F11. An initial image of the circuit board hole position is collected; the initial image of the circuit board hole position is converted into a grayscale image, and the image hole position noise is removed to obtain a circuit board hole position image.

4. The method for intelligent test management of circuit boards according to claim 1, characterized in that: The step S2 of identifying the internal features of the hole positions of the circuit board hole position image and extracting the defective areas of the internal features of the hole positions includes: Traverse the pixel points of the circuit board hole image and extract the pixel values of the pixel points; Binarize the hole image of the circuit board according to the pixel value. If the pixel value is 0-125, it is divided into the hole area; if the pixel value is 126-255, it is divided into the non-hole area; Determine the flatness and thickness of the circuit board in the non-hole area; identify the hole contour boundary of the hole area based on the flatness of the circuit board; Calculate the circuit board hole depth based on the circuit board thickness; calculate the maximum inscribed circle diameter of the hole contour boundary to obtain the circuit board hole diameter; identify the hole wall texture degree at the hole contour boundary to obtain the hole wall roughness; Combine the circuit board hole depth, circuit board hole diameter and hole wall roughness into the hole internal features; The defective area where the internal features of the hole are located is extracted and marked as the potential defective area of the hole.

5. The method for intelligent test management of circuit boards according to claim 1, characterized in that: If the abnormal state time in step S3 is greater than the preset abnormal state duration, laser detection of the potential defect area of the hole position includes: If the abnormal state time is longer than the preset abnormal state duration, aim the laser camera of the laser detection equipment at the potential defect area of the hole; Start the laser detection equipment and set the emission wavelength parameter to 532 nm to 1064 nm, the power range parameter to 10 mW to 100 mW, the laser beam emission time parameter to 10 msec to 100 msec, and the emission frequency to 1 Hz to 10 Hz; Receive the laser signal reflected from the potential defect area of the hole, and extract the signal intensity and reflection time of the laser signal; The laser signal is fitted into defect laser detection data based on signal intensity and reflection time.

6. The method for intelligent test management of circuit boards according to claim 1, characterized in that: The structural topology recognition of the defect laser detection data in step S3 includes: Determine the coordinates of defect holes based on defect laser detection data; Measure the distance between the hole and the adjacent component pins according to the coordinates of the defective hole to obtain the distance between the hole and the component pins; Measure the distance between the hole and the edge of the circuit board according to the coordinates of the defective hole to obtain the hole edge spacing; Measure the hole verticality deviation and hole wall concentricity deviation according to the defect hole coordinates; Detect the conductive connection relationship of the hole based on the hole component pin spacing and the hole edge spacing; detect the hole stacking misalignment structure based on the hole verticality deviation and hole wall concentricity deviation; The defect laser detection data is subjected to structural topology recognition through the hole conductive connection relationship and the hole stacking dislocation structure to obtain the defect structural topology data.

7. The method for intelligent testing and management of circuit boards according to claim 1, characterized in that: Determining the circuit board defect optimization solution based on the defect structure topology data in step S3 includes: The defect structure topology data is divided into structural short circuit data and structural dislocation data; Marking the short circuit position of the circuit board on the structural short circuit data, and determining the short circuit impact range of the short circuit position on the circuit board to generate short circuit impact range data; detecting the affected components on the short circuit impact range data to obtain short circuit impact component data; The structural dislocation data is used to mark the circuit board dislocation area, and the wiring path of the circuit board dislocation area is identified to generate the dislocation wiring path data.

8. The method for intelligent test management of circuit boards according to claim 1, characterized in that: Determining the circuit board defect optimization solution based on the defect structure topology data in step S3 further includes: Determine the type and quantity of components affected by the short circuit based on the short-circuit affected component data, and repair the short-circuit points of the components on the circuit board to obtain component short-circuit repair data; Determine the area affected by the misaligned wiring based on the misaligned wiring path data, and rearrange the wiring paths of the misaligned wiring area of the circuit board to obtain wiring path optimization data; Integrate component short-circuit repair data and wiring path optimization data to obtain a circuit board defect optimization solution.

9. The method for intelligent test management of a circuit board according to claim 1, characterized in that: Step S4 includes the following steps: Step S41: monitoring the current value of the circuit board hole position in real time, and triggering the circuit board positioning and acquisition device switch when the current value of the circuit board hole position is lower than the preset current conduction threshold again; Step S42: performing real-time detection of the circuit board edge by the circuit board positioning and acquisition equipment to extract the real-time edge of the circuit board; Step S43: Calculating the X-coordinate value and the Y-coordinate value of the abnormal hole position on the circuit board in the X-axis and Y-axis directions parallel to the real-time edge of the circuit board; and calculating the Z-coordinate value of the abnormal hole position on the circuit board in the Z-axis direction perpendicular to the real-time edge of the circuit board; Step S44: obtaining the real-time abnormal site coordinates based on the X coordinate value, the Y coordinate value, and the Z coordinate value; Step S45: When the real-time abnormal site coordinates match the abnormal initial site coordinates, the circuit board is optimized and repaired according to the circuit board defect optimization solution.

10. A system for intelligent testing and management of circuit boards, characterized in that: For executing the circuit board intelligent test management method according to claim 1, the circuit board intelligent test management system comprises: The initial abnormality monitoring module is used to continuously monitor the current conduction of the circuit board hole position; when the current conduction is detected to be lower than the preset current conduction threshold, it is determined to be an abnormal current conduction state of the hole position, and the abnormal state time and the coordinates of the abnormal initial position are recorded; The hole image recognition module is used to obtain the hole image of the circuit board based on the coordinates of the abnormal initial site; identify the internal features of the hole in the hole image of the circuit board, extract the defect area of the hole internal features, and mark it as the potential defect area of the hole; The defect structure topology detection module is used to perform laser detection on the potential defect area of the hole position if the abnormal state time is greater than the preset abnormal state duration, generate defect laser detection data; perform structural topology recognition on the defect laser detection data to obtain defect structure topology data; and determine the circuit board defect optimization plan based on the defect structure topology data; The circuit board optimization and repair module is used to monitor the current value of the circuit board hole position in real time. When the current value of the circuit board hole position is lower than the preset current conduction threshold again, the real-time abnormal site coordinates are obtained; when the real-time abnormal site coordinates match the abnormal initial site coordinates, the circuit board is optimized and repaired according to the circuit board defect optimization plan.

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