Server and Processor Error Handling Methods, Devices, Media, and Program Products

Abstract

The present invention discloses a server and a method, device, medium and program product for processor error handling, relating to the technical field of servers. The method includes: when a correctable error occurs in the processor, displaying a setting interface including error parameter configuration options, and setting a target fault tolerance allowable value corresponding to the correctable error for the error parameter configuration options; in an execution environment corresponding to the system management mode, selecting error severity data corresponding to the processor from multi-device error collection information according to error type identifiers assigned to different errors by an error register; determining whether to generate an error reporting and clearing instruction according to the processor error severity data and the target fault tolerance allowable value. The present invention can solve the problem in the related art that error reporting cannot be decoupled, resulting in untimely discovery of CPU CE faults. Users can perceive the CE error type, which is beneficial to improving the accuracy and efficiency of fault identification, reducing the probability of CE storms, and enhancing the reliability of the server.

Description

Technical Field

[0001] The present invention relates to the technical field of servers, and in particular to a processor error handling method, an electronic device, a computer-readable storage medium, a computer program product, and a server. Background Art

[0002] The stable operation of a server depends on an accurate fault diagnosis strategy. Based on the RAS (Reliability, Availability, Serviceability) characteristics, CPU (Central Processing Unit) faults have the greatest impact on the server. CPU errors include CPU CE (Corrected Error), and CPU CE can be processed by the built-in error correction mechanism of the system. In related technologies, in order to facilitate the detection and processing of CE alarms by the CPU, all CE alarms in the current computer system are aggregated, and then a larger error reporting threshold is set for processing. Users cannot perceive the reported CE types, and it is easy to accumulate a large number of CPU CEs, which may lead to the CE storm phenomenon and is not conducive to the timely discovery of faults. Summary of the Invention

[0003] The present invention provides a processor error handling method, an electronic device, a computer-readable storage medium, a computer program product, and a server, enabling users to perceive the CE error type, which is beneficial to improving the accuracy and efficiency of fault identification, effectively reducing the probability of the occurrence of the CE storm, and enhancing the stability and reliability of the server.

[0004] To solve the above technical problems, the present invention provides the following technical solutions:

[0005] The present invention provides a processor error handling method, including:

[0006] When a correctable error occurs in the processor, a setting interface including error parameter configuration options is displayed, and a target fault tolerance allowable value corresponding to the correctable error is set for the error parameter configuration options; the target fault tolerance allowable value is the maximum number of correctable errors that can occur within an allowable time period; in the execution environment corresponding to the system management mode, multi-device error collection information stored in different error type partitions of each error register at the current moment is obtained, and according to the error type of the correctable error of the processor, the number of correctable errors generated by the processor within the target time period is determined in the multi-device error collection information as the processor error degree data; according to the processor error degree data and the target fault tolerance allowable value, it is determined whether to generate an error reporting instruction and an error clearing instruction, so as to send the correctable error to the management controller through the error reporting instruction, and clear the record data of the correctable error from the target register through the error clearing instruction.

[0007] The present invention further provides an electronic device, including a memory and a processor. When the processor executes a computer program stored in the memory, the steps of any of the above-mentioned processor error handling methods are implemented.

[0008] The present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned processor error handling methods are implemented.

[0009] The present invention finally further provides a computer program product, including a computer program / instructions. When the computer program / instructions are executed by a processor, the steps of any of the above-mentioned processor error handling methods are implemented.

[0010] The present invention finally further provides a server, including a basic input / output system, a central processing unit, and a baseboard management controller. Among them, the central processing unit includes at least one register for storing hardware error information, and the basic input / output system includes a setting interface, which is used to implement the steps of any of the above-mentioned processor error handling methods when executing a computer program, and send the generated error reporting instruction to the baseboard management controller.

[0011] The advantages of the technical solution provided by the present invention are as follows: when storing various errors, the error register will be marked according to different error types. In this way, after obtaining all the error reporting information of the computer system at the current moment, it is possible to identify which errors belong to the CE errors of the processor according to the error types. Then, by setting the target fault tolerance allowable value of the CE of the processor on the setting page, the CE errors of the processor can be reported and processed separately in combination with their own unique corresponding target fault tolerance allowable values. This can not only decouple the CE reporting process of the processor and the memory CE reporting process, enabling the customer to effectively perceive whether the reported CE is from the processor or the memory, locate the error reporting device in a timely and accurate manner, and improve reliability and stability, but also the user can customize the target fault tolerance allowable value, which not only improves flexibility but also can obtain error reporting data that better conforms to the actual situation of the device. Further, according to the comparison between the processor error degree data and the target fault tolerance allowable value, the user can timely identify a large number of CPU CE error reports occurring in a short period of time, timely check the cause of the error report, and timely and effectively clear the CE, effectively reducing the risk of a CE storm and filtering out the phenomenon of a small number of CPU CE occurring within a long period of time. This not only saves a large amount of investment by operation and maintenance personnel but also reduces the risk of serious anomalies of the machine.

[0012] In addition, the present invention also provides corresponding implementation electronic devices, computer-readable storage media, computer program products, and servers for the processor error handling method, further making the method more practical, and the electronic devices, computer-readable storage media, computer program products, and servers have corresponding advantages. Description of the Drawings

[0013] In order to more clearly illustrate the technical solutions of the present invention or related technologies, the following will briefly introduce the drawings required for use in the embodiments or related technology descriptions. Obviously, the drawings in the following descriptions are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0014] Figure 1 A framework schematic diagram of the processor error handling method provided by the present invention in an exemplary application scenario;

[0015] Figure 2 A flowchart of a processor error handling method provided by the present invention;

[0016] Figure 3 A flowchart of another processor error handling method provided by the present invention;

[0017] Figure 4 A structural framework diagram of the processor error handling device provided by the present invention under an exemplary embodiment;

[0018] Figure 5 A structural diagram of an exemplary embodiment of the server provided by the present invention. Detailed Embodiments

[0019] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the following will further elaborate on the present invention in conjunction with the drawings and specific embodiments. Among them, the terms "first", "second", "third", "fourth", etc. in the specification and the above drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. The term "exemplary" means "serving as an example, embodiment, or illustration". Any embodiment described here as "exemplary" does not have to be construed as superior to or better than other embodiments.

[0020] It is a problem to be considered in the computer production and R & D process that the computer system can operate stably and have fewer problems during operation. In order to ensure that the computer system runs as long and reliably as possible without going offline, a system with RAS (Reliability Availability Serviceability) characteristics is built in, such as the systems used in server and data center environments. The efficient diagnosis of the whole machine failure based on RAS can minimize the downtime of the computer system and ensure the integrity of data and the continuous operation of the system.

[0021] At present, common RAS fault diagnosis strategies include predictive fault analysis, such as using built-in sensors to monitor the status of components such as the CPU (Central Processing Unit), and giving early warnings of possible faults. It also includes a detailed review of the log files generated by the operating system, BIOS (Basic Output and Input), application programs, etc. to find error messages or warnings. It also includes the use of redundant design to improve the reliability and availability of the system. When a component fails, a standby component is enabled to continue providing services. It also includes operation and maintenance personnel accessing the server status through remote management, such as BMC (Baseboard Management Controller), to perform diagnostic tests, system restarts, component replacements, etc. It also includes timely updating of software and firmware to fix known vulnerabilities and improve performance, keeping the latest versions of the BIOS, operating system, and application programs, and ensuring that all security patches are correctly installed. It also includes error detection and filtering of devices such as the CPU, memory, and PCIe (peripheral component interconnect express) through relevant registers built into the CPU.

[0022] Among them, the CPU is one of the core components of a computer system, used to execute the instruction set in a computer program, perform arithmetic and logical operations, control the data flow, and process input / output operations. Considering the RAS characteristics, compared with errors in devices such as memory and PCIe, when an error occurs in the CPU, it has a greater impact on the system stability. Common CPU errors include CPU CE and CPU UCE (UnCorrected Error). Among them, CE errors can be handled by the built-in error correction mechanism of the system, such as ECC (Error Checking and Correcting) memory, and will not cause system crashes or data loss. However, UCE errors exceed the self-repair ability range of the computer system and may lead to service interruptions or other serious consequences. Compared with UCE, CE is very common in RAS. A small number of CPU CEs will not affect the normal operation of the computer system. Correspondingly, customers usually do not perceive CPU CE error reports. However, a storm of CPU CE error reports is very likely to cause CPU failures and evolve into CPU UCE in a short time. In addition, recording and analyzing CPU CEs can help identify potential problems and take preventive measures. To avoid CE storms, identifying a large number of CE error reports within a certain period of time and reporting them to BMC and the OS (operating system) in a timely manner have become issues that the CPU CE RAS mechanism needs to focus on.

[0023] Currently, after a CPU CE error is reported, the error is stored in the MCA (Machine Check Architecture) register. During the startup process, the BIOS will read the error information from the CPU MCA register through the SMI handler that processes specific RAS events and report it to BMC and the OS. To better control the number of CEs in the MCA register, a related technology has built a register in the CPU to control the number of CPU CEs. According to the customer's requirements, when the number of CPU CEs accumulates to a threshold, the error is written into the MCA register. There is also a related technology that sets a threshold for reporting CEs to BMC and the OS for the handling of CPU CEs, and does not handle the writing of CEs in the MCA register.

[0024] It can be seen that by setting a relatively large reporting threshold or simply blocking the reporting of CEs, generally, it will not cause serious or fatal harm to the computer system. However, the processing solutions of related technologies will lead to the accumulation of CEs. Sometimes, a large number of accumulated CEs or CE storms will affect the CPU processing process and become irreparable errors. After the CPU recognizes them, it will shut down or restart the machine, affecting the operation of the machine. Therefore, too many CPU CEs are very unfavorable and need to be cleaned regularly. In addition, the occurrence of CPU CEs is generally due to information processing timeouts in the CPU's own firmware or hardware, or abnormal CPU contacts. For a sophisticated device like the CPU, minute changes such as internal bus processing timeouts in the CPU or current jitters in the CPU hardware itself will cause CPU CEs to occur, and the CPU itself can recover from such errors, so there is no need for customers to perceive such errors. However, unstable firmware will directly affect the accuracy of the CPU's processing of customer services. Seriously, security vulnerabilities may occur, resulting in the loss of customer service data; abnormal CPU contacts will affect the normal use of some registers and also affect the CPU's heat dissipation. In scenarios with high requirements for heat dissipation and service processing accuracy, these CPU CE errors need to be processed as soon as possible. However, users of related technologies are not aware of CPU CE error reports, which is not conducive to normal use. Therefore, for different scenarios in which CPU CEs occur, users need to be aware of CPU CE error reports in order to achieve the effect of not misreporting or missing reports. In addition, for the convenience of CPU detection and processing of CE alarms, related technologies do not distinguish between CPUs, memory, and PCIe devices when setting thresholds. That is to say, the CPUs of related technologies will aggregate all CE alarms on the current computer system and report them without classifying and identifying the error types. This makes it impossible for server manufacturers to effectively identify the error types, and thus impossible to select CPU CE errors and report them separately. This is very unfavorable for the handling of faults.

[0025] In view of this, in order to solve the problems in related technologies, where there is a risk of the computer system stopping running due to the large accumulation of CEs and CE storms, and simply blocking the reporting of CPU CEs cannot let customers perceive the status of the entire machine, resulting in the inability to effectively and timely handle CE errors and affecting user services. When the CPU can normally write CPU CEs into the MCA register, a target fault tolerance allowable value is set for CPU CEs, which is used to identify the threshold for reporting to the OS and BMC, that is, the maximum number of correctable errors that can occur within the allowable time period. It is confirmed whether the accumulated number of CPU CEs has reached the user-specified cumulative quantity threshold, and the cleaning rules required by the customer are executed according to the performance of the CE quantity. Based on this technical solution, first, in combination with Figure 1Some possible application scenarios related to the technical solution of the present invention are introduced by way of example. Figure 1 It is a schematic diagram of the hardware composition framework applicable to a processor error handling method provided by the present invention. This embodiment is an improved implementation scheme for timing and quantifying the cleaning of CPU CE error reports on the AMD (Advanced Micro Devices) platform. That is, the improvement for the current AMD platform may include the following content:

[0026] The hardware composition framework may include a first electronic device 11 and a second electronic device 12, which are connected by a network 13. The first electronic device 11 deploys a processor for executing the processor error handling method recorded in any one of the above embodiments, and the second electronic device 12 deploys a user terminal for providing a human-computer interaction interface. One of the application scenarios of the embodiment of the present invention can be realized through the interaction between the second electronic device 12 and the user. In this application scenario, when a correctable error occurs in the processor of the first electronic device 11, a setting interface including error parameter configuration options is displayed. The second electronic device 12 inputs a target fault tolerance allowable value, which is transmitted to the first electronic device 11 through the network 13. The first electronic device 11 sets the target fault tolerance allowable value corresponding to the correctable error for the error parameter configuration option. The error register of the processor of the first electronic device 11 will pre-assign a unique identifier to different error types. Whenever an error occurs, the error register determines the corresponding error type identifier according to the error type to which the current error belongs, and stores the currently generated error and its error type identifier. In the execution environment corresponding to the system management mode, during the process of obtaining the multi-device error collection information at the current moment from each error register, according to the error type identifier of the correctable error of the processor, the correctable error of the processor is selected from each error register, and the correctable error of the processor is separately accumulated to the target area of the corresponding error register. The number of times of generating correctable errors of the processor within the target time period is determined according to the accumulated data in the target area, as the processor error degree data; according to the processor error degree data and the target fault tolerance allowable value, it is determined whether to generate an error reporting instruction and an error clearing instruction, so as to send the correctable error to the management controller through the error reporting instruction, clear the record data of the correctable error from the target register through the error clearing instruction, and at the same time send the error reporting instruction to the second electronic device 12, so that the user perceives the CPU CE error report.

[0027] It should be noted that the above application scenarios are only shown for the convenience of understanding the ideas and principles of the present invention, and the embodiments of the present invention are not limited in this regard. On the contrary, the embodiments of the present invention can be applied to any applicable scenario. After introducing the technical solutions of the present invention, the various non-limiting embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments. Please refer to the following Figure 2 , Figure 2 which is a schematic flowchart of a processor error handling method provided in this embodiment. In this embodiment, an error register that stores multi-device errors of a computer system assigns a unique identifier to different error types. Whenever an error occurs, the error register determines the corresponding error type identifier according to the error type to which the current error belongs, and stores the currently generated error and its error type identifier. In this way, each error register stores the corresponding error type identifier when storing an error. During the processor error handling process, a hardware device that executes the processor error handling method, such as BIOS, can identify the error type corresponding to each error when obtaining the error. The processor error handling process may include the following content:

[0028] S201: When a correctable error occurs in the processor, display a setting interface including error parameter configuration options, and set the target fault tolerance allowable value corresponding to the correctable error for the error parameter configuration options.

[0029] In this embodiment, a correctable error refers to a correctable error of the processor. When a correctable error occurs in the processor, it can be a CPU CE of the computer system. Of course, if there are other processors in the computer system, CE errors may also occur, and the processor here also includes the processors in such cases. The setting interface is a page that allows users to perform basic settings on the computer hardware configuration during the startup process of the computer system, such as the setting interface of BIOS or UEFI (Unified Extensible Firmware Interface). The error parameter configuration options refer to the options for configuring and reporting the CE error of the processor to the OS and BMC, including the cumulative time threshold and the cumulative quantity threshold. The setting interface will pre-join the error parameter configuration options and set the trigger display condition, which is that a correctable error occurs in the processor. Users can set the target fault tolerance allowable value in advance according to actual needs. The target fault tolerance allowable value is the maximum number of correctable errors that can occur within the allowable time period, and is stored at a specified location. When the setting page displays the error parameter configuration options, the operation of reading the target fault tolerance allowable value is triggered simultaneously, and the value setting page is filled according to the read target fault tolerance allowable value. Of course, the target fault tolerance allowable value can also be directly input by the user to the corresponding location after the setting interface including the error parameter configuration options, which does not affect the implementation of the present invention.

[0030] S202: In the execution environment corresponding to the system management mode, during the process of obtaining the multi-device error collection information at the current moment from each error register, according to the error type identifier of the correctable error of the processor, the correctable errors of the processor are selected from each error register, and the correctable errors of the processor are separately accumulated to the target area of the corresponding error register. The number of times of correctable error generation of the processor within the target time period is determined according to the accumulated data in the target area, and used as the processor error degree data.

[0031] When a CE occurs in the processor, the computer system will call the RAS fault diagnosis driver to handle the processor CE fault. First, it is determined whether the computer system supports the PFEH (Platform First Error Handling) function. If this condition is met, the system management mode (SMM) software scheduling protocol is loaded to ensure that the system can effectively manage and respond to underlying hardware events. Entering the SMM mode by executing the SMI (System Management Interrupt) handler, that is, entering the execution environment corresponding to the system management mode. In this execution environment, errors occurring in multiple devices of the computer system are obtained, including all types of errors in multiple devices such as memory, PCIe, and CPU. That is, the multi-device error collection information includes various types of errors occurring in multiple devices of the computer system. Since the present invention is directed to the handling of processor CE errors, in order for the user to perceive the processor CE and decouple the reporting of processor CE and memory CE, it is necessary to identify the CE of the processor from the multi-device error collection information and continuously count the number of occurrences of the processor CE. The target time period is the duration of accumulating the processor CE, and the processor error degree data can be used to measure whether the correctable error is a small number of processor CEs occurring for a long time or a large number of processor CEs occurring in a short time. The error register is a register that stores the errors reported by the computer system, such as the MCA Bank. When storing an error in the error register, it will store the corresponding error type identifier, such as ID. In this embodiment, when obtaining errors from each error register, the obtained errors are of multiple types from multiple devices. The devices include but are not limited to the CPU, memory device, and PCIe device, and the error types include but are not limited to LS (Load Store), IF (Instruction Fetch), L2 (Level 2 Cache), DE (Data Error), EX (Execution Unit), FP (Floating Point), L3 (Level 3 Cache), CS (Cache Subsystem), PIE (Processor Integrated Error), UMC (Unified Memory Controller), and PB (Processor Bus).Taking the error register as an example of MCA Bank, MCA Bank assigns a unique ID to each type of error for differentiation. For example, the ID of UMC can be MCA_UMC_ID, and the ID of PCIe can be MCA_PCIE_ID. In this way, the BIOS can identify the error type by polling the IDs of all error types in the MCA Bank register. When the identified error type is a correctable error of the processor, in order to achieve separate reporting of the correctable errors of the processor, a storage area will be pre-set in the error register specifically for storing the correctable errors of the processor. For the convenience of description, it is defined as the target area. Whenever an error is identified as a correctable error of the processor, it will be separately accumulated in the target area. Separate accumulation can only count the correctable errors of the processor, and at the same time set a pointer to directly find the correctable errors of the processor. Separate accumulation can also directly copy the correctable errors of the processor to the target area. In this way, according to the accumulated data in the target area of each error register, the error degree data of the processor can be separately determined so that when its threshold reaches the target fault tolerance allowable value, the CPU CE error information can be reported separately.

[0032] S203: Determine whether to generate an error reporting instruction and an error clearing instruction according to the processor error degree data and the target fault tolerance allowable value.

[0033] Among them, the target fault tolerance allowable value is used to measure the maximum number of correctable errors that can occur within the allowed time period. The processor error degree data can indicate how long the correctable errors that have occurred have lasted. By comparing these two parameters, taking into account not having a large number of CE accumulations or CE storms, and being able to effectively prompt the user that a processor CE has occurred, to determine whether to generate an error reporting instruction and an error clearing instruction. The error reporting instruction sends the correctable error to the management controller, such as BMC, and can also be sent to the operating system and the user client. The error clearing instruction clears the recorded data of the correctable error from the target register. The target register refers to the register that stores the correctable error, and all or part of the correctable errors stored in the target register can be deleted.

[0034] In the technical solution provided in this embodiment, when storing various errors, the error register will identify them according to different error types. In this way, after obtaining all the error reporting information of the computer system at the current moment, it is possible to identify which errors belong to the CE errors of the processor based on the error types. Then, by setting the target fault tolerance allowable value of the CE of the processor on the setting page, the CE errors of the processor can be reported separately in combination with their own uniquely corresponding target fault tolerance allowable values. This can not only decouple the CE reporting process of the processor from the memory CE reporting process, enabling the customer to effectively perceive whether the reported CE is from the processor or the memory, timely and accurately locate the faulty device, and improve reliability and stability, but also allow the user to customize the target fault tolerance allowable value, which not only improves flexibility but also enables the user to obtain error reporting data that better conforms to the actual situation of the device. Further, based on the comparison between the processor error degree data and the target fault tolerance allowable value, the user can promptly identify a large number of CPU CE error reports occurring in a short period of time, promptly investigate the cause of the error reports, promptly and effectively clear the CE, effectively reduce the risk of a CE storm, and filter out the phenomenon of a small number of CPU CE occurring within a long period of time. This not only saves a large amount of investment by the operation and maintenance personnel but also reduces the risk of serious anomalies in the machine.

[0035] In the above embodiment, there is no limitation on how to set the target fault tolerance allowable value corresponding to the correctable error for the error parameter configuration option. Based on the above embodiment, the present invention also provides an exemplary implementation method, which may include the following content:

[0036] In this embodiment, the target fault tolerance allowable value may include a number fault tolerance allowable value and a corresponding duration value. Correspondingly, a setting interface including the error parameter configuration option is displayed; the error type is selected as the correctable error in the error parameter configuration option of the setting interface, and a setting interface including an error occurrence number option and a corresponding error cumulative time option is displayed; the number fault tolerance allowable value corresponding to the correctable error is set for the error occurrence number option, and the duration value corresponding to the correctable error is set for the error cumulative time option.

[0037] In this embodiment, the CPU CE error reports are cleaned up regularly and quantitatively through double judgments of the error tolerance allowable value of the number of times and the corresponding duration value. The computer system uses the error tolerance allowable value of the number of times set for the CPU CE cleaning by the BIOS as the cumulative time threshold, which can be represented as CPUCECountThrottle for example. Generally, users choose 2000 as the standard, and this value will be opened as a BIOS option on the Setup for customers to modify the cumulative number of CEs. The corresponding duration value can also be set as the cumulative quantity threshold, which can be represented as CPUCETimeThrottle for example. Generally, users choose 24 hours as the standard, and this value will be opened as a BIOS option on the Setup for customers to modify the cumulative time. During the computer system process, the computer system can execute the program for initializing and assigning values through the BIOS, thereby forming BIOS options with multiple selectable values displayed on the Setup. The initialization can be set to 0 or a pre-set value. During this process, it can be set according to the customer's requirements how many CPU CEs need to be accumulated within a certain period of time before the BIOS reports the CE error to the BMC and the OS.

[0038] As can be seen from the above, this embodiment uses double judgments of the time threshold and the number threshold to clean up the CPU CE error reports regularly and quantitatively. When a large number of CPU CE error reports occur in the computer system in a short period of time, they can be reported in time within a certain period of time. After the user perceives it, the cause of the error can be investigated in time, effectively reducing the risk of CE storms. In addition, for a small number of CPU CEs that occur within a long period of time, there is no need for the customer to perceive them, realizing the user's selective perception of CPU errors. After filtering out some normal scenarios, the scenarios that require more attention are reported to the user in time, thus saving a large amount of investment of the operation and maintenance personnel and reducing the risk of serious anomalies of the computer. Further, the original CPU CE reporting mechanism and the memory CE reporting mechanism are decoupled, and the user can effectively perceive whether the CE error reported by the system is from the CPU or the memory, which is convenient for the user to locate the error device. Through the dynamic intelligent reporting of CPUCE, users can have more choices and higher flexibility.

[0039] Further, for the case of pre-storage, it is also supported to be adjusted according to the application scenario. For example, in the scenario where the heat dissipation requirement and the business processing accuracy requirement are high, the maximum number of correctable error occurrences can be adjusted to a smaller value, or the allowed time period can be shortened, or both can be adjusted to a smaller value. Exemplarily, the user can send an error parameter adjustment instruction to the computer. When the error parameter adjustment instruction is detected, a setting interface including the number tolerance allowable value and the corresponding duration value is displayed, and the newly stored new number tolerance allowable value and the corresponding new duration value are read and then automatically filled in the corresponding positions. Of course, when the user issues an error parameter adjustment instruction, the error parameter adjustment instruction carries the new number tolerance allowable value and the corresponding duration value. Correspondingly, the computer system receives the error parameter input instruction input by the user, and by parsing the error parameter input instruction, obtains the new number tolerance allowable value and the corresponding new duration value; according to the new number tolerance allowable value and the new duration value, updates the local number tolerance allowable value and the corresponding duration value.

[0040] As can be seen from the above, this embodiment supports real-time adjustment of the number tolerance allowable value and the corresponding duration value, matches more application scenarios, and effectively improves the effectiveness of the processor CE error reporting.

[0041] The above embodiments do not make any limitations on how to determine the number of correctable error occurrences of the processor within the target time period. Based on the above embodiments, the present invention also gives an exemplary implementation manner, which may include the following contents:

[0042] The target tolerance allowable value of this embodiment includes the number tolerance allowable value and the corresponding duration value. When the processor has the platform error priority processing function, an error information collection thread is triggered through the callback interface of the system management interrupt; through the error information collection thread, the error type identifiers of the errors in each error register storing the hardware error information are polled; if the error type identifier of the current error is not the error type identifier of the first type of error and is not the error type identifier of the second type of error either, the current error is marked as an error generated by the processor itself and the current error is accumulated to the target area of the corresponding error register; the correctable errors of the processor are identified from each target area according to the error type of the correctable errors of the processor, and the number of occurrences of the correctable errors is counted; when the number of occurrences of the correctable errors is greater than or equal to the number tolerance allowable value, the current time is determined through the address of the clock processor, and the current duration is determined according to the current time and the time initial value; the current duration and the total number of occurrences of the correctable errors corresponding to the current moment are used as the processor error degree data at the current moment.

[0043] In this embodiment, when the SMI handler enters the SMM mode, it will determine whether the PFEH function is supported. If not, it will confirm the processor model and the RAS policy used, and end the entire process. If supported, the system can be ensured to effectively manage and respond to underlying hardware events by loading the SMM software scheduling protocol, and then trigger the SMI program to poll the error information in the registers of all storage hardware error information by calling the software SMI callback interface, such as the CPU Bank (a set of registers for storing hardware error information) registers. The errors polled include all types of errors of devices such as memory, PCIe, and CPU. That is, the multi-device error collection information includes at least the error information of two hardware devices. In the present invention, in order to improve the overall efficiency, improve the efficiency of the error register when storing errors, and improve the efficiency of finding correctable errors of the processor, when the error register allocates error identification information, the errors can be divided into three categories. The first category of errors and the second category of errors include all error types except the correctable errors of the processor, which are applicable to scenarios with high requirements for the reporting accuracy of the processor's correctable errors, or all error types except the errors of the processor itself, which are applicable to scenarios where the errors of the processor need to be reported separately, such as the scenario where the CE errors of memory and the CE errors of the processor are reported separately. In this way, it is not necessary to set an error type identifier for the errors of the processor itself. If the error type identifier of the current error is not the error type identifier of the first category of errors and is not the error type identifier of the second category of errors, the current error is marked as an error generated by the processor itself, and the current error is accumulated to the target area of the corresponding error register. In the first scenario, the errors accumulated here refer to the correctable errors of the processor. For the second scenario, the errors accumulated here are all the errors of the processor stored in the error register. If in the second scenario, it is necessary to further identify the CE errors of the processor, the error register only needs to set the corresponding error type identification information for the CE errors of the processor, and there is no need to allocate, generate, and store the error type identifiers for other types of errors of the processor. For example, in the error register MCA Bank, a unique ID is assigned to each type of error for distinction. The ID of UMC can be MCA_UMC_ID, and the ID of PCIe can be MCA_PCIE_ID. In this way, the BIOS can identify the stored error types by polling the IDs of all error types in the MCA Bank register. When the detected error information ID is not MCA_UMC_ID and MCA_PCIE_ID, it can be marked as an error generated by the CPU itself, and then accumulated separately in the specified area of the target register, so that when its threshold reaches the target fault tolerance allowable value, the CPU CE error information can be reported separately.When the total number of occurrences of the processor CE reaches CPUCECountThrottle, the current time is read based on the address of the clock processor to determine the duration accumulated to CPUCECountThrottle. Exemplarily, the initial time can be the timestamp recorded when the computer system is powered on. Based on the timestamp corresponding to the power-on operation, the initial value of the time for correctable errors is determined; based on the day parameter and hour parameter corresponding to the current time, the current moment value is determined; based on the day parameter and hour parameter corresponding to the initial time value, the initial moment value is determined; the difference between the current moment value and the initial moment value is used as the current duration value.

[0044] As can be seen from the above, in this embodiment, the determination of the duration is triggered only after the number of CE times accumulates to the maximum allowable value, which can not only effectively improve the effectiveness of CE error reporting, but also shorten the comparison operation in S203 and improve the overall processor error handling.

[0045] Furthermore, in order to accurately determine the current time, the clock processor of the present invention uses an RTC (Real-time Clock). The RTC processor communicates with the computer system through specific I / O ports. Its register addresses are located at 0x70 and 0x71. The register addresses are used to access the control register and data register of the RTC processor. That is, the address of the control register is 0x70, and the data register is 0x71. The address port is 0x70, and the data port is 0x71. The present invention also provides a method for determining the current time, which may include the following content:

[0046] When receiving the current time acquisition instruction, the BIOS generates an SMI event to access the RTC through the SMM protocol. The RTC processor is accessed through the address port and data port of the I / O port. Based on the control register address, the BIOS writes a specific command byte to the control register of the RTC processor to specify the register address to be read. After sending the read command, the BIOS obtains the time data stored in the RTC processor by reading the data register and converts the read current time data into target format data.

[0047] In this embodiment, the CPU can be switched to the SMM mode by writing to the APM (Advanced Power Management Port) control port, such as 0xB2, or by configuring the register to generate an SMI event. At this time, the CPU saves the current context and jumps to the SMM handler for execution. The CPU runs the predefined SMM handler code in the SMM memory area. For example, to read the seconds register, the BIOS writes 0x00 to port 0x70. When writing, the highest bit can be set, such as 0x80, to disable the NMI (Non-Maskable Interrupt) to ensure the atomicity of the operation. Read the register value from port 0x71, such as: minutes register: address 0x02; hours register: address 0x04; day register: address 0x07; month register: address 0x08; year register: address 0x09. The RTC processor returns each part of the current time, such as seconds, minutes, hours, date, month, and year. The time data in the RTC processor is usually stored in the BCD (Binary-Coded Decimal) format. The BIOS needs to convert this BCD format data into the binary format for further processing. After reading and converting the time data, the BIOS stores this data in the memory and passes this time information to the operating system during the system startup process. Then, read the UIP (Update In Progress) bit of the status register A (address 0x0A). If UIP = 1, the RTC is updating the data and it is necessary to wait for it to complete. After it completes, that is, after the time reading is completed, the BIOS exits the SMM mode and resumes the normal system operation. For example, it can exit the SMM through the RSM instruction, restore the CPU context, and return to the original execution flow.

[0048] As can be seen from the above, the BIOS of this embodiment can use the SMM protocol and the address of the RTC processor to accurately read the current time and pass it to the computer system, so as to obtain the accurate time interval when the customer's required time threshold is accumulated. Based on the customer's demand for timed and quantitative cleaning of the CPU CE, the function of dynamically cleaning the CPU CE by opening the Setup option is realized, which not only reduces the risk of generating a CE storm, but also selectively makes the CPU anomalies perceived by the operation and maintenance personnel in a timely manner, reducing the ineffective investment of the customer's operation and maintenance personnel.

[0049] In order to further improve the processor error handling efficiency, after polling the error type identifier of the error in each error register that stores the hardware error information through the error information collection thread, the obtained error data can also be stored in a specified data structure to facilitate more quickly determining the number of CPU CEs. It can include the following content:

[0050] Pre-construct an error storage structure; if the currently queried register is a target register that stores at least correctable errors, update the register parameters; update the processor parameters according to the physical parameter information of the processor to which the target register belongs; update the error information according to the correctable errors stored in the target register. If the register parameters in the error storage structure are not empty, construct a correctable error loop screening thread; use the correctable error loop screening thread to identify correctable errors by querying the error information in the error storage structure and count the occurrence times of the correctable errors.

[0051] In this embodiment, the error storage structure can be represented as RAS_MCA_ERROR_INFO for example. The error storage structure includes at least processor parameters, register parameters and error information. The processor parameters can at least include the identification information of the processor where the CE occurs. The register parameters at least include the error type information corresponding to the correctable errors of the processor, such as the error type identifier uniquely corresponding to the error type. Of course, it can also include the corresponding target area, register identifier and the number of registers belonging to the correctable error corresponding to the error type information of the processor. For example, this structure contains the CPU ID (identification number), the number of MCA Bank registers with correctable errors of the processor, and all error information in the MCA Bank registers. The BIOS will judge whether the number of MCA Bank registers in this structure is 0. If it is 0, then the CPU has not detected error information at this time; if it is not 0, the BIOS will use a for loop to screen out the CPU CE error information by judging the value of the MCA register. This value is the data that can identify the correctable errors of the processor, and its number is recorded as CPUCECount. That is, the occurrence times of the correctable errors can be represented by CPUCECount.

[0052] The above embodiments do not make any limitations on how to generate error reporting instructions and error clearing instructions. Based on the above embodiments, the present invention also gives an exemplary implementation method, which may include the following content:

[0053] The target fault tolerance allowable values of this embodiment include the number fault tolerance allowable value and the corresponding duration value. When it is determined according to the processor error degree data that the number of correctable errors occurring in the processor is greater than or equal to the duration of the number fault tolerance allowable value within the duration value, an error reporting instruction and an error clearing instruction are generated simultaneously. At this time, the log recording function is triggered to record the target correctable errors exceeding the number fault tolerance allowable value into the target error file; the target error file is a file that records the error information during the startup process and participates in the statistics of the number of correctable errors in the next round; an error update instruction is generated to enable the management controller to display the target correctable error record in the system log; based on the error clearing instruction, the register clearing function is called to clear the correctable error in the target register. When it is determined according to the processor error degree data that the number of correctable errors occurring in the processor is greater than or equal to the duration of the number fault tolerance allowable value and exceeds the duration value, only the error clearing instruction is generated. At this time, based on the error clearing instruction, the register clearing function is called to clear the correctable error in the target register.

[0054] In this embodiment, for example, the initial time can be expressed as T0D * 24 + T0H, the current time can be expressed as T2D * 24 + T2H, and the duration value can be (T2D * 24 + T2H) - (T0D * 24 + T0H). When CPUCECount is greater than or equal to CPUCECountThrottle, calculate whether the time of (T2D * 24 + T2H) - (T0D * 24 + T0H) exceeds CPUCETimeThrottle to confirm whether this CPU CE error needs to be reported. When the value of (T2D * 24 + T2H) - (T0D * 24 + T0H) is less than or equal to CPUCETimeThrottle, calculate the value of CPUCECount – CPUCECountThrottle, which can trigger the log recording function to record each CE quantity exceeding the threshold into the BERT table of the operating system (a mechanism for recording and reporting error information during system startup), and at the same time trigger the SMI to report to the BMC, and then the BMC will display it in the system log of the BMC. Finally, use the register clearing function to subtract the CPU CE errors within the MCA register threshold, and the remaining CPU CE errors enter the next round of accumulation. When the value of (T2D * 24 + T2H) - (T0D * 24 + T0H) is greater than CPUCETimeThrottle, the current CPU CE quantity is not sufficient to threaten the normal operation of the CPU, and the register clearing function can be directly called to completely clear the CPU CE errors in the MCA register and start the next round of accumulation.

[0055] To make the technical solution of the present invention clearer to those skilled in the art, the present invention also provides an implementation of an example. In this embodiment, the processor CE is the CPU CE, the setting interface is the Setup (setting page) of the BIOS, and the target fault tolerance allowable values may include the number fault tolerance allowable value CPUCECountThrottle and the corresponding duration value CPUCETimeThrottle, as Figure 3 shown, the central processing unit error handling process may include the following:

[0056] After the CPU CE occurs, the BIOS calls the RAS fault diagnosis driver to handle the CPU CE fault. At this stage, the BIOS executes the program for initializing and assigning values to CPUCETimeThrottle and CPUCECountThrottle, forming BIOS options with multiple selectable values displayed on the Setup. During this process, it is possible to set according to user requirements how many CPU CEs need to accumulate within a certain time before the BIOS reports the CE error to the BMC and the OS.

[0057] The BIOS executes the SMI handler for entering the SMM mode: determines whether the CPU supports the PFEH function. If it does not support, the CPU model and the corresponding RAS policy are recorded, and then the entire process ends. If it supports, the BIOS loads the SMM software scheduling protocol to manage and respond to underlying hardware events, triggers the SMI program to poll the error information inside all CPU Bank registers by calling the software SMI callback interface. After all errors are polled, the BIOS creates RAS_MCA_ERROR_INFO that stores all the error information in the MCA register. This structure contains CPU information, the number of MCA Bank registers with error information, and all the error information in the MCA Bank registers. The BIOS determines whether the number of MCA Bank registers in RAS_MCA_ERROR_INFO is 0. If it is 0, then at this time the CPU has not detected error information; if it is not 0, the BIOS uses a for loop to filter out the CPU CE error information by judging the value of the MCA status register, and records the CPU CE count through CPUCECount.

[0058] When the computer system is just powered on, the BIOS records the timestamp including day, hour, minute, and second based on the power-on action as the initial time, which can be represented as T0D, T0H, T0M, and T0S. When the CPUCECount collected by the BIOS is greater than or equal to CPUCECountThrottle, the BIOS obtains the current time according to the address of the RTC clock processor, which can be represented as T2D, T2H, T2M, and T2S. The BIOS calculates whether the time of (T2D * 24 + T2H) - (T0D * 24 + T0H) exceeds CPUCETimeThrottle. When the value of (T2D * 24 + T2H) - (T0D * 24 + T0H) is less than or equal to CPUCETimeThrottle, calculate the value of CPUCECount – CPUCECountThrottle, which can trigger the logging function to record the exceeded CE counts one by one into the BERT table of the operating system. At the same time, trigger the SMI to report to the BMC, and then the BMC displays it in the system log of the BMC. Finally, the BIOS uses the register clearing function to subtract the CPU CE errors within the MCA register threshold, and the remaining CPU CE errors enter the next round of accumulation. When the value of (T2D * 24 + T2H) - (T0D * 24 + T0H) is greater than CPUCETimeThrottle, the current CPU CE count is not sufficient to threaten the normal operation of the CPU, and the register clearing function can be directly called to completely clear the CPUCE errors in the MCA register and start the next round of accumulation. At the same time, the BIOS assigns T2D, T2H, T2M, and T2S to T0D, T0H, T0M, and T0S to start a new cycle count.

[0059] As can be seen from the above, this embodiment can effectively reduce the probability of the occurrence of CPU CE storms. Users can perceive the CE error types, which is beneficial to improving the accuracy and efficiency of fault identification and enhancing the stability and reliability of the server.

[0060] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method. The present invention also provides a corresponding device for the processor error handling method, further making the method more practical. Among them, the device can be described from the perspective of functional modules and the perspective of hardware respectively. The following introduces the language task processing device provided by the present invention, which is used to implement the processor error handling method provided by the present invention. The description of the features in the corresponding embodiment of the language task processing device can refer to the relevant description of the corresponding embodiment of the processor error handling method, and the device embodiment will not be elaborated one by one.

[0061] From the perspective of functional modules, please refer to Figure 4 , Figure 4 which is the structural diagram of the processor error handling device provided in this embodiment under an exemplary implementation manner. The device may include:

[0062] A parameter configuration module 401, configured to display a setting interface including error parameter configuration options when a correctable error occurs in the processor, and set a target fault tolerance allowable value corresponding to the correctable error for the error parameter configuration options; the target fault tolerance allowable value is the maximum number of correctable errors that can occur within an allowable time period.

[0063] An error degree determination module 402, configured to, in the execution environment corresponding to the system management mode, during the process of obtaining multi-device error collection information at the current moment from each error register, select the correctable error of the processor from each error register according to the error type identifier of the correctable error of the processor, and separately accumulate the correctable error of the processor to the target area of the corresponding error register, and determine the number of times of generation of the correctable error of the processor within the target time period based on the accumulated data in the target area as the processor error degree data. Among them, the error register will pre-assign a unique identifier to different error types. Whenever an error occurs, the error register determines the corresponding error type identifier according to the error type to which the current error belongs, and stores the currently generated error and its error type identifier.

[0064] An instruction generation module 403, configured to determine whether to generate an error reporting instruction and an error clearing instruction according to the processor error degree data and the target fault tolerance allowable value, so as to send the correctable error to the management controller through the error reporting instruction, and clear the record data of the correctable error from the target register through the error clearing instruction.

[0065] Exemplarily, in some implementations of this embodiment, the above error degree determination module 402 may further be configured to: The target fault tolerance allowable value includes a number fault tolerance allowable value and a corresponding duration value. When the processor has the platform error priority processing function, trigger an error information collection thread through the callback interface of the system management interrupt; through the error information collection thread, poll the error type identifiers of the errors in each error register storing hardware error information. If the error type identifier of the current error is not the error type identifier of the first type of error and is not the error type identifier of the second type of error, then mark the current error as an error generated by the processor itself and accumulate the current error to the target area of the corresponding error register; identify the correctable errors of the processor from each target area according to the error types of the correctable errors of the processor, and count the occurrence times of the correctable errors; when the occurrence times of the correctable errors are greater than or equal to the number fault tolerance allowable value, determine the current time through the address of the clock processor, and determine the current duration according to the current time and the time initial value; use the current duration and the total number of occurrences of the correctable errors corresponding to the current moment as the processor error degree data at the current moment.

[0066] As an exemplary implementation manner of the above embodiment, the above error degree determination module 402 may be configured to: determine the time initial value of the correctable error according to the time stamp corresponding to the power-on operation; determine the current moment value according to the day parameter and hour parameter corresponding to the current time; determine the initial moment value according to the day parameter and hour parameter corresponding to the time initial value; use the difference between the current moment value and the initial moment value as the current duration value.

[0067] Exemplarily, in some implementations of this embodiment, the above device may further include a data storage module, and this module may be configured to: pre-construct an error storage structure; the error storage structure at least includes processor parameters, register parameters, and error information; the register parameters at least include the error type information corresponding to the correctable errors of the processor; if the currently queried register is a target register that stores at least the correctable errors of the processor, then update the register parameters; update the processor parameters according to the physical parameter information of the processor to which the target register belongs; update the error information according to the correctable errors stored in the target register.

[0068] As an exemplary implementation manner of the above embodiment, the above error degree determination module 402 may further be configured to: if the register parameters in the error storage structure are not empty, then construct a correctable error loop screening thread; use the correctable error loop screening thread to identify the correctable errors by querying the error information in the error storage structure, and count the occurrence times of the correctable errors.

[0069] Exemplarily, in some other embodiments of this embodiment, the above instruction generation module 403 may further be configured to: The target fault tolerance allowable value includes a number fault tolerance allowable value and a corresponding duration value. When it is determined according to the processor error degree data that the number of correctable errors occurring in the processor is greater than or equal to the duration of the number fault tolerance allowable value and within the duration value, an error reporting instruction and an error clearing instruction are generated simultaneously. When it is determined according to the processor error degree data that the number of correctable errors occurring in the processor is greater than or equal to the duration of the number fault tolerance allowable value and exceeds the duration value, only an error clearing instruction is generated.

[0070] As an exemplary implementation manner of the above embodiment, the above instruction generation module 403 may be configured to: When an error reporting instruction and an error clearing instruction are generated simultaneously, trigger a logging function to record the target correctable error exceeding the number fault tolerance allowable value into the target error file; the target error file is a file for recording error information during the startup process and participates in the statistics of the number of correctable errors in the next round; generate an error update instruction to enable the management controller to display the target correctable error record in the system log; based on the error clearing instruction, call a register clearing function to clear the correctable error in the target register. When only an error clearing instruction is generated, based on the error clearing instruction, call a register clearing function to clear the correctable error in the target register.

[0071] Exemplarily, in some other embodiments of this embodiment, the above parameter configuration module 401 may further be configured to: When an error parameter adjustment instruction is detected, display a setting interface including the number fault tolerance allowable value and the corresponding duration value; receive a user input error parameter input instruction, and obtain a new number fault tolerance allowable value and a corresponding new duration value by parsing the error parameter input instruction; update the local number fault tolerance allowable value and the corresponding duration value according to the new number fault tolerance allowable value and the new duration value.

[0072] Exemplarily, in some other embodiments of this embodiment, the above parameter configuration module 401 may further be configured to: The target fault tolerance allowable value includes a number fault tolerance allowable value and a corresponding duration value. Display a setting interface including error parameter configuration options; select the error type as a correctable error in the error parameter configuration options of the setting interface, and display a setting interface including an error occurrence times option and a corresponding error cumulative time option; set the number fault tolerance allowable value corresponding to the correctable error for the error occurrence times option, and set the duration value corresponding to the correctable error for the error cumulative time option.

[0073] The processor error handling device mentioned above is described from the perspective of functional modules. Further, the present invention also provides an electronic device, which is described from the hardware perspective. The electronic device includes a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned processor error handling method embodiments.

[0074] An embodiment of the present application also provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps in any of the above-mentioned processor error handling method embodiments when running.

[0075] In an exemplary embodiment, the above-mentioned computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memories (ROM for short), random access memories (RAM for short), mobile hard disks, magnetic disks, or optical discs, etc., all kinds of media that can store computer programs.

[0076] An embodiment of the present application also provides a computer program product. The above-mentioned computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-mentioned processor error handling method embodiments.

[0077] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above-mentioned processor error handling method embodiments.

[0078] Finally, the present invention also provides a server, as Figure 5 shown, the server may include a basic input / output system 501, a central processing unit 502, and a baseboard management controller 503.

[0079] Among them, the central processing unit 502 includes cores, caches, and registers. It usually contains multiple cores, each of which can execute instructions independently; the cache can be divided into different levels such as L1, L2, and L3, which are used to store the most recent or frequently used data to speed up access; the registers are high-speed storage units inside the CPU, which are used to temporarily store the data required during the execution of instructions. At least one register stores the error information of the hardware device, such as the MAC register. The central processing unit 502 performs arithmetic and logical operations, controls the data flow, and processes input / output operations by executing the instruction set in the computer program. The instruction cycle includes three basic stages: instruction fetching, decoding, and execution; the pipeline improves efficiency by decomposing instructions into several small steps and simultaneously processing different parts of multiple instructions; hyper-threading allows a physical core to simulate two logical cores, thereby improving the concurrent processing ability. The performance metrics of the CPU include: the clock frequency (Clock Speed) that measures how many clock cycles the CPU can complete per second, and the unit is usually GHz; IPC (Instructions Per Cycle): the number of instructions that can be executed within each clock cycle; the number of cores and threads: more cores and threads mean stronger parallel processing ability; TDP (Thermal Design Power, power consumption): represents the maximum thermal design power of the CPU, which affects the thermal design and power supply requirements. The maintenance and optimization of the CPU include: heat dissipation management needs to be carried out to ensure good heat dissipation conditions and avoid frequency reduction or even damage due to overheating; keep the operating system and related driver programs up-to-date through driver updates to obtain the best compatibility and performance. By reasonably configuring the BIOS options, such as adjusting parameters such as the working frequency and voltage of the CPU, the performance can be improved or energy can be saved to a certain extent.

[0080] In this embodiment, the basic input / output system 501 includes a setup interface, which is used to implement the steps in any of the above-mentioned embodiments of the processor error handling method when executing a computer program. When the CPU can normally write the CPU CE into the MCA register, the BIOS 501 sets two Setup options for the CPU CE on the Setup page to identify the cumulative time threshold and the cumulative quantity threshold for reporting to the OS and the BMC 503. The BIOS obtains the time interval when the cumulative time reaches the customer-requested time threshold with the help of the RTC clock processor according to the SMM-related protocol. When the number of CPU CEs accumulated in the MCA register reaches the allowable value of the number of fault tolerances for the customer-requested number of times, the time judgment is triggered. When the duration is less than the allowable value of the number of fault tolerances and the corresponding duration value, an error reporting instruction and an error clearing instruction are generated, and the generated error reporting instruction is sent to the baseboard management controller 503, and the data in the MAC register is cleared through the error clearing instruction.

[0081] The above has introduced in detail a processor error handling method, an electronic device, a computer-readable storage medium, and a computer program product provided by the present invention. Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is the difference from other embodiments. For the same or similar parts between the embodiments, reference can be made to each other. Whether the units and algorithm steps of each example described in the disclosed embodiments are executed in the form of electronic hardware or computer software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, and such implementation should not be considered to exceed the scope of the present invention. Without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A processor error handling method, characterized in that, Including: The error register classifies error types into first - type errors, second - type errors, and errors generated by the processor itself. The first - type errors and the second - type errors include all error types except for the correctable errors of the processor, which is applicable to scenarios with high requirements for the reporting accuracy of the processor's correctable errors; or, the first - type errors and the second - type errors include all error types except for the errors of the processor itself, which is applicable to scenarios where the errors of the processor need to be reported separately; Whenever an error occurs, the error register assigns a unique identifier to the first - type errors and the second - type errors. If the error type identifier of the current error is not the error type identifier of the first - type error and is also not the error type identifier of the second - type error, then the current error is marked as an error generated by the processor itself, so as to accumulate the current error to the target area of the corresponding error register and store the currently generated error and its error type identifier; When a correctable error occurs in the processor, a setting interface including error parameter configuration options is displayed, and the target fault tolerance allowable value corresponding to the correctable error of the processor is set for the error parameter configuration options; The target fault tolerance allowable value is the maximum number of times that the correctable error of the processor occurs within the allowable time period; In the execution environment corresponding to the system management mode, during the process of obtaining the multi - device error collection information at the current moment from each error register, according to the error type identifier of the correctable error of the processor, the correctable error of the processor is selected from each error register, and the correctable error of the processor is separately accumulated to the target area of the corresponding error register. According to the accumulated data in the target area, the number of times of the correctable error generated by the processor within the target time period is determined as the processor error degree data; According to the processor error degree data and the target fault tolerance allowable value, it is determined whether to generate an error reporting instruction and an error clearing instruction, so as to send the correctable error to the management controller through the error reporting instruction and clear the record data of the correctable error from the target register through the error clearing instruction; 2. The processor error handling method according to claim 1, wherein The target fault tolerance allowable value includes a number fault tolerance allowable value and a corresponding duration value. Determining the number of times of the correctable error generated by the processor within the target time period according to the accumulated data in the target area includes: When the processor has the platform error priority processing function, an error information collection thread is triggered through the callback interface of the system management interrupt; Through the error information collection thread, the error type identifiers of the errors in each error register storing hardware error information are polled; If the error type identifier of the current error is not the error type identifier of the first - type error and is also not the error type identifier of the second - type error, then the current error is marked as an error generated by the processor itself and the current error is accumulated to the target area of the corresponding error register; The correctable error of the processor is identified from each target area according to the error type of the correctable error of the processor, and the number of occurrences of the correctable error is counted; When the occurrence times of the correctable error are greater than or equal to the allowable value of the error tolerance times, the current time is determined through the address of the clock processor, and the current duration is determined according to the current time and the initial time value; The current duration and the total occurrence times of the correctable error corresponding to the current moment are used as the processor error degree data at the current moment.

3. The processor error handling method according to claim 2, wherein Determining the current duration according to the current time and the initial time value includes: Determining the initial time value of the correctable error according to the time stamp corresponding to the power-on operation; Determining the current moment value according to the day parameter and the hour parameter corresponding to the current time; Determining the initial moment value according to the day parameter and the hour parameter corresponding to the initial time value; Taking the difference between the current moment value and the initial moment value as the current duration value.

4. The processor error handling method according to claim 2, wherein After polling the error type identifiers of the errors in each error register storing hardware error information through the error information collection thread, it further includes: Pre-constructing an error storage structure; the error storage structure at least includes processor parameters, register parameters and error information; the register parameters at least include the error type information corresponding to the correctable error of the processor; If the currently queried register is a target register that stores at least the correctable error of the processor, update the register parameters; Update the processor parameters according to the physical parameter information of the processor to which the target register belongs; update the error information according to the correctable error stored in the target register.

5. The processor error handling method according to claim 4, wherein Determining the generation times of the correctable error of the processor within the target time period according to the cumulative data of the target area includes: If the register parameters in the error storage structure are not empty, construct a correctable error loop screening thread; Using the correctable error loop screening thread, identify the correctable error by querying the error information in the error storage structure, and count the occurrence times of the correctable error.

6. The processor error handling method according to claim 1, wherein The target error tolerance allowable value includes an allowable value of error tolerance times and a corresponding duration value. Determining whether to generate an error reporting instruction and an error clearing instruction according to the processor error degree data and the target error tolerance allowable value includes: When it is determined according to the processor error degree data that the occurrence times of the correctable error of the processor are greater than or equal to the duration of the allowable value of the error tolerance times within the duration value, generate an error reporting instruction and an error clearing instruction simultaneously.

7. The processor error handling method according to claim 6, characterized in that, After generating the error clearing instruction, it further includes: Trigger a log recording function to record the target correctable error exceeding the allowable value of the error tolerance times into a target error file; the target error file is a file recording the error information during the startup process and participates in the statistics of the next round of occurrence times of the correctable error; Generate an error update instruction to enable the management controller to display the record of the target correctable error in the system log; Based on the error clearing instruction, call a register clearing function to clear the correctable error in the target register.

8. The processor error handling method according to claim 1, wherein The target fault tolerance allowable value includes a number fault tolerance allowable value and a corresponding duration value. Based on the processor error degree data and the target fault tolerance allowable value, determining whether to generate an error reporting instruction and an error clearing instruction includes: When, according to the processor error degree data, it is determined that the number of times the correctable error occurs in the processor is greater than or equal to the duration of the number fault tolerance allowable value and exceeds the duration value, only an error clearing instruction is generated.

9. The processor error handling method according to claim 8, wherein After only generating the error clearing instruction, it further includes: Based on the error clearing instruction, calling a register clearing function to clear the correctable error in the target register.

10. The processor error handling method according to claim 1, wherein Before setting the target fault tolerance allowable value corresponding to the correctable error for the error parameter configuration option, it further includes: When an error parameter adjustment instruction is detected, a setting interface including the number fault tolerance allowable value and the corresponding duration value is displayed; Receiving an error parameter input instruction input by the user, and obtaining a new number fault tolerance allowable value and a corresponding new duration value by parsing the error parameter input instruction; Updating the local number fault tolerance allowable value and the corresponding duration value according to the new number fault tolerance allowable value and the new duration value.

11. The processor error handling method according to any one of claims 1 to 10, characterized in that The target fault tolerance allowable value includes a number fault tolerance allowable value and a corresponding duration value. Displaying a setting interface including an error parameter configuration option, and setting the target fault tolerance allowable value corresponding to the correctable error for the error parameter configuration option includes: Displaying a setting interface including an error parameter configuration option; Selecting the error type as the correctable error in the error parameter configuration option of the setting interface, and displaying a setting interface including an error occurrence times option and a corresponding error accumulation time option; Setting the number fault tolerance allowable value corresponding to the correctable error for the error occurrence times option, and setting the duration value corresponding to the correctable error for the error accumulation time option.

12. An electronic device, characterized in that, Includes: A memory for storing a computer program; A processor for implementing the steps of the processor error handling method according to any one of claims 1 to 11 when executing the computer program.

13. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the processor error handling method according to any one of claims 1 to 11 are implemented.

14. A computer program product, comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by a processor, the steps of the processor error handling method according to any one of claims 1 to 11 are implemented.

15. A server, characterized in that, Includes a basic input / output system, a central processing unit, and a baseboard management controller; Wherein, the central processing unit includes at least one register for storing hardware error information, and the basic input / output system includes a setting interface for implementing the steps of the processor error handling method according to any one of claims 1 to 11 when executing a computer program, and sending the generated error reporting instruction to the baseboard management controller.

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