Circuit board test point processing method and device, equipment and storage medium

Abstract

The invention provides a circuit board test point processing method and device, equipment and a storage medium, and the method comprises the steps: obtaining a design document of a to-be-tested circuit board, the design document at least comprising electronic components and a connection relation of the electronic components; obtaining a network list based on the design document of the circuit board to be tested and retrieving whether a test point exists in the network list, wherein the network list is used for recording a signal name list in a circuit and connection information of the signal name list; screening out a network containing a plurality of test points based on the network list and determining information of the plurality of test points; and determining a target test point from the plurality of test points based on a preset rule. Through the method, the problem of multiple test points in the circuit board file can be efficiently solved, the layout of the test points is optimized, and the test efficiency and accuracy are improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of printed circuit boards, and in particular, to a method, device, equipment, and storage medium for processing test points on a circuit board. Background Art

[0002] During the design stage of a printed circuit board (PCB), in order to ensure the performance and reliability of the circuit board, strict tests need to be carried out on network signals. Using an integrated circuit tester (ICT) for testing is a commonly used testing method. It uses probes to contact the test points on the PCB board to check the correctness of circuit connections and the performance of components.

[0003] In order to perform ICT testing, designers need to add test points on the PCB. These test points are the positions where the probes contact the circuit board, and they allow the testing instrument to read the status of network signals. However, in the actual design process, sometimes two or more test points are added to the same network signal. The repetitive number of network signal test points will not only reduce the design efficiency of designers, but also increase the cost of the ICT testing needle placement fixture and the later maintenance cost, and increase the solder paste cost of the PCB made test points on the soldering surface. Summary of the Invention

[0004] The present disclosure provides a method, device, equipment, and storage medium for processing test points on a circuit board to at least solve the above technical problems existing in the prior art.

[0005] According to a first aspect of the present disclosure, a method for processing test points on a circuit board is provided. The method includes:

[0006] Obtain a design document of the circuit board to be tested, where the design document at least includes electronic components and the connection relationships of the electronic components;

[0007] Based on the design document of the circuit board to be tested, obtain a network list and retrieve whether there are test points in the network list. The network list is used to record the list of signal names in the circuit and their connection information;

[0008] Based on the network list, filter out the networks containing multiple test points and determine the information of the multiple test points;

[0009] Determine a target test point from the multiple test points based on a preset rule.

[0010] In an implementable embodiment, the step of obtaining a network list based on the design document of the circuit board to be tested and retrieving whether there are test points in the network list includes:

[0011] Analyze the design document of the circuit board to be tested to obtain design data;

[0012] Obtain a network list based on the design data.

[0013] In one implementable manner, the screening out the networks containing multiple test points based on the network list and determining the information of the multiple test points includes:

[0014] Traverse the network list, detect whether each network contains test points and record the number of test points;

[0015] Determine the networks containing multiple test points from the networks containing test points and obtain the position information of each test point.

[0016] In one implementable manner, the determining the target test point from multiple test points based on preset rules includes:

[0017] Preset the priority rules for the positions of the test points;

[0018] Determine the priority order of each test point based on the position of each test point and the priority rules;

[0019] Determine the test point with the highest priority order as the target test point.

[0020] In one implementable manner, the method further includes:

[0021] Determine the other test points except the target test point among the multiple test points as the test points to be cleared, and output a prompt message.

[0022] In one implementable manner, the method further includes:

[0023] Respond to the deletion instruction and delete the test points to be cleared.

[0024] According to the second aspect of the present disclosure, there is provided a circuit board test point processing device, the device includes:

[0025] An acquisition module, configured to acquire a design document of a circuit board to be tested, where the design document at least includes electronic components and the connection relationship of the electronic components;

[0026] A retrieval module, configured to obtain a network list based on the design document of the circuit board to be tested and retrieve whether there are test points in the network list, where the network list is used to record the signal name list in the circuit and its connection information;

[0027] A screening module, configured to screen out the networks containing multiple test points based on the network list and determine the information of the multiple test points;

[0028] A determination module, configured to determine a target test point from multiple test points based on a preset rule.

[0029] In an implementable embodiment, the apparatus further includes:

[0030] A deletion module, configured to determine other test points except the target test point among the multiple test points as test points to be cleared, and output a prompt message;

[0031] In response to a deletion instruction, delete the test points to be cleared.

[0032] According to a third aspect of the present disclosure, there is provided an electronic device, including:

[0033] At least one processor; and

[0034] A memory communicatively connected to the at least one processor; wherein,

[0035] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method described in the present disclosure.

[0036] According to a fourth aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions, and the computer instructions are used to cause a computer to execute the method described in the present disclosure.

[0037] The present disclosure provides a method, apparatus, device and storage medium for processing circuit board test points. By obtaining a design document of a circuit board to be tested, the design document at least includes electronic components and the connection relationship of the electronic components; then obtaining a network list based on the design document of the circuit board to be tested and retrieving whether there are test points in the network list, where the network list is used to record the signal name list and its connection information in the circuit; screening out the networks containing multiple test points based on the network list and determining the information of the multiple test points; finally determining the target test point from the multiple test points based on a preset rule. Through this method, the problem of multiple test points in the circuit board file can be efficiently processed, thereby optimizing the test point layout and improving the test efficiency and accuracy.

[0038] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] By referring to the drawings and reading the following detailed description, the above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become easily understood. In the drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, wherein:

[0040] In the accompanying drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[0041] Figure 1 A schematic flowchart of a method for processing test points on a circuit board according to an embodiment of the present disclosure is shown;

[0042] Figure 2 A schematic flowchart of another method for processing test points on a circuit board according to an embodiment of the present disclosure is shown;

[0043] Figure 3 A schematic diagram of a device for processing test points on a circuit board according to an embodiment of the present disclosure is shown;

[0044] Figure 4 A schematic diagram of another device for processing test points on a circuit board according to an embodiment of the present disclosure is shown;

[0045] Figure 5 A schematic diagram of the composition structure of an electronic device according to an embodiment of the present disclosure is shown. Detailed implementation manners

[0046] To make the objectives, features, and advantages of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present disclosure.

[0047] When there are two or more test points added to the same network signal on a PCB, the following problems will occur: (1) Repeatedly adding test points requires designers to spend more time and effort in checking and modifying the design. This not only increases the design cost but also reduces the design efficiency. (2) The ICT test cost is increased. The ICT test pinning fixture needs to be customized according to the test points on the PCB. If there are too many test points, especially when there are repeated test points, the complexity and cost of the fixture will increase accordingly. In addition, the later maintenance cost will also increase due to the increase in test points. (3) The solder paste cost is increased. During the PCB manufacturing process, the test points need to be tinned to ensure good contact with the probes. Therefore, the repeatedly added test points will increase the usage amount of solder paste, thereby increasing the manufacturing cost. Based on this, the present disclosure provides a method for processing test points on a circuit board (PCB) to solve the problem of multiple test points on the PCB, optimize the test point layout, and improve the test efficiency and accuracy.

[0048] According to an embodiment of the present disclosure, as Figure 1 A schematic flowchart of a method for processing test points on a circuit board is shown, and the method includes:

[0049] S1. Obtain the design document of the circuit board to be tested, where the design document at least includes electronic components and the connection relationships of the electronic components.

[0050] The design document of a PCB is a file used to store the circuit board design, containing all information such as the layout of the circuit board and electrical connections. The design formats include.brd files, Gerber files, netlist files, etc.

[0051] .brd file is a binary file used to describe the layout of a circuit board, containing the layout information of each component on the circuit board, such as the position, size, rotation angle of the components, etc. In addition, it may also contain some wiring information.

[0052] Gerber file is a set of document formats in the circuit board industry software to describe the images of the circuit board (such as the wiring layer, solder mask layer, character layer, etc.) and drilling and milling data, and it is the standard format for image conversion in the circuit board industry. The Gerber file contains a complete description of the images of each layer of the circuit board, with all the elements required for circuit board imaging. It uses the ASCII format, containing a series of control codes and coordinate information, and can accurately describe the graphics and drilling information on the circuit board.

[0053] The netlist file (Netlist) is a file used to describe the connection relationships between circuit components, containing information about all components in the circuit and their connection relationships. This information is usually represented in the form of nodes (nets) or connections, describing the electrical connections between components.

[0054] S2. Obtain a network list based on the design document of the circuit board to be tested and retrieve whether there are test points in the network list. The network list is used to record the list of signal names in the circuit and their connection information.

[0055] By parsing the design document of the PCB to be tested, extract the network list from the parsed PCB data, that is, the list of signal names in the circuit and their connection information.

[0056] S3. Screen out the networks containing multiple test points based on the network list and determine the information of the multiple test points.

[0057] Traverse the network list to detect whether each network contains test points. Test points are set at specific positions on the PCB for testing or debugging. By traversing each network, identify the networks containing multiple test points, that is, it can be determined that there are multiple test points in this network. Multiple test points refer to the existence of multiple measurement points for testing in a network. For the networks containing multiple test points, obtain the information of each test point, such as position, type, attributes, etc.

[0058] S4. Determine the target test point from multiple test points based on a preset rule.

[0059] Set a preset rule according to factors such as test requirements, circuit performance, testability, etc. The preset rule is used to select an optimal test point from multiple test points as the target test point.

[0060] In the above solution, by obtaining the design document of the circuit board to be tested, the design document at least includes electronic components and the connection relationship of the electronic components; then obtain the network list based on the design document of the circuit board to be tested and retrieve whether there are test points in the network list, where the network list is used to record the list of signal names in the circuit and their connection information; screen out the networks containing multiple test points based on the network list and determine the information of multiple test points; finally, determine the target test point from multiple test points based on the preset rule. Through this method, the problem of multiple test points in the circuit board file can be efficiently processed, the test point layout can be optimized, and the test efficiency and accuracy can be improved.

[0061] In one example, the obtaining the network list based on the design document of the circuit board to be tested and retrieving whether there are test points in the network list includes:

[0062] Parse the design document of the circuit board to be tested to obtain design data;

[0063] Obtain the network list based on the design data.

[0064] Based on the format type of the design document, use the corresponding parsing tool or library to read and parse these design documents, convert the information in the documents into a computer - processable format, such as a data structure or an object model, to obtain design data. The generated design data contains all the key information of the circuit board, such as component positions, network connections, test point positions, etc.

[0065] Extract the network connection information from the design data and organize it into a network list. The network list can be a list that lists all the signal names in the circuit and their connection relationships, and each signal may be connected to multiple components or test points.

[0066] In one example, the screening out the networks containing multiple test points based on the network list and determining the information of multiple test points includes:

[0067] Traverse the network list, detect whether each network contains test points and record the number of test points;

[0068] Determine the networks containing multiple test points from the networks containing test points and obtain the position information of each test point.

[0069] Starting from the beginning of the network list, check each network one by one. For the network currently being checked, see if it contains test points. For example, it can be determined whether there are test points by checking the attributes or marks of the network. For the network containing test points, count and record the number of test points. Compare the number of test points recorded for each network, and filter out those networks with more than 1 test point. Then generate a list or data structure of networks containing multiple test points. For the filtered networks containing multiple test points, further obtain the location information of each test point, such as including the coordinates of the test point on the circuit board, the layer it is on, and its relative position to the surrounding components.

[0070] In one example, determining the target test point from multiple test points based on a preset rule and deleting the remaining test points includes:

[0071] A priority rule for the positions of preset test points;

[0072] Determine the priority order of each test point based on the position of each test point and the priority rule;

[0073] Determine the test point with the highest priority order as the target test point.

[0074] In one example, the priority rule for the positions of test points is Pin (priority 1) > Via (priority 2) > Cline (priority 3) > Shape (priority 4).

[0075] Where Pin means the test point is a pin and has the highest priority; Via means the test point is a via, which will be retained and may replace the pad; Cline means the test point is a test point on the connection line; Shape means the test point is a test point on the shape.

[0076] Traverse the filtered networks containing multiple test points, and sort the test points in each network according to their positions and the preset priority rule. Check the type (Pin, Via, Cline, Shape) of each test point, and assign the corresponding priority according to its type. A list of test points sorted by priority can also be generated for each network. In the list of test points for each network, select the test point with the highest priority as the target test point. If the network contains a Pin, then the Pin is the target test point; if the network does not contain a Pin, then select the test point with the second highest priority (such as Via), and so on.

[0077] In one example, as Figure 2 shown, the method further includes:

[0078] S5. Determine the other test points except the target test point among the multiple test points as the test points to be cleared, and output a prompt message.

[0079] After determining the target test point, determine all other test points in the network except the target test point as the test points to be cleared, and output a prompt message to the user indicating which test points are marked as test points to be cleared. The prompt message may include information such as the number, location (such as coordinates), type, etc. of the test points to be cleared, so that the user can understand the content to be deleted. This step ensures that the user understands the upcoming deletion operation and avoids accidentally deleting important test points.

[0080] The method further includes:

[0081] In response to the deletion instruction, delete the test points to be cleared.

[0082] After outputting the prompt message, wait for the user to input a deletion instruction or perform other confirmation operations. For example, the user can confirm whether to delete the test points to be cleared by clicking a button, entering a command, etc. If the user confirms the deletion (i.e., enters a deletion instruction), then perform the deletion operation and delete all the test points to be cleared from the circuit board design document. For example, the test points can be located and deleted in the circuit board design document according to the identifiers or location information of the test points to be cleared. After the deletion operation is completed, it should be verified whether the deletion is successful, and it should be checked whether the circuit board design still maintains integrity and consistency.

[0083] According to an embodiment of the present disclosure, as Figure 3 FIG. shows a schematic diagram of a circuit board test point processing device provided by the present disclosure. The device includes:

[0084] An acquisition module 10, configured to acquire a design document of a circuit board to be tested, where the design document at least includes electronic components and the connection relationships of the electronic components;

[0085] A retrieval module 20, configured to obtain a network list based on the design document of the circuit board to be tested and retrieve whether there are test points in the network list, where the network list is used to record a list of signal names in the circuit and their connection information;

[0086] A screening module 30, configured to screen out the networks containing multiple test points based on the network list and determine the information of the multiple test points;

[0087] A determination module 40, configured to determine a target test point from the multiple test points based on a preset rule.

[0088] In one example, the retrieval module 20 is further configured to:

[0089] Parse the design document of the circuit board to be tested to obtain design data;

[0090] Obtain a network list based on the design data.

[0091] In one example, the screening module 30 is further configured to:

[0092] Traverse the network list, detect whether each network contains test points, and record the number of test points;

[0093] Determine the networks containing multiple test points from the networks containing test points and obtain the location information of each test point.

[0094] In one example, the determination module 40 is further configured to:

[0095] Preset the priority rules for the positions of the test points;

[0096] Determine the priority order of each test point based on the position of each test point and the priority rules;

[0097] Determine the test point with the highest priority order as the target test point.

[0098] In one example, as Figure 4 shown, the device further includes:

[0099] A deletion module 50, configured to determine the other test points except the target test point among the multiple test points as the test points to be cleared, and output a prompt message.

[0100] The deletion module 50 is further configured to respond to a deletion instruction and delete the test points to be cleared.

[0101] In the above solution, the acquisition module obtains the design document of the circuit board to be tested, and the design document at least includes electronic components and the connection relationship of the electronic components; then the retrieval module obtains the network list based on the design document of the circuit board to be tested and retrieves whether there are test points in the network list, where the network list is used to record the list of signal names in the circuit and their connection information; the screening module filters out the networks containing multiple test points based on the network list and determines the information of the multiple test points; finally, the determination module determines the target test point from the multiple test points based on the preset rules. Through this method, the problem of multiple test points in the circuit board file can be efficiently processed, the test point layout can be optimized, and the test efficiency and accuracy can be improved.

[0102] According to an embodiment of the present disclosure, the present disclosure further provides an electronic device, including:

[0103] At least one processor; and

[0104] A memory communicatively connected to the at least one processor; wherein,

[0105] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method described in the present disclosure.

[0106] According to an embodiment of the present disclosure, the present disclosure also provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the method of the present disclosure.

[0107] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

[0108] Figure 5 FIG. shows a schematic block diagram of an exemplary electronic device 800 that can be used to implement embodiments of the present disclosure. The electronic device is intended to represent various forms of digital computers, such as, for example, a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as, for example, a personal digital processor, a cellular phone, a smart phone, a wearable device, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely exemplary and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0109] As Figure 5 shown, the device 800 includes a computing unit 801 that can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0110] A plurality of components in the device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the device 800 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0111] The computing unit 801 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 executes the various methods and processes described above, such as the circuit board test point processing method. For example, in some embodiments, the circuit board test point processing method can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed onto the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the circuit board test point processing method described above can be executed. Alternatively, in other embodiments, the computing unit 801 can be configured to execute the circuit board test point processing method in any other suitable manner (e.g., by means of firmware).

[0112] Various embodiments of the systems and techniques described above in this document can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a dedicated or general-purpose programmable processor, and can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0113] The program code for implementing the methods of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the program codes are executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program codes can be executed entirely on the machine, partially on the machine, as an independent software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0114] In the context of this disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0115] In order to provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, speech input, or tactile input).

[0116] The systems and techniques described herein can be implemented in a computing system including backend components (e.g., as a data server), or a computing system including middleware components (e.g., an application server), or a computing system including frontend components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system including any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0117] A computer system can include a client and a server. The client and the server are generally remote from each other and typically interact through a communication network. The relationship between the client and the server is generated by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, a server of a distributed system, or a server incorporating blockchain.

[0118] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution disclosed in this disclosure can be achieved, and no limitations are imposed herein.

[0119] In addition, the terms "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of this disclosure, "a plurality" means two or more, unless otherwise specifically defined.

[0120] As described above, the above are only specific embodiments of this disclosure, but the protection scope of this disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed in this disclosure can easily think of changes or substitutions, which should all be covered by the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be subject to the protection scope of the claims.

Claims

1. A circuit board test point processing method, characterized in that: The method comprises: Obtaining a design document of the circuit board to be tested, wherein the design document at least includes electronic components and connection relationships of the electronic components; Based on the design document of the circuit board to be tested, a network list is obtained and whether there is a test point in the network list is retrieved, wherein the network list is used to record a list of signal names in the circuit and their connection information; Filtering out a network including a plurality of test points based on the network list and determining information of the plurality of test points; A target test point is determined from a plurality of test points based on a preset rule.

2. The method according to claim 1, characterized in that The obtaining of a network list based on the design document of the circuit board to be tested and searching whether there is a test point in the network list includes: Parsing the design document of the circuit board to be tested to obtain design data; A netlist is obtained based on the design data.

3. The method according to claim 1, characterized in that The step of screening out a network including a plurality of test points based on the network list and determining information of the plurality of test points includes: Traversing the network list, detecting whether each network contains a test point and recording the number of test points; A network including a plurality of test points is determined from among the networks including the test points, and location information of each test point is obtained.

4. The method according to claim 1, characterized in that: The step of determining a target test point from a plurality of test points based on a preset rule includes: Priority rules for preset test point locations; Determine a priority order for each test point based on the position of each test point and the priority rule; The test point with the highest priority is determined as the target test point.

5. The method according to claim 1, characterized in that The method further includes: The other test points among the multiple test points except the target test point are determined as test points to be cleared, and prompt information is output.

6. The method according to claim 5, characterized in that The method further includes: In response to the deletion instruction, the test point to be cleared is deleted.

7. A circuit board test point processing device, characterized in that: The device comprises: An acquisition module, used to acquire a design document of the circuit board to be tested, wherein the design document at least includes electronic components and connection relationships of the electronic components; A retrieval module, used to obtain a network list based on the design document of the circuit board to be tested and to retrieve whether there is a test point in the network list, wherein the network list is used to record a list of signal names in the circuit and their connection information; A screening module, configured to screen out a network including a plurality of test points based on the network list and determine information of the plurality of test points; The determination module is used to determine a target test point from a plurality of test points based on a preset rule.

8. The device according to claim 7, characterized in that The device also includes: A deletion module, used for determining other test points among the multiple test points except the target test point as test points to be deleted, and outputting prompt information; In response to the deletion instruction, the test point to be cleared is deleted.

9. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to execute: Obtaining a design document of the circuit board to be tested, wherein the design document at least includes electronic components and connection relationships of the electronic components; Based on the design document of the circuit board to be tested, a network list is obtained and whether there is a test point in the network list is retrieved, wherein the network list is used to record a list of signal names in the circuit and their connection information; Filtering out a network including a plurality of test points based on the network list and determining information of the plurality of test points; A target test point is determined from a plurality of test points based on a preset rule.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute: Obtaining a design document of the circuit board to be tested, wherein the design document at least includes electronic components and connection relationships of the electronic components; Based on the design document of the circuit board to be tested, a network list is obtained and whether there is a test point in the network list is retrieved, wherein the network list is used to record a list of signal names in the circuit and their connection information; Filtering out a network including a plurality of test points based on the network list and determining information of the plurality of test points; A target test point is determined from a plurality of test points based on a preset rule.

Images