Manufacturing method of N-type deep buried layer and semiconductor device

Abstract

The embodiment of the invention provides a manufacturing method of an N-type deep buried layer and a semiconductor device, and the method comprises the steps: providing a substrate, coating the substrate with a photoresist layer, carrying out the exposure of the photoresist layer, carrying out the development of the exposed photoresist layer, obtaining a target substrate region, carrying out the first ion implantation processing of the target substrate region, and carrying out at least one time of ion implantation treatment containing phosphorus element on the target substrate region after the first ion implantation treatment is completed to form an N-type deep buried layer in the substrate, removing the residual photoresist layer on the substrate, and carrying out annealing treatment on the substrate. Transverse and longitudinal diffusion of the phosphorus element of the N-type deep buried layer is reduced, complex compensation measures are not needed, reasonable diffusion of the phosphorus element can be effectively controlled while the area of the device is prevented from being increased, and abnormity of the device is reduced.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor technology, and in particular, to a method for manufacturing an N-type buried layer and a semiconductor device. Background Art

[0002] Currently, in order to reduce the leakage current of the substrate, an ion implantation method including phosphorus element is used on a P-type substrate to form an N-type buried layer, and the P-type well region is isolated by the N-type buried layer. In the specific use process, the N-type well is connected to the N-type buried layer to provide a suitable potential to achieve a good isolation effect. However, phosphorus has the characteristic of easy diffusion, which is likely to generate abnormal leakage paths or cause isolation failure.

[0003] In related technologies, the ion implantation range of the N-type buried layer is reduced, and the shallow trench isolation distance in the X-axis direction is enlarged so that the required coverage range can be achieved after subsequent phosphorus diffusion, while leaving a safety isolation area. However, reducing the ion implantation range requires specifically formulating design process rules and adjusting according to different process processes. For example, different ion concentrations of the N-type buried layer result in different diffusion ranges. Also, for example, different thermal budgets in the production process of different products result in different diffusion ranges. The foregoing compensation measures are complex in operation, which will increase the device area and need to be improved. Summary of the Invention

[0004] Embodiments of the present application provide a method for manufacturing an N-type buried layer and a semiconductor device, which solve the problem that the compensation measures in related technologies are complex in operation and will increase the device area. It is realized that through an ion co-implantation process that comprehensively includes a first ion implantation process containing argon element and at least one ion implantation process containing phosphorus element, the phosphorus element in the N-type buried layer can have small lateral and longitudinal diffusion, high thermal stability after annealing, is not easily affected by heat treatment in subsequent processes, and does not require complex compensation measures. While avoiding an increase in the device area, it can effectively control the reasonable diffusion of phosphorus element and reduce device abnormalities.

[0005] In a first aspect, embodiments of the present application provide a method for manufacturing an N-type buried layer, including: Providing a substrate, coating a photoresist layer on the substrate, exposing the photoresist layer, and developing the exposed photoresist layer to obtain a target substrate region; Performing a first ion implantation process containing argon element on the target substrate region; Performing at least one ion implantation process containing phosphorus element on the target substrate region after the first ion implantation process is completed to form an N-type buried layer in the substrate; Removing the remaining photoresist layer on the substrate and annealing the substrate.

[0006] Optionally, the ion concentration of the first ion implantation process is , and the ion energy of the first ion implantation process is , and the implantation angle of the first ion implantation process is .

[0007] Optionally, the at least one ion implantation process including phosphorus element on the target substrate region after the first ion implantation process includes: Performing a second ion implantation process including phosphorus element on the target substrate region after the first ion implantation process, where the ion concentration of the second ion implantation process is , the ion energy of the second ion implantation process is , and the implantation angle of the second ion implantation process is .

[0008] Optionally, the at least one ion implantation process including phosphorus element on the target substrate region after the first ion implantation process includes: Performing a third ion implantation process including antimony element on the target substrate region after the first ion implantation process, where the ion concentration of the third ion implantation process is , the ion energy of the third ion implantation process is , and the implantation angle of the third ion implantation process is ; Performing a fourth ion implantation process including phosphorus element on the target substrate region after the third ion implantation process, where the ion concentration of the fourth ion implantation process is , the ion energy of the fourth ion implantation process is , and the implantation angle of the fourth ion implantation process is .

[0009] Optionally, the at least one ion implantation process including phosphorus element on the target substrate region after the first ion implantation process includes: Performing a fifth ion implantation process including antimony element on the target substrate region after the first ion implantation process, where the ion concentration of the fifth ion implantation process is , the ion energy of the fifth ion implantation process is , and the implantation angle of the fifth ion implantation process is ; Performing a sixth ion implantation process including phosphorus element on the target substrate region after the fifth ion implantation process, where the ion concentration of the sixth ion implantation process is , the ion energy of the sixth ion implantation process is , the implantation angle of the sixth ion implantation process is ; Perform a seventh ion implantation process containing phosphorus element on the target substrate region after the sixth ion implantation process is completed. The ion concentration of the seventh ion implantation process is , the ion energy of the seventh ion implantation process is , the implantation angle of the seventh ion implantation process is .

[0010] Optionally, performing at least one ion implantation process containing phosphorus element on the target substrate region after the first ion implantation process is completed includes: Perform an eighth ion implantation process containing antimony element on the target substrate region after the first ion implantation process is completed. The ion concentration of the eighth ion implantation process is , the ion energy of the eighth ion implantation process is , the implantation angle of the eighth ion implantation process is ; Perform a ninth ion implantation process containing antimony element on the target substrate region after the eighth ion implantation process is completed. The ion concentration of the ninth ion implantation process is , the ion energy of the ninth ion implantation process is , the implantation angle of the ninth ion implantation process is ; Perform a tenth ion implantation process containing phosphorus element on the target substrate region after the ninth ion implantation process is completed. The ion concentration of the tenth ion implantation process is , the ion energy of the tenth ion implantation process is , the implantation angle of the tenth ion implantation process is .

[0011] Optionally, the temperature of the first ion implantation process is .

[0012] Optionally, the temperature of the at least one ion implantation process is .

[0013] Optionally, the temperature of the annealing process is .

[0014] In a second aspect, an embodiment of the present application further provides a semiconductor device, and the manufacturing method of any embodiment of the present application is used to prepare an N-type buried layer.

[0015] In the embodiment of the present application, a substrate is provided, a photoresist layer is coated on the substrate, the photoresist layer is exposed, and the exposed photoresist layer is developed to obtain a target substrate region. Then, a first ion implantation process containing argon element is performed on the target substrate region, and then at least one ion implantation process containing phosphorus element is performed on the target substrate region after the first ion implantation process is completed to form an N-type buried layer in the substrate. Finally, the remaining photoresist layer on the substrate is removed, and the substrate is annealed. In the above solution, through the co-implantation process that comprehensively includes the first ion implantation process containing argon element and at least one ion implantation process containing phosphorus element, the phosphorus element in the N-type buried layer can have small lateral and longitudinal diffusion, high thermal stability after annealing, is not easily affected by heat treatment in subsequent processes, and does not require complex compensation measures. It can avoid the increase of device area while effectively controlling the reasonable diffusion of phosphorus element and reducing device anomalies. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a flowchart of a manufacturing method of an N-type buried layer structure provided by an embodiment of the present application; Figure 2 It is a cross-sectional structure schematic diagram of a semiconductor structure provided in step S101 of the manufacturing method provided by an embodiment of the present application; Figure 3 It is a cross-sectional structure schematic diagram of a semiconductor structure provided in step S102 and step S103 of the manufacturing method provided by an embodiment of the present application; Figure 4 It is a cross-sectional structure schematic diagram of a semiconductor structure provided in step S104 of the manufacturing method provided by an embodiment of the present application; Figure 5 It is a cross-sectional structure schematic diagram of a semiconductor device for preparing an N-type buried layer by applying the manufacturing method provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] The following further describes the embodiments of the present application in detail with reference to the drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the embodiments of the present application, rather than limiting the embodiments of the present application. Additionally, it should be noted that for the sake of description, only parts related to the embodiments of the present application are shown in the drawings rather than all structures.

[0018] The terms "first", "second", etc. in the description and claims of this application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of this application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are usually of the same kind, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the description and claims means at least one of the connected objects, and the character " / " generally means an "or" relationship between the associated objects before and after.

[0019] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. can be used herein to describe the relationship of one element or feature shown in the figure to other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, an element or feature described as "under" or "beneath" or "below" another element will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "below" can include both upward and downward orientations. In addition, the device may also include other orientations (for example, rotated 90 degrees or other orientations), and the spatial descriptors used herein are accordingly interpreted.

[0020] As used herein, the singular forms "a", "an" and " / the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprise" and / or "include" are used in this specification, the presence of features, integers, steps, operations, elements and / or components can be determined, but one or more other features, integers, steps, operations, elements, components and / or groups are not excluded from existence or addition. At the same time, as used herein, the term "and / or" includes any and all combinations of the related listed items.

[0021] At present, in order to reduce the leakage current of the substrate, ion implantation containing phosphorus elements is used on the P-type substrate to form an N-type buried layer, and the P-type well region is isolated through the N-type buried layer. During specific use, the N-type well is connected to the N-type buried layer to provide an appropriate potential to achieve a good isolation effect. However, phosphorus has the characteristic of easy diffusion, which is likely to generate abnormal leakage paths or cause isolation failure. In related technologies, the ion implantation range of the N-type buried layer is reduced, and the shallow trench isolation distance in the X-axis direction is increased so that the required coverage range can be achieved after subsequent phosphorus diffusion, while leaving a safe isolation area. However, reducing the ion implantation range requires specifically formulating design process rules and adjusting according to different process technologies. For example, different ion concentrations of the N-type buried layer result in different diffusion ranges, and for another example, different thermal budgets in the production process of different products result in different diffusion ranges. The foregoing compensation measures are complex in operation, which will lead to an increase in the device area and need to be improved. Therefore, the present application aims to provide a manufacturing method of an N-type buried layer and a semiconductor device to solve the problems that the compensation measures in related technologies are complex in operation and will lead to an increase in the device area.

[0022] Figure 1 As shown in the flowchart of a manufacturing method of an N-type buried layer structure provided by an embodiment of the present application, Figure 1 the manufacturing method includes the following steps: S101. Provide a substrate, coat a photoresist layer on the substrate, expose the photoresist layer, and develop the exposed photoresist layer to obtain a target substrate area.

[0023] Among them, the substrate may be a P-type substrate, and the specific material of the substrate may be silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), or other III-V group compounds, etc., as well as a multilayer structure composed of the foregoing semiconductor materials. In addition, it may also be silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanide on insulator (S-SiGeOI), silicon germanide on insulator (SiGeOI), and germanium on insulator (GeOI), or double-sided polished wafers (DSP), etc. The embodiments of the present application do not limit this here. Among them, the target substrate area is the target position on the substrate where ion implantation treatment for forming the N-type buried layer needs to be performed. Developing the exposed photoresist layer can remove the photoresist corresponding to the target substrate area and retain the photoresist in other areas to ensure the accurate positioning of subsequent ion implantation treatment. Among them, in one embodiment, the semiconductor structure provided in step S101 can be referred to Figure 2, the semiconductor structure includes a substrate 101 and a photoresist layer 201. It can be understood that the area not covered by the photoresist layer is the target substrate area. Of course, for the convenience of understanding the present invention, Figure 2 is an example of the cross-sectional structure diagram of the semiconductor structure provided in step S101 of the manufacturing method provided in the embodiment of the present application. There can be other suitable examples, and the present invention does not limit them here.

[0024] S102. Perform a first ion implantation process containing argon element on the target substrate area.

[0025] In a specific embodiment, the ion concentration of the first ion implantation process is , the ion energy of the first ion implantation process is , the implantation angle of the first ion implantation process is , the temperature of the first ion implantation process is , so as to improve the stability of the N-type buried layer by means of cold implantation. Specifically, it can be adaptively selected according to the requirements of specific application scenarios, and the present application does not limit it here.

[0026] S103. Perform at least one ion implantation process containing phosphorus element on the target substrate area after the first ion implantation process is completed to form an N-type buried layer in the substrate.

[0027] It should be noted that in the embodiment of the present application, the ion implantation process adopts the co-implantation method. First, perform the first ion implantation process containing argon element, and then perform at least one ion implantation process that must contain phosphorus element. The at least one ion implantation process can be one or more ion implantation processes. Optionally, the temperature of the at least one ion implantation process is , so as to improve the stability of the N-type buried layer by means of cold implantation. Among them, in one embodiment, the semiconductor structure provided in step S102 and step S103 can be referred to Figure 3 , the semiconductor structure includes a substrate 101, a photoresist layer 201 and an N-type buried layer 102. Of course, for the convenience of understanding the present invention, Figure 3 is an example of the cross-sectional structure diagram of the semiconductor structure provided in step S102 and step S103 of the manufacturing method provided in the embodiment of the present application. There can be other suitable examples, and the present invention does not limit them here.

[0028] In a specific embodiment, the specific process and parameters of the at least one ion implantation process containing phosphorus element are described. Among them, only one injection of phosphorus element is involved. Specifically, perform at least one ion implantation process containing phosphorus element on the target substrate area after the first ion implantation process is completed, including: Perform a second ion implantation process containing phosphorus element on the target substrate region after the first ion implantation process, where the ion concentration of the second ion implantation process is , and the ion energy of the second ion implantation process is , and the implantation angle of the second ion implantation process is .

[0029] In a specific embodiment, the specific process and parameters of at least one ion implantation process containing phosphorus element are described. Among them, one implantation of antimony element and one implantation of phosphorus element are involved in sequence. Specifically, at least one ion implantation process containing phosphorus element is performed on the target substrate region after the first ion implantation process, including: Perform a third ion implantation process containing antimony element on the target substrate region after the first ion implantation process, where the ion concentration of the third ion implantation process is , and the ion energy of the third ion implantation process is , and the implantation angle of the third ion implantation process is ; Perform a fourth ion implantation process containing phosphorus element on the target substrate region after the third ion implantation process, where the ion concentration of the fourth ion implantation process is , and the ion energy of the fourth ion implantation process is , and the implantation angle of the fourth ion implantation process is .

[0030] In a specific embodiment, the specific process and parameters of at least one ion implantation process containing phosphorus element are described. Among them, one implantation of antimony element and two implantations of phosphorus element are involved in sequence. Specifically, at least one ion implantation process containing phosphorus element is performed on the target substrate region after the first ion implantation process, including: Perform a fifth ion implantation process containing antimony element on the target substrate region after the first ion implantation process, where the ion concentration of the fifth ion implantation process is , and the ion energy of the fifth ion implantation process is , and the implantation angle of the fifth ion implantation process is ; Perform a sixth ion implantation process containing phosphorus element on the target substrate region after the fifth ion implantation process, where the ion concentration of the sixth ion implantation process is , and the ion energy of the sixth ion implantation process is , and the implantation angle of the sixth ion implantation process is ; Perform a seventh ion implantation process containing phosphorus element on the target substrate region after the sixth ion implantation process, where the ion concentration of the seventh ion implantation process is , the ion energy of the seventh ion implantation process is , the implantation angle of the seventh ion implantation process is .

[0031] In a specific embodiment, the specific process and parameters of at least one ion implantation process containing phosphorus element are described. Among them, two ion implantations of antimony element and one ion implantation of phosphorus element are involved in sequence. Specifically, at least one ion implantation process containing phosphorus element is performed on the target substrate region after the first ion implantation process, including: Perform an eighth ion implantation process containing antimony element on the target substrate region after the first ion implantation process. The ion concentration of the eighth ion implantation process is , the ion energy of the eighth ion implantation process is , the implantation angle of the eighth ion implantation process is ; Perform a ninth ion implantation process containing antimony element on the target substrate region after the eighth ion implantation process. The ion concentration of the ninth ion implantation process is , the ion energy of the ninth ion implantation process is , the implantation angle of the ninth ion implantation process is ; Perform a tenth ion implantation process containing phosphorus element on the target substrate region after the ninth ion implantation process. The ion concentration of the tenth ion implantation process is , the ion energy of the tenth ion implantation process is , the implantation angle of the tenth ion implantation process is .

[0032] The foregoing multiple ion implantation processes containing N-type doping elements are only exemplary descriptions. Specifically, one or more group V elements can be used, such as arsenic element, phosphorus element, or antimony element, etc., but phosphorus element must be included. The depth and coverage of the multiple ion implantation processes can be adaptively changed by adjusting the ion energy and implantation angle according to the requirements of specific application scenarios. Uniform doping can be formed through multi-energy and multi-angle ion implantation processes, which are not limited in this application.

[0033] S104. Remove the remaining photoresist layer on the substrate and perform an annealing process on the substrate to form a deep N-type layer in the substrate.

[0034] Optionally, the following 3 process methods can be used to remove the remaining photoresist layer on the substrate: wet process, dry process, or dry process followed by wet process. The selection of the specific process method needs to match different photoresist characteristics to ensure that the residual photoresist can be completely removed, which is not limited in this application. Among them, in one embodiment, the semiconductor structure provided in step S104 can be referred to Figure 4, the semiconductor structure includes a substrate 101 and an N-type buried layer 102. Of course, for the convenience of understanding the present invention, Figure 4 This is an example of the cross-sectional structure diagram of the semiconductor structure provided in step S104 of the manufacturing method provided in the embodiments of the present application. There may be other suitable examples, and the present invention does not limit them here.

[0035] Optionally, the temperature of the annealing treatment is , which can be beneficial to activate the acceptor doping element and repair the lattice damage.

[0036] As described above, by providing a substrate, coating a photoresist layer on the substrate, exposing the photoresist layer, and developing the exposed photoresist layer to obtain a target substrate region, then performing a first ion implantation treatment including argon element on the target substrate region, and then performing at least one ion implantation treatment including phosphorus element on the target substrate region after the first ion implantation treatment to form an N-type buried layer in the substrate, and finally removing the remaining photoresist layer on the substrate and performing an annealing treatment on the substrate. In the above solution, through the ion co-implantation treatment combining the first ion implantation treatment including argon element and at least one ion implantation treatment including phosphorus element, the phosphorus element in the N-type buried layer can have small lateral and longitudinal diffusion, high thermal stability after annealing, is not easily affected by the heat treatment in the subsequent process, does not require complex compensation measures, can avoid the increase of the device area, effectively control the reasonable diffusion of phosphorus element, and reduce device anomalies.

[0037] The present application also provides a semiconductor device, and the manufacturing method of any of the above solutions is used to prepare the N-type buried layer. The technical effects that can be achieved by the manufacturing method in the foregoing embodiments can also be achieved by this semiconductor device, and will not be elaborated here one by one.

[0038] In one embodiment, the specific structure of the semiconductor device can refer to Figure 5 , the semiconductor device includes a substrate 101, an N-type buried layer 102, an N-type well 103, a P-type well 104, a source region 105, a gate 106, a drain region 107, a Bulk terminal 108, an ISO (Isolation) terminal 109, and a shallow trench isolation 110. Of course, for the convenience of understanding the present invention, Figure 5 This is an example of the cross-sectional structure diagram of the semiconductor device prepared by applying the manufacturing method provided in the embodiments of the present application for the N-type buried layer. There may be other suitable examples, and the present invention does not limit them here.

[0039] It should also be noted that the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, commodity or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the existence of additional identical elements in the process, method, commodity or device comprising the element.

[0040] Note that the above is only a preferred embodiment of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the specific embodiments here, and various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments only. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for manufacturing an N-type deep buried layer, characterized in that: include: Providing a substrate, coating a photoresist layer on the substrate, exposing the photoresist layer, and developing the exposed photoresist layer to obtain a target substrate region; Performing a first ion implantation process containing argon element on the target substrate region; Performing at least one ion implantation process containing phosphorus on the target substrate region after the first ion implantation process to form an N-type deep buried layer in the substrate; The remaining photoresist layer on the substrate is removed, and the substrate is annealed.

2. The manufacturing method according to claim 1, characterized in that: The ion concentration of the first ion implantation process is , the ion energy of the first ion implantation process is , the implantation angle of the first ion implantation process is .

3. The manufacturing method according to claim 1, characterized in that: The step of performing at least one ion implantation process containing phosphorus on the target substrate region after the first ion implantation process is completed comprises: After the first ion implantation, the target substrate region is subjected to a second ion implantation containing phosphorus. The ion concentration of the second ion implantation is , the ion energy of the second ion implantation process is , the implantation angle of the second ion implantation process is .

4. The manufacturing method according to claim 1, characterized in that: The step of performing at least one ion implantation process containing phosphorus on the target substrate region after the first ion implantation process is completed comprises: A third ion implantation treatment containing antimony element is performed on the target substrate region after the first ion implantation treatment. The ion concentration of the third ion implantation treatment is , the ion energy of the third ion implantation process is The implantation angle of the third ion implantation process is ; A fourth ion implantation treatment containing phosphorus is performed on the target substrate region after the third ion implantation treatment. The ion concentration of the fourth ion implantation treatment is , the ion energy of the fourth ion implantation process is , the implantation angle of the fourth ion implantation process is .

5. The manufacturing method according to claim 1, characterized in that: The step of performing at least one ion implantation process containing phosphorus on the target substrate region after the first ion implantation process is completed comprises: The target substrate region after the first ion implantation is subjected to a fifth ion implantation containing antimony element, wherein the ion concentration of the fifth ion implantation is , the ion energy of the fifth ion implantation process is The implantation angle of the fifth ion implantation process is ; A sixth ion implantation treatment containing phosphorus is performed on the target substrate region after the fifth ion implantation treatment. The ion concentration of the sixth ion implantation treatment is , the ion energy of the sixth ion implantation process is The implantation angle of the sixth ion implantation process is ; The target substrate region after the sixth ion implantation is subjected to a seventh ion implantation containing phosphorus. The ion concentration of the seventh ion implantation is , the ion energy of the seventh ion implantation process is The implantation angle of the seventh ion implantation process is .

6. The manufacturing method according to claim 1, characterized in that: The step of performing at least one ion implantation process containing phosphorus on the target substrate region after the first ion implantation process is completed comprises: The target substrate region after the first ion implantation is subjected to an eighth ion implantation containing antimony element, wherein the ion concentration of the eighth ion implantation is , the ion energy of the eighth ion implantation process is The implantation angle of the eighth ion implantation process is ; A ninth ion implantation treatment containing antimony element is performed on the target substrate region after the eighth ion implantation treatment. The ion concentration of the ninth ion implantation treatment is The ion energy of the ninth ion implantation process is The implantation angle of the ninth ion implantation process is ; The target substrate region after the ninth ion implantation is subjected to a tenth ion implantation containing phosphorus, wherein the ion concentration of the tenth ion implantation is The ion energy of the tenth ion implantation process is The implantation angle of the tenth ion implantation process is .

7. The manufacturing method according to claim 1, characterized in that: The temperature of the first ion implantation process is .

8. The manufacturing method according to claim 1, characterized in that: The temperature of the at least one ion implantation process is .

9. The manufacturing method according to claim 1, characterized in that: The temperature of the annealing treatment is .

10. A semiconductor device, characterized in that: The N-type deep buried layer is prepared by the manufacturing method described in any one of claims 1 to 9.

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