Chip packaging structure and chip packaging method

Abstract

The invention discloses a chip packaging structure and a chip packaging method. The chip packaging structure comprises a glass substrate, a chip, a flexible circuit board and anisotropic conductive adhesive, a hollow part and a lead group are arranged on the glass substrate, and the lead group is arranged between the hollow part and the first side of the glass substrate; the wire group comprises a plurality of wires, and a first distance between every two adjacent wires close to one side of the hollow part is smaller than a second distance between every two adjacent wires far away from one side of the hollow part; the chip covers the hollow part, and the projection of the functional area of the chip on the glass substrate is in the hollow part; the plurality of pins of the chip are connected with the first pins of the plurality of wires in a one-to-one correspondence manner through the anisotropic conductive adhesive, and the second pins of the plurality of wires are connected with the plurality of pins of the flexible circuit board in a one-to-one correspondence manner. According to the invention, the requirement of ultra-high-density pin packaging is met.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and particularly to a chip packaging structure and a chip packaging method. Background Art

[0002] With the development trend of electronic products towards miniaturization, thinness, lightness, and high integration, chip packaging technology is also facing higher requirements.

[0003] In the prior art, traditional chip packaging methods have problems such as large packaging size and low pin density, and it is difficult to meet the requirements of ultra-high density pin packaging. Summary of the Invention

[0004] The present invention provides a chip packaging structure and a chip packaging method to meet the requirements of ultra-high density pin packaging.

[0005] According to one aspect of the present invention, a chip packaging structure is provided. The chip packaging structure includes:

[0006] A glass substrate, a chip, a flexible circuit board, and an anisotropic conductive adhesive;

[0007] A hollowed-out portion and a wire group are provided on the glass substrate, and the wire group is disposed between the hollowed-out portion and the first side of the glass substrate; the wire group includes a plurality of wires, and a first spacing between every two adjacent wires on the side close to the hollowed-out portion is less than a second spacing between every two adjacent wires on the side far from the hollowed-out portion;

[0008] The chip covers the hollowed-out portion, and the projection of the functional area of the chip on the glass substrate is within the hollowed-out portion; a plurality of pins of the chip are connected to the first pins of the plurality of wires in one-to-one correspondence through the anisotropic conductive adhesive, and the second pins of the plurality of wires are connected to the plurality of pins of the flexible circuit board in one-to-one correspondence.

[0009] Further, the first spacing between every two adjacent wires on the side close to the hollowed-out portion is equal.

[0010] Further, the second spacing between every two adjacent wires on the side far from the hollowed-out portion is equal.

[0011] Further, the chip packaging structure further includes:

[0012] A connection layer;

[0013] The connection layer is disposed between the chip and the glass substrate.

[0014] Further, the connection layer includes a bonding wire layer, a glue injection layer, or a plastic encapsulation layer.

[0015] Further, the wires include gold wires, silver wires, or copper wires.

[0016] Further, the range of the first spacing is 80 μm - 100 μm;

[0017] The range of the second spacing is 120 μm - 150 μm.

[0018] Further, the diameter range of the hollowed-out part is 5 - 8 μm.

[0019] Further, the chip includes a thin-film piezoelectric printing chip.

[0020] According to another aspect of the present invention, there is provided a chip packaging method for manufacturing the chip packaging structure described in any of the above embodiments. The method includes:

[0021] Fix the chip on the carrier stage of the packaging device, and evenly coat the anisotropic conductive adhesive on the pin area of the chip;

[0022] Connect the multiple pins of the chip and the first pins of the multiple wires in the glass substrate in one-to-one correspondence;

[0023] Evenly coat the anisotropic conductive adhesive on the second pins of the multiple wires in the glass substrate;

[0024] Connect the second pins of the multiple wires in the glass substrate and the multiple pins of the flexible circuit board in one-to-one correspondence.

[0025] The chip packaging structure provided by the embodiment of the present invention includes a glass substrate, a chip, a flexible circuit board, and an anisotropic conductive adhesive. By setting a hollowed-out part and a wire group on the glass substrate, and setting the wire group to include multiple wires, the first spacing between every two adjacent wires on the side close to the hollowed-out part is less than the second spacing between every two adjacent wires on the side far from the hollowed-out part. The multiple pins of the chip are connected to the first pins of the multiple wires in one-to-one correspondence through the anisotropic conductive adhesive, and the second pins of the multiple wires are connected to the multiple pins of the flexible circuit board in one-to-one correspondence. Compared with directly connecting the chip and the flexible circuit board in the prior art, it can meet the requirements of ultra-high density pin packaging, and avoid the difficulty in alignment when connecting the connection pins of the flexible circuit board and the ultra-high density chip pins due to the flexible characteristics of the flexible circuit board, thus avoiding connection difficulties.

[0026] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Description of the Drawings

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0028] Figure 1 is a schematic structural diagram of a chip packaging structure provided according to an embodiment of the present invention;

[0029] Figure 2 is a schematic structural diagram of another chip packaging structure provided according to an embodiment of the present invention;

[0030] Figure 3 is a flowchart of a chip packaging method provided according to an embodiment of the present invention. Detailed implementation manners

[0031] In order to enable those skilled in the art to better understand the solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0032] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those clearly listed steps or units, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0033] The embodiments of the present invention provide a chip packaging structure, Figure 1 is a schematic structural diagram of a chip packaging structure provided according to an embodiment of the present invention, Figure 2 is a schematic structural diagram of another chip packaging structure provided according to an embodiment of the present invention. Refer to Figure 1 and Figure 2 , the chip packaging structure includes:

[0034] A glass substrate 1, a chip 2, a flexible circuit board 3, and an anisotropic conductive adhesive;

[0035] A hollow portion 11 and a wire group 12 are provided on the glass substrate 1. The wire group 12 is disposed between the hollow portion 11 and the first side of the glass substrate 1. The wire group 12 includes a plurality of wires 121. The first distance between every two adjacent wires 121 on the side close to the hollow portion 11 is smaller than the second distance between every two adjacent wires 121 on the side far from the hollow portion 11.

[0036] The chip 2 covers the hollow portion 11, and the projection of the functional area of the chip 2 on the glass substrate 1 is within the hollow portion 11. A plurality of pins of the chip 2 are connected to the first pins of the plurality of wires 121 in one-to-one correspondence through the anisotropic conductive adhesive, and the second pins of the plurality of wires 121 are connected to the plurality of pins of the flexible circuit board in one-to-one correspondence.

[0037] Specifically, the chip 2 can be a thin-film piezoelectric printing chip or other chips, and the embodiments of the present invention do not limit this. The hollow portion 11 can be a through hole. The size of the first pins of the wires 121 in the wire group 12 is the same as the size between adjacent pins on the chip 2. By setting the first distance between every two adjacent wires 121 on the side close to the hollow portion 11 to be smaller than the second distance between every two adjacent wires 121 on the side far from the hollow portion 11, the chip with ultra-high density pins is encapsulated with the flexible circuit board 3 through the glass substrate 1, avoiding the misalignment when the connection pins of the flexible circuit board 3 are connected to the ultra-high density chip pins due to the flexible characteristics of the flexible circuit board 3, thereby causing connection difficulties. The thickness of the glass substrate 1 and the diameter of the hollow portion 11 can be optimized according to the sizes of the chip 2 and the wires 121 to perfectly match different sizes of the chip 2 and the wires 121. Among them, ultra-high density pins can be understood as pins with an adjacent pin pitch less than or equal to 100 μm.

[0038] Exemplarily, in the first encapsulation structure, the pitch between the first pins of adjacent wires 121 can be set to 100 μm, while the pitch between the second pins of adjacent wires 121 is 150 μm. The thickness of the glass substrate 1 is 150 μm, and the diameter of the hollow portion 11 is 5 μm to exactly match the size of the chip 2, where the size of the chip 2 is 100 μm × 100 μm, the wire 121 is a gold wire with a diameter of 25 μm; alternatively, in the second encapsulation structure, the pitch between the first pins of adjacent wires 121 can be set to 80 μm, while the pitch between the second pins of adjacent wires 121 is 120 μm. The thickness of the glass substrate 1 is 180 μm, and the diameter of the hollow portion 11 is 8 μm to exactly match the size of the chip 2, where the size of the chip 2 is 80 μm × 80 μm, the wire 121 is a silver wire with a diameter of 20 μm; further, in the third encapsulation structure, the pitch between the first pins of adjacent wires 121 can be set to 90 μm, while the pitch between the second pins of adjacent wires 121 is 135 μm. The thickness of the glass substrate 1 is 160 μm, and the diameter of the hollow portion 11 is 6 μm to exactly match the size of the chip 2, where the size of the chip 2 is 90 μm × 90 μm, the wire 121 is a copper wire with a diameter of 18 μm.

[0039] The chip encapsulation structure provided by the embodiment of the present invention includes a glass substrate 1, a chip 2, a flexible circuit board 3, and an anisotropic conductive adhesive. By providing a hollow portion 11 and a wire group 12 on the glass substrate 1, and setting the wire group 12 to include a plurality of wires 121, the first pitch between every two adjacent wires 121 on the side close to the hollow portion 11 is smaller than the second pitch between every two adjacent wires 121 on the side far from the hollow portion 11. The multiple pins of the chip 2 are connected to the first pins of the plurality of wires 121 one by one through the anisotropic conductive adhesive, and the second pins of the plurality of wires 121 are connected to the multiple pins of the flexible circuit board one by one. Compared with directly connecting the chip to the flexible circuit board in the prior art, it can meet the requirements of ultra-high density pin packaging, and avoid the misalignment when connecting the connection pins of the flexible circuit board 3 to the ultra-high density chip pins due to the flexible characteristics of the flexible circuit board 3, thereby causing connection difficulties.

[0040] Further, referring to Figure 1 and Figure 2 , the first pitch between every two adjacent wires 121 on the side close to the hollow portion 11 is equal.

[0041] Specifically, setting the first pitch between every two adjacent wires 121 on the side close to the hollow portion 11 to be equal can facilitate the encapsulation of the glass substrate 1 and the chip 2.

[0042] Further, referring to Figure 1 and Figure 2, the second spacing between every two adjacent wires 121 on the side away from the hollow portion 11 is equal.

[0043] Specifically, setting the second spacing between every two adjacent wires 121 on the side away from the hollow portion 11 to be equal facilitates the encapsulation of the glass substrate 1 and the flexible circuit board 3.

[0044] Furthermore, the chip packaging structure further includes:

[0045] A connection layer;

[0046] The connection layer is disposed between the chip and the glass substrate.

[0047] Specifically, setting a connection layer between the chip and the glass substrate enhances the bonding force between the chip and the substrate and improves the reliability of the packaging. Exemplarily, the connection layer includes a bonding wire layer, a glue injection layer, or a plastic encapsulation layer.

[0048] Furthermore, the connection layer includes a bonding wire layer, a glue injection layer, or a plastic encapsulation layer.

[0049] Furthermore, the wire includes a gold wire, a silver wire, or a copper wire.

[0050] Specifically, the wire can be a gold wire, a silver wire, a copper wire, or other electrically conductive materials. In this embodiment, a gold wire is preferably used, which has a smaller resistance and better conductivity efficiency.

[0051] Furthermore, the range of the first spacing is 80μm - 100μm;

[0052] The range of the second spacing is 120μm - 150μm.

[0053] Furthermore, the diameter range of the hollow portion is 5 - 8μm.

[0054] Furthermore, the chip includes a thin film piezoelectric printing chip.

[0055] An embodiment of the present invention provides a chip packaging method for manufacturing the chip packaging structure described in any of the above embodiments. Figure 3 It is a flowchart of a chip packaging method provided according to an embodiment of the present invention. Refer to Figure 3 , the chip packaging method includes:

[0056] S110. Fix the chip on the carrier stage of the packaging device and uniformly coat anisotropic conductive adhesive on the pin area of the chip.

[0057] S120. Connect the multiple pins of the chip and the first pins of multiple wires in the glass substrate in a one-to-one correspondence.

[0058] Specifically, align the glass substrate with the chip so that the pins on the chip are aligned with the first pins on the glass substrate, and then apply pressure and perform heat curing treatment to complete the encapsulation of the chip and the glass substrate. Exemplarily, during the formation of the first encapsulation structure, the applied pressure can be set to 100 N / cm 2 , the heating temperature during the heat curing treatment is 180 °C, and the heat preservation time is 30 minutes; during the formation of the second encapsulation structure, the applied pressure can be set to 150 N / cm 2 , the heating temperature during the heat curing treatment is 200 °C, and the heat preservation time is 45 minutes; during the formation of the third encapsulation structure, the applied pressure is 120 N / cm 2 , the heating temperature during the heat curing treatment is 190 °C, and the heat preservation time is 40 minutes.

[0059] S130. Uniformly coat anisotropic conductive adhesive on the second pins of multiple wires in the glass substrate.

[0060] S140. Connect the second pins of multiple wires in the glass substrate to the multiple pins of the flexible circuit board one by one.

[0061] Specifically, after aligning the glass substrate with the flexible circuit board, align the pins on the glass substrate with the pins on the flexible circuit board, and then apply pressure and perform heat curing treatment to complete the encapsulation of the flexible circuit board and the glass substrate.

[0062] The chip encapsulation method provided by the embodiments of the present invention fixes the chip on the carrier table of the encapsulation device, uniformly coats anisotropic conductive adhesive in the pin area of the chip, connects the multiple pins of the chip to the first pins of multiple wires in the glass substrate one by one, uniformly coats anisotropic conductive adhesive on the second pins of multiple wires in the glass substrate, and connects the second pins of multiple wires in the glass substrate to the multiple pins of the flexible circuit board one by one. Compared with directly connecting the chip to the flexible circuit board in the prior art, it can meet the requirements of ultra-high density pin encapsulation, and avoid the difficulty in alignment when connecting the connection pins of the flexible circuit board to the ultra-high density chip pins due to the flexible characteristics of the flexible circuit board, thereby avoiding connection difficulties.

[0063] It should be understood that various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitations are imposed herein.

[0064] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A chip packaging structure, characterized in that: include: Glass substrates, chips, flexible circuit boards and anisotropic conductive adhesives; The glass substrate is provided with a hollow portion and a wire group, the wire group is provided between the hollow portion and the first side of the glass substrate; the wire group includes a plurality of wires, and a first spacing between every two adjacent wires on a side close to the hollow portion is smaller than a second spacing between every two adjacent wires on a side away from the hollow portion; The chip covers the hollow portion, and the functional area of ​​the chip is projected on the glass substrate within the hollow portion; multiple pins of the chip are connected one-to-one with the first pins of multiple wires through the anisotropic conductive adhesive, and the second pins of multiple wires are connected one-to-one with the multiple pins of the flexible circuit board.

2. The chip packaging structure according to claim 1, characterized in that: The first spacing between every two adjacent wires close to one side of the hollow portion is equal.

3. The chip packaging structure according to claim 2, characterized in that: The second spacing between every two adjacent wires on the side away from the hollow portion is equal.

4. The chip packaging structure according to claim 1, characterized in that: Also includes: Connection layer; The connection layer is disposed between the chip and the glass substrate.

5. The chip packaging structure according to claim 4, characterized in that: The connection layer includes a bonding wire layer, a glue injection layer or a plastic packaging material layer.

6. The chip packaging structure according to claim 1, characterized in that: The conductive wire includes a gold wire, a silver wire or a copper wire.

7. The chip packaging structure according to claim 1, characterized in that: The first spacing ranges from 80 μm to 100 μm; The second spacing ranges from 120 μm to 150 μm.

8. The chip packaging structure according to claim 1, characterized in that: The diameter of the hollow portion is in the range of 5-8 μm.

9. The chip packaging structure according to claim 1, characterized in that: The chip comprises a thin film piezoelectric printing chip.

10. A chip packaging method, used for manufacturing the chip packaging structure according to any one of claims 1 to 9, characterized in that: include: Fixing the chip on a packaging equipment carrier, and evenly coating the anisotropic conductive adhesive on the pin area of ​​the chip; Connecting the plurality of pins of the chip to the first pins of the plurality of wires in the glass substrate in a one-to-one correspondence; Uniformly coating the anisotropic conductive adhesive on the second pins of the plurality of wires in the glass substrate; The second pins of the plurality of wires in the glass substrate are connected to the plurality of pins of the flexible circuit board in a one-to-one correspondence.

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