Three-phase intelligent electric meter power supply switching method and circuit

Abstract

The invention relates to a three-phase intelligent electric meter power supply switching method and circuit. The circuit comprises a power supply circuit, a super capacitor circuit, a meter reading stopping battery circuit, a clock battery circuit and a battery control circuit which are electrically connected. The power supply circuit comprises a power supply BAT1 and a direct current step-down circuit which are electrically connected; the DC step-down circuit comprises a DC-DC chip UQ3; the super capacitor circuit comprises a voltage stabilizer UQ2; a pin 1 of the voltage stabilizer UQ2 is grounded, and a pin 2 of the voltage stabilizer UQ2 is connected with three paths of input voltage; a pin 2 of the voltage stabilizer UQ2 is grounded through a super capacitor EV1; a pin 3 outputs three paths, one path outputs 4.0 V, one path outputs MVDD through a capacitor CV4, and the other path outputs MVDD through a diode DV9; the device is reasonable in design, compact in structure and convenient to use.

Description

Technical Field

[0001] The present invention relates to a three-phase smart meter power switching method and circuit. Background Art

[0002] Today, with the increasing popularity of smart grids, three-phase smart meters not only shoulder the important task of accurately measuring electrical energy, but also integrate advanced functions such as remote communication, data analysis, and fault warning. These all pose more stringent standards for their power supply systems.

[0003] To ensure stable and accurate execution of various tasks when the mains power supply is normal, three-phase smart meters use stable mains power as the main power source. However, considering possible emergencies in the power grid, such as natural disasters, equipment failures, or planned power outages, the importance of backup power supplies is particularly emphasized in the design of the meters. In the event of a mains power outage, three-phase smart meters rely on internally integrated energy storage devices (such as supercapacitors or electrolytic capacitors), which can provide sufficient energy in a short period of time to support the meter to complete key functions such as carrier data reporting (i.e., power outage reporting function). This function allows the meter to immediately send power outage information to the power grid management system after losing the main power source, including the total number of power outages and the cumulative power outage time, the moments of occurrence and end of the last 100 power outages, and the average current value three minutes before the power outage. This helps the power grid operation unit analyze and judge power outage events, initiate emergency response mechanisms, and reduce the impact of power outages on users.

[0004] In addition, to ensure on-site meter reading operations can still be carried out during power outages, three-phase smart meters are also equipped with dedicated power outage meter reading batteries. These batteries are designed to have a long service life and can provide continuous power supply to the display module and meter reading interface of the meter when both the main power source and the carrier communication power source fail. In this way, even in a completely power-off environment, meter reading personnel can accurately read electricity consumption data relying on handheld meter reading devices or the display interface of the smart meter itself.

[0005] At the same time, to ensure that the meter still has an accurate clock under extreme conditions and prevent unauthorized opening of the meter cover for power theft, three-phase smart meters are built-in with clock batteries. Clock batteries are low-power, long-life batteries that can supply power to the microcontroller of the meter and the cover opening detection circuit when all external power supplies completely fail, ensuring the continuous accuracy of time information and recording cover opening events.

[0006] In summary, the technical background of three-phase smart meters reflects a comprehensive consideration of power supply stability, emergency power management, and time synchronization capabilities. These designs ensure that the meters can perform their due functions under various conditions, providing solid technical support for the reliable operation of smart grids.

[0007] In a new intelligent three-phase meter power supply system, to ensure that the meter can achieve long-term and stable operating performance, a multi-path power supply architecture must be constructed. This architecture covers multiple power supply modes: the main power supply is the commercial power under normal power supply conditions; at the initial stage of a sudden power outage, it switches to a super capacitor to maintain short-term power supply; when the super capacitor runs out of power, the outage meter reading battery is enabled to continue maintaining the system operation; finally, if all the aforementioned power supply means fail, the clock battery is relied on to maintain the most basic operating functions of the microcontroller (MCU). Given that the input / output (IO) port resources of the MCU are precious and limited, how to achieve seamless switching and coordinated operation of the above four power supply modes in accordance with the preset order without occupying additional MCU resources and ensure the stability of the meter power supply has become an urgent problem to be solved in the intelligent three-phase meter power supply system. Summary of the Invention

[0008] Generally speaking, the technical problem to be solved by the present invention is to provide a three-phase intelligent meter power switching method and circuit.

[0009] To solve the above problems, the technical solutions adopted by the present invention are as follows:

[0010] A three-phase intelligent meter power switching circuit includes a power supply circuit, a super capacitor circuit, an outage meter reading battery circuit, a clock battery circuit, and a battery control circuit that are electrically connected;

[0011] Among them, the power supply circuit outputs a 5.2V voltage and is connected to the super capacitor circuit; each of the super capacitor circuit, the outage meter reading battery circuit, and the clock battery circuit outputs a path of MVDD to supply power to the main system in the intelligent meter; the battery control circuit outputs a control signal Power Battery Ctr and is connected to the outage meter reading battery circuit and the clock battery circuit to control two battery switches.

[0012] The power supply circuit includes a power supply BAT1 and a DC buck circuit that are electrically connected; the DC buck circuit includes a DC-DC chip UQ3;

[0013] The super capacitor circuit includes a voltage regulator UQ2; the pin 1 of the voltage regulator UQ2 is grounded, and the pin 2 is connected to three input voltages respectively; the pin 2 of the voltage regulator UQ2 is grounded through the super capacitor EV1; the pin 3 outputs three paths, one path outputs 4.0V, one path passes through the capacitor CV4, and one path outputs MVDD through the diode DV9;

[0014] The outage meter reading battery circuit includes an outage meter reading battery BAT1 and a voltage regulator UQ1 that are electrically connected; the pin 3 of the voltage regulator UQ1 is connected to the pin 2 of the PMOS transistor QK2;

[0015] The pin 1 of the MOS transistor QK2 is connected to Power Battery Ctr through the resistor RV5, and the pin 3 is connected to the MVDD terminal through the diode DV6;

[0016] The foot 1 of the stop-copy battery BAT1 is grounded and the foot 2 is electrically connected to the foot 2 of the voltage regulator UQ1 through the diode DV5;

[0017] The clock battery circuit includes the PMOS transistor QK1; the foot 2 of the PMOS transistor QK1 is connected to the clock battery BAT2 through the diode DV3; the foot 1 of the PMOS transistor QK1 is connected to the Power Battery Ctr through the resistor RV4; the foot 3 of the PMOS transistor QK1 is connected to the MVDD terminal through the diode DV4;

[0018] The battery control circuit includes that the Power Battery Ctr is connected to three paths. One path is grounded through the resistor RV1, the second path is connected to the MVDD terminal through the diode DV2, and the MVDD terminal is grounded through the resistor RV2; the third path is connected to the voltage VCC1 through the resistor RV3 and the Zener diode DV1.

[0019] As a further improvement of the above technical solution:

[0020] In the power supply circuit, in the DC-DC chip UQ3, the foot 5 is connected to the VCC1 terminal, and the foot 5 is connected to the VCC1 terminal through the resistor RQ1; the foot 2 is grounded, and the foot 6 outputs two paths. One path outputs 5.2V through the inductor LQ1, and one path is grounded through the reverse-connected Zener diode DV10; the foot 1 is connected to the foot 6 through the series-connected resistor RQ3 and CQ2, and the foot 3 is divided into two paths. One path is grounded through the resistor RQ2, and one path outputs 5.2V after passing through the series voltage-dividing resistors RQ4 and RQ5;

[0021] The 5.2V terminal is grounded through the parallel-connected capacitors CQ3 and CQ4;

[0022] The VCC1 terminal is grounded through the capacitor CQ1;

[0023] The foot 3 of the DC-DC chip UQ3 outputs 0.97V, and the output voltage is set through the voltage-dividing resistors RQ4 and RQ5.

[0024] In the supercapacitor circuit, one of the two input voltages is connected to 5.2V through the diode DV8, and the second path is connected to 5.2V through the capacitor CV3 and the resistor group of the parallel-connected resistors RV6 and RV7.

[0025] In the stop-copy battery circuit, the foot 1 of the voltage regulator UQ1 is grounded, the foot 2 is grounded through the capacitor CV1, the foot 3 outputs, and the foot 3 is grounded through the capacitor CV2.

[0026] In the DC-DC chip UQ3, the VIN pin is the input voltage pin, connected to the input voltage VCC1; the EN pin is the enable pin of the chip, which is active high and is connected to the input voltage VCC1 through the resistor RQ1; the GND pin is the ground pin of the DC-DC chip UQ3, connected to GND; the SW pin is the output pin of the DC-DC chip UQ3, connected to the inductor LQ1; the BST pin is connected to the SW pin through the capacitor CQ5 and the resistor RQ3; FB is the feedback pin, and the required output voltage value is set through the voltage-dividing resistors RQ4, RQ5, and RQ6; the Zener diode DV11 is a freewheeling diode, which forms a freewheeling circuit with the inductor LQ1; the capacitors CQ3 and CQ4 are output capacitors; the capacitor CQ1 is the input capacitor, which provides a stable input current for UQ3 and stabilizes the input voltage.

[0027] In the supercapacitor circuit, the 5.2V DC power output by the DC buck circuit is supplied to the supercapacitor EV1 through the diode DV7 and the parallel resistors RV6 and RV7; the resistors RV6 and RV7 are current-limiting resistors, and the diode DV7 is used to prevent the electricity of the supercapacitor from flowing back to the front end; the 5.2V and the supercapacitor EV1 pass through the double diode DV8 to obtain a 5V voltage, and a 4V DC voltage is output through the voltage regulator UQ2; the capacitors CV3 and CV4 are the input and output capacitors of the voltage regulator UQ2.

[0028] In the stop-copy battery circuit, the 6V voltage output by the stop-copy battery is input to the voltage regulator UQ1 through the diode DV5, and the voltage regulator UQ1 outputs a 3.6V DC voltage; the capacitors CV1 and CV2 are the input and output capacitors of the voltage regulator UQ1 respectively; the Power_Battery_Ctr voltage controls the conduction and cutoff of the PMOS transistor QK2, determining whether the voltage of the battery BAT1 is supplied to MVDD.

[0029] In the clock battery circuit, the Power_Battery_Ctr voltage controls the conduction and cutoff of the PMOS transistor QK1, determining whether the clock battery BAT2 voltage is supplied to MVDD;

[0030] In the battery control circuit, during normal power-on, the voltage at the Power_Battery_Ctr point is clamped at MVDD + Vf, where Vf is the forward conduction voltage drop of the diode DV2; the Zener voltage of the Zener diode DV1 is 5.1V, and the 12V VCC1 is reduced to 6.9V after passing through the Zener diode DV1; the resistor RV3 is used to limit the current size and bear the voltage difference between the positive pole of the Zener diode and Power_Battery_Ctr; when the voltage of VCC1 is lower than 5.1V, the voltage supply to the circuit is stopped, and at this time, the remaining energy in the circuit is discharged through the resistor RV1, and the voltage at the Power_Battery_Ctr point begins to gradually decrease;

[0031] The resistors RV1 and RV2 are in parallel and jointly determine the magnitude of the current in the path from VCC1 to GND when DV2 conducts.

[0032] A three-phase smart meter power switching method includes the above circuit; when powered on normally, there is a 12V DC voltage at VCC1, and a 5.2V voltage is obtained through the DC-DC chip UQ3; one path of the 5.2V voltage passes through the diode DV7 and then charges the supercapacitor EV1 to charge the supercapacitor EV1 to 5V; the other path of the 5.2V voltage passes through the diode DV8, with a voltage drop of 0.2V, to obtain a 5V voltage as the input voltage of the voltage regulator UQ2; the voltage regulator UQ2 outputs a stable 4V DC voltage, which passes through the diode DV9 with a voltage drop of about 0.2V to obtain 3.8V of MVDD to supply power to the corresponding modules in the meter.

[0033] As a further improvement of the above technical solution:

[0034] When a sudden power outage occurs, the supercapacitor EV1 starts to supply power, and a 4.8V voltage is obtained after passing through the diode DV8 as the input voltage of the voltage regulator UQ2; the voltage regulator UQ2 outputs a stable 4V DC voltage, which passes through the diode DV9 with a voltage drop of about 0.2V to obtain 3.8V of MVDD to supply power to the corresponding modules in the meter;

[0035] At the same time, after the power outage, the voltage of VCC1 gradually decreases. When it decreases to 5.1V, the Zener diode DV1 stops conducting and stops supplying voltage to the circuit. At this time, the remaining energy in the circuit is dissipated through the resistor RV1, and the voltage at the Power_Battery_Ctr point gradually decreases;

[0036] When the voltage at Power_Battery_Ctr drops to the output voltage of the voltage regulator UQ1 + Vgs, that is, 3.05V, the PMOS transistor QK2 conducts;

[0037] At this time, the outage copy battery starts to supply power to MVDD through the 3.6V voltage output by the voltage regulator UQ1. There is a voltage drop of 0.2V after passing through the diode DV6 to obtain 3.4V of MVDD; when the voltage at Power_Battery_Ctr drops to the clock battery voltage - the forward conduction voltage drop of the diode DV3 + Vgs, the voltage regulator UQ2 conducts, and the clock battery starts to supply power to MVDD; after the voltage drops of the diodes DV3 and DV4, MVDD is obtained.

[0038] The present invention realizes seamless switching among four power supply modes: mains power supply, supercapacitor power supply, outage copy battery power supply, and clock battery power supply. The specific advantages are as follows:

[0039] 1. It does not require occupying the IO port resources of the MCU. To control the switching between different power supplies, it is certainly possible to control triodes or MOS transistors through the IO ports of the MCU to achieve the goal. However, with the increasing functions of three-phase smart meters today, the IO port resources of the MCU are becoming increasingly tense, and there is no way to spare resources for power switching. The present invention does not require occupying IO port resources and completes circuit switching through Power_Battery_Ctr and voltage competition, saving MCU resources.

[0040] 2. The battery is started through a switch, ensuring that the battery power is not wasted when there is other power supply. When there is mains power supply, MOS transistors QK1 and QK2 are in the off state, and the battery will only be automatically turned on when the VCC1 voltage is insufficient, avoiding the slow loss of battery power during mains power supply.

[0041] The present invention is reasonable in design, low in cost, durable, safe and reliable, simple in operation, time-saving and labor-saving, cost-saving, compact in structure and convenient to use. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is the DC buck circuit of the present invention.

[0043] Figure 2 is the supercapacitor circuit of the present invention.

[0044] Figure 3 is the outage meter reading battery circuit of the present invention.

[0045] Figure 4 is the clock battery circuit of the present invention.

[0046] Figure 5 is the battery control circuit of the present invention.

[0047] Figure 6 is the block diagram of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0048] As Figure 1-6 , the solution of the present invention is specifically divided into five parts: a power supply circuit, a supercapacitor circuit, an outage meter reading battery circuit, a clock battery circuit, and a battery control circuit.

[0049] The DC buck circuit is as Figure 1As shown in the figure, its core is the DC-DC chip UQ3, which can step down the 12V VCC1 to 5.2V. Among them, the VIN pin is the input voltage pin, connected to the input voltage VCC1; the EN pin is the enable pin of the chip, which is active high and is connected to the input voltage VCC1 through the resistor RQ1; the GND pin is the grounding pin of UQ3, connected to GND; the SW pin is the output pin of the DC-DC chip, connected to the inductor LQ1; the BST pin is connected to the SW pin through the bootstrap capacitor CQ5 and the current-limiting resistor RQ3; FB is the feedback pin, and its typical voltage is 797mV. The required output voltage value is set through the voltage-dividing resistors RQ4, RQ5, and RQ6; DV11 is a freewheeling diode, which forms a freewheeling circuit with the inductor LQ1; CQ3 and CQ4 are output capacitors, which reduce the output ripple voltage and ripple current of the DCDC circuit; CQ1 is an input capacitor, which provides a stable input current for UQ3 and stabilizes the input voltage.

[0050] The supercapacitor circuit is as Figure 2 shown. The 5.2V DC power output by the DC buck circuit is supplied to the supercapacitor through the diode DV7 and the parallel resistors RV6 and RV7. RV6 and RV7 are current-limiting resistors to prevent excessive current at the initial stage of charging; the diode DV7 is used to prevent the electricity of the supercapacitor from flowing back to the front end. The 5.2V and the supercapacitor pass through the double diode DV8 to obtain a voltage of about 5V, and a stable 4V DC voltage is output through the low-dropout regulator UQ2. The capacitors CV3 and CV4 are the input and output capacitors of UQ2, which are used to suppress the influence of input interference on the LDO and the interference of the LDO output on other circuits respectively.

[0051] The power-off battery circuit is as Figure 3 shown. BAT1 is a 6V power-off battery. The 6V voltage output by the power-off battery is input to the low-dropout regulator UQ1 through the diode DV5, and UQ1 outputs a stable 3.6V DC voltage; the diode DV5 prevents the current from flowing back to charge the battery; the capacitors CV1 and CV2 are the input and output capacitors of UQ1, which are used to suppress the influence of input interference on the LDO and the interference of the LDO output on other circuits respectively. The Power_Battery_Ctr voltage controls the on and off of the PMOS transistor QK2, determining whether the battery voltage is supplied to MVDD; the resistor RV5 at the gate of the MOS transistor is used to limit the current and eliminate the oscillation signal; the diode DV6 prevents the MVDD current from flowing back.

[0052] The clock battery circuit is as Figure 4 shown. BAT2 is a 3.6V clock battery.

[0053] The Power_Battery_Ctr controls the on and off of the voltage control PMOS transistor QK1, which determines whether the clock battery voltage is supplied to MVDD; the resistor RV4 at the gate of the MOS transistor is used to limit the current and eliminate the oscillation signal; the diodes DV3 and DV4 prevent the current from flowing back and provide a voltage drop of about 0.4V.

[0054] The battery control circuit is as Figure 5 shown. When powered on normally, the voltage at the Power_Battery_Ctr point is clamped at MVDD + Vf, where Vf is the forward conduction voltage drop of the diode DV2; the Zener voltage of the Zener diode DV1 is 5.1V, and the 12V VCC1 is reduced to 6.9V after passing through the Zener diode DV1; the resistor RV3 is used to limit the current magnitude and bear the voltage difference between the positive pole of the Zener diode and Power_Battery_Ctr; when the voltage of VCC1 is lower than 5.1V, it can no longer supply voltage to the circuit, and at this time, the remaining energy in the circuit is discharged through the resistor RV1, and the voltage at the Power_Battery_Ctr point starts to gradually decrease. The resistors RV1 and RV2 are in parallel and jointly determine the magnitude of the current in the path from VCC1 to GND when DV2 conducts.

[0055] Among them, RQ1 is a surface mount resistor with a resistance value of 100KΩ;

[0056] RQ2 is a surface mount resistor with a resistance value of 12KΩ;

[0057] RQ3 is a surface mount resistor with a resistance value of 10Ω;

[0058] RQ4 is a surface mount resistor with a resistance value of 20KΩ;

[0059] RQ5 is a surface mount resistor with a resistance value of 47KΩ;

[0060] RV1 is a surface mount resistor with a resistance value of 1MΩ;

[0061] RV2 is a surface mount resistor with a resistance value of 5.1KΩ;

[0062] RV3 is a surface mount resistor with a resistance value of 51KΩ;

[0063] RV4, RV5, RV6, RV7 are surface mount resistors with a resistance value of 100Ω;

[0064] CQ1 is a surface mount ceramic capacitor with a capacitance of 4.7uf and a breakdown voltage of 50V;

[0065] CQ2, CQ4 are surface mount ceramic capacitors with a capacitance of 100nf and a breakdown voltage of 50V;

[0066] CQ3 is a surface mount ceramic capacitor with a capacitance of 10uf and a breakdown voltage of 10V;

[0067] CV1, CV2, CV3, and CV4 are surface mount ceramic capacitors with a capacitance of 10 μF and a breakdown voltage of 16 V.

[0068] EV1 is a supercapacitor with a voltage of 5.5 V and a capacitance of 1.5 F.

[0069] LQ1 is a power inductor with an inductance of 22 μH.

[0070] DV3, DV4, DV5, DV6, DV7, and DV9 are surface mount Schottky diodes with a reverse breakdown voltage of 30 V and a low forward conduction voltage drop.

[0071] DV1 is a surface mount Zener diode with a Zener voltage of 5.1 V.

[0072] DV2 is a surface mount switching diode with a reverse breakdown voltage of 100 V.

[0073] DV9 is a surface mount Schottky double diode with a reverse breakdown voltage of 40 V and a low forward conduction voltage drop.

[0074] DV10 is a surface mount Schottky diode with a fast reverse recovery time and a reverse peak breakdown voltage of 60 V.

[0075] UQ1 is a low dropout regulator with an output voltage of 3.6 V.

[0076] UQ2 is a low dropout regulator with an output voltage of 4 V.

[0077] UQ3 is a DC-DC chip with an FB of 0.97 V, and the output voltage can be set through a voltage dividing resistor.

[0078] BAT1 is a 6 V anti-copying battery.

[0079] BAT2 is a 3.6 V clock battery.

[0080] QK1 and QK2 are PMOS transistors with Vgs = -0.45 V.

[0081] Working principle: When power is normally applied, there is a 12 V DC voltage at VCC1. After passing through the DC-DC chip UQ3, a 5.2 V voltage is obtained. One path of the 5.2 V voltage charges the supercapacitor through the diode DV7, and the supercapacitor can be charged to 5 V. The other path of the 5.2 V voltage passes through the diode DV8 and drops by 0.2 V to obtain a 5 V voltage, which serves as the input voltage of the low dropout regulator UQ2. The low dropout regulator UQ2 outputs a stable 4 V DC voltage, which drops by about 0.2 V through the diode DV9 to obtain 3.8 V of MVDD to power the corresponding modules in the meter.

[0082] When a sudden power outage occurs, the supercapacitor EV1 starts to supply power. After passing through the diode DV8, a 4.8V voltage is obtained as the input voltage of the low-dropout regulator UQ2. The low-dropout regulator UQ2 outputs a stable 4V DC voltage. After the voltage is reduced by about 0.2V through the diode DV9, 3.8V of MVDD is obtained to supply power to the corresponding modules in the electric meter.

[0083] At the same time, after the power outage, the voltage of VCC1 gradually decreases. When it drops to 5.1V, the Zener diode DV1 stops conducting and can no longer supply voltage to the circuit. At this time, the remaining energy in the circuit is discharged through the resistor RV1, and the voltage at the Power_Battery_Ctr point gradually decreases. When the voltage at Power_Battery_Ctr drops to the output voltage of UQ1 + Vgs, that is, 3.05V, the PMOS transistor QK2 conducts. At this time, the 3.6V voltage output by the outage copy battery through the low-dropout regulator UQ1 starts to supply power to MVDD. After passing through the diode DV6, there is a voltage drop of 0.2V, and 3.4V of MVDD is obtained. When the voltage at Power_Battery_Ctr drops to the clock battery voltage - the forward conduction voltage drop of the diode DV3 + Vgs, that is, 2.95V, UQ2 conducts, and the clock battery starts to supply power to MVDD. After passing through a total voltage drop of 0.4V through the diodes DV3 and DV4, 3.2V of MVDD is obtained.

[0084] Since the MVDD voltages obtained from the supercapacitor, the outage copy battery, and the clock battery are different, there is a competition mechanism here, that is: when the supercapacitor has sufficient power, the 3.8V MVDD output by the supercapacitor is dominant, and at this time, it is powered by the supercapacitor. As the energy of the supercapacitor is consumed and its voltage gradually decreases, when the MVDD voltage output by the supercapacitor is less than 3.4V, the voltage output by the outage copy battery starts to take the lead, and at this time, it is powered by the outage copy battery. When the energy of the outage copy battery is insufficient, the MVDD voltage output by the outage copy battery gradually decreases, and the voltage output by the clock battery starts to take the lead, and at this time, it is powered by the last outage copy battery.

[0085] Thus, this circuit realizes seamless switching and coordinated operation of four power supply modes, namely mains power supply, supercapacitor power supply, outage copy battery power supply, and clock battery power supply, in accordance with the preset order, ensuring the stability of the power supply to the electric meter.

[0086] The present invention uses low-dropout regulators of different specifications and the voltage drops of diodes to set different voltage gradients, realizing the voltage switching of the mains power supply, supercapacitor, outage copy battery, and clock battery while meeting the power supply voltage requirements of the electrical components, ensuring that the electric meter can operate continuously and stably under various power supply conditions, and improving the working reliability and data integrity of the electric meter. The present invention does not require the MCU's IO port to control the power supply switching, providing a solution in the context of tight MCU resources.

[0087] The present invention is fully described for a clearer disclosure, and the prior art will not be enumerated one by one.

[0088] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; it is obvious for those skilled in the art to combine multiple technical solutions of the present invention. And these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. The technical content not elaborately described in the present invention is well-known technology.

Claims

1. A three-phase smart meter power switching circuit, characterized in that: It includes an electrically connected power supply circuit, a super capacitor circuit, a stop-copy battery circuit, a clock battery circuit and a battery control circuit; Wherein, the power supply is electrically connected to the supercapacitor circuit; The supercapacitor circuit, the meter-stopping battery circuit, and the clock battery circuit each output one MVDD, which supplies power to the main system in the smart meter. The battery control circuit outputs a control signal Power Battery Ctr, which is electrically connected to the stop battery circuit and the clock battery circuit to control the two-way battery switches; The power supply circuit includes an electrically connected power supply BAT1 and a DC step-down circuit; the DC step-down circuit includes a DC-DC chip UQ3; The supercapacitor circuit includes a voltage regulator UQ2; pin 1 of the voltage regulator UQ2 is grounded, and pin 2 is connected to three input voltages respectively; pin 2 of the voltage regulator UQ2 is grounded through the supercapacitor EV1; pin 3 outputs three paths, one of which outputs 4.0V, one through the capacitor CV4, and one through the diode DV9 to output MVDD; The stop-copy battery circuit includes an electrically connected stop-copy battery BAT1 and a voltage regulator UQ1; a pin 3 of the voltage regulator UQ1 is connected to a pin 2 of a PMOS tube QK2; Pin 1 of MOS tube QK2 is connected to Power Battery Ctr through resistor RV5, and pin 3 is connected to MVDD terminal through diode DV6; The pin 1 of the stop copy battery BAT1 is grounded and the pin 2 is electrically connected to the pin 2 of the voltage regulator UQ1 through the diode DV5; The clock battery circuit includes a PMOS tube QK1; the pin 2 of the PMOS tube QK1 is connected to the clock battery BAT2 through a diode DV3; the pin 1 of the PMOS tube QK1 is connected to the Power Battery Ctr through a resistor RV4; the pin 3 of the PMOS tube QK1 is connected to the MVDD terminal through a diode DV4; The battery control circuit is divided into three paths, one path is connected to the ground through the resistor RV1, the second path is connected to the MVDD terminal through the diode DV2, and the MVDD terminal is grounded through the resistor RV2; the third path is connected to the voltage VCC1 through the resistor RV3 and the Zener diode DV1.

2. The three-phase smart meter power switching circuit according to claim 1 is characterized in that: The power supply circuit outputs a 5.2V voltage; In the power supply circuit, in the DC-DC chip UQ3, pin 5 is connected to the VCC1 terminal, and pin 5 is connected to the VCC1 terminal through the resistor RQ1; pin 2 is grounded, and pin 6 outputs two paths, one is 5.2V through the inductor LQ1, and the other is grounded through the reverse Zener diode DV10; pin 1 is connected to pin 6 through the series resistors RQ3 and CQ2, and pin 3 is divided into two paths, one is grounded through the resistor RQ2, and the other is 5.2V after being connected to the series voltage divider resistors RQ4 and RQ5; The 5.2V terminal is grounded through parallel capacitors CQ3 and CQ4; The VCC1 terminal is grounded through capacitor CQ1; Pin 3 of the DC-DC chip UQ3 outputs 0.97V, and the output voltage is set by the voltage-dividing resistors RQ4 and RQ5.

3. The three-phase smart meter power switching circuit according to claim 2 is characterized in that: In the supercapacitor circuit, one of the two input voltages is connected to 5.2V through a diode DV8, and the other is connected to 5.2V through a capacitor CV3 and a resistor group of parallel resistors RV6 and RV7.

4. The three-phase smart meter power switching circuit according to claim 3 is characterized in that: In the stop-copy battery circuit, pin 1 of the voltage regulator UQ1 is grounded, pin 2 is grounded through capacitor CV1, pin 3 is output, and pin 3 is grounded through capacitor CV2.

5. The three-phase smart meter power switching circuit according to claim 4 is characterized in that: In the DC-DC chip UQ3, the VIN pin is the input voltage pin, connected to the input voltage VCC1; the EN pin is the enable pin of the chip, which is valid at a high level and is connected to the input voltage VCC1 through a resistor RQ1; the GND pin is the ground pin of the DC-DC chip UQ3 and is connected to GND; the SW pin is the output pin of the DC-DC chip UQ3 and is connected to the inductor LQ1; the BST pin and the SW pin are connected through a capacitor CQ5 and a resistor RQ3; FB is the feedback pin, and the required output voltage value is set through the voltage-dividing resistors RQ4, RQ5 and RQ6; the Zener diode DV11 is a freewheeling diode, which forms a freewheeling circuit with the inductor LQ1; capacitors CQ3 and CQ4 are output capacitors; capacitor CQ1 is an input capacitor, which provides a stable input current and a stable input voltage for UQ3.

6. The three-phase smart meter power switching circuit according to claim 5, characterized in that: In the supercapacitor circuit, the 5.2V DC power output by the DC step-down circuit is supplied to the supercapacitor EV1 through the diode DV7 and the parallel resistors RV6 and RV7; the resistors RV6 and RV7 are current limiting resistors, and the diode DV7 is used to prevent the electricity of the supercapacitor from flowing back to the front end; the 5.2V and the supercapacitor EV1 are connected through the dual diode DV8 to obtain a 5V voltage, and a 4V DC voltage is output through the voltage regulator UQ2; the capacitors CV3 and CV4 are the input and output capacitors of the voltage regulator UQ2.

7. The three-phase smart meter power switching circuit according to claim 6, characterized in that: In the shutdown battery circuit, the 6V voltage output by the shutdown battery is input to the voltage regulator UQ1 through the diode DV5, and the voltage regulator UQ1 outputs a 3.6V DC voltage; capacitors CV1 and CV2 are the input and output capacitors of the voltage regulator UQ1 respectively; the Power_Battery_Ctr voltage controls the conduction and shutdown of the PMOS tube QK2, and determines whether the voltage of the battery BAT1 is supplied to MVDD.

8. The three-phase smart meter power switching circuit according to claim 7, characterized in that: In the clock battery circuit, the Power_Battery_Ctr voltage controls the on / off of the PMOS tube QK1, and determines whether the clock battery BAT2 voltage supplies MVDD; In the battery control circuit, when powered on normally, the voltage at the Power_Battery_Ctr point is clamped at MVDD+Vf, where Vf is the forward conduction voltage drop of the diode DV2; the Zener voltage of the Zener diode DV1 is 5.1V, and the 12V VCC1 is reduced to 6.9V after passing through the Zener diode DV1; the resistor RV3 is used to limit the current and withstand the voltage difference between the positive electrode of the Zener diode and Power_Battery_Ctr; when the voltage of VCC1 is lower than 5.1V, it stops providing voltage to the circuit, and the remaining energy in the circuit is discharged through the resistor RV1, and the voltage at the Power_Battery_Ctr point begins to gradually decrease; Resistors RV1 and RV2 are connected in parallel and together determine the magnitude of the current in the path from VCC1 to GND when DV2 is turned on.

9. A three-phase smart meter power switching method, characterized in that: It includes the circuit described in claim 1; it is characterized in that: when powered on normally, there is a 12V DC voltage at VCC1, and a 5.2V voltage is obtained through the DC-DC chip UQ3; the 5.2V voltage passes through the diode DV7 one way to charge the supercapacitor EV1, and the supercapacitor EV1 is charged to 5V; the 5.2V voltage passes through the diode DV8 another way, and the voltage is reduced by 0.2V to obtain a 5V voltage, which is used as the input voltage of the voltage regulator UQ2; the voltage regulator UQ2 outputs a stable 4V DC voltage, which is reduced by about 0.2V through the diode DV9 to obtain a 3.8V MVDD to power the corresponding module in the meter.

10. The three-phase smart meter power switching method according to claim 9, characterized in that: When a sudden power outage occurs, supercapacitor EV1 starts to supply power, and after passing through diode DV8, a 4.8V voltage is obtained, which is used as the input voltage of voltage regulator UQ2; voltage regulator UQ2 outputs a stable 4V DC voltage, which is reduced by about 0.2V through diode DV9 to obtain a 3.8V MVDD, which supplies power to the corresponding modules in the meter; At the same time, after the power outage, the voltage of VCC1 gradually decreases. When it drops to 5.1V, the Zener diode DV1 stops conducting and stops providing voltage to the circuit. At this time, the remaining energy in the circuit is discharged through the resistor RV1, and the voltage at the Power_Battery_Ctr point gradually decreases. When the Power_Battery_Ctr voltage drops to the output voltage of the voltage regulator UQ1 +Vgs, i.e. 3.05V, the PMOS tube QK2 is turned on; At this time, the 3.6V voltage output by the stop copy battery through the regulator UQ1 starts to power MVDD. After passing through the diode DV6, there is a 0.2V voltage drop, and a 3.4V MVDD is obtained; when the Power_Battery_Ctr voltage drops to the clock battery voltage - the forward conduction voltage drop of the diode DV3 + Vgs, the regulator UQ2 is turned on, and the clock battery starts to power MVDD; after the voltage drops of the diodes DV3 and DV4, MVDD is obtained.

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