A power supply topology circuit and control method for high conversion ratio dc-dc converters

Abstract

This application discloses a power supply topology and control method for a high-conversion-ratio DC-DC level converter. The circuit includes a conversion ratio boosting structure, a voltage stress halving structure, a power inductor, and an output capacitor. The method includes: acquiring a control signal and an input voltage signal; based on the control signal, boosting the input voltage signal and magnetizing the power inductor, with the output capacitor supplying power to the output load; and based on the control signal, demagnetizing the power inductor and supplying power to the output load through the inductor current. The embodiments of this application can achieve a higher voltage conversion ratio and higher conversion efficiency at a lower duty cycle. This application can be widely applied in the field of integrated circuit design technology.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and in particular to a power supply topology circuit and control method for a high-ratio DC-DC level converter. Background Technology

[0002] In boost converter design, a high voltage conversion ratio (CR, the ratio of output to output voltage) can bring many challenges, including higher voltage and current stresses and higher requirements for passive components, thus limiting the conversion efficiency of the level converter.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0004] The main objective of this application is to propose a power supply topology circuit and control method for a high-conversion-ratio DC-level converter, which can achieve a higher voltage conversion ratio and higher conversion efficiency at a lower duty cycle.

[0005] To achieve the above objectives, one aspect of this application proposes a power supply topology circuit for a high-conversion-ratio DC-DC level converter. The circuit includes a conversion ratio boosting structure, a voltage stress halving structure, a power inductor, and an output capacitor. The output terminal of the conversion ratio boosting structure is connected to the input terminal of the power inductor, the output terminal of the power inductor is connected to the input terminal of the voltage stress halving structure, and the output terminal of the voltage stress halving structure is connected to the input terminal of the output capacitor, wherein:

[0006] The voltage ratio boosting structure is used to perform voltage ratio boosting processing on the input voltage signal to obtain a boosted voltage signal.

[0007] The voltage stress halving structure is used to reduce the voltage stress on the power switching transistor.

[0008] The power inductor is used to transmit the boosted voltage signal to the voltage stress halving structure;

[0009] The output capacitor is used to smooth the output of the boosted voltage signal.

[0010] In some embodiments, the turn ratio enhancement structure includes a first power switch, a second power switch, a third power switch, and a first flying capacitor. The first terminal of the first power switch and the first terminal of the third power switch are connected and connected to a high level. The second terminal of the first power switch, the first terminal of the first flying capacitor, and the first terminal of the second power switch are connected to the voltage stress halving structure at a first node. The second terminal of the third power switch and the second terminal of the first flying capacitor are connected to the power inductor at a second node. The second terminal of the second power switch is grounded.

[0011] In some embodiments, the voltage stress halving structure includes a fourth power switch, a fifth power switch, a sixth power switch, a seventh power switch, a second flying capacitor, and a third flying capacitor. The first terminal of the second flying capacitor is connected to the turn ratio boosting structure. The second terminal of the second flying capacitor, the first terminal of the fourth power switch, and the first terminal of the sixth power switch are connected to a fourth node. The second terminal of the fourth power switch, the first terminal of the fifth power switch, and the first terminal of the third flying capacitor are connected to the power inductor at a third node. The second terminal of the third flying capacitor, the second terminal of the sixth power switch, and the first terminal of the seventh power switch are connected to a fifth node. The second terminal of the fifth power switch is grounded, and the second terminal of the seventh power switch is connected to the output capacitor.

[0012] In some embodiments, a first end of the power inductor is connected to the turn ratio boosting structure, and a second end of the power inductor is connected to the voltage stress halving structure.

[0013] In some embodiments, the first terminal of the output capacitor is connected to the voltage stress reduction structure, and the second terminal of the output capacitor is grounded.

[0014] To achieve the above objectives, another aspect of this application proposes a control method for a power supply topology circuit of a high-conversion-ratio DC-DC level converter, the method comprising the following steps:

[0015] Acquire control signals and input voltage signals;

[0016] Based on the control signal, the input voltage signal is boosted and the power inductor is magnetized, and the output capacitor supplies power to the output load.

[0017] Based on the control signal, the power inductor is demagnetized, and the inductor current supplies power to the output load.

[0018] In some embodiments, during the inductor magnetization process, the first, fifth, and sixth power switches are all in a closed state, while the second, third, fourth, and seventh power switches are all in an open state. The second terminal of the power inductor is grounded through the fifth power switch, the first node is connected to the input voltage signal through the first power switch, the terminal voltage of the first flying capacitor is set to the input voltage, and the terminal voltage of the second node is increased to twice the input voltage to magnetize the power inductor.

[0019] In some embodiments, the inductor magnetization process further includes a charge redistribution between the second and third flying capacitors connected in series through the first, fifth, and sixth power switches, with the charge of the second flying capacitor flowing to the third flying capacitor.

[0020] In some embodiments, during the inductor demagnetization process, the second power switch, the third power switch, the fourth power switch, and the seventh power switch are all in a closed state, while the first power switch, the fifth power switch, and the sixth power switch are all in an open state. The first terminal of the power inductor is connected to the input voltage signal through the third power switch, and the first flying capacitor is connected to the input voltage signal through the second power switch and the third power switch.

[0021] In some embodiments, the inductor demagnetization process further includes the following steps: the first direction of the inductor current charges the second flying capacitor through the second power switch and the fourth power switch; the second direction of the inductor current supplies power to the output load through the seventh power switch and the third flying capacitor.

[0022] The embodiments of this application include at least the following beneficial effects: This application provides a power supply topology circuit and control method for a high-conversion-ratio DC-DC level converter. This scheme performs voltage conversion ratio enhancement processing on the input voltage signal through a conversion ratio enhancement structure, which can achieve a higher voltage conversion ratio at a lower duty cycle, resulting in smaller inductor current ripple and allowing for a larger switching frequency. Furthermore, the voltage stress on the power switch is reduced through a voltage stress halving structure, so that the voltage pressure on the power switch only needs to bear half of the output voltage stress, thereby allowing lower voltage switches to be used in this topology, effectively improving the system's conversion efficiency. Finally, the introduction of a power inductor and an output capacitor, adopting a hybrid structure of inductor and capacitor, fully utilizes the advantages brought by different structures, and can achieve higher conversion efficiency. Attached Figure Description

[0023] Figure 1This is a schematic diagram of a power supply topology circuit for a high-ratio DC-to-level converter provided in an embodiment of this application;

[0024] Figure 2 This is a flowchart illustrating the steps of a control method for a power supply topology circuit for a high-ratio DC-to-level converter provided in an embodiment of this application.

[0025] Figure 3 This is a schematic diagram of the workflow of the power topology provided in the embodiments of this application;

[0026] Figure 4 This is a topological schematic diagram of the magnetization stage provided in an embodiment of this application;

[0027] Figure 5 This is a topological schematic diagram of the demagnetization stage provided in an embodiment of this application;

[0028] Figure 6 This is a schematic diagram of the power stage circuit of the topology provided in the embodiments of this application;

[0029] Figure 7 This is a schematic diagram of the controller and driver provided in the embodiments of this application. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of systems and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0031] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0032] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0034] First, it should be noted that hybrid converter power topologies offer many advantages for improving converter performance in high-voltage, high-conversion-ratio scenarios. By combining the advantages of switch-capacitor converters and inductive converters, and leveraging the greater design freedom of hybrid architectures, this invention proposes a hybrid power topology suitable for high-voltage, high-conversion-ratio applications to achieve higher energy conversion efficiency.

[0035] The related technologies have the following shortcomings:

[0036] 1) In high-voltage, high-ratio scenarios, the voltage stress on switching devices is very high, and it is necessary to use high-voltage devices with poor quality factor and high withstand voltage, which increases the conduction loss and drive loss of the switching devices.

[0037] 2) According to the law of conservation of energy, V IN *I IN =V OUT *I OUT Therefore, when the output voltage is high and the input voltage is low, there will be a large input current on the input side, which increases the overall heat dissipation along the path.

[0038] 3) In pulse width modulation (PWM), the output voltage modulation of the converter depends on changing the duty cycle D, i.e., D and CR are positively correlated. Therefore, in order to achieve a high conversion ratio, traditional converters have to use extreme duty cycles (D>0.9). Such a large duty cycle brings difficulties to the design of controllers and drivers, makes it more difficult to control the dead time, and limits the further increase of switching frequency.

[0039] Based on this, embodiments of the present invention provide a hybrid power topology suitable for high voltage and high conversion ratio applications to achieve higher energy conversion efficiency.

[0040] Reference Figure 1 , Figure 1This is a schematic diagram of a power supply topology circuit for a high-ratio DC-to-level converter provided in an embodiment of the present invention, with reference to... Figure 1 The circuit includes a turn ratio boosting structure, a voltage stress halving structure, a power inductor, and an output capacitor. The output terminal of the turn ratio boosting structure is connected to the input terminal of the power inductor. The output terminal of the power inductor is connected to the input terminal of the voltage stress halving structure. The output terminal of the voltage stress halving structure is connected to the input terminal of the output capacitor.

[0041] The voltage ratio boosting structure is used to perform voltage ratio boosting on the input voltage signal to obtain the boosted voltage signal.

[0042] Specifically, the turn ratio boosting structure includes a first power switch S1, a second power switch S2, a third power switch S3, and a first flying capacitor C. F1 The first terminal of the first power switch is connected to the first terminal of the third power switch and is connected to a high level. The second terminal of the first power switch, the first terminal of the first flying capacitor, and the first terminal of the second power switch are connected to the voltage stress reduction structure at the first node V. SW1 The second terminal of the third power switch, the second terminal of the first flying capacitor, and the power inductor are connected to the second node V. SW2 The second terminal of the second power switch is grounded.

[0043] In this embodiment, on the input side, the first power switch S1, the second power switch S2, the third power switch S3, and the first flying capacitor C F1 This structure forms a conversion ratio boosting structure, operating similarly to a 1:2 charge pump. It utilizes switched capacitors to effectively increase the input voltage, thereby achieving a higher conversion ratio (CR) for the entire power topology.

[0044] The voltage stress reduction structure is used to reduce the voltage stress on power switching transistors.

[0045] Specifically, the voltage stress halving structure includes a fourth power switch S4, a fifth power switch S5, a sixth power switch S6, a seventh power switch S7, and a second flying capacitor C. F2 With the third flying capacitor C F3 The first terminal of the second flying capacitor is connected to the turn ratio boosting structure, and the second terminal of the second flying capacitor, the first terminal of the fourth power switch, and the first terminal of the sixth power switch are connected to the fourth node V. SW4 The second terminal of the fourth power switch, the first terminal of the fifth power switch, and the first terminal of the third flying capacitor are connected to the power inductor and the third node V. SW3 The second terminal of the third flying capacitor, the second terminal of the sixth power switch, and the first terminal of the seventh power switch are connected to the fifth node V. SW5The second terminal of the fifth power switch is grounded, and the second terminal of the seventh power switch is connected to the output capacitor.

[0046] In this embodiment, on the output side, the fourth power switch S4, the fifth power switch S5, the sixth power switch S6, the seventh power switch S7, and the second flying capacitor C... F2 With the third flying capacitor C F3 A halved voltage stress structure (HVS) is constructed, which uses a switched capacitor to bear part of the output voltage, thereby reducing the stress of the output voltage on the switch and inductor.

[0047] The power inductor is used to transmit the boosted voltage signal to the voltage stress halving structure;

[0048] Specifically, the first end of the power inductor is connected to the turn ratio enhancement structure, and the second end of the power inductor is connected to the voltage stress reduction structure.

[0049] Output capacitor C OUT Used to smooth the output boosted voltage signal.

[0050] Specifically, the first terminal of the output capacitor is connected to the voltage stress reduction structure, and the second terminal of the output capacitor is grounded.

[0051] Please see Figure 2 This application also provides a control method for a power supply topology circuit for a high-ratio DC-level converter, which can realize the above-mentioned power supply topology circuit for a high-ratio DC-level converter. The method includes the following steps:

[0052] S100: Acquire control signals and input voltage signals;

[0053] In some specific embodiments, the power topology of the present invention is divided into two stages based on the different states of the switch closure and the inductor: the inductor magnetization stage and the inductor demagnetization stage, such as... Figure 3 As shown, the control signal is a periodic signal, and the proposed power topology operates alternately in these two states according to the control signal.

[0054] S200: Based on the control signal, the input voltage signal is boosted and the power inductor is magnetized. The output capacitor supplies power to the output load.

[0055] In some specific embodiments, during the inductor magnetization stage, the first, fifth, and sixth power switches are all in the closed state, while the second, third, fourth, and seventh power switches are all in the open state. The second terminal of the power inductor is grounded through the fifth power switch, and the first node is connected to the input voltage signal through the first power switch. The terminal voltage of the first flying capacitor is set to the input voltage. The terminal voltage of the second node is increased to twice the input voltage to magnetize the power inductor. The second and third flying capacitors are connected in series through the first, fifth, and sixth power switches to redistribute charge, with the charge flowing from the second flying capacitor to the third flying capacitor.

[0056] In this embodiment, as Figure 4 As shown, in this stage, the first power switch, the fifth power switch, and the sixth power switch are closed, and the right side of the inductor is grounded through the fifth power switch. The first node V SW1 The first power switch is connected to the input voltage, and the voltage across the first flying capacitor is set to V during the demagnetization phase. IN Therefore, the second node V SW2 Boosted to 2V IN Magnetize the inductor.

[0057] Meanwhile, the second and third flying capacitors on the output side are connected in series through the first, fifth, and sixth power switches. At this time, the two capacitors undergo charge redistribution, with charge transferred from the second flying capacitor to the third flying capacitor, replenishing the charge of the third flying capacitor.

[0058] During this stage, since the seventh power switch remains off, the output capacitor C... OUT Power the output load.

[0059] S300: Based on the control signal, the power inductor is demagnetized, and the inductor current supplies power to the output load.

[0060] In some specific embodiments, during the inductor demagnetization stage, the second, third, fourth, and seventh power switches are all in a closed state, while the first, fifth, and sixth power switches are all in an open state. The first terminal of the power inductor is connected to the input voltage signal through the third power switch, and the first flying capacitor is connected to the input voltage signal through the second and third power switches. The first direction of the inductor current charges the second flying capacitor through the second and fourth power switches, and the second direction of the inductor current supplies power to the output load through the seventh power switch and the third flying capacitor.

[0061] In this embodiment, as Figure 5As shown, in this stage, the second, third, fourth, and seventh power switches are closed, while the remaining switches are open. The right side of the inductor is connected to the input voltage through the third power switch. Simultaneously, the first flying capacitor is connected to the input voltage through the second and third power switches. Therefore, the voltage across the first flying capacitor is set to V. IN .

[0062] On the output side, the inductor current has two paths. The first path charges the second flying capacitor through the second and fourth power switches. The second path supplies power to the output through the seventh power switch and the third flying capacitor. Due to the presence of the third flying capacitor, the output current C... OUT The high voltage on the capacitor is partially isolated, thus significantly reducing the voltage stress on the fifth and sixth power switches.

[0063] Finally, it should also be stated that, as Figure 6 The diagram shows the power stage circuit implementation of the topology in an embodiment of the present invention. The power switches, controller, and driver are all integrated on a silicon wafer using integrated circuit technology. The power stage topology is consistent with the above, including a first power switch S1, a second power switch S2, a third power switch S3, a fourth power switch S4, a fifth power switch S5, a sixth power switch S6, a seventh power switch S7, and a first flying capacitor C. F1 Second flying capacitor C F2 Third flying capacitor C F3 Output capacitor C OUT A power inductor is provided, wherein the first power switch S1, the second power switch S2, the third power switch S3, the fourth power switch S4, the fifth power switch S5, the sixth power switch S6, and the seventh power switch S7 are all MOS transistors, supplemented by corresponding drivers. The driver for each switch includes a bootstrap capacitor C. BST and buffers. Furthermore, in addition to the power stage, such as... Figure 7 As shown, in order to achieve the normal operation of the proposed power supply topology, a controller structure is adopted, which includes: a feedback network, a compensator, a comparator, dead-time control logic, a level shifter, and a drive circuit.

[0064] In summary, the embodiments of the present invention have the following advantages compared with the prior art:

[0065] 1) The proposed topology adopts a hybrid structure of inductors and capacitors, which makes full use of the advantages of different structures and can achieve higher conversion efficiency.

[0066] 2) Due to the output-side switched capacitor C F2 and C F3 The application of this makes the output capacitor C OUTThe high output voltage on the switch capacitor C is controlled by the switch capacitor C. F2 and C F3 This means that the voltage stress on the power switch is only half of the output voltage stress. Consequently, lower voltage switches can be used in this topology, which effectively improves the system's conversion efficiency.

[0067] 3) The proposed converter has a conversion ratio (CR) of (3+D) / (1-D), which is 3 to 4 times higher than that of conventional boost converters. This characteristic helps to achieve higher Vc at a lower duty cycle. OUT / V IN For example, when CR=10, D=0.64 instead of D=0.9 in a traditional boost converter, which results in a smaller inductor current ripple (ΔI). L ), and allows for a larger switching frequency (F SW ).

[0068] 4) The proposed power topology redesigns the inductor's magnetization and demagnetization voltages using switched capacitors, resulting in shorter charging and longer discharging times, allowing more time for the inductor current to be delivered to the output. This leads to lower inductor current under the same load, significantly reducing Joule heat dissipation along the path and improving conversion efficiency. At the same conversion ratio, the inductor current can be reduced to half its original value.

[0069] It is understood that the content of the above method embodiments is applicable to this system embodiment. The specific functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0070] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A power supply topology circuit for a high-ratio DC-level converter, characterized in that, The circuit includes a turn ratio boosting structure, a voltage stress halving structure, a power inductor, and an output capacitor. The output terminal of the turn ratio boosting structure is connected to the input terminal of the power inductor. The output terminal of the power inductor is connected to the input terminal of the voltage stress halving structure. The output terminal of the voltage stress halving structure is connected to the input terminal of the output capacitor. Wherein: The voltage ratio boosting structure is used to perform voltage ratio boosting processing on the input voltage signal to obtain a boosted voltage signal. The voltage stress halving structure is used to reduce the voltage stress on the power switching transistor. The power inductor is used to transmit the boosted voltage signal to the voltage stress halving structure; The output capacitor is used to smooth the output of the boosted voltage signal; The turn ratio enhancement structure includes a first power switch, a second power switch, a third power switch, and a first flying capacitor. The first terminal of the first power switch and the first terminal of the third power switch are connected and connected to a high level. The second terminal of the first power switch, the first terminal of the first flying capacitor, and the first terminal of the second power switch are connected to the voltage stress halving structure at a first node. The second terminal of the third power switch, the second terminal of the first flying capacitor, and the first terminal of the power inductor are connected to a second node. The second terminal of the second power switch is grounded. The voltage stress halving structure includes a fourth power switch, a fifth power switch, a sixth power switch, a seventh power switch, a second flying capacitor, and a third flying capacitor. The first terminal of the second flying capacitor is connected to the first node. The second terminal of the second flying capacitor, the first terminal of the fourth power switch, and the first terminal of the sixth power switch are connected to the fourth node. The second terminal of the fourth power switch, the first terminal of the fifth power switch, the first terminal of the third flying capacitor, and the second terminal of the power inductor are connected to the third node. The second terminal of the third flying capacitor, the second terminal of the sixth power switch, and the first terminal of the seventh power switch are connected to the fifth node. The second terminal of the fifth power switch is grounded, and the second terminal of the seventh power switch is connected to the output capacitor.

2. The circuit according to claim 1, characterized in that, The first terminal of the output capacitor is connected to the voltage stress reduction structure, and the second terminal of the output capacitor is grounded.

3. A control method for a power supply topology circuit used in a high-ratio DC-to-level converter, characterized in that, The method is applied to a power supply topology circuit for a high-ratio DC-level converter as described in claim 1, and the method includes the following steps: Acquire control signals and input voltage signals; Based on the control signal, the input voltage signal is boosted and the power inductor is magnetized, and the output capacitor supplies power to the output load. Based on the control signal, the power inductor is demagnetized, and the output load is powered by the inductor current. During the inductor magnetization process, the first, fifth, and sixth power switches are all in the closed state, while the second, third, fourth, and seventh power switches are all in the open state. The second terminal of the power inductor is grounded through the fifth power switch, the first node is connected to the input voltage signal through the first power switch, the terminal voltage of the first flying capacitor is set to the input voltage, and the terminal voltage of the second node is increased to twice the input voltage to magnetize the power inductor. During the inductor demagnetization process, the second, third, fourth, and seventh power switches are all in a closed state, while the first, fifth, and sixth power switches are all in an open state. The first terminal of the power inductor is connected to the input voltage signal through the third power switch, and the first flying capacitor is connected to the input voltage signal through the second and third power switches.

4. The method according to claim 3, characterized in that, The inductor magnetization process also includes a charge redistribution process where the second and third flying capacitors are connected in series through the first, fifth, and sixth power switches, with the charge flowing from the second flying capacitor to the third flying capacitor.

5. The method according to claim 3, characterized in that, The inductor demagnetization process further includes the following steps: the first direction of the inductor current charges the second flying capacitor through the second power switch and the fourth power switch; the second direction of the inductor current supplies power to the output load through the seventh power switch and the third flying capacitor.

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