Variable gain power amplifier architecture with low phase error and high rollback efficiency

Abstract

The invention discloses a variable gain power amplifier architecture with low phase error and high rollback efficiency, and belongs to the technical field of radio frequency front ends. Comprising a first transformer, a variable gain amplifier module, a second transformer, a power amplifier module and a coupling line output matching network, the coupling coefficient of the first transformer is k1, and the coupling coefficient of the second transformer is k2; each of the variable gain amplifier module and the power amplifier module comprises two self-adaptive bias modules, and the bias state of the power amplifier module is adjusted through the self-adaptive bias modules, so that the power additional efficiency and the linearity of the power amplifier module are improved; the phase change is offset by simultaneously adjusting the control voltage of the variable gain amplifier module and the grid voltage of the adaptive bias module. Due to good phase error, high output power and high rollback efficiency, the antenna is suitable for a millimeter wave phased array transmitter.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency front - ends, and particularly to a variable - gain power amplifier architecture with low phase error and high back - off efficiency. Background Art

[0002] With the development of 5G technology, applications such as the Internet of Things, autonomous driving, intelligent drones, and virtual reality have rapidly emerged, posing higher requirements for the data rate of wireless systems. The millimeter - wave band has richer frequency - band resources than the Sub - 6G band: its bandwidth is much larger than that of Sub - 6G, which gives the millimeter - wave band the potential for higher data rates and enables more data to be sent in a single communication; at the same time, the higher frequency of millimeter - waves means that more information can be transmitted in a shorter time, so millimeter - waves have the characteristic of low latency; in addition, the higher frequency of millimeter - waves represents a relatively smaller size, enabling more systems to be arranged in a limited area. Because of these many advantages of the millimeter - wave band, it has attracted a lot of attention in the academic and industrial fields.

[0003] However, millimeter - waves face problems such as low antenna gain and large atmospheric attenuation, which restrict the working distance of wireless systems. To increase the working distance of wireless systems, phased - array technology is widely used in millimeter - wave wireless systems. By controlling the phases of the signals transmitted by N channels of the phased - array system, the electromagnetic waves in space can be in - phase superimposed in a specific direction, so as to achieve a high - gain effect in a specific direction, that is, to improve the directivity of the array transceiver.

[0004] In a phased array transmitter, the VGA and PA are important modules in the system. Ideally, the phase of the VGA should remain unchanged during the process of changing the gain. However, in reality, the phase of the VGA will change with the gain state, which will cause the sidelobe level of the phased array pattern to increase and deteriorate the directivity of the phased array. The PA is the last module of the phased array transmitter, and its output power represents the output power of the overall system. At the same time, as the device with the largest power consumption in the transmitter system, the efficiency of the PA often determines the level of system power consumption. The VGA adjusts the radiation pattern of the phased array system by controlling the gain states of each RF channel in the phased array system. By weighting the signal amplitudes of different channels, the sidelobe suppression ratio can be improved. As the last stage of the transmitter, the PA determines the output power and efficiency of the transmitter. In the 5G system, in order to contain more information, the transmitted signal generally uses high-order modulation, and the peak-to-average ratio of the high-order modulation signal is relatively large, which requires the PA to have high efficiency in a large dynamic range. In a typical transmitter system, the VGA and PA are usually designed as two independent modules. The main design goal of the VGA is to achieve high gain resolution and low phase change in the phased array system to improve the sidelobe suppression ratio of the phased array system and optimize the pattern of the phased array system. The design goal of the PA is to obtain high output power and high efficiency to ensure the output power of the overall system and as low power consumption as possible. In a conventional system, the VGA and PA are designed separately as two modules, which often results in a waste of chip layout area.

[0005] The following problems exist in the prior art: (1) The designed architecture does not specifically consider the broadband index, the bandwidth is very small, and it is not suitable for broadband systems, so it cannot support the requirements of international roaming. (2) The form of a numerically controlled gate array is used, so more MOS transistors are used and the layout design is relatively complex; (3) The PAE performance under high peak-to-average ratio is not considered and it is not suitable for high-order modulation signals; Summary of the Invention

[0006] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a variable gain power amplifier architecture with low phase error and high back-off efficiency.

[0007] The object of the present invention is achieved by the following technical solutions: A variable-gain power amplifier architecture with low phase error and high back-off efficiency, comprising: a first transformer, the input end of the first transformer is connected to an external input, and the output end of the first transformer is connected to a variable-gain amplifier module; the variable-gain amplifier module is connected to a second transformer; the second transformer is connected to a power amplifier module; the power amplifier module is connected to a coupled-line output matching network; the coupled-line output matching network is connected to a subsequent circuit; the coupling coefficient of the first transformer is k1, and the coupling coefficient of the second transformer is k2; both the variable-gain amplifier module and the power amplifier module include two adaptive bias modules, and the bias state of the power amplifier module is adjusted through the adaptive bias modules, thereby improving the power-added efficiency and linearity of the power amplifier module; by simultaneously adjusting the control voltage of the variable-gain amplifier module and the gate voltage of the adaptive bias module, the phase change is offset.

[0008] Preferably, the circuit structures of the adaptive bias modules in the variable-gain amplifier module and the power amplifier module are the same; the adaptive bias module includes an input terminal resistor Rin, an input terminal capacitor Cin, a first resistor R1, a fifteenth MOS transistor M15, a second resistor R2, and a first capacitor C1; the first end of the input terminal resistor Rin is connected to a pre-stage input circuit, and the second end of the input terminal resistor Rin is connected to the first end of the input terminal capacitor Cin; the second end of the input terminal Cin is connected to the first end of the first resistor R1 and the gate of the fifteenth MOS transistor M15; the second end of the first resistor R1 is connected to the gate voltage VG ABM ; the drain of the fifteenth MOS transistor M15 is connected to the power supply VDD ABM , the source of the fifteenth MOS transistor M15 is connected to the first end of the second resistor R2, the first end of the first capacitor C1, and a post-stage output circuit; the second ends of the second resistor R2 and the first capacitor C1 are connected to the ground GND.

[0009] Preferably, the variable gain amplifier module includes a first neutralization capacitor CC1, a second neutralization capacitor CC2, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a first adaptive bias module ABM1, and a second adaptive bias module ABM2; the second terminal of the first transformer is connected to the ground GND, the third terminal of the first transformer is connected to the input terminal of the first adaptive bias module ABM1, the gate of the third MOS transistor M3, and the first terminal of the second neutralization capacitor CC2, the fourth terminal of the first transformer is connected to the first bias voltage Vbias1, the fifth terminal of the first transformer is connected to the input terminal of the second adaptive bias module ABM2, the gate of the fourth MOS transistor M4, and the first terminal of the first neutralization capacitor CC1; the output terminal of the first adaptive bias module ABM1 is connected to the gate of the first MOS transistor M1; the second terminal of the first neutralization capacitor CC1 is connected to the drain of the third MOS transistor M3, and the sources of the fifth MOS transistor M5 and the seventh MOS transistor M7; the source of the third MOS transistor M3 is connected to the source of the fourth MOS transistor M4, and the drains of the first MOS transistor M1 and the second MOS transistor M2; the drain of the fourth MOS transistor M4 is connected to the second terminal of the second neutralization capacitor CC2, and the sources of the sixth MOS transistor M6 and the eighth MOS transistor M8; the output terminal of the second adaptive bias module ABM2 is connected to the gate of the second MOS transistor M2; the sources of the first MOS transistor M1 and the second MOS transistor M2 are connected to the ground GND; the gate of the seventh MOS transistor M7 is connected to the control voltage VC, and the drain of the seventh MOS transistor M7 is connected to the power supply VDD; the gate of the fifth MOS transistor M5 is connected to the gate of the sixth MOS transistor M6 and the second bias voltage Vbias2, and the drain of the fifth MOS transistor M5 is connected to the first terminal of the second transformer; the drain of the sixth MOS transistor M6 is connected to the third terminal of the second transformer; the gate of the eighth MOS transistor M8 is connected to the control voltage VC, and the drain of the eighth MOS transistor M8 is connected to the power supply VDD.

[0010] Preferably, the capacitance values of the first neutralization capacitor CC1 and the second neutralization capacitor CC2 are equal.

[0011] Preferably, the power amplifier module includes a third adaptive bias module ABM3, a fourth adaptive bias module ABM4, a third neutralizing capacitor CC3, a fourth neutralizing capacitor CC4, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, and a fourteenth MOS transistor M14; the second end of the second transformer is connected to the power supply VDD, the fourth end of the second transformer is connected to the input end of the third adaptive bias module ABM3, the first end of the fourth neutralizing capacitor CC4, and the gate of the eleventh MOS transistor M11, the fifth end of the second transformer is connected to the third bias voltage Vbias3, the sixth end of the second transformer is connected to the input end of the fourth adaptive bias module ABM4, the first end of the third neutralizing capacitor CC3, and the gate of the twelfth MOS transistor M12; the output end of the third adaptive bias module ABM3 is connected to the gate of the ninth MOS transistor M9; the second end of the third neutralizing capacitor CC3 is connected to the drain of the eleventh MOS transistor M11 and the source of the thirteenth MOS transistor M13; the source of the eleventh MOS transistor M11 is connected to the source of the twelfth MOS transistor M12 and the drains of the ninth MOS transistor M9 and the tenth MOS transistor M10; the drain of the twelfth MOS transistor M12 is connected to the second end of the fourth neutralizing capacitor CC4 and the source of the fourteenth MOS transistor M14; the output end of the fourth adaptive bias module ABM4 is connected to the gate of the tenth MOS transistor M10; the sources of the ninth MOS transistor M9 and the tenth MOS transistor M10 are connected to the ground GND; the drain of the thirteenth MOS transistor is connected to the coupled line output matching network, the gate of the thirteenth MOS transistor is connected to the gate of the fourteenth MOS transistor and the fourth bias voltage Vbias4; the drain of the fourteenth MOS transistor is connected to the coupled line output matching network. Preferably, the capacitance values of the third neutralizing capacitor CC3 and the fourth neutralizing capacitor CC4 are equal.

[0012] Preferably, the coupled-line output matching network includes a first coupled line Couple1, a second coupled line Couple2, a first output matching capacitor Cout1, and a second output matching capacitor Cout2; a first end of the first coupled line Couple1 is connected to the drain of the thirteenth MOS transistor, a second end of the first coupled line Couple1 is connected to the power supply VDD, a third end of the first coupled line Couple1 is connected to a first end of the second coupled line Couple2, and a fourth end of the first coupled line Couple1 is connected to first ends of the first output matching capacitor Cout1 and the second output matching capacitor Cout2; a second end of the first output matching capacitor Cout1 is connected to the ground GND; a second end of the second output matching capacitor Cout2 is connected to a subsequent output circuit; a second end of the second coupled line Couple2 is connected to the ground GND, a third end of the second coupled line Couple2 is connected to the drain of the fourteenth MOS transistor, and a fourth end of the second coupled line Couple2 is connected to the power supply VDD.

[0013] The beneficial effects of the present invention are as follows: 1) A current source is introduced between the source (AC ground) of the conventional circuit and the ground, and the bias of the current source is adjusted through the adaptive bias module, which can adaptively adjust the bias state of the PA, improving the PAE and linearity of the PA in the back-off region.

[0014] 2) The Current Steering structure is used to design the VGA. A current source is introduced between the source and the ground, and the bias of the current source is adjusted by the adaptive bias module. By simultaneously adjusting the control voltage of the Current Steering VGA and the gate voltage of the adaptive bias module, the phase change is cancelled. The phase remains unchanged while the gain is changed.

[0015] 3) The VGA and the PA in the traditional phased array system are jointly designed to achieve a more compact layout area. In the present invention, the adaptive bias module is connected to the input end of the amplifier, which can automatically control the bias state of the PA according to the magnitude of the input signal, improving the linearity of the PA and its PAE in the back-off region. In the variable gain stage, the present invention uses the Current-steering structure to increase the gain and introduces the adaptive bias module to improve the phase error. By simultaneously adjusting the control voltage of the Current Steering VGA and the gate voltage of the adaptive bias module, the phase error is cancelled, and finally the phase remains basically unchanged when the gain state is changed. The present invention is applicable to millimeter-wave phased array transmitters due to its good phase error, high output power, and high back-off efficiency. Description of the Drawings

[0016] Figure 1Schematic circuit diagram of a variable gain power amplifier architecture with low phase error and high back-off efficiency; Figure 2 Schematic diagram for analyzing the optimal load impedance Zopt; Figure 3 Schematic diagram of the electromagnetic simulation structure of the output matching network of the coupled-line balun; Figure 4 Schematic diagram of the overall output matching network; Figure 5 Schematic diagram of the input impedance of the matching network after absorbing the capacitor Cdev into the matching network; Figure 6 Schematic diagram of the PAE improvement principle; Figure 7 Schematic diagram of the implementation effect of PAE improvement; Figure 8 Schematic circuit diagram of the adaptive bias module; Figure 9 Schematic diagram of the curve of the output voltage of the adaptive bias module changing with the input power; Figure 10 Comparison diagram of gain and efficiency with and without using the PAE improvement technology; Figure 11 Schematic circuit diagram of the variable gain amplifier module; Figure 12 Schematic diagram of the change of the relative phase with the attenuation amount when adjusting the voltage VC; Figure 13 For adjusting the voltage VG ABM Schematic diagram of the change of the relative phase with the attenuation amount; Figure 14 Schematic diagram of the parameter change when using the phase compensation technology. Detailed implementation manner

[0017] Next, in combination with the embodiments, the technical solutions of the present invention will be clearly and completely described. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention.

[0018] First, the definitions of some professional terms in the present invention are as follows: VGA: Variable Gain Amplifier, variable gain amplifier; PA: Power Amplifier, power amplifier; 5G: fifth-generation, fifth-generation mobile communication technology; Sidelobe suppression ratio: It represents the ratio of the main lobe to the sidelobe gain in the phased array pattern. The larger it is, the better the directivity of the phased array; Peak-to-average power ratio: Peak to Average Power Ratio (PAPR); Current Steering VGA: Current Steering VGA, a type of VGA structure; PAE: Power Added Efficiency, which reflects the ability of the PA to convert DC power consumption into output power. The larger the PAE, the higher the efficiency of the PA; Back-off: As the input signal decreases, the output power of the PA gradually decreases, and the PAE of the PA will gradually decline.

[0019] Refer to Figures 1 - 14 , the present invention provides a technical solution: a variable gain power amplifier architecture with low phase error and high back-off efficiency, comprising: a first transformer, the input end of the first transformer is connected to an external input, and the output end of the first transformer is connected to a variable gain amplifier module; the variable gain amplifier module is connected to a second transformer; the second transformer is connected to a power amplifier module; the power amplifier module is connected to a coupled line output matching network; the coupled line output matching network is connected to a subsequent circuit; the coupling coefficient of the first transformer is k1, and the coupling coefficient of the second transformer is k2; both the variable gain amplifier module and the power amplifier module include two adaptive bias modules, and the bias state of the power amplifier module is adjusted through the adaptive bias modules, thereby improving the power added efficiency and linearity of the power amplifier module; by simultaneously adjusting the control voltage of the variable gain amplifier module and the gate voltage of the adaptive bias module, the phase change is cancelled.

[0020] In this embodiment, as Figure 1As shown, Vin and Vout represent the input port and the output port respectively; VC is the control voltage for controlling the gain variation; k1 and k2 represent the transformer coupling coefficients, that is, the input matching and inter-stage matching of this circuit are designed using a transformer matching network; Vbias1 - 4 all represent bias voltages, where Vbias1 represents the gate bias of the common-source transistor of the first-stage amplifier (variable gain amplifier module); Vbias2 represents the gate bias of the common-gate transistor of the first-stage amplifier; where Vbias3 represents the gate bias of the common-source transistor of the second-stage amplifier (power amplifier module); Vbias4 represents the gate bias of the common-gate transistor of the second-stage amplifier; In order to obtain higher gain in the millimeter-wave band, a two-stage structure is adopted. The first stage is a variable gain amplifier to achieve gain control; the second stage is a power amplifier to ensure output power and efficiency. The input matching network and the inter-stage matching network are designed using transformers, and the output matching network is designed using a coupled-line balun.

[0021] The PA stage is designed using a Cascode structure, which has higher gain than a common-source amplifier. In the design of the output matching network of the PA, Loadpull technology is used to determine the load impedance seen when the PA reaches its maximum saturated output power, that is, the optimum load impedance (Zopt). Zopt can be approximated as a parallel combination of an optimum resistance (Ropt) and an inductive part. As Figure 2 is a common analysis method for amplifier Load Pull. When parasitic effects are not considered, the optimum output impedance of the amplifier is purely real. However, due to the influence of parasitic capacitance, the amplifier output can be approximated as having a capacitor C in parallel. dev , in this case, in order to achieve better matching, an equivalent inductor is needed to cancel the effect of capacitor C dev . After calculation, its value is 1 / (ω 2 C dev ), and its impedance is jω(1 / (ω 2 C dev )) = -1 / (jωC dev ). At this time, Zopt is approximated as the parallel combination of Ropt and -1 / (jωC dev ). This invention uses Load Pull technology to extract the optimum load impedance of the amplifier to determine the design parameters of the output matching network. The equivalent parallel inductor of the optimum load impedance can be: This is to cancel out the C dev caused by parasitic capacitance in order to obtain the maximum saturated output power; in the design of this invention, R opt is 45 ohms, and C dev is 104 fF.

[0022] The electromagnetic simulation model of the output matching coupled-line balun is asFigure 3 As shown, its coupling coefficient is 0.65, the even-mode impedance is 108 Ω, and the odd-mode impedance is 23 Ω. The output network is further optimized by introducing Cout1 and Cout2. After absorbing C dev into the matching network, the input impedance of the entire network is as Figure 5 shown. It can be seen that the output matching network achieves good broadband performance.

[0023] As Figure 6 shown, the present invention introduces current sources M9 and 10 between the Cascode source and the ground. When the gate voltages of M9 and M10 are low, the PA current is small, the PA is close to being turned off, and the PA power consumption is low; as the gate voltage increases, the current in the Cascode amplifier increases, and the PA can achieve higher output power. From Figure 7 it can be seen that as the gate voltage increases, the maximum value of PAE moves from low power to high power. If the gate voltage is adaptively adjusted according to the input power, the PAE in the low power region will increase, which is equivalent to extracting the envelope of PAE.

[0024] In some embodiments, the circuit structures of the adaptive bias modules in the variable gain amplifier module and the power amplifier module are the same; the adaptive bias module includes an input terminal resistor Rin, an input terminal capacitor Cin, a first resistor R1, a fifteenth MOS transistor M15, a second resistor R2, and a first capacitor C1; the first end of the input terminal resistor Rin is connected to the pre-stage input circuit, and the second end of the input terminal resistor Rin is connected to the first end of the input terminal capacitor Cin; the second end of the input terminal Cin is connected to the first end of the first resistor R1 and the gate of the fifteenth MOS transistor M15; the second end of the first resistor R1 is connected to the gate voltage VG ABM ; the drain of the fifteenth MOS transistor M15 is connected to the power supply VDD ABM , the source of the fifteenth MOS transistor M15 is connected to the first end of the second resistor R2, the first end of the first capacitor C1, and the post-stage output circuit; the second ends of the second resistor R2 and the first capacitor C1 are connected to the ground GND.

[0025] In this embodiment, in order to adaptively adjust the voltage according to the input power, the present invention introduces an adaptive bias module (ABM), and its schematic diagram is as Figure 8 shown. The adaptive bias module can detect the input signal power of the amplifier. As the input signal power increases, M15 gradually enters the on state, and the output voltage gradually increases. Therefore, we obtain a bias voltage that increases with the input signal. By using ABM and current sources M9 and M10, the PAE in the low power region is improved, and the output 1dB compression point is also increased by 3dB.

[0026] In some embodiments, the variable gain amplifier module includes a first neutralization capacitor CC1, a second neutralization capacitor CC2, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M8, a first adaptive bias module ABM1, and a second adaptive bias module ABM2; the second terminal of the first transformer is connected to the ground GND, the third terminal of the first transformer is connected to the input terminal of the first adaptive bias module ABM1, the gate of the third MOS transistor M3, and the first terminal of the second neutralization capacitor CC2, the fourth terminal of the first transformer is connected to the first bias voltage Vbias1, the fifth terminal of the first transformer is connected to the input terminal of the second adaptive bias module ABM2, the gate of the fourth MOS transistor M4, and the first terminal of the first neutralization capacitor CC1; the output terminal of the first adaptive bias module ABM1 is connected to the gate of the first MOS transistor M1; the second terminal of the first neutralization capacitor CC1 is connected to the drain of the third MOS transistor M3, and the sources of the fifth MOS transistor M5 and the seventh MOS transistor M7; the source of the third MOS transistor M3 is connected to the source of the fourth MOS transistor M4, and the drains of the first MOS transistor M1 and the second MOS transistor M2; the drain of the fourth MOS transistor M4 is connected to the second terminal of the second neutralization capacitor CC2, and the sources of the sixth MOS transistor M6 and the eighth MOS transistor M8; the output terminal of the second adaptive bias module ABM2 is connected to the gate of the second MOS transistor M2; the sources of the first MOS transistor M1 and the second MOS transistor M2 are connected to the ground GND; the gate of the seventh MOS transistor M7 is connected to the control voltage VC, and the drain of the seventh MOS transistor M7 is connected to the power supply VDD; the gate of the fifth MOS transistor M5 is connected to the gate of the sixth MOS transistor M6 and the second bias voltage Vbias2, and the drain of the fifth MOS transistor M5 is connected to the first terminal of the second transformer; the drain of the sixth MOS transistor M6 is connected to the third terminal of the second transformer; the gate of the eighth MOS transistor M8 is connected to the control voltage VC, and the drain of the eighth MOS transistor M8 is connected to the power supply VDD.

[0027] In this embodiment, the variable gain stage adopts a Current-steering VGA, which controls the gain by changing the bias voltage of VC. As VC increases, the currents of M7 and M8 increase, while the currents of M5 and M6 decrease, so the gain decreases. However, at the same time, due to the influence of parasitic capacitance, the relative phase shift of the VGA will also increase, which is not desirable in a phased array system. Therefore, we introduce a new gain control method. The same current source and ABM as described above are introduced into the VGA. By reducing the gate voltage of the ABM, the VGA gain decreases, and the relative phase will also decrease accordingly. Reducing the VGA gain can be achieved by increasing VC and reducing the gate voltage of the ABM, but the phase change trends of the two are opposite. Therefore, we can adjust the gate voltages of VC and ABM simultaneously so that their phase changes can cancel each other out, thereby keeping the phase unchanged when controlling the gain.

[0028] In some embodiments, the capacitance values of the first neutralization capacitor CC1 and the second neutralization capacitor CC2 are equal.

[0029] In some embodiments, the power amplifier module includes a third adaptive bias module ABM3, a fourth adaptive bias module ABM4, a third neutralization capacitor CC3, a fourth neutralization capacitor CC4, a ninth MOS transistor M9, a tenth MOS transistor M10, an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, and a fourteenth MOS transistor M14. The second terminal of the second transformer is connected to the power supply VDD. The fourth terminal of the second transformer is connected to the input terminal of the third adaptive bias module ABM3, the first terminal of the fourth neutralization capacitor CC4, and the gate of the eleventh MOS transistor M11. The fifth terminal of the second transformer is connected to the third bias voltage Vbias3. The sixth terminal of the second transformer is connected to the input terminal of the fourth adaptive bias module ABM4, the first terminal of the third neutralization capacitor CC3, and the gate of the twelfth MOS transistor M12. The output terminal of the third adaptive bias module ABM3 is connected to the gate of the ninth MOS transistor M9. The second terminal of the third neutralization capacitor CC3 is connected to the drain of the eleventh MOS transistor M11 and the source of the thirteenth MOS transistor M13. The source of the eleventh MOS transistor M11 is connected to the source of the twelfth MOS transistor M12, and the drains of the ninth MOS transistor M9 and the tenth MOS transistor M10. The drain of the twelfth MOS transistor M12 is connected to the second terminal of the fourth neutralization capacitor CC4 and the source of the fourteenth MOS transistor M14. The output terminal of the fourth adaptive bias module ABM4 is connected to the gate of the tenth MOS transistor M10. The sources of the ninth MOS transistor M9 and the tenth MOS transistor M10 are connected to the ground GND. The drain of the thirteenth MOS transistor is connected to the coupled line output matching network, and the gate of the thirteenth MOS transistor is connected to the gate of the fourteenth MOS transistor and the fourth bias voltage Vbias4. The drain of the fourteenth MOS transistor is connected to the coupled line output matching network. In some embodiments, the capacitance values of the third neutralizing capacitor CC3 and the fourth neutralizing capacitor CC4 are equal.

[0030] In some embodiments, the coupled-line output matching network includes a first coupled line Couple1, a second coupled line Couple2, a first output matching capacitor Cout1, and a second output matching capacitor Cout2; a first end of the first coupled line Couple1 is connected to the drain of the thirteenth MOS transistor, a second end of the first coupled line Couple1 is connected to the power supply VDD, a third end of the first coupled line Couple1 is connected to a first end of the second coupled line Couple2, and a fourth end of the first coupled line Couple1 is connected to first ends of the first output matching capacitor Cout1 and the second output matching capacitor Cout2; a second end of the first output matching capacitor Cout1 is connected to the ground GND; a second end of the second output matching capacitor Cout2 is connected to a subsequent output circuit; a second end of the second coupled line Couple2 is connected to the ground GND, a third end of the second coupled line Couple2 is connected to the drain of the fourteenth MOS transistor, and a fourth end of the second coupled line Couple2 is connected to the power supply VDD.

[0031] The above are only the preferred embodiments of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications, and environments, and can be changed within the scope of the concept described herein through the above teachings or the technology or knowledge in related fields. Any changes and variations made by those skilled in the art without departing from the spirit and scope of the present invention shall fall within the protection scope of the appended claims of the present invention.

Claims

1. A low phase error and high back-off efficiency variable gain power amplifier architecture, characterized by: include: A first transformer, wherein an input end of the first transformer is connected to an external input, and an output end of the first transformer is connected to a variable gain amplifier module; The variable gain amplifier module is connected to the second transformer; The second transformer is connected to the power amplifier module; the power amplifier module is connected to the coupling line output matching network; the coupling line output matching network is connected to the subsequent circuit; the coupling coefficient of the first transformer is k1, and the coupling coefficient of the second transformer is k2; the variable gain amplifier module and the power amplifier module both include two adaptive bias modules, and the bias state of the power amplifier module is adjusted by the adaptive bias module, thereby improving the power added efficiency and linearity of the power amplifier module; by simultaneously adjusting the control voltage of the variable gain amplifier module and the gate voltage of the adaptive bias module, the phase change is offset.

2. The low phase error and high back-off efficiency variable gain power amplifier architecture according to claim 1, characterized in that: The circuit structure of the adaptive bias module in the variable gain amplifier module and the power amplifier module is the same; the adaptive bias module includes an input resistor Rin, an input capacitor Cin, a first resistor R1, a fifteenth MOS tube M15, a second resistor R2, and a first capacitor C1; the first end of the input resistor Rin is connected to the front-stage input circuit, and the second end of the input resistor Rin is connected to the first end of the input capacitor Cin; the second end of the input Cin is connected to the first end of the first resistor R1 and the gate of the fifteenth MOS tube M15; the second end of the first resistor R1 is connected to the gate voltage VG ABM The drain of the fifteenth MOS tube M15 is connected to the power supply VDD ABM The source of the fifteenth MOS tube M15 is connected to the first end of the second resistor R2, the first end of the first capacitor C1 and the subsequent output circuit; the second ends of the second resistor R2 and the first capacitor C1 are connected to the ground GND.

3. The low phase error and high back-off efficiency variable gain power amplifier architecture according to claim 1, characterized in that: The variable gain amplifier module includes a first neutralization capacitor CC1, a second neutralization capacitor CC2, a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a sixth MOS tube M6, a seventh MOS tube M7, an eighth MOS tube M8, a first adaptive bias module ABM1, and a second adaptive bias module ABM2; the second end of the first transformer is connected to the ground GND, the third end of the first transformer is connected to the input end of the first adaptive bias module ABM1, the gate of the third MOS tube M3, and the first end of the second neutralization capacitor CC2, the fourth end of the first transformer is connected to the first bias voltage Vbias1, the fifth end of the first transformer is connected to the input end of the second adaptive bias module ABM2, the gate of the fourth MOS tube M4, and the first end of the first neutralization capacitor CC1; the output end of the first adaptive bias module ABM1 is connected to the gate of the first MOS tube M1; the second end of the first neutralization capacitor CC1 is connected to the drain of the third MOS tube M3, the drain of the first MOS tube M4, and the drain of the second MOS tube M5; the output end of the first adaptive bias module ABM1 is connected to the gate of the first MOS tube M1; the second end of the first neutralization capacitor CC1 is connected to the drain of the third MOS tube M3, the drain of the first MOS tube M4, and the drain of the second MOS tube M5. The source of the fifth MOS tube M5 and the seventh MOS tube M7; the source of the third MOS tube M3 is connected to the source of the fourth MOS tube M4, the drain of the first MOS tube M1 and the second MOS tube M2; the drain of the fourth MOS tube M4 is connected to the second end of the second neutralization capacitor CC2, the source of the sixth MOS tube M6 and the source of the eighth MOS tube M8; the output end of the second adaptive bias module ABM2 is connected to the gate of the second MOS tube M2; the source of the first MOS tube M1 and the second MOS tube M2 is connected to the ground GND; the gate of the seventh MOS tube M7 is connected to the control voltage VC, and the drain of the seventh MOS tube M7 is connected to the power supply VDD; the gate of the fifth MOS tube M5 is connected to the gate of the sixth MOS tube M6 and the second bias voltage Vbias2, and the drain of the fifth MOS tube M5 is connected to the first end of the second transformer; the drain of the sixth MOS tube M6 is connected to the third end of the second transformer; the gate of the eighth MOS tube M8 is connected to the control voltage VC, and the drain of the eighth MOS tube M8 is connected to the power supply VDD.

4. The low phase error and high back-off efficiency variable gain power amplifier architecture according to claim 3, characterized in that: The capacitance values ​​of the first neutralization capacitor CC1 and the second neutralization capacitor CC2 are equal.

5. The low phase error and high back-off efficiency variable gain power amplifier architecture according to claim 1, characterized in that: The power amplifier module includes a third adaptive bias module ABM3, a fourth adaptive bias module ABM4, a third neutralization capacitor CC3, a fourth neutralization capacitor CC4, a ninth MOS tube M9, a tenth MOS tube M10, an eleventh MOS tube M11, a twelfth MOS tube M12, a thirteenth MOS tube M13, and a fourteenth MOS tube M14; the second end of the second transformer is connected to the power supply VDD, the fourth end of the second transformer is connected to the input end of the third adaptive bias module ABM3, the first end of the fourth neutralization capacitor CC4, and the gate of the eleventh MOS tube M11, the fifth end of the second transformer is connected to the third bias voltage Vbias3, and the sixth end of the second transformer is connected to the input end of the fourth adaptive bias module ABM4, the first end of the third neutralization capacitor CC3, and the gate of the twelfth MOS tube M12; the output end of the third adaptive bias module ABM3 is connected to the first voltage Vbias2. The gate of the ninth MOS tube M9; the second end of the third neutralization capacitor CC3 is connected to the drain of the eleventh MOS tube M11 and the source of the thirteenth MOS tube M13; the source of the eleventh MOS tube M11 is connected to the source of the twelfth MOS tube M12, the drains of the ninth MOS tube M9 and the tenth MOS tube M10; the drain of the twelfth MOS tube M12 is connected to the second end of the fourth neutralization capacitor CC4 and the source of the fourteenth MOS tube M14; the output end of the fourth adaptive bias module ABM4 is connected to the gate of the tenth MOS tube M10; the sources of the ninth MOS tube M9 and the tenth MOS tube M10 are connected to the ground GND; the drain of the thirteenth MOS tube is connected to the coupling line output matching network, and the gate of the thirteenth MOS tube is connected to the gate of the fourteenth MOS tube and the fourth bias voltage Vbias4; the drain of the fourteenth MOS tube is connected to the coupling line output matching network.

6. The low phase error and high back-off efficiency variable gain power amplifier architecture according to claim 5, characterized in that: The capacitance values ​​of the third neutralization capacitor CC3 and the fourth neutralization capacitor CC4 are equal.

7. The low phase error and high back-off efficiency variable gain power amplifier architecture according to claim 5, characterized in that: The coupled line output matching network includes a first coupled line Couple1, a second coupled line Couple2, a first output matching capacitor Cout1 and a second output matching capacitor Cout2; a first end of the first coupled line Couple1 is connected to the drain of the thirteenth MOS tube, a second end of the first coupled line Couple1 is connected to the power supply VDD, a third end of the first coupled line Couple1 is connected to the first end of the second coupled line Couple2, and a fourth end of the first coupled line Couple1 is connected to the first end of the first output matching capacitor Cout1 and the first end of the second output matching capacitor Cout2; a second end of the first output matching capacitor Cout1 is connected to the ground GND; a second end of the second output matching capacitor Cout2 is connected to the post-stage output circuit; a second end of the second coupled line Couple2 is connected to the ground GND, a third end of the second coupled line Couple2 is connected to the drain of the fourteenth MOS tube, and a fourth end of the second coupled line Couple2 is connected to the power supply VDD.

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