A high-efficiency high-linearity power amplifier with adaptive bias circuit

Abstract

The application discloses a high-efficiency high-linearity power amplifier with an adaptive bias circuit. The application realizes the technical scheme as follows: the high-efficiency high-linearity power amplifier with the adaptive bias circuit comprises a voltage reference source circuit, an adaptive bias circuit and a power amplifier. The adaptive bias circuit is used to provide a dynamically adjusted bias voltage for the power amplifier according to the input signal, so that the power amplifier can realize relatively constant gain under different power supply voltages, the problem of gain compression of the power amplifier under low-power-consumption bias voltage when the input power increases is relieved, and the linearity and power-added efficiency of the low-power-consumption power amplifier are greatly improved. The application relates to a power amplifier in a radio frequency receiver in the field of wireless communication, and particularly relates to a high-efficiency high-linearity power amplifier with an adaptive bias circuit based on a CMOS process.

Description

Technical Field

[0001] The present invention relates to a power amplifier in a radio frequency receiver in the field of wireless communications, and in particular to a high-efficiency and high-linearity power amplifier with an adaptive bias circuit based on a CMOS process. Background Art

[0002] Radio Frequency (RF), commonly abbreviated as RF, refers to electromagnetic frequencies radiated into space, ranging from 300 kHz to 30 GHz. RF, short for radio frequency electromagnetic waves, is a type of high-frequency alternating current electromagnetic wave. RF signals, like the concept of radio frequency, are modulated electromagnetic waves with a specific transmission frequency. RF power amplifiers (RFPAs) are core components in wireless communication systems, responsible for amplifying RF signals to sufficient power levels to ensure long-distance, high-quality transmission. They play a crucial role in equipment such as base stations, radar, satellite communications, and radio transmitters. RF power amplifiers precisely control the signal's gain and phase, boosting weak RF signals to a level that allows them to penetrate the atmosphere and overcome path loss. Their design requires a balance of high efficiency, linearity, and stability to maintain excellent performance in complex and changing communication environments. RF power amplifiers are crucial for achieving long-distance, high-speed, and high-quality communication in wireless communication systems. Their technological advancements continue to push the boundaries of wireless technology, providing strong support for the informatization of modern society.

[0003] The 1dB gain compression point (GCP) is a key parameter that describes the nonlinear characteristics of an amplifier. When an amplifier is operating normally and before saturation, its output power increases linearly with input power. However, when the input power increases to a certain level, the rate of increase in output power slows due to the amplifier's nonlinear effects, and the gain begins to decrease. The 1dB compression point is the point at which the input and output power change by only 1dB when the input power changes by 2dB. This point marks the beginning of the amplifier's nonlinearity and is a key indicator for evaluating an amplifier's linearity and dynamic range.

[0004] PAE, or Power Added Efficiency, is defined as the difference between the RF power output of a power amplifier and its DC input power, divided by the DC input power. It is usually expressed as a percentage. PAE reflects the power amplifier's ability to convert DC input power into RF power. Ideally, all DC power supplied to the amplifier should be converted to RF output power. However, in reality, due to factors such as the amplifier's internal resistance and transistor nonlinearities, some DC power is lost as heat. Therefore, PAE is a key indicator of amplifier performance.

[0005] The CMOS process, short for complementary metal oxide semiconductor (CMOS), combines N-type MOS transistors (NMOS) and P-type MOS transistors (PMOS) on the same silicon substrate. It is a mainstream integrated circuit manufacturing process developed from the PMOS and NMOS processes. The CMOS process offers advantages such as high integration and design flexibility, making it widely used in portable electronic devices, high-performance computing, communications technology, and the Internet of Things. CMOS processes can integrate devices such as MOS transistors, bipolar junction transistors (BJTs), polysilicon resistors, metal capacitors, and metal inductors.

[0006] In traditional CMOS power amplifier designs, there are three main approaches to implementing bias circuits. The first approach uses an off-chip circuit to provide bias voltage for each amplifier gate. This approach has the following drawbacks: 1. The off-chip circuit must provide precise bias voltages, which increases product cost and reduces integration. 2. While the bias voltage is constant, the threshold voltage and mobility of the amplifiers vary with temperature, degrading amplifier gain and linearity. 3. The bias voltage provided to the gates of each amplifier cannot be dynamically adjusted to accommodate changes in the input signal. The second approach uses resistors to divide the supply voltage or current mirrors with resistive loads to provide bias voltage for each amplifier gate. This approach has the following drawbacks: 1. To obtain a precise bias voltage, a precise off-chip supply voltage is required. 2. While the supply voltage is constant, the threshold voltage and mobility of the amplifiers vary with temperature, degrading amplifier gain and linearity. 3. The bias voltage provided to the gates of each amplifier cannot be dynamically adjusted to accommodate changes in the input signal. The third method is to use an on-chip reference circuit to provide a reference voltage, which provides a bias voltage for the gate of the CMOS amplifier tube that is independent of the power supply voltage. There is no need to provide a precise power supply voltage outside the chip. Its disadvantage is that the bias voltage provided for the gate of the amplifier tube cannot be dynamically adjusted as the input signal changes. In particular, when the CMOS amplifier tube biases the gate at a lower bias voltage to improve efficiency, the gain of the amplifier will slowly compress as the input signal increases.

[0007] To prevent the amplifier's gain from slowly compressing as the input signal increases, the traditional approach is to directly increase the bias voltage of the CMOS transistors. However, this significantly increases the amplifier's power consumption and reduces its PAE efficiency. Therefore, designing an adaptive bias circuit for a high-linearity power amplifier in applications where the input signal power varies significantly is a major challenge in RFIC design. Summary of the Invention

[0008] The purpose of the present invention is to address the shortcomings of the existing technology and provide an on-chip fully integrated adaptive bias circuit for high-efficiency and high-linearity power amplifiers, which can provide a bias voltage for the power amplifier gate that is independent of the power supply voltage and dynamically adjusted with changes in the input signal.

[0009] To achieve the above objectives, the present invention employs the following technical solution: a high-efficiency, high-linearity power amplifier with an adaptive bias circuit, comprising: a voltage reference source circuit 1, an adaptive bias circuit 1, and a power amplifier 1. The bias voltage reference source circuit 1 provides a reference voltage Vref1 for the adaptive bias circuit 1 that is independent of the power supply voltage; the adaptive bias circuit 1 senses changes in the input signal amplitude and generates a bias voltage Vb1 that is dynamically adjusted in response to changes in the input signal.

[0010] Compared to the prior art, the present invention has the following advantages: All circuits and devices involved in the present invention can be implemented on a CMOS process chip, resulting in a small size, light weight, and low cost. A bias voltage reference source circuit is used to provide a reference voltage independent of the power supply voltage to the gate of the amplifier tube. When the input signal amplitude is low, this ensures that the NMOS amplifier tube of the power amplifier maintains a relatively constant transconductance, thereby achieving a power amplifier with relatively constant gain. An adaptive bias circuit is used to provide the power amplifier with a bias voltage that dynamically adjusts with changes in the input signal, alleviating the problem of gain compression that occurs when the input power increases in the power amplifier under low-power bias voltage, significantly improving the linearity and power-added efficiency of the low-power power amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a schematic diagram of the principle of a traditional power amplifier with a constant transconductance voltage reference source;

[0012] Figure 2 This is a block diagram of a high-efficiency and high-linearity power amplifier system with an adaptive bias circuit according to the present invention;

[0013] Figure 3 This is a schematic diagram of the principle of a high-efficiency and high-linearity power amplifier with an adaptive bias circuit of the present invention;

[0014] Figure 4 yesFigure 3 Principle diagram of voltage reference source circuit 2;

[0015] Figure 5 is Figure 3 Principle diagram of voltage reference source circuit 3;

[0016] Figure 6 is Figure 3 Principle diagram of operational transconductance amplifier OTA1;

[0017] Figure 7 is the application and Figure 1 Simulation result comparison of DC bias voltage of power amplifier 1a in case of gradually increasing input RF signal;

[0018] Figure 8 is the application and Figure 1 Simulation result comparison of gain compression characteristic of RF amplifier 1a in case of gradually increasing input RF signal;

[0019] Figure 9 is the application and Figure 1 Simulation result comparison of power added efficiency of RF amplifier 1a in case of gradually increasing input RF signal. DETAILED DESCRIPTION

[0020] Referring to Figure 2 In one preferred embodiment of the following embodiment description, the high-efficiency high-linearity power amplifier with adaptive bias circuit comprises: voltage reference source circuit 1, adaptive bias circuit 1 and power amplifier 1 connected in parallel between common terminal GND and power supply terminal VDD. The reference voltage Vref1 output terminal of the voltage reference source circuit 1 is connected with the reference voltage Vref1 input terminal of the adaptive bias circuit 1; the bias voltage Vb1 output terminal of the adaptive bias circuit 1 is connected with the bias voltage Vb1 input terminal of the power amplifier 1; the induced signal AC voltage Va1 input terminal of the adaptive bias circuit 1 is connected with the induced signal AC voltage Va1 output terminal of the power amplifier 1.

[0021] Referring to Figure 3The voltage reference source circuit 1 comprises NMOS NM3, NMOS NM4, NMOS NM5, PMOS PM1, PMOS PM2, PMOS PM3, resistor R2, and reference voltage Vref1 output end of the voltage reference source circuit 1. The gate of PMOS PM1 is connected with the gate of PMOS PM2, the drain of PMOS PM2, the gate of PMOS PM3, and the drain of NMOS NM4; the drain of PMOS PM1 is connected with the drain of NMOS NM3, and the gate of NMOS NM3; the source of PMOS PM1 is connected with power supply end VDD; the gate of PMOS PM2 is connected with the drain of PMOS PM2, the gate of PMOS PM1, and the gate of PMOS PM3; the source of PMOS PM2 is connected with power supply end VDD; the gate of PMOS PM3 is connected with the gate of PMOS PM2, the drain of PMOS PM2, and the gate of PMOS PM1; the drain of PMOS PM3 is connected with the drain of NMOS NM5, the gate of NMOS NM5, and the reference voltage Vref1 output end of the voltage reference source circuit 1; the source of PMOS PM3 is connected with power supply end VDD; the gate of NMOS NM3 is connected with the drain of NMOS NM3, the drain of PMOS PM1, and the gate of NMOS NM4; the source of NMOS NM3 is connected with common end GND; the gate of NMOS NM4 is connected with the drain of NMOS NM3, the drain of PMOS PM1, and the gate of NMOS NM4; the gate of PMOS PM2 is connected with the drain of PMOS PM2, the gate of PMOS PM1, and the gate of PMOS PM3; the drain of NMOS NM4 is connected with the gate of PMOS PM2, the drain of PMOS PM2, the gate of PMOS PM3, and the gate of PMOS PM1; the source of NMOS NM4 is connected with one end of resistor R2; one end of resistor R2 is connected with the source of NMOS NM4, and the other end of resistor R2 is connected with common end GND; the gate of NMOS NM5 is connected with the drain of NMOS NM5, the drain of PMOS PM3, and the reference voltage Vref1 output end of the voltage reference source circuit 1; the source of NMOS NM5 is connected with common end GND.

[0022] The voltage reference source circuit 1 comprises PMOS PM1, PM2, and PM3 with their gates connected back to back, and their sources connected to power supply end VDD. Transistors PM1, PM2, and PM3 are of the same size and form a current mirror, which forces the currents flowing through the drains of NMOS NM3, NM4, and NM5 to be equal.

[0023] Reference is made to Figure 3The power amplifier comprises NMOS NM1, NMOS NM2, inductor L1, capacitor C1, capacitor C2, capacitor C3, resistor R1, radio frequency signal input end RFin1, radio frequency signal output end RFout1, bias voltage Vb1 input end of the power amplifier, and induced signal alternating voltage Va1 output end of the power amplifier. The drain of NMOS NM1 is connected with the source of NMOS NM2, the gate of NMOS NM1 is connected with one end of resistor R1, one end of capacitor C1, and one end of capacitor C3, and the source of NMOS NM1 is connected to common end GND; the drain of NMOS NM2 is connected with one end of inductor L1 and one end of capacitor C2, the gate of NMOS NM1 is connected to power supply end VDD, and the source of NMOS NM2 is connected with the drain of NMOS NM1; one end of inductor L1 is connected with the drain of NMOS NM2, and the other end of inductor L1 is connected with power supply end VDD; one end of capacitor C2 is connected with the drain of NMOS NM2 and one end of inductor L1, and the other end of capacitor C2 is connected with radio frequency signal output end RFout1 through output stage matching network 1; one end of capacitor C1 is connected with the gate of NMOS NM1, one end of resistor R1, and one end of capacitor C3, and the other end of capacitor C1 is connected with radio frequency signal input end RFin1 through input stage matching network 1; one end of resistor R1 is connected with the gate of NMOS NM1, one end of capacitor C1, and one end of capacitor C3, and the other end of resistor R1 is connected with bias voltage Vb1 input end of the power amplifier; one end of capacitor C3 is connected with the gate of NMOS NM1, one end of capacitor C1, and one end of resistor R1, and the other end of capacitor C3 is connected with induced signal alternating voltage Va1 output end of the power amplifier.

[0024] Referring to Figure 4The voltage reference source circuit 2 comprises a BJT tube Q1, a PMOS tube PM4, a resistor R7, a resistor R8, an induced signal alternating voltage Va2 input end of the voltage reference source circuit 2, and a reference voltage Vref2 output end of the voltage reference source circuit 2. The collector of the BJT tube Q1 is connected to the base of the BJT tube Q1, the gate of the PMOS tube PM4, one end of the resistor R8, and the induced signal alternating voltage Va2 input end of the voltage reference source circuit 2, and the emitter of the BJT tube Q1 is connected to the common end GND; the gate of the PMOS tube PM4 is connected to the base of the BJT tube Q1, the collector of the BJT tube Q1, one end of the resistor R8, and the induced signal alternating voltage Va2 input end of the voltage reference source circuit 2, the source of the PMOS tube PM4 is connected to the power supply end VDD, and the drain of the PMOS tube PM4 is connected to one end of the resistor R7 and the reference voltage Vref2 output end of the voltage reference source circuit 2; one end of the resistor R8 is connected to the base of the BJT tube Q1, the gate of the PMOS tube PM4, the collector of the BJT tube Q1, and the induced signal alternating voltage Va2 input end of the voltage reference source circuit 2, and the other end of the resistor R8 is connected to the power supply end VDD; one end of the resistor R7 is connected to the drain of the PMOS tube PM4 and the reference voltage Vref2 output end of the voltage reference source circuit 2, and the other end of the resistor R7 is connected to the common end GND.

[0025] The induced signal alternating voltage Va2 input end of the voltage reference source circuit 2 is connected to the induced signal alternating voltage Va1 input end of the adaptive bias circuit, can receive the radio frequency alternating signal coupled by the capacitor C1 from the power amplifier input end, and is connected to the BJT tube Q1 adopting the diode connection (the base and the collector are short-circuited). When the radio frequency alternating signal gradually increases, the direct current voltage of Va2 decreases, the direct current gate-source voltage of the PMOS tube PM4 increases, the drain-source current of the PMOS tube PM4 increases in turn, the current flowing through the resistor R7 increases, and finally the direct current voltage of Vref2 increases.

[0026] Referring to Figure 5The voltage reference source circuit 3 includes a BJT transistor Q2 , a PMOS transistor PM5 , a resistor R9 , a resistor R10 , and a reference voltage Vref3 output terminal of the voltage reference source circuit 3 . The collector of the BJT transistor Q2 is connected to the base of the BJT transistor Q2, the gate of the PMOS transistor PM5, and one end of the resistor R10, and the emitter of the BJT transistor Q2 is connected to the common terminal GND; the gate of the PMOS transistor PM5 is connected to the base of the BJT transistor Q2, the collector of the BJT transistor Q2, and one end of the resistor R10; the source of the PMOS transistor PM5 is connected to the power supply terminal VDD; the drain of the PMOS transistor PM5 is connected to one end of the resistor R9 and the output end of the reference voltage Vref3 of the voltage reference source circuit 3; one end of the resistor R10 is connected to the base of the BJT transistor Q2, the gate of the PMOS transistor PM5, and the collector of the BJT transistor Q2, and the other end of the resistor R10 is connected to the power supply terminal VDD; one end of the resistor R9 is connected to the drain of the PMOS transistor PM5 and the output end of the reference voltage Vref3 of the voltage reference source circuit 3, and the other end of the resistor R9 is connected to the common terminal GND.

[0027] The voltage reference source circuit 3 has a BJT transistor Q2 of the same size as the BJT transistor Q1 in the voltage reference source circuit 2, a PMOS transistor PM5 of the same size as the PMOS transistor PM4 in the voltage reference source circuit 2, a resistor R9 of the same size as the resistor R7 in the voltage reference source circuit 2, and a resistor R10 of the same size as the resistor R8 in the voltage reference source circuit 2. The value of the reference voltage Vref3 output by the voltage reference source circuit 3 is the same as the value of the reference voltage Vref2 output by the voltage reference source circuit 2 when the RF AC signal is weak.

[0028] See Figure 6The operational transconductance amplifier OTA1 includes NMOS NM8, NMOS NM9, NMOS NM10, NMOS NM11, NMOS NM12, NMOS NM13, NMOS NM14, PMOS PM6, PMOS PM7, PMOS PM8, PMOS PM9, PMOS PM10, PMOS PM11, PMOS PM12, PMOS PM13, PMOS PM14, PMOS PM15, PMOS PM16, PMOS PM17, PMOS PM18, PMOS PM19, resistor R11, input positive end IN1+ of the operational transconductance amplifier OTA1, input negative end IN1- of the operational transconductance amplifier OTA1, and output end OUT1 of the operational transconductance amplifier OTA1. The drain of the NMOS NM8 is connected to the source of the NMOS NM10 and the drain of the PMOS PM19. The gate of the NMOS NM8 is connected to the gate of the NMOS NM9, the gate of the NMOS NM13, the source of the NMOS NM12, the gate of the NMOS NM14, and the drain of the NMOS NM14. The source of the NMOS NM8 is connected to the common end GND. The drain of the NMOS NM9 is connected to the source of the NMOS NM11 and the drain of the PMOS PM18. The gate of the NMOS NM9 is connected to the gate of the NMOS NM8, the gate of the NMOS NM13, the source of the NMOS NM12, the gate of the NMOS NM14, and the drain of the NMOS NM14. The source of the NMOS NM9 is connected to the common end GND. The drain of the NMOS NM10 is connected to the drain of the PMOS PM8, the gate of the PMOS PM6, and the gate of the PMOS PM7. The gate of the NMOS NM10 is connected to the gate of the NMOS NM11, the gate of the NMOS NM12, and the drain of the NMOS NM12. The source of the NMOS NM10 is connected to the drain of the NMOS NM8 and the drain of the PMOS PM19. The drain of the NMOS NM11 is connected to the drain of the PMOS PM9 and the output end OUT1 of the operational transconductance amplifier OTA1. The gate of the NMOS NM11 is connected to the gate of the NMOS NM10, the gate of the NMOS NM12, and the drain of the NMOS NM12. The source of the NMOS NM11 is connected to the drain of the NMOS NM9 and the drain of the PMOS PM18.The drain of the NMOS transistor NM12 is connected to the gate of the NMOS transistor NM12, the gate of the NMOS transistor NM10, the drain of the PMOS transistor PM11, and the gate of the NMOS transistor NM11, and the source of the NMOS transistor NM12 is connected to the gate of the NMOS transistor NM8, the gate of the NMOS transistor NM13, the gate of the NMOS transistor NM9, the gate of the NMOS transistor NM14, and the drain of the NMOS transistor NM14; the drain of the NMOS transistor NM13 is connected to the gate of the PMOS transistor PM15, the drain of the PMOS transistor PM15, and the gate of the PMOS transistor PM17, the gate of the NMOS transistor NM13 is connected to the gate of the NMOS transistor NM8, the source of the NMOS transistor NM12, the gate of the NMOS transistor NM9, the gate of the NMOS transistor NM14, and the drain of the NMOS transistor NM14, and the source of the NMOS transistor NM13 is connected to the common terminal GND; the drain of the NMOS transistor NM14 is connected to the gate of the NMOS transistor NM14, the gate of the NMOS transistor NM8, the source of the NMOS transistor NM12, the gate of the NMOS transistor NM9, and the gate of the NMOS transistor NM13, and the source of the NMOS transistor NM14 is connected to the common terminal GND; the drain of the PMOS transistor PM6 is connected to the source of the PMOS transistor PM8, the gate of the PMOS transistor PM6 is connected to the drain of the PMOS transistor PM8, the drain of the NMOS transistor NM10, and the gate of the PMOS transistor PM7, and the source of the PMOS transistor PM6 is connected to the power terminal VDD; the drain of the PMOS transistor PM7 is connected to the source of the PMOS transistor PM9, the gate of the PMOS transistor PM7 is connected to the drain of the PMOS transistor PM8, the drain of the NMOS transistor NM10, and the gate of the PMOS transistor PM6, and the source of the PMOS transistor PM7 is connected to the power terminal VDD; the drain of the PMOS transistor PM8 is connected to the gate of the PMOS transistor PM7, the drain of the NMOS transistor NM10, and the gate of the PMOS transistor PM6, the gate of the PMOS transistor PM8 is connected to the gate of the PMOS transistor PM9, the drain of the PMOS transistor PM16, and the source of the PMOS transistor PM17, and the source of the PMOS transistor PM8 is connected to the drain of the PMOS transistor PM6; the drain of the PMOS transistor PM9 is connected to the drain of the NMOS transistor NM11 and the gate of the PMOS transistor PM6, the gate of the PMOS transistor PM9 is connected to the gate of the PMOS transistor PM8, the drain of the PMOS transistor PM16, and the source of the PMOS transistor PM17, and the source of the PMOS transistor PM8 is connected to the drain of the PMOS transistor PM6.The drain of the PMOS transistor PM10 is connected with the source of the PMOS transistor PM18 and the source of the PMOS transistor PM19, the gate of the PMOS transistor PM10 is connected with the gate of the PMOS transistor PM11, the source of the PMOS transistor PM13, the gate of the PMOS transistor PM12 and the drain of the PMOS transistor PM12, the source of the PMOS transistor PM10 is connected to the power supply terminal VDD; the drain of the PMOS transistor PM11 is connected with the gate of the NMOS transistor NM12, the gate of the NMOS transistor NM10, the drain of the NMOS transistor NM12 and the gate of the NMOS transistor NM11, the gate of the PMOS transistor PM11 is connected with the gate of the PMOS transistor PM10, the source of the PMOS transistor PM13, the gate of the PMOS transistor PM12 and the drain of the PMOS transistor PM12, the source of the PMOS transistor PM11 is connected to the power supply terminal VDD; the drain of the PMOS transistor PM12 is connected with the gate of the PMOS transistor PM12, the source of the PMOS transistor PM13, the gate of the PMOS transistor PM10 and the gate of the PMOS transistor PM11, the source of the PMOS transistor PM12 is connected to the power supply terminal VDD; the drain of the PMOS transistor PM13 is connected with the gate of the PMOS transistor PM13 and one end of the resistor R11, the source of the PMOS transistor PM13 is connected with the gate of the PMOS transistor PM12, the drain of the PMOS transistor PM12, the gate of the PMOS transistor PM10 and the gate of the PMOS transistor PM11; the drain of the PMOS transistor PM14 is connected with the gate of the PMOS transistor PM14, the source of the PMOS transistor PM15 and the gate of the PMOS transistor PM16, the source of the PMOS transistor PM14 is connected to the power supply terminal VDD; the drain of the PMOS transistor PM15 is connected with the gate of the PMOS transistor PM15, the gate of the PMOS transistor PM17 and the drain of the NMOS transistor NM13, the source of the PMOS transistor PM15 is connected with the gate of the PMOS transistor PM14, the drain of the PMOS transistor PM14 and the gate of the PMOS transistor PM16; the drain of the PMOS transistor PM16 is connected with the gate of the PMOS transistor PM9, the gate of the PMOS transistor PM8 and the source of the PMOS transistor PM17, the gate of the PMOS transistor PM16 is connected with the gate of the PMOS transistor PM14, the source of the PMOS transistor PM15 and the drain of the PMOS transistor PM14, the source of the PMOS transistor PM16 is connected to the power supply terminal VDD; the drain of the PMOS transistor PM17 is connected to the common terminal GND, the gate of the PMOS transistor PM17 is connected with the gate of the PMOS transistor PM15, the drain of the PMOS transistor PM15 and the drain of the NMOS transistor NM13, the source of the PMOS transistor PM17 is connected with the gate of the PMOS transistor PM9, the gate of the PMOS transistor PM8 and the drain of the PMOS transistor PM16.The drain of the PMOS transistor PM18 is connected with the drain of the NMOS transistor NM9 and the source of the NMOS transistor NM11, the gate of the PMOS transistor PM18 is connected with the negative input IN1- of the operational transconductance amplifier OTA1, and the source of the PMOS transistor PM18 is connected with the drain of the PMOS transistor PM10 and the source of the PMOS transistor PM19; the drain of the PMOS transistor PM19 is connected with the drain of the NMOS transistor NM8 and the source of the NMOS transistor NM10, the gate of the PMOS transistor PM19 is connected with the positive input IN1+ of the operational transconductance amplifier OTA1, and the source of the PMOS transistor PM19 is connected with the drain of the PMOS transistor PM10 and the source of the PMOS transistor PM18; one end of the resistor R11 is connected with the gate and the drain of the PMOS transistor PM13, and the other end of the resistor R11 is connected to the common terminal GND.

[0029] Referring to Figure 3 The adaptive bias circuit 1 comprises the voltage reference source circuit 2, the voltage reference source circuit 3, the operational transconductance amplifier OTA1 and the NMOS transistor NM6, the resistor R3, the resistor R4, the resistor R5, the resistor R6, the sensing signal AC voltage Va1 input terminal of the adaptive bias circuit 1 and the bias voltage Vb1 output terminal of the adaptive bias circuit 1, which are connected in parallel between the common terminal GND and the power supply terminal VDD. The gate of the NMOS transistor NM6 is connected with the output terminal OUT1 of the operational transconductance amplifier OTA1, the drain of the NMOS transistor NM6 is connected to the power supply terminal VDD, and the source of the NMOS transistor NM6 is connected with one end of the resistor R5 and the bias voltage Vb1 output terminal of the adaptive bias circuit 1; one end of the resistor R5 is connected with the source of the NMOS transistor NM6 and the bias voltage Vb1 output terminal of the adaptive bias circuit 1, and the other end of the resistor R5 is connected with one end of the resistor R6 and the negative input IN1- of the operational transconductance amplifier OTA1; one end of the resistor R6 is connected with the other end of the resistor R5 and the negative input IN1- of the operational transconductance amplifier OTA1, and the other end of the resistor R6 is connected with the reference voltage Vref3 output terminal of the voltage reference source circuit 3; one end of the resistor R3 is connected with the positive input IN1+ of the operational transconductance amplifier OTA1 and one end of the resistor R4, and the other end of the resistor R3 is connected with the reference voltage Vref2 output terminal of the voltage reference source circuit 2; one end of the resistor R4 is connected with the positive input IN1+ of the operational transconductance amplifier OTA1 and one end of the resistor R3, and the other end of the resistor R4 is connected with the reference voltage Vref1 output terminal of the voltage reference source circuit 1; the sensing signal AC voltage Va2 input terminal of the voltage reference source circuit 2 is connected with the sensing signal AC voltage Va1 input terminal of the adaptive bias circuit 1.

[0030] In the adaptive bias circuit 1, resistors R3 and R4 are equal in size, and resistors R5 and R6 are equal in size. Through the feedback loop formed by the operational transconductance amplifier OTA1, the NMOS transistor NM6, and the resistors R3, R4, R5, and R6, the bias voltage Vb1, the reference voltage Vref1, the reference voltage Vref2, and the reference voltage Vref3 have the following relationship: Vb1 = Vref1 + Vref2 - Vref3.

[0031] The operating mechanism of the adaptive bias circuit 1 is as follows: when the RF input signal is low, the bias voltage Vb1 is equivalent to the reference voltage Vref1 provided by the voltage reference source circuit 1; as the RF input signal gradually increases, the reference voltage Vref2 output by the reference source circuit 2 increases accordingly, while the reference voltage Vref3 output by the reference source circuit 3 remains at the level before Vref2 increases; by implementing Vref2-Vref3 through an operational amplifier, a voltage positively correlated with the RF input signal is obtained; when the RF input signal is at a low level, Vref2-Vref3=0; finally, through the operational amplifier, (Vref2-Vref3) is superimposed on the reference voltage Vref1 provided by the voltage reference source circuit 1.

[0032] Based on the above circuit structure, the operating mechanism of the high-efficiency, high-linearity power amplifier with an adaptive bias circuit of the present invention is as follows: when the RF input signal is small, the adaptive bias circuit provides a bias voltage Vb1 equal to the reference voltage Vref1 to the gate of the NMOS amplifier tube NM1 of the power amplifier 1, which can ensure that the NMOS amplifier tube NM1 of the power amplifier maintains a relatively constant transconductance when the power supply voltage fluctuates, thereby realizing a power amplifier with a relatively constant gain; when the RF input signal gradually increases, the adaptive bias circuit provides a bias voltage Vb1 gradually increasing to the gate of the NMOS amplifier tube NM1 of the power amplifier 1, thereby increasing the gate-source voltage and drain-source current of the NMOS amplifier tube NM1, alleviating the gain compression that occurs when the input power increases under low-power bias voltage, and improving the 1dB compression point of the power amplifier.

[0033] See Figure 7 In order to verify the above mechanism, the present invention and Figure 1 The bias voltage of the medium power amplifier 1a was simulated and compared. When the input RF signal gradually increased, the DC bias voltage Vb1 gradually increased, while the DC bias voltage Vb1a slightly decreased.

[0034] See Figure 8 In order to verify the improvement of linearity performance of the present invention, the present invention and Figure 1The simulation comparison of gain compression of the middle power amplifier 1a is carried out. The gain Gain1 of the power amplifier 1a is compressed when the input radio frequency signal is greater than -30dBm, the input 1dB compression point is -15dBm, and the output 1dB compression point is 5dBm; the gain Gain2 of the radio frequency amplifier 1 is compressed when the input radio frequency signal is greater than -10dBm, the input 1dB compression point is -8dBm, and the output 1dB compression point is 12dBm.

[0035] Reference is made to Figure 9 In order to verify the improvement of the power additional efficiency of the present application, the simulation comparison of the power additional efficiency of the present application and Figure 1 The simulation comparison of the power additional efficiency of the present application and the middle power amplifier 1a is carried out. The power additional efficiency PAE1 of the power amplifier 1a at the input 1dB compression point (-15dBm) is 11.6%; the power additional efficiency PAE2 of the radio frequency amplifier 1 at the input 1dB compression point (-8dBm) is 22.1%; the power additional efficiency PAE2 of the radio frequency amplifier 1 at the input power backoff to -15dBm is 12.2%, which is still greater than the power additional efficiency PAE1 (11.6%) of the power amplifier 1a at the same input power.

[0036] In summary, the adaptive bias circuit is used to provide a bias voltage for the power amplifier which is dynamically adjusted according to the input signal, which guarantees the relatively constant gain of the power amplifier under different power supply voltages, alleviates the gain compression problem of the power amplifier under low power consumption bias voltage when the input power increases, and greatly improves the linearity and power additional efficiency of the low power consumption power amplifier.

[0037] Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. The scope of the application is not intended to be limited to the described specific embodiments. Any alternatives to these described specific embodiments which fall within the general principles defined herein are to be regarded as falling within the scope of the application.

Claims

1. A high-efficiency, high-linearity power amplifier with an adaptive bias circuit, characterized by: It includes a voltage reference source circuit 1, an adaptive bias circuit 1 and a power amplifier 1 connected in parallel between a common terminal GND and a power supply terminal VDD; The reference voltage Vref1 output terminal of the voltage reference source circuit 1 is connected to the reference voltage Vref1 input terminal of the adaptive bias circuit 1; The bias voltage Vb1 output terminal of the adaptive bias circuit 1 is connected to the bias voltage Vb1 input terminal of the power amplifier 1; The sensing signal AC voltage Va1 input terminal of the adaptive bias circuit 1 is connected to the sensing signal AC voltage Va1 output terminal of the power amplifier 1; When the RF input signal is small, the bias voltage Vb1 is equivalent to the reference voltage Vref1 provided by the voltage reference source circuit 1; when the input RF signal is large, the DC bias voltage Vb1 gradually increases; The gate of the NMOS transistor NM6 is connected to the output terminal OUT1 of the operational transconductance amplifier OTA1, the drain of the NMOS transistor NM6 is connected to the power supply terminal VDD, and the source of the NMOS transistor NM6 is connected to one end of the resistor R5 and the bias voltage Vb1 output terminal of the adaptive bias circuit 1; One end of the resistor R5 is connected to the source of the NMOS transistor NM6 and the bias voltage Vb1 output terminal of the adaptive bias circuit 1, and the other end of the resistor R5 is connected to one end of the resistor R6 and the negative input terminal IN1- of the operational transconductance amplifier OTA1; One end of the resistor R6 is connected to the other end of the resistor R5 and the negative input terminal IN1- of the operational transconductance amplifier OTA1, and the other end of the resistor R6 is connected to the reference voltage Vref3 output terminal of the voltage reference source circuit 3; One end of the resistor R3 is connected to the positive input terminal IN1+ of the operational transconductance amplifier OTA1 and one end of the resistor R4, and the other end of the resistor R3 is connected to the reference voltage Vref2 output terminal of the voltage reference source circuit 2; One end of the resistor R4 is connected to the positive input terminal IN1+ of the operational transconductance amplifier OTA1 and one end of the resistor R3, and the other end of the resistor R4 is connected to the reference voltage Vref1 output terminal of the voltage reference source circuit 1; The induced signal AC voltage Va2 input terminal of the voltage reference source circuit 2 is connected to the induced signal AC voltage Va1 input terminal of the adaptive bias circuit 1; The collector of the BJT tube Q1 is connected to the base of the BJT tube Q1, the gate of the PMOS tube PM4, one end of the resistor R8, and the input end of the induced signal AC voltage Va2 of the voltage reference source circuit 2, and the emitter of the BJT tube Q1 is connected to the common terminal GND; The gate of the PMOS transistor PM4 is connected to the base of the BJT transistor Q1, the collector of the BJT transistor Q1, one end of the resistor R8, and the input end of the induced signal AC voltage Va2 of the voltage reference source circuit 2. The source of the PMOS transistor PM4 is connected to the power supply terminal VDD. The drain of the PMOS transistor PM4 is connected to one end of the resistor R7 and the output end of the reference voltage Vref2 of the voltage reference source circuit 2. One end of the resistor R8 is connected to the base of the BJT transistor Q1, the gate of the PMOS transistor PM4, the collector of the BJT transistor Q1, and the input end of the induced signal AC voltage Va2 of the voltage reference source circuit 2, and the other end of the resistor R8 is connected to the power supply terminal VDD; One end of the resistor R7 is connected to the drain of the PMOS transistor PM4 and the reference voltage Vref2 output end of the voltage reference source circuit 2 , and the other end of the resistor R7 is connected to the common end GND.

2. The high-efficiency and high-linearity power amplifier with an adaptive bias circuit according to claim 1, wherein: The voltage reference source circuit 1 is characterized in that: The gate of the PMOS transistor PM1 is connected to the gate of the PMOS transistor PM2, the drain of the PMOS transistor PM2, the gate of the PMOS transistor PM3, and the drain of the NMOS transistor NM4. The drain of the PMOS transistor PM1 is connected to the drain of the NMOS transistor NM3 and the gate of the NMOS transistor NM3. The source of the PMOS transistor PM1 is connected to the power supply terminal VDD. The gate of the PMOS transistor PM2 is connected to the drain of the PMOS transistor PM2, the gate of the PMOS transistor PM1, and the gate of the PMOS transistor PM3, and the source of the PMOS transistor PM2 is connected to the power supply terminal VDD; The gate of the PMOS transistor PM3 is connected to the gate of the PMOS transistor PM2, the drain of the PMOS transistor PM2, and the gate of the PMOS transistor PM1. The drain of the PMOS transistor PM3 is connected to the drain of the NMOS transistor NM5, the gate of the NMOS transistor NM5, and the reference voltage Vref1 output terminal of the voltage reference source circuit 1. The source of the PMOS transistor PM3 is connected to the power supply terminal VDD. The gate of the NMOS transistor NM3 is connected to the drain of the NMOS transistor NM3, the drain of the PMOS transistor PM1, and the gate of the NMOS transistor NM4, and the source of the NMOS transistor NM3 is connected to the common terminal GND; The gate of the NMOS transistor NM4 is connected to the drain of the NMOS transistor NM3, the drain of the PMOS transistor PM1, and the gate of the NMOS transistor NM4. The gate of the PMOS transistor PM2 is connected to the drain of the PMOS transistor PM2, the gate of the PMOS transistor PM1, and the gate of the PMOS transistor PM3. The drain of the NMOS transistor NM4 is connected to the gate of the PMOS transistor PM2, the drain of the PMOS transistor PM2, the gate of the PMOS transistor PM3, and the gate of the PMOS transistor PM1. The source of the NMOS transistor NM4 is connected to one end of the resistor R2. One end of the resistor R2 is connected to the source of the NMOS transistor NM4, and the other end of the resistor R2 is connected to the common terminal GND; The gate of the NMOS transistor NM5 is connected to the drain of the NMOS transistor NM5 , the drain of the PMOS transistor PM3 , and the reference voltage Vref1 output terminal of the voltage reference source circuit 1 , and the source of the NMOS transistor NM5 is connected to the common terminal GND.

3. The high-efficiency and high-linearity power amplifier with an adaptive bias circuit according to claim 1, wherein: The power amplifier 1 is characterized by: The drain of the NMOS transistor NM1 is connected to the source of the NMOS transistor NM2, the gate of the NMOS transistor NM1 is connected to one end of the resistor R1, one end of the capacitor C1, and one end of the capacitor C3, and the source of the NMOS transistor NM1 is connected to the common terminal GND; The drain of the NMOS transistor NM2 is connected to one end of the inductor L1 and one end of the capacitor C2, the gate of the NMOS transistor NM1 is connected to the power supply terminal VDD, and the source of the NMOS transistor NM2 is connected to the drain of the NMOS transistor NM1; One end of the inductor L1 is connected to the drain of the NMOS transistor NM2, and the other end of the inductor L1 is connected to the power supply terminal VDD; One end of the capacitor C2 is connected to the drain of the NMOS transistor NM2 and one end of the inductor L1, and the other end of the capacitor C2 is connected to the RF signal output terminal RFout1 through the output stage matching network 1; One end of the capacitor C1 is connected to the gate of the NMOS transistor NM1, one end of the resistor R1, and one end of the capacitor C3. The other end of the capacitor C1 is connected to the RF signal input terminal RFin1 through the input stage matching network 1. One end of the resistor R1 is connected to the gate of the NMOS transistor NM1, one end of the capacitor C1, and one end of the capacitor C3, and the other end of the resistor R1 is connected to the bias voltage Vb1 input terminal of the power amplifier; One end of the capacitor C3 is connected to the gate of the NMOS transistor NM1, one end of the capacitor C1, and one end of the resistor R1, and the other end of the capacitor C3 is connected to the output end of the induction signal AC voltage Va1 of the power amplifier.

4. The high-efficiency and high-linearity power amplifier with an adaptive bias circuit according to claim 1, wherein: The voltage reference source circuit 3 is characterized in that: The collector of the BJT tube Q2 is connected to the base of the BJT tube Q2, the gate of the PMOS tube PM5, and one end of the resistor R10, and the emitter of the BJT tube Q2 is connected to the common terminal GND; The gate of the PMOS transistor PM5 is connected to the base of the BJT transistor Q2, the collector of the BJT transistor Q2, and one end of the resistor R10. The source of the PMOS transistor PM5 is connected to the power supply terminal VDD. The drain of the PMOS transistor PM5 is connected to one end of the resistor R9 and the output end of the reference voltage Vref3 of the voltage reference source circuit 3. One end of the resistor R10 is connected to the base of the BJT tube Q2, the gate of the PMOS tube PM5, and the collector of the BJT tube Q2, and the other end of the resistor R10 is connected to the power supply terminal VDD; One end of the resistor R9 is connected to the drain of the PMOS transistor PM5 and the output end of the reference voltage Vref3 of the voltage reference source circuit 3 , and the other end of the resistor R9 is connected to the common end GND.

5. The high-efficiency and high-linearity power amplifier with an adaptive bias circuit according to claim 1, wherein: The characteristics of the operational transconductance amplifier OTA1 are: The drain of NMOS transistor NM8 is connected to the source of NMOS transistor NM10 and the drain of PMOS transistor PM19. The gate of NMOS transistor NM8 is connected to the gate of NMOS transistor NM9, the gate of NMOS transistor NM13, the source of NMOS transistor NM12, the gate of NMOS transistor NM14, and the drain of NMOS transistor NM14. The source of NMOS transistor NM8 is connected to the common terminal GND. The drain of the NMOS transistor NM9 is connected to the source of the NMOS transistor NM11 and the drain of the PMOS transistor PM18. The gate of the NMOS transistor NM9 is connected to the gate of the NMOS transistor NM8, the gate of the NMOS transistor NM13, the source of the NMOS transistor NM12, the gate of the NMOS transistor NM14, and the drain of the NMOS transistor NM14. The source of the NMOS transistor NM9 is connected to the common terminal GND. The drain of the NMOS transistor NM10 is connected to the drain of the PMOS transistor PM8, the gate of the PMOS transistor PM6, and the gate of the PMOS transistor PM7. The gate of the NMOS transistor NM10 is connected to the gate of the NMOS transistor NM11, the gate of the NMOS transistor NM12, and the drain of the NMOS transistor NM12. The source of the NMOS transistor NM10 is connected to the drain of the NMOS transistor NM8 and the drain of the PMOS transistor PM19. The drain of the NMOS transistor NM11 is connected to the drain of the PMOS transistor PM9 and the output terminal OUT1 of the operational transconductance amplifier OTA1. The gate of the NMOS transistor NM11 is connected to the gate of the NMOS transistor NM10, the gate of the NMOS transistor NM12, and the drain of the NMOS transistor NM12. The source of the NMOS transistor NM11 is connected to the drain of the NMOS transistor NM9 and the drain of the PMOS transistor PM18. The drain of the NMOS transistor NM12 is connected to the gate of the NMOS transistor NM12, the gate of the NMOS transistor NM10, the drain of the PMOS transistor PM11, and the gate of the NMOS transistor NM11. The source of the NMOS transistor NM12 is connected to the gate of the NMOS transistor NM8, the gate of the NMOS transistor NM13, the gate of the NMOS transistor NM9, the gate of the NMOS transistor NM14, and the drain of the NMOS transistor NM14. The drain of the NMOS transistor NM13 is connected to the gate of the PMOS transistor PM15, the drain of the PMOS transistor PM15, and the gate of the PMOS transistor PM17. The gate of the NMOS transistor NM13 is connected to the gate of the NMOS transistor NM8, the source of the NMOS transistor NM12, the gate of the NMOS transistor NM9, the gate of the NMOS transistor NM14, and the drain of the NMOS transistor NM14. The source of the NMOS transistor NM13 is connected to the common terminal GND. The drain of the NMOS transistor NM14 is connected to the gate of the NMOS transistor NM14, the gate of the NMOS transistor NM8, the source of the NMOS transistor NM12, the gate of the NMOS transistor NM9, and the gate of the NMOS transistor NM13, and the source of the NMOS transistor NM14 is connected to the common terminal GND; The drain of the PMOS transistor PM6 is connected to the source of the PMOS transistor PM8, the gate of the PMOS transistor PM6 is connected to the drain of the PMOS transistor PM8, the drain of the NMOS transistor NM10, and the gate of the PMOS transistor PM7, and the source of the PMOS transistor PM6 is connected to the power supply terminal VDD; The drain of the PMOS transistor PM7 is connected to the source of the PMOS transistor PM9, the gate of the PMOS transistor PM7 is connected to the drain of the PMOS transistor PM8, the drain of the NMOS transistor NM10, and the gate of the PMOS transistor PM6, and the source of the PMOS transistor PM7 is connected to the power supply terminal VDD; The drain of the PMOS transistor PM8 is connected to the gate of the PMOS transistor PM7, the drain of the NMOS transistor NM10, and the gate of the PMOS transistor PM6. The gate of the PMOS transistor PM8 is connected to the gate of the PMOS transistor PM9, the drain of the PMOS transistor PM16, and the source of the PMOS transistor PM17. The source of the PMOS transistor PM8 is connected to the drain of the PMOS transistor PM6. The drain of the PMOS transistor PM9 is connected to the drain of the NMOS transistor NM11 and the gate of the PMOS transistor PM6. The gate of the PMOS transistor PM9 is connected to the gate of the PMOS transistor PM8, the drain of the PMOS transistor PM16, and the source of the PMOS transistor PM17. The source of the PMOS transistor PM8 is connected to the drain of the PMOS transistor PM6. The drain of the PMOS transistor PM10 is connected to the source of the PMOS transistor PM18 and the source of the PMOS transistor PM19. The gate of the PMOS transistor PM10 is connected to the gate of the PMOS transistor PM11, the source of the PMOS transistor PM13, the gate of the PMOS transistor PM12, and the drain of the PMOS transistor PM12. The source of the PMOS transistor PM10 is connected to the power supply terminal VDD. The drain of the PMOS transistor PM11 is connected to the gate of the NMOS transistor NM12, the gate of the NMOS transistor NM10, the drain of the NMOS transistor NM12, and the gate of the NMOS transistor NM11. The gate of the PMOS transistor PM11 is connected to the gate of the PMOS transistor PM10, the source of the PMOS transistor PM13, the gate of the PMOS transistor PM12, and the drain of the PMOS transistor PM12. The source of the PMOS transistor PM11 is connected to the power supply terminal VDD. The drain of the PMOS transistor PM12 is connected to the gate of the PMOS transistor PM12, the source of the PMOS transistor PM13, the gate of the PMOS transistor PM10, and the gate of the PMOS transistor PM11. The source of the PMOS transistor PM12 is connected to the power supply terminal VDD. The drain of the PMOS transistor PM13 is connected to the gate of the PMOS transistor PM13 and one end of the resistor R11. The source of the PMOS transistor PM13 is connected to the gate of the PMOS transistor PM12, the drain of the PMOS transistor PM12, the gate of the PMOS transistor PM10, and the gate of the PMOS transistor PM11. The drain of the PMOS transistor PM14 is connected to the gate of the PMOS transistor PM14 , the source of the PMOS transistor PM15 , and the gate of the PMOS transistor PM16 . The source of the PMOS transistor PM14 is connected to the power supply terminal VDD. The drain of the PMOS transistor PM15 is connected to the gate of the PMOS transistor PM15, the gate of the PMOS transistor PM17, and the drain of the NMOS transistor NM13. The source of the PMOS transistor PM15 is connected to the gate of the PMOS transistor PM14, the drain of the PMOS transistor PM14, and the gate of the PMOS transistor PM16. The drain of the PMOS transistor PM16 is connected to the gate of the PMOS transistor PM9, the gate of the PMOS transistor PM8, and the source of the PMOS transistor PM17. The gate of the PMOS transistor PM16 is connected to the gate of the PMOS transistor PM14, the source of the PMOS transistor PM15, and the drain of the PMOS transistor PM14. The source of the PMOS transistor PM16 is connected to the power supply terminal VDD. The drain of the PMOS transistor PM17 is connected to the common terminal GND, the gate of the PMOS transistor PM17 is connected to the gate of the PMOS transistor PM15, the drain of the PMOS transistor PM15, and the drain of the NMOS transistor NM13, and the source of the PMOS transistor PM17 is connected to the gate of the PMOS transistor PM9, the gate of the PMOS transistor PM8, and the drain of the PMOS transistor PM16; The drain of the PMOS transistor PM18 is connected to the drain of the NMOS transistor NM9 and the source of the NMOS transistor NM11. The gate of the PMOS transistor PM18 is connected to the negative input terminal IN1- of the operational transconductance amplifier OTA1. The source of the PMOS transistor PM18 is connected to the drain of the PMOS transistor PM10 and the source of the PMOS transistor PM19. The drain of the PMOS transistor PM19 is connected to the drain of the NMOS transistor NM8 and the source of the NMOS transistor NM10. The gate of the PMOS transistor PM19 is connected to the positive input terminal IN1+ of the operational transconductance amplifier OTA1. The source of the PMOS transistor PM19 is connected to the drain of the PMOS transistor PM10 and the source of the PMOS transistor PM18. One end of the resistor R11 is connected to the gate of the PMOS transistor PM13 and the drain of the PMOS transistor PM13 , and the other end of the resistor R11 is connected to the common terminal GND.

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