A Four-Phase Clock and Two-Phase Clock Compatible FFE System and Method

Abstract

The object of the present invention is to provide a four-phase clock and two-phase clock compatible FFE system and method. The method includes: in the four-phase clock mode, using a slow clock to convert six-beat data into three-beat data; when the four-phase clock mode is converted to the two-phase clock mode, using 0° and 180° phase clocks for clocking; in the two-phase clock mode, adding one beat of delay after the sampling clock of the fourth data group. The present invention can reduce the calibration of a necessary DCC and the phase calibration between clocks, and effectively improve noise and power consumption.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly relates to a four-phase clock and two-phase clock compatible FFE system and method. Background Art

[0002] ‌The FFE system is short for Feed Forward Equalizer, which is mainly used in communication systems to optimize signal transmission quality. The FFE system is an equalization technology mainly used to compensate for signal distortion caused by channel characteristics during transmission. Its core idea is to adjust the frequency response characteristics of the signal to make the frequency response characteristics of the entire system flatter, thereby reducing inter-symbol interference (ISI). The FFE system is usually implemented using a digital filter, and the most common is the finite impulse response (FIR) filter‌. The working principle of the FFE system is to apply appropriate delays at the transmitter or receiver to generate multipath signals, and then linearly scale and combine these signals to eliminate ISI caused by the channel. Specifically, the FFE system uses a digital filter to perform high-pass filtering on the signal, and adjusts the tap coefficients of the filter to change the frequency response characteristics, so that the high-frequency and low-frequency components are attenuated uniformly, optimizing the eye diagram‌. The FFE system is widely used in various communication systems, especially in high-speed serial interfaces such as PCIe. In the PCIe standard, the FFE system uses pre-emphasis and de-emphasis technologies to optimize signal transmission. Pre-emphasis is to intentionally enhance the signal amplitude of the signal transition edge, and de-emphasis is to reduce the signal amplitude outside the transition edge to reduce power consumption and external radiation.

[0003] In recent years, in high-speed clock transmission, the clock sampled at both rising and falling edges can no longer meet the requirements of high-speed transmission. When the transmission rate reaches 56G, the bandwidth limitation of the process cannot reach the required 28GHz. Therefore, the 4-phase 14GHz clock has become the mainstream. However, for some low-speed applications, the additional phase calibration error brought by the 4-phase clock is a disadvantage. So this set of compatible FFE system is necessary. In high-speed design, the calibration scheme for four-phase clocks is generally to first calibrate the duty cycle (abbreviation: DCC) of ck0 / c180 and ck90 / ck270 clocks. After calibrating the duty cycle, XOR is used to adjust the phase difference (abbreviation: QEC) between the two groups of clocks. When the system is compatible with low-speed protocols, the clock will be downscaled at the front end and then go through the low-speed DCC / QEC in sequence. Each stage of the clock will bring additional power consumption and noise. However, if it is directly output at the DCC output, these power consumption noises can be effectively reduced, but it will cause incompatibility problems for the subsequent FFE design. Summary of the Invention

[0004] The object of the present invention is to provide a four-phase clock and two-phase clock compatible FFE system and method, which can reduce the calibration of a necessary set of DCC and the phase calibration between clocks, and effectively improve noise and power consumption.

[0005] A method for a four-phase clock and two-phase clock compatible FFE system, comprising:

[0006] In the four-phase clock mode, use a slow clock to convert six-beat data into three-beat data;

[0007] When the four-phase clock mode is converted to the two-phase clock mode, use 0° and 180° phase clocks for clocking;

[0008] In the two-phase clock mode, add one beat of delay after the sampling clock of the fourth data group.

[0009] Preferably, before using a slow clock to convert six-beat data into three-beat data in the four-phase clock mode, data preprocessing is further included, specifically:

[0010] Perform retimer processing on the data before entering the 4to1mux;

[0011] Add two additional data before and after the current data to complete the data preprocessing.

[0012] Preferably, when the four-phase clock mode is converted to the two-phase clock mode, using 0° and 180° phase clocks for clocking includes:

[0013] Use two phases of the 4-phase clock as the clock mode of the DFF and add it to the FFE;

[0014] When the four-phase clock switches to the two-phase clock, two clocks of the four-phase clock are set to CK90:0 and CK270:1 by RST, that is, the two clocks are turned off;

[0015] The adjacent clocks generate the sampling clock PULSE, reducing the original four sampling clock PULSEs to two, and they are the sampling clock PULSEs of the latter two phases, that is, 0° and 180° phase clocks.

[0016] Preferably, the conversion of the four-phase clock mode to the two-phase clock mode includes:

[0017] When the sampling clock becomes two-phase, fully multiplex the third data and the fourth data in the four groups of data of the four-phase clock;

[0018] Connect the first data transmission line of the four-phase clock to the transmission line of the third data;

[0019] Connect the second data transmission line of the four-phase clock to the transmission line of the fourth data.

[0020] Preferably, the transmission line connecting the first data transmission line of the four-phase clock to the third data includes:

[0021] A clock mode control selector according to the FFE system;

[0022] When the FFE system is in the two-phase clock mode, connect the first data transmission line of the four-phase clock to the transmission line of the third data.

[0023] Preferably, the transmission line connecting the second data transmission line of the four-phase clock to the fourth data includes:

[0024] A clock mode control selector according to the FFE system;

[0025] When the FFE system is in the two-phase clock mode and when the second data needs to be transmitted, the selector adds a delay after the sampling clock of the fourth data for transmitting the second data.

[0026] A four-phase clock and two-phase clock compatible FFE system, comprising: a third data sampling circuit;

[0027] The third data sampling circuit includes: a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop and a first selector;

[0028] The CK terminal of the first flip-flop is connected to the clock signal, the D terminal is connected to the input signal for sampling the third data, and the Q terminal is connected to the pre-signal for sampling the third data;

[0029] The CK terminal of the second flip-flop is connected to the inverted clock signal, the D terminal is connected to the pre-signal for sampling the third data, and the Q terminal is connected to the main signal for sampling the third data;

[0030] The CK terminal of the third flip-flop is connected to the clock signal, the D terminal is connected to the main signal for sampling the third data, and the Q terminal is connected to the post-signal for sampling the third data;

[0031] The CK terminal of the fourth flip-flop is connected to the inverted clock signal, the D terminal is connected to the post-signal for sampling the third data, and the Q terminal is connected to the delayed signal of the post-signal for sampling the third data;

[0032] The positive input terminal of the first selector is connected to the Q terminal of the third flip-flop, and the negative input terminal is connected to the Q terminal of the fourth flip-flop.

[0033] Preferably, it further includes: a first data sampling circuit;

[0034] The first data sampling circuit includes: a fifth flip-flop, a sixth flip-flop, a seventh flip-flop, an eighth flip-flop and a second selector;

[0035] The D terminal of the fifth flip-flop is connected to the input signal for sampling the first data, the Q terminal is connected to the negative input terminal of the second selector, and the CK terminal is connected to the inverted clock signal;

[0036] The D terminal of the sixth flip-flop is connected to the output terminal of the second selector, the Q terminal is connected to the pre-signal for sampling the first data, and the CK terminal is connected to the clock signal;

[0037] The D terminal of the seventh flip-flop is connected to the pre-signal for sampling the first data, the Q terminal is connected to the main signal for sampling the first data, and the CK terminal is connected to the inverted clock signal;

[0038] The D terminal of the eighth flip-flop is connected to the main signal for sampling the first data, the Q terminal is connected to the post-signal for sampling the first data, and the CK terminal is connected to the clock signal;

[0039] The positive input terminal of the second selector is connected to the input signal for sampling the first data.

[0040] An electronic device, comprising: a chip, a processor, and a memory, where the memory is used to store computer program code, the computer program code includes computer instructions, and when the chip executes the computer instructions, the electronic device executes a method for a four-phase clock and two-phase clock compatible FFE system.

[0041] A computer-readable storage medium stores a computer program, the computer program includes program instructions, and when the program instructions are executed by a processor of an electronic device, the processor is caused to execute a method for a four-phase clock and two-phase clock compatible FFE system.

[0042] The beneficial effects of the present invention are as follows: 1. In the low-speed protocol of the present invention, switching to use a two-phase clock can reduce a set of necessary DCC calibrations and the phase calibration between clocks, effectively improving noise and power consumption; 2. The present invention uses a two-phase clock as the input clock of the DFF. Although it sacrifices a part of the setup time, it saves a large amount of power consumption and also makes this part of the circuit compatible; 3. The present invention only needs to modify a small part of the circuit to be compatible with both a four-phase clock and a two-phase clock, and does not affect the setup time of data sampling. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The drawings here are incorporated into the specification and constitute a part of this specification, indicating the embodiments conforming to the present invention, and are used together with the specification to explain the principles of the present invention.

[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0045] Figure 1 It is a flowchart of a method for a four-phase clock and two-phase clock compatible FFE system of the present invention;

[0046] Figure 2 It is the third data sampling circuit diagram of the present invention;

[0047] Figure 3 It is the first data sampling circuit diagram of the present invention;

[0048] Figure 4 It is the four-phase clock sampling timing diagram of the present invention;

[0049] Figure 5 It is the four-phase clock sampling timing diagram with FFE TAP added in the present invention;

[0050] Figure 6 It is the optimized four-phase clock sampling timing diagram of the present invention;

[0051] Figure 7 It is the optimized four-phase clock sampling timing diagram with FFE TAP added in the present invention;

[0052] Figure 8 It is the four-phase clock sampling phase diagram of the present invention;

[0053] Figure 9 It is the two-phase clock sampling phase diagram of the present invention;

[0054] Figure 10 It is the two-phase clock FFE sampling and data distribution diagram of the present invention. Detailed implementation manners

[0055] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0056] It should be noted that all the directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative position relationship and movement conditions between components in a specific posture (as shown in the drawings). If the specific posture changes, the directional indications will also change accordingly.

[0057] In addition, the descriptions involving "first", "second", etc. in the present invention are only for descriptive purposes and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between various embodiments may be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0058] In high-speed clock transmission, the clock sampled at both rising and falling edges can no longer meet the requirements of high-speed transmission. When the transmission rate reaches 56G, the bandwidth limitation of the process cannot reach the required 28GHz. Therefore, the 4-phase 14GHz clock has become the mainstream. However, for some low-speed applications, the additional phase calibration error brought by the 4-phase clock is instead a disadvantage. So this set of compatible FFE system is necessary. In high-speed design, the calibration scheme for four-phase clocks is generally to first calibrate the duty cycle (abbreviation: DCC) of ck0 / c180 and ck90 / ck270 clocks. After calibrating the duty cycle, the XOR is used to adjust the phase difference between the two groups of clocks (abbreviation: QEC). When the system is compatible with low-speed protocols, the clock will be downscaled at the front end and then sequentially pass through the low-speed DCC / QEC. Each stage of the clock will bring additional power consumption and noise. But if it is directly output at the DCC output end, these power consumption noises can be effectively reduced, but it will cause incompatibility problems for the subsequent FFE design.

[0059] The present invention can reduce a necessary DCC calibration and the direct phase calibration of the clock by switching to use two-phase clocks in low-speed protocols, effectively improving noise and power consumption; the present invention uses two-phase clocks as the input clock of DFF. Although it sacrifices a part of the setup time, it saves a large amount of power consumption and also makes this part of the circuit compatible; the present invention only needs to modify a small part of the circuit to be compatible with four-phase clocks and two-phase clocks at the same time without affecting the setup time of data sampling.

[0060] Embodiment 1

[0061] A method for a four-phase clock and two-phase clock compatible FFE system, referring to Figure 1 , includes:

[0062] S100, in the four-phase clock mode, using a slow clock to convert six-beat data into three-beat data;

[0063] In a communication system, a FFE (Feed-Forward Equalizer) is used to compensate for channel distortion. It usually contains multiple taps, which are divided into three parts: PRE, MAIN, and POST. PRE TAP: Processes the leading part of the signal, mainly compensating for pre-cursor distortion (interference caused by the previous symbol). The PRE TAP can reduce the interference of the previous symbol on the current symbol. MAIN TAP: Processes the current part of the signal, compensating for the main cursor distortion (interference of the current symbol). The MAIN TAP can enhance the strength of the current symbol. POST TAP: Processes the subsequent part of the signal, compensating for post-cursor distortion (interference caused by subsequent symbols). The POST TAP can reduce the interference of subsequent symbols on the current symbol.

[0064] Reference Figure 6 , in the four-phase clock mode, there are a total of four groups of data, namely D0, D1, D2, and D3. Each group of data consists of three taps, namely D0 PRE, D0 MAIN, D0 POST; D1 PRE, D1 MAIN, D1 POST; D2 PRE, D2 MAIN, D2 POST; D3 PRE, D3 MAIN, D3 POST; Reference Figure 5 , a total of six clock beats are required to finish all the data. However, six DFFs are needed for six clock beats. Obviously, this will cause a large amount of power consumption and area. Therefore, in the embodiments of the present invention, by sampling the slow clock, the clock that originally required six beats is converted into a clock that requires three beats. Although the setup time of sampling is sacrificed, power consumption and area are saved. Reference Figure 7 , when this mode is combined with FFE, there is no need to add an extra DFF group to process the Data. It is still three groups, making the power consumption advantage even greater.

[0065] S200, when the four-phase clock mode is converted to the two-phase clock mode, 0° and 180° phase clocks are used for clocking;

[0066] In a four-phase clock system, using 0° and 180° phase clock signals for "clocking" usually means using these two phase signals for some kind of synchronization or control operation. A four-phase clock system consists of four clock signals with a phase difference of 90°, usually represented as: 0° phase clock (Phase 0), 90° phase clock (Phase 90), 180° phase clock (Phase 180), 270° phase clock (Phase 270). These clock signals are usually used for high-precision timing control, data sampling, or multi-phase signal processing. In the embodiments of the present invention, when the four-phase clock mode is converted to the two-phase clock mode, by using 0° and 180° phase clocks for clocking, it is possible to easily switch to the two-phase clock mode.

[0067] S300 , in a two-phase clock mode, adding a one-beat delay after the sampling clock of the fourth data group.

[0068] As mentioned above, although the four-phase clock can be directly switched to a two-phase clock by directly shutting down two phases of the four-phase clock, this will cause the clock signals to be misaligned. Therefore, the circuit needs to be modified so that in the two-phase clock mode, a delay can be added after the sampling clock of the fourth data group to align the clocks, making the FFE system compatible with both the four-phase clock mode and the two-phase clock mode.

[0069] Preferably, reference Figure 4 and Figure 5 In S100, in the four-phase clock mode, the data is pre-processed before the six-beat data is converted into three-beat data using the slow clock, specifically:

[0070] Perform retimer processing on the data before entering the 4to1mux;

[0071] A retimer is a hardware device used to improve signal quality. When signals are attenuated or distorted due to long-distance or high-speed transmission, a retimer receives these signals and regenerates and retimes them, restoring signal quality.

[0072] Add two extra data before and after the current data to complete data preprocessing.

[0073] This invention uses the TAP (PRE, MAIN, POST) of three FFEs as an example. When the transmission frequency reaches 56G or above, the final parallel-to-serial circuit is generally completed by a 4to1 mux. To ensure sufficient setup time and hold time for each bit during the 4to1 mux clock sampling, data undergoes retimer processing before entering the 4to1. This retimer processing is completed by adding two additional sets of data before and after the retimer. However, this method has a drawback. Due to the large amount of data, each data beat requires a set of DFFs, resulting in significant power consumption and area. Therefore, only two phases of the four-phase clock are used as the DFF clock. This sacrifices sampling setup time in exchange for power consumption and area. In other words, a slow clock is used to convert six beats of data into three beats, resulting in lower power consumption.

[0074] Preferably, reference Figure 8 and Figure 9 , S200, when the four-phase clock mode is converted to the two-phase clock mode, the 0° and 180° phase clocks are used for beating, including:

[0075] The mode of using two phases of a four-phase clock as the clock of the DFF is added to the FFE;

[0076] When the four-phase clock switches to the two-phase clock, two of the four-phase clock's clocks are set to CK90:0 and CK270:1 by RST, that is, the two clocks are turned off;

[0077] The adjacent clocks generate the sampling clock PULSE, reducing the original four sampling clock PULSEs to two, and they are the sampling clock PULSEs of the latter two phases, that is, the 0° and 180° phase clocks.

[0078] The 0° and 180° phase clocks are inverted, that is, their waveforms are completely opposite. When the 0° phase clock is high, the 180° phase clock is low, and vice versa. "Beating" usually refers to triggering certain operations using the edges (rising edge or falling edge) of the clock signal. In the 0° and 180° phase clocks, their rising edges or falling edges can be used for alternating operations. The edges of the 0° and 180° phase clocks appear alternately and can be used to alternately trigger two operations. For example, the 0° rising edge triggers operation A, and the 180° rising edge triggers operation B. Using the edges of two inverted clocks can double the operation frequency. For example, if the frequency of a single clock is ff, using the 0° and 180° clocks can achieve an operation frequency of 2f2f. In a system that requires strict synchronization, the 0° and 180 clocks can be used to control two alternately working modules. In high-speed data acquisition, using the 0° and 180° clocks for alternating sampling can increase the sampling rate. In a communication system, multi-phase clocks are used for signal demodulation or modulation. In a digital circuit, using the 0° and 180° clocks to alternately trigger two modules can improve the system efficiency. By combining the 0° and 180° clocks, a lower-frequency clock signal can be generated. Suppose there is a four-phase clock system with a clock frequency of ff, and the 0° and 180° clocks are used for alternating operations: 0° clock rising edge: triggers operation A. 180° clock rising edge: triggers operation B. Result: Operations A and B are alternately executed, and the overall operation frequency is 2f2f. In a four-phase clock system, using the 0° and 180° phase clocks to "beat" means using their inverted relationship to improve the timing accuracy or operation frequency by alternately triggering operations.

[0079] In the embodiment of the present invention, Figure 8 is the schematic diagram of the four-phase clock sampling clock and phase of the present invention, Figure 9 is the schematic diagram of the two-phase clock sampling clock and phase of the present invention.

[0080] Preferably, referring to Figure 10 , the conversion of the four-phase clock mode to the two-phase clock mode includes:

[0081] When the sampling clock becomes two-phase, the third and fourth data in the four groups of data of the four-phase clock are fully multiplexed;

[0082] Connect the first data transmission line of the four-phase clock to the transmission line of the third data;

[0083] Connect the second data transmission line of the four-phase clock to the transmission line of the fourth data.

[0084] When the four-phase clock mode is converted to the two-phase clock mode, the four phases originally used to transmit four groups of data become two phases to transmit four groups of data. The conversion method from the four-phase clock mode to the two-phase clock mode is to turn off two groups of clocks. At this time, there are still two groups of clocks left. These two groups of clocks were originally used to transmit D2 and D3 data. At this time, the sampling clocks of D0 and D1 are turned off. Therefore, the clocks used to transmit D2 and D3 data should also transmit D0 and D1 while transmitting D2 and D3 data.

[0085] After the clock in the circuit becomes two-phase with the structure unchanged, the correct sampling DATA order of the present invention is as Figure 9 shown. It is very close to the four-phase here. The difference is that the Data order is incorrect. In the Figure 10 right half, the middle two groups of these groups of data can be fully multiplexed (D3_pre / D2 and D3 / D2_POST). The first group D2_PRE does not exist, but the two-phase clock D0 / D1 signals are not used at all. Therefore, when inputting, D0 = D2; D1 = D3 can be set. Then, by replacing the first group of the two-phase clock with D0_PRE, the correct result can be directly obtained without modifying the circuit.

[0086] In addition, there will be one more group of DATA in the FFE data of the two phases. Originally, one more group of DFF was needed to generate this signal, but here only generating this one signal is enough. This is the only place that needs to be repaired for compatibility with the two groups of circuits. This part of the circuit can be moved forward logically to the DFF inside the retimer instead of using a MUX selection after the retimer finally, so as to ensure that the delay of each branch is equal.

[0087] Preferably, connecting the first data transmission line of the four-phase clock to the transmission line of the third data includes:

[0088] A selector controlled according to the clock mode of the FFE system;

[0089] When the FFE system is in the two-phase clock mode, connect the first data transmission line of the four-phase clock to the transmission line of the third data.

[0090] In Figure 9Among them, by comparing the DATA in the second and third rows, the present invention can be directly reused (D3_PRE / D2 and D3 / D2_POST). Then for the DATA in the first row, although there is no reusable DATA, there are some D0 and D1 signals that are not used in the two-phase clock. Some simple processing can be performed at the low-speed parallel port of the data input, so that in the two-phase clock mode, the DATA of D2 / D3 is copied to D1 / D0. In this way, when taking DATA from the first row, D0_PRE can be directly taken, and the same result as D2_PRE will be obtained.

[0091] However, there is still an unsolved technical problem, that is, there is no corresponding DATA available for the data in the fourth row. The reason is that the four-phase clock plus PRE / POST requires a total of 6 (4 + 2) cycles, but after optimizing the four-phase clock, all PRE / POST signals can be completed within three half-speed cycles, so the DFF is only delayed by two cycles, while the two-phase clock requires a total of 4 (2 + 2) cycles, and the original circuit system cannot achieve this. It is necessary to add one more beat after the original D3_POST to obtain D3_POST_POST to correspond to the data on the left. The circuit implementation is as Figure 2 .

[0092] Preferably, connecting the second data transmission line of the four-phase clock to the fourth data transmission line includes:

[0093] A clock mode control selector according to the FFE system;

[0094] When the FFE system is in the two-phase clock mode and when the second data needs to be transmitted, the selector adds a delay after the sampling clock of the fourth data for transmitting the second data.

[0095] As shown in the previous text, after adding the supplementary circuit, the data compatibility problem between the two-phase clock and the four-phase clock is perfectly solved, and only one MUX in the figure needs to be added. However, the addition of this MUX increases the timing delay of one MUX in the 4-phase high-speed mode. The next-level circuit is extremely sensitive to timing, so this design must be further optimized. Therefore, Figure 3 , Figure 3 By adjusting the position where the MUX appears in [], the timing from the last-level Tck-q to the next level can be made consistent. Such adjustment will also cause the D3_PRE and D3_MAIN in the original signal to be misaligned again, generating incorrect data. However, there is still a group of D1 data mentioned before that has not been used. If changes are made in the path of the D1 data and D3_POST in the figure is connected to D1_POST in the two-phase clock mode. Then the problem is truly and perfectly solved.

[0096] Embodiment 2

[0097] A four-phase clock and two-phase clock compatible FFE system, comprising: a third data sampling circuit;

[0098] The third data sampling circuit includes: a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop and a first selector;

[0099] The CK terminal of the first flip-flop is connected to the clock signal, the D terminal is connected to the input signal for sampling the third data, and the Q terminal is connected to the pre-signal for sampling the third data;

[0100] The CK terminal of the second flip-flop is connected to the inverted clock signal, the D terminal is connected to the pre-signal for sampling the third data, and the Q terminal is connected to the main signal for sampling the third data;

[0101] The CK terminal of the third flip-flop is connected to the clock signal, the D terminal is connected to the main signal for sampling the third data, and the Q terminal is connected to the post-signal for sampling the third data;

[0102] The CK terminal of the fourth flip-flop is connected to the inverted clock signal, the D terminal is connected to the post-signal for sampling the third data, and the Q terminal is connected to the delayed signal of the post-signal for sampling the third data;

[0103] The positive input terminal of the first selector is connected to the Q terminal of the third flip-flop, and the negative input terminal is connected to the Q terminal of the fourth flip-flop.

[0104] In the embodiment of the present invention, the first selector makes a signal selection according to whether it is an enable signal of the two-phase clock. If the third data sampling circuit operates in the two-phase clock mode, then one more clock cycle is added after the original D3 POST to obtain D3 POST POST. If it is in the four-phase mode, no modification is required for D3 POST.

[0105] Preferably, it further includes: a first data sampling circuit;

[0106] The first data sampling circuit includes: a fifth flip-flop, a sixth flip-flop, a seventh flip-flop, an eighth flip-flop and a second selector;

[0107] The D terminal of the fifth flip-flop is connected to the input signal for sampling the first data, the Q terminal is connected to the negative input terminal of the second selector, and the CK terminal is connected to the inverted clock signal;

[0108] The D terminal of the sixth flip-flop is connected to the output terminal of the second selector, the Q terminal is connected to the pre-signal for sampling the first data, and the CK terminal is connected to the clock signal;

[0109] The D terminal of the seventh flip-flop is connected to the pre-signal for sampling the first data, the Q terminal is connected to the main signal for sampling the first data, and the CK terminal is connected to the inverted clock signal;

[0110] The D terminal of the eighth flip-flop is connected to the main signal for sampling the first data, the Q terminal is connected to the post-signal for sampling the first data, and the CK terminal is connected to the clock signal;

[0111] The positive input terminal of the second selector is connected to the input signal for sampling the first data.

[0112] In the embodiment of the present invention, the position of the selector needs to be moved forward to make up for the timing misalignment problem in the four-phase clock mode. Figure 3 By adjusting the appearance position of the second selector, the timing from the last-stage Tck-q to the next stage can be made consistent. Such an adjustment will also cause the D3_PRE and D3_MAIN in the original signal to be misaligned again, generating incorrect data. However, there is still a group of D1 data mentioned before that has not been used. If changes are made in the path of the D1 data and then D1_POST in the D3_POST connection diagram is connected in the two-phase clock mode, the timing misalignment problem and the problem of data transmission without a sampling clock can be solved.

[0113] Embodiment 3

[0114] An electronic device includes: a chip, a processor, and a memory. The memory is used to store computer program code, and the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a method for a four-phase clock and two-phase clock compatible FFE system.

[0115] Embodiment 4

[0116] A computer-readable storage medium stores a computer program, and the computer program includes program instructions. When the program instructions are executed by the processor of the electronic device, the processor executes a method for a four-phase clock and two-phase clock compatible FFE system.

[0117] In the present invention, switching to use a two-phase clock in a low-speed protocol can reduce a group of necessary DCC calibrations and the phase calibration of the clock directly, effectively improving noise and power consumption; the present invention uses a two-phase clock as the input clock of the DFF. Although it sacrifices a part of the setup time, it saves a large amount of power consumption and also makes this part of the circuit compatible; the present invention only needs to modify a small part of the circuit to be compatible with both a four-phase clock and a two-phase clock, and does not affect the setup time of data sampling.

[0118] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for a four-phase clock and two-phase clock compatible FFE, characterized in that, Including: In the four-phase clock mode, a slow clock is used to convert six-beat data into three-beat data; When the four-phase clock mode is converted to the two-phase clock mode, 0° and 180° phase clocks are used for clocking; The statement that when the four-phase clock mode is converted to the two-phase clock mode, 0° and 180° phase clocks are used for clocking includes: Using two phases of the 4-phase clock as the clock of the DFF and adding FFE in this mode; When the four-phase clock switches to the two-phase clock, two clocks of the four-phase clock are set to CK90:0 and CK270:1 by RST, that is, the two clocks are turned off; Adjacent clocks generate the sampling clock PULSE, reducing the original four sampling clock PULSEs to two, and they are the sampling clock PULSEs of the latter two phases, that is, 0° and 180° phase clocks; When the sampling clock becomes two-phase, the third and fourth data in the four groups of data of the four-phase clock are fully multiplexed; Connect the first data transmission line of the four-phase clock to the transmission line of the third data; Connect the second data transmission line of the four-phase clock to the transmission line of the fourth data; The statement that the second data transmission line of the four-phase clock is connected to the transmission line of the fourth data includes: Controlling the selector according to the clock mode of the FFE system; When the FFE system is in the two-phase clock mode, when the second data needs to be transmitted, the selector adds a delay after the sampling clock of the fourth data for transmitting the second data; In the two-phase clock mode, add one beat of delay after the sampling clock of the fourth data group to align the clocks.

2. The compatible FFE method for a quarter clock and a half clock according to claim 1, characterized in that, Before converting six-beat data into three-beat data using a slow clock in the four-phase clock mode, data preprocessing is also included. Specifically: Perform retimer processing on the data before entering the 4to1mux; Add two additional data before and after the current data to complete data preprocessing.

3. A method for a four-minute clock and a two-minute clock compatible FFE according to claim 1, characterized in that The statement that the first data transmission line of the four-phase clock is connected to the transmission line of the third data includes: Controlling the selector according to the clock mode of the FFE system; When the FFE system is in the two-phase clock mode, connect the first data transmission line of the four-phase clock to the transmission line of the third data.

4. A four-phase clock and two-phase clock compatible FFE system, applied to the four-phase clock and two-phase clock compatible FFE method according to any one of claims 1-3, characterized in that Including: The third data sampling circuit; The third data sampling circuit includes: the first flip-flop, the second flip-flop, the third flip-flop, the fourth flip-flop and the first selector; The CK terminal of the first flip-flop is connected to the clock signal, the D terminal is connected to the input signal for sampling the third data, and the Q terminal is connected to the pre-signal for sampling the third data; The CK terminal of the second flip-flop is connected to the inverted clock signal, the D terminal is connected to the pre-signal for sampling the third data, and the Q terminal is connected to the main signal for sampling the third data; The CK terminal of the third flip-flop is connected to the clock signal, the D terminal is connected to the main signal for sampling the third data, and the Q terminal is connected to the post-signal for sampling the third data; The CK terminal of the fourth flip-flop is connected to the inverted clock signal, the D terminal is connected to the post-signal for sampling the third data, and the Q terminal is connected to the delayed signal of the post-signal for sampling the third data; The positive input terminal of the first selector is connected to the Q terminal of the third flip-flop, and the negative input terminal is connected to the Q terminal of the fourth flip-flop.

5. A four-minute clock and two-minute clock compatible FFE system according to claim 4, characterized in that, Also including: The first data sampling circuit; The first data sampling circuit includes: a fifth flip-flop, a sixth flip-flop, a seventh flip-flop, an eighth flip-flop, and a second selector; The D terminal of the fifth flip-flop is connected to the input signal for sampling the first data, the Q terminal is connected to the negative input terminal of the second selector, and the CK terminal is connected to the inverted clock signal; The D terminal of the sixth flip-flop is connected to the output terminal of the second selector, the Q terminal is connected to the pre-signal for sampling the first data, and the CK terminal is connected to the clock signal; The D terminal of the seventh flip-flop is connected to the pre-signal for sampling the first data, the Q terminal is connected to the main signal for sampling the first data, and the CK terminal is connected to the inverted clock signal; The D terminal of the eighth flip-flop is connected to the main signal for sampling the first data, the Q terminal is connected to the post-signal for sampling the first data, and the CK terminal is connected to the clock signal; The positive input terminal of the second selector is connected to the input signal for sampling the first data.

6. An electronic device, characterized in that, including: a chip, a processor, and a memory. The memory is used to store computer program code, and the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a four-phase clock and two-phase clock compatible FFE method according to any one of claims 1 to 3.

7. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium. The computer program includes program instructions. When the program instructions are executed by the processor of the electronic device, the processor executes a four-phase clock and two-phase clock compatible FFE method according to any one of claims 1 to 3.

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