Programmable gate driver circuit for integrated power switch

Abstract

The invention relates to a programmable gate driver circuit for an integrated power switch. A gate driver circuit and a corresponding gate driver system are presented. The gate driver circuit may be configured to drive a gallium nitride (GaN) transistor. The gate driver circuit may include a communication interface configured to receive gate driver parameters. The communication interface may be an asynchronous serial communication interface (such as, for example, a UART communication interface). The gate driver parameters may be forwarded from one gate driver circuit to the next using an asynchronous serial communication protocol. One or more digital isolators may be coupled between the gate driver circuits.

Description

Technical Field

[0001] This document relates to gate driver circuits for integrated power switches. In particular, this document relates to programming one or more gate driver circuits, where each gate driver circuit is configured to drive a GaN transistor. Background Art

[0002] Compared to its corresponding MOSFET, a GaN transistor has a high breakdown tolerance, faster switching speed, enhanced thermal conductivity, and lower on-resistance. However, as with most power transistors, the key to obtaining all the benefits from a GaN transistor is proper gate control. The physical properties of the GaN transistor and the implemented gate concept have a significant impact on the optimal drive scheme. Therefore, there is a desire for a reliable mechanism to program and reprogram (i.e., program in real-time or during operation) a gate driver circuit for driving a GaN transistor. In addition, there is a desire for a reliable mechanism to program multiple gate driver circuits in an efficient manner. Furthermore, an object of the present invention is to reliably program a gate driver circuit even in the presence of electromagnetic noise, CMTI, and other interferences. Summary of the Invention

[0003] According to one aspect, a gate driver circuit is provided. The gate driver circuit may be configured to drive a gallium nitride (GaN) transistor. The gate driver circuit may include a communication interface configured to receive gate driver parameters. The communication interface may be an asynchronous serial communication interface.

[0004] The GaN transistor may be implemented using a III-V compound semiconductor material. For example, the GaN transistor may be a GaN high electron mobility transistor (HEMT). The GaN transistor may operate as a switching element. The GaN transistor may have one or more gates to which a corresponding drive signal (such as a drive voltage / current) may be applied to turn on the GaN transistor (i.e., close the switching element) or turn off the GaN transistor (i.e., open the switching element). The GaN transistor may be a GaN bidirectional switch (BDS). In other words, the GaN transistor may be configured to block current in both directions when off. The GaN transistor may have two gates, two sources, and a common drain. Without loss of generality, one gate of the GaN transistor may be denoted as the positive gate with respect to the source, and the other gate of the GaN transistor may be denoted as the negative gate with respect to the source.

[0005] The gate driver circuit can be an isolated gate driver circuit. The gate driver circuit can be configured to generate drive voltage / current for driving the gates (e.g., positive and negative gates) of the GaN transistors. In particular, the gate driver circuit can be configured to generate drive voltage / current based on received gate driver parameters.

[0006] Compared with a synchronous serial communication interface (such as, for example, an inter-integrated circuit I2C communication interface), an asynchronous serial communication interface does not require continuous synchronization (e.g., via a common clock signal).

[0007] The communication interface can be configured to forward the received gate driver parameters to another gate driver circuit or an external control circuit.

[0008] Forwarding the received gate driver parameters can have several advantages. On the one hand, by forwarding the received gate driver parameters to another gate driver circuit, it becomes possible to daisy-chain gate driver circuits. In this way, compared with the case where the external control circuit is electrically connected to each gate driver circuit and separately transmits the gate driver parameters to each gate driver circuit, the number of pins of the external control circuit can be reduced. On the other hand, forwarding the received gate driver parameters to the external control circuit can enable the external control circuit to verify whether the gate driver parameters are correctly transmitted to one or more gate driver circuits by comparing the gate driver parameters received from the last gate driver circuit in one or more gate driver circuits with the gate driver parameters initially sent by the external control circuit to the first gate driver circuit in one or more gate driver circuits. Alternatively or additionally, parity bits and / or cyclic redundancy check CRC can be used to increase the security of data communication.

[0009] The external control circuit can be a microcontroller unit (MCU). For example, the MCU can be implemented on a single integrated circuit. The MCU can include one or more CPUs (processor cores) as well as memory and programmable input / output peripherals. As will be discussed in the following description, the external control unit can include a communication interface (such as an asynchronous serial communication interface) similar to or the same as the gate driver circuit for enabling communication between the gate driver circuits.

[0010] The gate driver parameters can be gate current parameters, and the gate driver circuit can be configured to generate a gate current for driving the GaN transistor based on the gate current parameters.

[0011] For example, the gate current parameter may indicate a reduced holding current value. The gate driver circuit may be configured to reduce the gate current from an initial current value to the reduced holding current value. For example, the gate current may be the gate current applied to the positive gate of the GaN transistor. Additionally, the gate driver circuit may be configured not to reduce the initial current value during an initial time interval (e.g., 50Hz half cycle or 0.01s) after the GaN transistor has turned on. Subsequently, the gate driver circuit may be configured to reduce the initial current value to the reduced holding current value after the initial time interval has elapsed. In this way, damage to the negative gate (which may be in the off state) due to hole injection at the positive gate can be reduced / avoided, and the reliability of the GaN transistor can be increased. The gate current parameter may also indicate the duration of the initial time interval.

[0012] The gate driver parameter may be a gate voltage parameter, and the gate driver circuit may be configured to generate a gate voltage for driving the GaN transistor based on the gate voltage parameter. For example, the gate voltage parameter may indicate a voltage gradient dv / dt, and the gate driver circuit may be configured to generate a gate voltage according to the voltage gradient dv / dt.

[0013] The gate driver circuit may be configured to determine the temperature value of the GaN transistor, and the communication interface may be configured to transmit the temperature value to an external control circuit or another gate driver circuit.

[0014] For example, the temperature value may be a digital temperature value. The gate driver circuit may include a temperature sensing unit configured to determine the temperature value. Alternatively, the temperature sensing unit is partially implemented on the gate driver circuit and partially implemented on the GaN transistor. The temperature value may be directly transmitted to the external control circuit, or may be forwarded from the gate driver circuit to the gate driver circuit in sequence until it reaches the external control circuit.

[0015] The gate driver circuit may be configured to determine a current value indicating the current flowing through the GaN transistor, and the communication interface may be configured to transmit the current value to an external control circuit or another gate driver circuit.

[0016] The current flowing through the GaN transistor may be, for example, the drain-source current of the GaN transistor. The gate driver circuit may include a current sensing unit for sensing the current passing through the GaN transistor. Alternatively, the current sensing unit may be partially implemented on the gate driver circuit and partially implemented on the GaN transistor. The current value may be directly transmitted to the external control circuit, or may be forwarded from the gate driver circuit to the gate driver circuit in sequence until it reaches the external control circuit. The current value may be a digital current value.

[0017] The external control circuit can then be configured to receive the current value, determine updated gate driver parameters based on the current value received from the gate driver circuit, and transmit the updated gate driver parameters back to the gate driver circuit to minimize the power consumption of the gate driver circuit.

[0018] The gate driver circuit can be configured to determine a fault state associated with the GaN transistor or the gate driver circuit, and the communication interface can be configured to transmit a signal indicating the fault state to the external control circuit or another gate driver circuit.

[0019] The fault state can be triggered, for example, by a temperature exceeding a temperature threshold (over-temperature protection OTP), a voltage exceeding a voltage threshold (over-voltage protection OVP), or a current exceeding a current threshold (over-current protection OCP). In particular, the fault state can be triggered when saturation of the GaN transistor is detected (saturation detection) or a short circuit is detected (short-circuit protection SCP). Both saturation and short circuit can be detected based on the drain-source current and / or voltage of the GaN transistor (e.g., by sensing and comparing with appropriate threshold values). For example, the received gate driver parameters can indicate a saturation current threshold, or the gate driver circuit can be configured to determine the saturation current threshold based on the received gate driver parameters.

[0020] The communication interface can be a Universal Asynchronous Receiver-Transmitter UART interface.

[0021] According to another aspect, an integrated power switch is provided. The integrated power switch can include a GaN transistor and the gate driver circuit as described above. The gate driver circuit can be coupled to the gate of the GaN transistor.

[0022] According to yet another aspect, a gate driver system is provided. The gate driver system can include the first gate driver circuit as described above. The gate driver system can include a first digital isolator circuit configured to receive gate driver parameters and transmit the gate driver parameters to the first gate driver circuit.

[0023] The first digital isolator circuit can be configured to ensure forwarding of an isolation signal to the first gate driver. Generally, using a digital isolator circuit can facilitate signal transmission between systems with different ground potentials. With electrical isolation, the first digital isolator can enable communication without conducting ground loops or hazardous voltages.

[0024] For example, the first digital isolator circuit may be configured to receive the gate driver parameters from the control circuit. The first digital isolator circuit may be configured to receive and transmit the gate driver parameters using an asynchronous serial communication protocol and, in particular, the UART communication protocol.

[0025] Both the first digital isolator circuit and the first gate driver circuit may be coupled to the same reference potential. Throughout this document, the term "reference potential" is meant in its broadest possible sense. In particular, the reference potential is not limited to ground (i.e., a reference potential that is directly physically connected to the earth or a voltage of 0V). Instead, the term "reference potential" may refer to any reference point to which current may flow to or from, or from which voltage may be measured. Additionally, it should be noted that the reference potential mentioned in this document does not necessarily refer to the same physical contact. Instead, the reference potential mentioned in this document may be associated with different physical contacts, although for ease of presentation, only "the" reference potential is mentioned.

[0026] The first digital isolator circuit may include a push - pull output stage. The push - pull output stage may drive the digital input pad of the gate driver circuit with a very low impedance, which makes the digital input pad less susceptible to noise injection due to conducted or radiated electromagnetic interference (EMI) injection or common - mode transient immunity (CMTI).

[0027] The first digital isolator circuit may be a dual - channel digital isolator circuit. The output pin of the first digital isolator associated with the first channel may be coupled to the communication interface of the gate driver circuit. The input pin of the first digital isolator circuit associated with the second channel may be coupled to the communication interface of the gate driver circuit. The first digital isolator circuit may be configured to transmit the gate driver parameters from the output pin to the communication interface of the gate driver circuit. The gate driver circuit may be configured to forward the gate driver parameters to another gate driver circuit via the input pin of the first digital isolator circuit (and may be via another digital isolator circuit). Generally, a digital isolator circuit may include any number of channels. For example, the digital isolator circuit may also have three channels, where the third channel may be used to transmit a pulse - width modulation (PWM) signal for driving a GaN transistor. The gate driver circuit may also forward other feedback information (e.g., such as a sensed current value, a sensed temperature value, or a fault state) to another gate driver circuit via the input pin of the first digital isolator circuit (and may be via another digital isolator circuit).

[0028] A gate driver system may include a second gate driver circuit. The first gate driver circuit may be configured to transmit gate driver parameters to the second gate driver circuit via a first digital isolator circuit. The gate driver system may also include a second digital isolator circuit, and the first gate driver circuit may be configured to transmit gate driver parameters to the second gate driver circuit via the first digital isolator circuit and via the second digital isolator circuit. This may be particularly advantageous in a gate driver system where each gate driver circuit has its own digital isolator circuit, and all digital isolator circuits are implemented as dual-channel digital isolator circuits, where one channel is used to transmit gate driver parameters to the gate driver circuit, and where the other channel is used to receive gate driver parameters or other feedback information (e.g., such as sensed current values, sensed temperature values, or fault states) from the gate driver circuit.

[0029] Similarly, the second digital isolator circuit and the second gate driver circuit may be coupled to the same reference potential. Similarly, via daisy chaining, the gate driver parameters may be forwarded from one gate driver circuit to another gate driver circuit in sequence, thereby saving communication pins at an external control circuit (which controls / programs all gate driver circuits).

[0030] The gate driver system may include a control circuit configured to transmit gate driver parameters to the first digital isolator. The control circuit may be a microcontroller unit (MCU). For example, the MCU may be implemented on a single integrated circuit. The MCU may include one or more CPUs (processor cores) as well as memory and programmable input / output peripherals. The control circuit may be configured to receive gate driver parameters from a third digital isolator circuit that forwards the gate driver parameters from the second gate driver circuit to the control circuit. As already mentioned in the previous description, the control circuit may be configured to compare the received gate driver parameters with the gate driver parameters initially transmitted (via the first digital isolator circuit) to the first gate driver circuit.

[0031] The communication between all entities (i.e., between the control circuit, the gate driver circuits, and the digital isolator circuits) may be based on an asynchronous serial communication protocol and particularly on the UART communication protocol.

[0032] According to yet another aspect, a method for programming one or more gate driver circuits is provided. The method may include steps corresponding to the functional features of the gate driver system described throughout this document. In particular, the method may include: transmitting gate driver parameters to a first gate driver circuit via a first digital isolator using an asynchronous serial communication protocol. For example, the communication protocol may be a UART communication protocol. Both the first digital isolator circuit and the first gate driver circuit may be coupled to the same reference potential. The first digital isolator circuit may include a push-pull output stage.

[0033] The method may include: transmitting gate driver parameters to a second gate driver circuit via the first gate driver circuit using an asynchronous serial communication protocol via the first digital isolator circuit. In particular, the method may include transmitting gate driver parameters to the second gate driver circuit via the first digital isolator circuit and via a second digital isolator circuit. If a multi-channel isolator that cannot isolate different channels from each other is used, it is recommended to transmit via at least 2 digital isolator circuits. Last but not least, the method may include transmitting gate driver parameters to the first digital isolator via a control circuit.

[0034] It should be noted that the methods and systems (including their preferred embodiments) outlined in this document may be used alone or in combination with other methods and systems disclosed in this document. Additionally, the features outlined in the context of the system also apply to the corresponding methods. Furthermore, all aspects of the methods and systems outlined in this document may be combined arbitrarily. In particular, the features of the claims may be combined with each other in any way.

[0035] In this document, the terms "coupled" or "are coupled" refer to elements being in electrical communication with each other, whether directly connected (e.g., via wires) or indirectly connected via other circuit elements between them. For example, even if there are circuit elements (such as switches (which can be turned on and off)) between two elements, the two elements may be said to be coupled. On the other hand, the terms "connected" or "are connected" refer to elements being directly electrically connected to each other (e.g., via a wire) and there are no circuit elements between them. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The present invention is illustrated by way of example and not limitation in the accompanying drawings, in which like reference numerals refer to similar or identical elements and in which

[0037] Figure 1 an exemplary gate driver system including four daisy-chain gate driver circuits and a control circuit is shown,

[0038] Figure 2An exemplary gate driver system including two gate driver circuits directly programmed by a control circuit is shown, and

[0039] Figure 3 An exemplary gate driver system including four parallel gate driver circuits and a control circuit is shown. Detailed Description

[0040] Figure 1 An exemplary gate driver system 1 is shown. The gate driver system 1 includes four daisy-chain gate driver circuits 11, 12, 13, 14 and a control circuit 17. In addition, four digital isolators 20, 21, 22, 23 are depicted. Each gate driver circuit includes a communication interface having a receive (RX) part and a transmit (TX) part. For example, the communication interface can be configured to establish communication based on the UART protocol.

[0041] All the digital isolators depicted in the example are dual-channel digital isolators: The first channel is responsible for forwarding signals (including, for example, gate driver parameters) from the input pin INA to the output pin OUTA. The second channel is responsible for forwarding signals (including, for example, gate driver parameters) from the input pin INB to the output pin OUTB. In this way, signals can propagate from the control circuit 17 to all the gate driver circuits to program them. In this example, the gate driver system is configured to drive two half-bridges, where the first half-bridge includes a high-side GaN transistor driven by the gate driver circuit 11 and a low-side GaN transistor driven by the gate driver circuit 12. The second half-bridge includes a high-side GaN transistor driven by the gate driver circuit 13 and a low-side GaN transistor driven by the gate driver circuit 14. The proposed gate driver system 1 can be extended to drive any number of half-bridges.

[0042] In this way, the gate driver parameters can be forwarded to all the gate driver circuits and finally sent back to the control circuit 17 for consistency checking.

[0043] Figure 2 A power stage 2 is shown. The power stage 2 includes an exemplary gate driver system that includes two integrated gate driver circuits 211, 221 and a control circuit 230. The two integrated gate driver circuits 211, 221 can be directly programmed by the control circuit 232 via digital isolators 231, 232. Thus, contrary to Figure 1 the daisy-chain configuration, the gate driver circuits 211, 221 are controlled in parallel.

[0044] The gate driver circuit 211 is integrated together with the GaN transistor 210 in the integrated power switch 212. The gate driver circuit 211 senses the drain-source current of the GaN transistor 210 and performs, for example, saturation detection, short circuit protection SCP, and over-temperature protection OTP. The gate driver circuit 211 receives gate current parameters (as a first gate driver parameter) from the control circuit 230 via the pin 241. Similarly, the gate driver circuit 211 receives gate voltage parameters (as a second gate driver parameter) from the control circuit 230 via the pin 242. The gate driver circuit 211 drives the GaN transistor 210 based on the two received parameters. The pins 241 and 242 form part of a communication interface, which can be, for example, a UART communication interface.

[0045] Similarly, the gate driver circuit 221 is integrated together with the GaN transistor 22 in the integrated power switch 222. The gate driver circuit 221 receives the gate current parameters via the pin 243, via the digital isolator 232, and receives the gate voltage parameters via the pin 244, via the digital isolator 232. Both the gate driver circuits 211 and 221 can be similar or identical, and the repeated description is omitted here.

[0046] Therefore, Figure 2 the example circuit in depicts a scenario using three channels of the digital isolator: The first channel is used to transmit the gate voltage parameters to the gate driver circuit. The second channel is used to transmit the gate current parameters to the gate driver circuit. The third channel is used to transmit feedback information (e.g., such as sensed current values, sensed temperature values, or fault status) from the driver circuit back to the control circuit 230.

[0047] Using the UART protocol and daisy-chain gate driver circuits can reduce the number of pins used by the control circuit from Figure 1It is obvious. Communication can be established via a digital isolator. Therefore, there are several benefits to using the concepts proposed within the present disclosure. First, the digital isolator and the driver can share the same ground, which can be, for example, a Kelvin ground. Thus, the digital signals for the digital isolator and the digital input pad (RX) do not see significant ground movement. Second, the digital isolator can provide a push-pull output stage, which can drive the digital input pad (RX) with a very low impedance, making it less susceptible to noise injection due to conducted or radiated EMI injection or CMTI. Third, using a daisy chain, the number of pins required by the controller for programming and communication can be reduced to just 2, regardless of the number of devices used. And fourth, the security of data communication can be accomplished through parity bits or CRC, and by reading the data back into the controller to verify that it is the same as the data sent. All of these features make on-the-fly communication and programming more secure, and the data can be verified every time it is transmitted from device to device in a daisy chain topology.

[0048] The impact on the system can be significant. In cases where the controller requires at least two additional pins, the system can now perform real-time programming of, for example, dv / dt and hold current and saturation current levels. This can be important for the reliability, power consumption, and startup of certain topologies. In the event of a fault, it is also possible to read out which fault has been triggered, and the temperature can be read out in digital form. This can bring significant benefits as the amount of power used can be controlled, and thus the power consumption can be reduced when the load is not significant. Additionally, when they know that the load is about to increase, they can increase the saturation current by increasing the hold current. This can increase the reliability of the gate injection transistor GIT GaN device as it is not always driven at maximum gate current and ensures that saturation does not occur under normal operating conditions. This is a feature unique to GIT devices, and having programmability makes GIT devices more advantageous compared to other types of transistors that only use Schottky gates with uncontrollable saturation levels.

[0049] Figure 3 An exemplary gate driver system 3 is shown, which includes four parallel-linked gate driver circuits 31, 32, 33, 34 and a control circuit 30. Note that, without loss of generality, for the sake of clear illustration, Figure 3 the digital isolator circuits between the gate driver circuits are not shown in the figure. However, Figure 3Each of the gate driver circuits illustrated in the figure may require at least one digital isolator circuit. The term "parallel link" describes the fact that all gate drivers are programmed in parallel and can receive the same gate driver parameters from the controller 30. The gate drivers then report their feedback information back to the controller 30 individually. This parallel link driver topology can result in a large number of pins required by the controller 30 and can result in a shorter programming time (compared to the daisy chain driver topology discussed previously).

[0050] It should be noted that the description and the drawings illustrate only the principles of the proposed method and system. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within the spirit and scope of the invention. In addition, all examples and embodiments outlined in this document are mainly and explicitly intended for explanatory purposes only to assist the reader in understanding the principles of the proposed method and system. Furthermore, all statements providing the principles, aspects, and embodiments of the invention and specific examples thereof herein are intended to cover their equivalents.

Claims

1. A gate driver circuit configured to drive a gallium nitride (GaN) transistor, the gate driver circuit comprising a communication interface configured to receive gate driver parameters, wherein the communication interface is an asynchronous serial communication interface. 2 . The gate driver circuit according to claim 1 , wherein the communication interface is configured to forward the received gate driver parameters to another gate driver circuit or an external control circuit.

3. The gate driver circuit according to claim 1 or 2, wherein the gate driver parameter is a gate current parameter, and wherein the gate driver circuit is configured to generate a gate current for driving the GaN transistor based on the gate current parameter.

4. The gate driver circuit according to any one of the preceding claims, wherein the gate driver parameter is a gate voltage parameter, and wherein the gate driver circuit is configured to generate a gate voltage for driving the GaN transistor based on the gate voltage parameter.

5. The gate driver circuit of any of the preceding claims, wherein the gate driver circuit is configured to determine a temperature value of the GaN transistor, and wherein the communication interface is configured to transmit the temperature value to an external control circuit or another gate driver circuit.

6. A gate driver circuit according to any one of the preceding claims, wherein the gate driver circuit is configured to determine a current value indicative of a current flowing through the GaN transistor, and the communication interface is configured to transmit the current value to an external control circuit or another gate driver circuit.

7. A gate driver circuit according to any of the preceding claims, wherein the gate driver circuit is configured to determine a fault condition associated with the GaN transistor or the gate driver circuit, and wherein the communication interface is configured to transmit a signal indicative of the fault condition to an external control circuit or another gate driver circuit.

8. The gate driver circuit according to any one of the preceding claims, wherein the communication interface is a Universal Asynchronous Receiver-Transmitter (UART) interface.

9. An integrated power switch, comprising: GaN transistors, and A gate driver circuit according to any preceding claim, wherein the gate driver circuit is coupled to a gate of the GaN transistor.

10. A gate driver system comprising: The first gate driver circuit according to any one of claims 1 to 8, and A first digital isolator circuit is configured to receive the gate driver parameters and transmit the gate driver parameters to the first gate driver circuit.

11. The gate driver system of claim 10, wherein both the first digital isolator circuit and the first gate driver circuit are coupled to a same reference potential.

12. The gate driver system of claim 10 or 11, wherein the first digital isolator circuit comprises a push-pull output stage.

13. The gate driver system of any one of claims 10 to 12, wherein the first digital isolator circuit is a dual channel digital isolator circuit, and an output pin of the first digital isolator associated with a first channel is coupled to the communication interface of the gate driver circuit, and an input pin of the first digital isolator associated with a second channel is coupled to the communication interface of the gate driver circuit.

14. The gate driver system according to any one of claims 10 to 13, comprising a second gate driver circuit according to any one of claims 1 to 8, wherein: The first gate driver circuit is configured to transmit the gate driver parameters to the second gate driver circuit via the first digital isolator circuit.

15. The gate driver system according to any one of claims 10 to 14, comprising a control circuit configured to transmit the gate driver parameters to the first digital isolator.

16. A method of programming one or more gate driver circuits, the method comprising transmitting gate driver parameters to a first gate driver circuit using an asynchronous serial communication protocol through a first digital isolator.

17. The method according to claim 16, comprising: The gate driver parameters are transmitted by the first gate driver circuit to a second gate driver circuit via the first digital isolator circuit using the asynchronous serial communication protocol.

18. The method according to claim 16 or 17, comprising: The gate driver parameters are transmitted to the first digital isolator through a control circuit.

Images