Simplified turbo decoding circuit, decoder and decoding method

Abstract

The invention provides a simplified turbo decoding circuit, a decoder and a decoding method. Operators involved when predetermined algebraic expressions in a preset expansion formula for calculating state metrics of all states are the same multiplex the same arithmetic unit. By simplifying and merging forward state metric calculation / backward state metric calculation formulas of a decoding algorithm, the hardware operation resource overhead is reduced, and thus the chip area is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of communication coding and decoding, and in particular, to a simplified turbo decoding circuit, a decoder, and a decoding method. Background Art

[0002] Since Berrou proposed Turbo codes in 1993, channel coding has entered a new era. Turbo codes cleverly parallel - cascade two simple component codes through a pseudo - random interleaver, thus constructing a code with pseudo - random characteristics, and through repeated iteration between two component decoders, pseudo - random decoding is realized, and its performance far exceeds that of codewords with algebraic structures. Due to its excellent decoding performance close to the Shannon limit, it has caused a sensation in the coding field. The excellent performance of Turbo codes stems from its unique coding structure and the idea of iterative decoding. The encoder of Turbo codes mainly consists of two recursive systematic convolutional code component encoders, an interleaver, a puncturing matrix, and a multiplexer. Traditional Turbo code decoding is a feedback serial decoder. For each sub - decoder, its decoding has prior information input, source information input, and parity - check information input. As Figure 1 shown, the calculation part of the Turbo code decoder is mainly divided into forward state metric calculation, backward state metric calculation, soft - information calculation, and extrinsic - information calculation. Among them, the forward state metric calculation / backward state metric calculation formulas are very similar, both calculated from the calculated branch metric γ and the forward state metric at the previous moment / backward state metric at the next moment. The calculation process of the traditional radix - 4 Turbo code decoder when calculating the forward state metric / backward state metric is as follows:

[0003] (1) i = 1;

[0004] (2) Define the input systematic bits at the 2i - th and 2i + 1 - th moments as μ 2i μ 2i+1 , and use 0, 1, 2, 3 to represent its four input possibilities: 00, 01, 10, and 11 respectively:

[0005]

[0006] α 2i+2,j = max(α 2i+2,j,0 ,α 2i+2,j,1 ,α 2i+2,j,2 ,α 2i+2,j,3 )

[0007] Wherein, represents the state at the 2i - th moment. In this state, when the input systematic bits k = {μ 2i ,μ 2i+1}(k = 0, 1, 2, 3) at the 2i - th and 2i + 1 - th moments, the state at the 2i + 2 - th moment becomes j, Indicates that the state is The input information is μ 2i (μ 2i =0,1), the output of the encoder Indicates the state at the i-th moment. In this state, when the input system bit k={μ i}(k = 0,1) at the i-th moment, the state at the (i + 1)-th moment becomes j Indicates that the state is The input information is μ i (μ i =0,1), the output of the encoder

[0008] According to the above formula, calculate the formula α 2i+2,j , where j={0,1,...,7}, 64 additions and 24 2-to-1 max comparators are required, and the operation resource overhead is large Summary of the Invention

[0009] Based on the above, the present invention provides a simplified turbo decoding circuit, decoder and decoding method, aiming to solve the technical problems such as large consumption of operation resources in the existing decoding circuit

[0010] A simplified turbo decoding circuit for calculating forward state metrics or backward state metrics, consisting of several operation units

[0011] When the predetermined algebraic expressions in the preset expansion formula for calculating the state metrics of each state are the same, the same operation unit is used to perform the operation of the predetermined operator in the same predetermined algebraic expression

[0012] Furthermore, the preset expansion formula for calculating the state metric of the j-th state at the (2i + 2)-th moment is as follows:

[0013]

[0014] where α 2i+2,j represents the calculated value of the state metric of the j-th state at the (2i + 2)-th moment

[0015] Each of k0, k1, k2, k3 represents a possible value of the input system bit at the 2i-th and (2i + 1)-th moments

[0016] u1, u2, u3, u4 respectively represent one of k0, k1, k2, k3

[0017] α 2i+2,j,k represents the calculated value of the state metric when the input system bit is k at the 2i-th and (2i + 1)-th moments, and k represents k0, k1, k2 or k3

[0018] max(α 2i+2,j,u1 , α 2i+2,j,u2 ) and max(α 2i+2,j,u3 , α 2i+2,j,u4 ) when expanded, the expression forms are:

[0019] max(γ 1 - γ 2 , α 1 - α 2 ) + α 3 + γ 3 + γ 4 ;

[0020] Among them, γ 1 , γ 2 , γ 3 , γ 4 represent branch metrics;

[0021] α 1 , α 2 , α 3 represent the calculated values of relevant state metrics before the (2i + 2)-th moment;

[0022] Among them, γ 1 - γ 2 is the first algebraic expression, and the operation unit used is the first adder;

[0023] In the turbo decoding circuit, the same first algebraic expressions in the preset expansion formulas for calculating the state metrics of each state j share the same first adder.

[0024] Further, taking α 1 - α 2 as the second algebraic expression, and the operation unit used is the second adder;

[0025] In the turbo decoding circuit, the same second algebraic expressions in the preset expansion formulas for calculating the state metrics of each state j share the same second adder.

[0026] Further, taking max(γ 1 - γ 2 , α 1 - α 2 ) as the third algebraic expression, and using the first comparator for comparison operations;

[0027] In the turbo decoding circuit, the same third algebraic expressions in the preset expansion formulas for calculating the state metrics of each state j share the same first comparator.

[0028] Further, taking max(γ 1 - γ 2 , α 1 - α2 ) + α 3 As the fourth algebraic expression, max(γ 1 - γ 2 , α 1 - α 2 ) uses a first comparator, and the arithmetic unit for performing an operation with α 3 is a third adder;

[0029] In the turbo decoding circuit, the same fourth algebraic expression in the preset expansion formula for calculating the state metric of each state j shares the same third adder.

[0030] Furthermore, taking γ 3 + γ 4 as the fifth algebraic expression, the arithmetic unit used is a fourth adder;

[0031] In the turbo decoding circuit, the same fifth algebraic expression in the preset expansion formula for calculating the state metric of each state j reuses the fourth adder.

[0032] Furthermore, in the turbo decoding circuit, the second algebraic expressions with opposite signs in the preset expansion formula for calculating the state metric of each state j share the same second adder;

[0033] For the forward second algebraic expression, the operation result output by the second adder is directly input to one input terminal of the corresponding first comparator;

[0034] For the second algebraic expression opposite to the forward second algebraic expression, the operation result output by the second adder is inverted and then compared in the corresponding first comparator.

[0035] Furthermore, in the turbo decoding circuit, the adders for performing addition operations on the branch metrics with preset values of 0 in γ 2 , γ 3 , γ 4 are omitted.

[0036] A simplified turbo decoder includes the aforementioned simplified turbo decoding circuit.

[0037] A simplified turbo decoding method uses the aforementioned simplified turbo decoding circuit and includes:

[0038] Step B1, when calculating the state metric of each state j at the 2i + 2th moment, extract the data corresponding to each calculation term in the preset expansion formula according to the preset expansion formula for calculating the state metric;

[0039] Step B2: Input each piece of data into the corresponding arithmetic unit in the turbo decoding circuit, and the turbo decoding circuit outputs the calculation results of the state metrics of each state j at the (2i + 2)-th moment.

[0040] The beneficial technical effects of the present invention are as follows: By simplifying and combining the forward state metric calculation / backward state metric calculation formulas of the decoding algorithm, the hardware operation resource overhead is reduced, thereby reducing the chip area. Description of the Drawings

[0041] Figure 1 is a calculation flow chart of each SISO sub-decoder in the prior art decoder;

[0042] Figure 2 is a schematic diagram of the arithmetic unit used when calculating the state metrics of states 0 and 4 in the prior art;

[0043] Figure 3 is a circuit schematic diagram of the arithmetic unit used when calculating the state metrics of states 0 and 4 in the present invention;

[0044] Figure 4 is a step flow chart of a simplified turbo decoding method of the present invention. Detailed Embodiments

[0045] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0046] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments may be combined with each other.

[0047] Next, the present invention will be further described in conjunction with the accompanying drawings and specific embodiments, but it is not a limitation of the present invention.

[0048] The present invention provides a simplified turbo decoding circuit for calculating forward state metrics or backward state metrics, which is composed of several arithmetic units;

[0049] When the predetermined algebraic expressions in the preset expansion formula for calculating the state metrics of each state are the same, the same arithmetic unit is used to perform the operations of the predetermined operators in the same predetermined algebraic expression.

[0050] By simplifying and combining the forward state metric calculation / backward state metric calculation formulas of the radix-4 max-log-map decoding algorithm, the hardware operation resource overhead is reduced, thereby reducing the chip area.

[0051] Furthermore, the preset expansion formula for calculating the state metric of the j-th state at the (2i + 2)-th moment is as follows:

[0052]

[0053] where α 2i+2,j represents the calculated value of the state metric of the j-th state at the (2i + 2)-th moment;

[0054] each of k0, k1, k2, k3 represents a possible value of the input systematic bit at the 2i-th and (2i + 1)-th moments;

[0055] u1, u2, u3, u4 respectively represent one of k0, k1, k2, k3;

[0056] α 2i+2,j,k represents the calculated value of the state metric when the input systematic bit is k at the 2i-th and (2i + 1)-th moments, where k represents k0, k1, k2, or k3;

[0057] The expanded expressions of max(α 2i+2,j,u1 , α 2i+2,j,u2 ) and max(α 2i+2,j,u3 , α 2i+2,j,u4 ) are:

[0058] max(γ 1 - γ 2 , α 1 - α 2 ) + α 3 + γ 3 + γ 4 ;

[0059] where γ 1 , γ 2 , γ 3 , γ 4 represent branch metrics;

[0060] α 1 , α 2 , α 3 represent the relevant calculated values of the state metric before the (2i + 2)-th moment;

[0061] where γ 1 - γ 2 is the first algebraic expression, and the operation unit used is the first adder;

[0062] In the turbo decoding circuit, the same first algebraic expression in the preset expansion formula for calculating the state metrics of each state j shares a first adder.

[0063] Further, taking α 1 -α 2 as the second algebraic expression, the operation unit used is the second adder;

[0064] In the turbo decoding circuit, the same second algebraic expression in the preset expansion formula for calculating the state metrics of each state j shares a second adder.

[0065] Further, taking max(γ 1 -γ 2 ,α 1 -α 2 ) as the third algebraic expression, a first comparator is used for comparison operation;

[0066] In the turbo decoding circuit, the same third algebraic expression in the preset expansion formula for calculating the state metrics of each state j shares a first comparator.

[0067] Further, taking max(γ 1 -γ 2 ,α 1 -α 2 )+α 3 as the fourth algebraic expression, max(γ 1 -γ 2 ,α 1 -α 2 ) uses the first comparator, and the operation unit for operating with α 3 is the third adder;

[0068] In the turbo decoding circuit, the same fourth algebraic expression in the preset expansion formula for calculating the state metrics of each state j shares a third adder.

[0069] Further, taking γ 3 +γ 4 as the fifth algebraic expression, the operation unit used is the fourth adder;

[0070] In the turbo decoding circuit, the same fifth algebraic expression in the preset expansion formula for calculating the state metrics of each state j shares a fourth adder.

[0071] Further, in the turbo decoding circuit, the second algebraic expressions with opposite signs in the preset expansion formula for calculating the state metrics of each state j share a second adder;

[0072] For the forward second algebraic expression, the operation result output by the second adder is directly input to one input terminal of the corresponding first comparator;

[0073] For the second algebraic expression that is opposite to the positive second algebraic expression, the operation result output by the second adder is inverted and then compared in the corresponding first comparator.

[0074] Furthermore, in the turbo decoding circuit, the adder for performing addition operations on the branch metrics with preset values of 0 in γ 2 、γ 3 、γ 4 is omitted.

[0075] In the present invention, the output of the first adder and the output of the second adder are respectively connected to the inputs of the corresponding first comparators, and the output of the first comparator is connected to the input of the corresponding third adder.

[0076] The present invention also provides a simplified turbo decoder, which includes the aforementioned simplified turbo decoding circuit.

[0077] Furthermore, the turbo decoder includes two SISO decoders, and each SISO decoder includes the turbo decoding circuit.

[0078] Furthermore, each SISO decoder includes M processors, and the data to be decoded is divided into M data blocks and allocated to M processors; each processor includes N sliding windows (where N is an even number), and the M processors perform parallel decoding processing on the M data blocks to be decoded. Each processor includes a turbo decoding circuit for calculating the forward state metric and a turbo decoding circuit for calculating the backward state metric.

[0079] See Figure 4 , the present invention also provides a simplified turbo decoding method, which uses the aforementioned simplified turbo decoding circuit, and includes:

[0080] Step B1, when calculating the state metrics of each state j at the (2i + 2)-th moment, extract the data corresponding to each calculation term in the preset expansion formula according to the preset expansion formula for calculating the state metrics;

[0081] Step B2, input each data into the corresponding operation unit in the turbo decoding circuit, and the turbo decoding circuit outputs the calculation results of the state metrics of each state j at the (2i + 2)-th moment.

[0082] As Figure 2 shown, when the state j is 0, according to the calculation formula of the prior art, first sum to calculate α 2i+2,0,0 、α 2i+2,0,1 、α 2i+2,0,2 、α 2i+2,0,3, 8 adders are required. After pairwise comparison, 2 comparators are needed. For the final comparison of the two comparison results, 1 comparator is required. Similarly, when the state j is 4, 8 adders and 3 comparators are needed. As the state j ranges from 0 to 7, 64 adders and 24 comparators are required.

[0083] For specific applications, for example, calculating α in the prior art 2i+2,j The specific transformation process of the formula is as follows, j = {0, 1,..., 7}, and assume that in the transformation

[0084] (1) When the state j = 0, 4

[0085]

[0086] α 2i+2,0 = max(α 2i+2，0，0 , α 2i+2，0，1 , α 2i+2，0，2 , α 2i+2，0，3 ) = max(max(α 2i+2，0，0 , α 2i+2，0，2 ), max(α 2i+2，0，1 , α 2i+2,0,3 ))

[0087]

[0088] α 2i+2,4 = max(α 2i+2，4，0 , α 2i+2，4，1 , α 2i+2，4，2 , α 2i+2，4，3 ) =

[0089] max(max(α 2i+2，4，0 , α 2i+2，4，2 ), max(α 2i+2，4，1 , α 2i+2， 4, 3))

[0090]

[0091] As can be seen from the above formula, when the state j is 0 and 4:

[0092] There is the same first algebraic expression Reuse the first adder because is 0, and this first adder can also be omitted;

[0093] There is the same first algebraic expression Reuse 1 first adder ( Take the inverse and add);

[0094] There is the same second algebraic expression α 2i，1 -α2i,0 , reuse one second adder (α 2i,0 take the inverse and then add);

[0095] There is the same second algebraic expression α 2i，2 -α 2i,3 , reuse one second adder (α 2i,3 take the inverse and then add);

[0096] There is the same third algebraic expression reuse one first comparator;

[0097] There is the same third algebraic expression reuse one first comparator;

[0098] There is the same fourth algebraic expression reuse one third adder;

[0099] There is the same fourth algebraic expression reuse one and third adder;

[0100] In the fifth algebraic expression, omit one fourth adder;

[0101] In the fifth algebraic expression, one fourth adder is needed;

[0102] In addition, when the state j is 0, for and each addition operation requires one adder, that is, a total of 2 adders are needed;

[0103] In addition, when the state j is 4, an addition operation between the fourth algebraic expression and requires one fourth adder;

[0104] Finally, when the state j is 0 and 4, the last two outputs need to be finally compared and one result for each state is output, that is, 2 comparators are needed.

[0105] Therefore, when the state j is 0, 7 adders and 3 comparators are needed. When the state j is 4, due to the reuse of adders and comparators, only 2 additional adders and 1 comparator are needed, for a total of 9 adders and 4 comparators. The circuit diagram is as shown in Figure 3 shown.

[0106] (2) When the state j = 1, 5

[0107]

[0108] α 2i+2,5 = max(α 2i+2，5，0 , α2i+2，5，1 , α 2i+2，5，2 , α 2i+2，5，3 ) =

[0109] max(max(α 2i+2，5，0 , α 2i+2，5，2 ), max(α 2i+2，5，1 , α 2i+2,5,3 ))

[0110]

[0111] α 2i+2,1 = max(α 2i+2，1，0 , α 2i+2，1，1 , α 2i+2，1，2 , α 2i+2，1，3 ) =

[0112] max(max(α 2i+2，1，0 , α 2i+2，1，2 ), max(α 2i+2，1，1 , α 2i+2,1,3 ))

[0113]

[0114] As can be seen from the above formula, for states j = 1 and 5:

[0115] There is the same first algebraic expression and one first adder should be reused, but for 0, one adder can be omitted;

[0116] There is the same first algebraic expression and it is the same as states 0 and 4, so the above adder is reused and no additional adder is needed;

[0117] There is the same second algebraic expression α 2i，5 -α 2i,4 , and 1 second adder is reused (α 2i,4 is inverted and then added);

[0118] There is the same second algebraic expression α 2i,6 -α 2i,7 , and 1 second adder is reused (α 2i,7 is inverted and then added);

[0119] There is the same third algebraic expression and 1 first comparator is reused;

[0120] There is the same third algebraic expression and 1 first comparator is reused;

[0121] There is the same fourth algebraic expression Reuse one third adder;

[0122] There is the same fourth algebraic expression Reuse one third adder;

[0123] In the fifth algebraic expression, Omit the adder;

[0124] In the fifth algebraic expression, Use one adder, One adder is needed;

[0125] In addition, for the addition of the state pair of 1 2 adders are needed;

[0126] In addition, for the addition of the state pair of 5 2 adders are needed;

[0127] Finally, when the state j is 1 and 5, the last two outputs need to be finally compared and one result for each state needs to be output, that is, 2 comparators are needed.

[0128] Therefore, when the state j is 1 and 5, 10 additional adders and 4 comparators are needed.

[0129] When the state j is 0, 1, 4, 5, a total of 19 adders and 8 comparators are needed.

[0130] (3) When the state j = 2, 6

[0131]

[0132] α 2i+2,2 = max(α 2i+2，2，0 , α 2i+2，2，1 , α 2i+2，2，2 , α 2i+2，2，3 ) =

[0133] max(max(α 2i+2，2，0 , α 2i+2，2，2 ), max(α 2i+2，2，1 , α 2i+2，2，3 ))

[0134]

[0135] α 2i+2,6 = max(α 2i+2，6，0 , α 2i+2，6，1 , α 2i+2，6，2 , α 2i+2，6，3 ) =

[0136] max(max(α 2i+2，6，0, α 2i+2，6，2 ), max(α 2i+2，6，1 , α 2i+2,6，3 ))

[0137]

[0138] As can be seen from the above formula, for state j being 2 and 6:

[0139] There is the same first algebraic expression Reuse the adder, For the case of 0, one adder can be omitted;

[0140] There is the same first algebraic expression And it is the same as that in states 0 and 4. Reuse the above adder without the need for an additional adder;

[0141] There is the same second algebraic expression α 2i，0 -α 2i,1 , reuse the adder, and the second algebraic expression α 2i,1 -α 2i,0 in the previous states 0 and 4 has the opposite sign. Therefore, reuse the above adder without the need for an additional adder, but just take the inverse of the operation result and compare it in the corresponding comparator;

[0142] There is the same second algebraic expression α 2i,3 -α 2i,2 , reuse the adder, and the second algebraic expression α 2i,2 -α 2i,3 in the previous states 0 and 4 has the opposite sign. Therefore, reuse the above adder without the need for an additional adder, but just take the inverse of the operation result and compare it in the corresponding comparator;

[0143] There is the same third algebraic expression Reuse 1 first comparator;

[0144] There is the same third algebraic expression Reuse 1 first comparator;

[0145] There is the same fourth algebraic expression Reuse 1 third adder;

[0146] There is the same fourth algebraic expression Reuse 1 third adder;

[0147] In the fifth algebraic expression, Omit the adder;

[0148] There is the same fifth algebraic expression as that in state 1 Reuse the adder and omit one adder;

[0149] There is the same fifth algebraic expression as when the state is 5 Reuse the adder, saving one adder;

[0150] In state 2, the operation of the output result of the fourth algebraic expression and requires 1 adder;

[0151] In state 2, the operation of the output result of the fourth algebraic expression and requires 1 adder;

[0152] In state 6, the operation with requires 1 adder;

[0153] In state 6, the operation of the output result of the fourth algebraic expression and requires 1 adder.

[0154] Finally, when the state j is 2 and 6, the last two outputs need to be finally compared and one result for each state is output, that is, 2 comparators are required.

[0155] Therefore, when the state j is 2 and 6, 6 additional adders and 4 comparators are required.

[0156] When the state j is 0, 1, 3, 4, 5, 6, a total of 25 adders and 12 comparators are required.

[0157] (4) When the state j = 3, 7

[0158]

[0159] α 2i+2,3 = max(α 2i+2，3，0 , α 2i+2，3，1 , α 2i+2，3，2 , α 2i+2，3，3 ) =

[0160] max(max(α 2i+2，3，0 , α 2i+2，3，2 ), max(α 2i+2，3，1 , α 2i+2，3，3 ))

[0161]

[0162]

[0163] α 2i+2,7 = max(α 2i+2，7，0 , α 2i+2，7，1 , α 2i+2，7，2 , α 2i+2，7，3 ) =

[0164] max(max(α 2i+2，7，0, α 2i+2，7，2 ), max(α 2i+2，7，1 , α 2i+2,7,3 ))

[0165]

[0166] As can be seen from the above formula, for states j = 3 and 7:

[0167] There is the same first algebraic expression Reuse the adder, When it is 0, one adder can be omitted;

[0168] There is the same first algebraic expression And it is the same as that in states 0 and 4. Reuse the above adder without the need for an additional adder;

[0169] There is the same second algebraic expression α 2i，4 -α 2i,5 , reuse the adder, and it has the opposite sign to the second algebraic expression α 2i,5 -α 2i,4 in states 1 and 5 above. Therefore, reuse the above adder without the need for an additional adder, but just compare the result after taking the opposite in the corresponding comparator;

[0170] There is the same second algebraic expression α 2i,7 -α 2i,6 , reuse the adder, and it has the opposite sign to the second algebraic expression α 2i,6 -α 2i,7 in states 1 and 5 above. Therefore, reuse the above adder without the need for an additional adder, but just compare the result after taking the opposite in the corresponding comparator;

[0171] There is the same third algebraic expression Reuse 1 first comparator;

[0172] There is the same third algebraic expression Reuse 1 first comparator;

[0173] There is the same fourth algebraic expression Reuse 1 third adder;

[0174] There is the same fourth algebraic expression Reuse 1 third adder;

[0175] In the fifth algebraic expression, Omit the adder;

[0176] There is the same fifth algebraic expression as that in state 4 Reuse the adder and omit one adder;

[0177] When the state is 3, the operation of the output result of the fourth algebraic expression (the third adder) and requires 1 adder;

[0178] When the state is 3, the operation of the output result of the fourth algebraic expression (the third adder) and requires 1 adder;

[0179] When the state is 4, the operation of the output result of the fourth algebraic expression (the third adder) and requires 1 adder;

[0180] Finally, when the state j is 3 and 7, the last two outputs need to be finally compared and one result for each state is output, that is, 2 comparators are required.

[0181] Therefore, when the state j is 3 and 7, 5 additional adders and 4 comparators are required.

[0182] For the state j from 0 to 7, a total of 30 adders and 16 comparators are required. Compared with 64 adders and 24 adders in the prior art, 34 adders and 8 comparators are saved, reducing the number of operations and further reducing the hardware design area.

[0183] The above is only a preferred embodiment of the present invention, and thus does not limit the implementation manner and protection scope of the present invention. For those skilled in the art, it should be able to realize that all equivalent replacements and obvious changes made by using the description and illustration content of the present invention should be included in the protection scope of the present invention.

Claims

1. A simplified turbo decoding circuit for calculating a forward state metric or a backward state metric, characterized in that: It is composed of several computing units; When the predetermined algebraic expressions in the preset expansion formulas for calculating the state metrics of each state are the same, the same operation unit is used to perform the operation of the predetermined operator in the same predetermined algebraic expression.

2. A simplified turbo decoding circuit as claimed in claim 1, characterized in that: The preset expansion formula for calculating the state metric of the j-th state at the 2i+2th time is as follows: Among them, α 2i+2,j represents the calculated value of the state metric of the jth state at the 2i+2th time; Each of k0, k1, k2, and k3 represents a possible value of the input systematic bit at the 2ith and 2i+1th time instants; u1, u2, u3, u4 represent one of k0, k1, k2, k3 respectively; α 2i+2,j,k It is represented as the state metric calculation value when the input system bit is k at the 2ith and 2i+1th time, where k represents k0, k1, k2 or k3; max(α 2i+2,j,u1 ,α 2i+2,j,u2 ) and max(α 2i+2,j,u3 ,α 2i+2,j,u4 ) is expressed in the expanded form: max(γ1-γ2,α1-α2)+α3+γ3+γ4; Among them, γ1, γ2, γ3, and γ4 represent branch metrics; α1, α2, α3 represent the relevant state metric calculation values ​​before the 2i+2th moment; Wherein, γ1-γ2 is the first algebraic expression, and the operation unit used is the first adder; In the turbo decoding circuit, the same first algebraic expressions in the preset expansion formula for calculating the state metric of each state j share the same first adder.

3. A simplified turbo decoding circuit as claimed in claim 2, characterized in that: α1-α2 is used as the second algebraic expression, and the operation unit used is the second adder; In the turbo decoding circuit, the same second algebraic expressions in the preset expansion formula for calculating the state metric of each state j share the same second adder.

4. A simplified turbo decoding circuit as claimed in claim 2, characterized in that: Use max(γ1-γ2,α1-α2) as the third algebraic expression and use the first comparator for comparison operation; In the turbo decoding circuit, the same third algebraic expression in the preset expansion formula for calculating the state metric of each state j shares the same first comparator.

5. A simplified turbo decoding circuit as claimed in claim 2, characterized in that: max(γ1-γ2,α1-α2)+α3 is used as the fourth algebraic expression, max(γ1-γ2,α1-α2) uses the first comparator, and the operation unit that operates with α3 is the third adder; In the turbo decoding circuit, the same fourth algebraic expression in the preset expansion formula for calculating the state metric of each state j shares the same third adder.

6. A simplified turbo decoding circuit as claimed in claim 2, characterized in that: Taking γ3+γ4 as the fifth algebraic expression, the operation unit used is the fourth adder; In the turbo decoding circuit, the same fifth algebraic expression in the preset expansion formula for calculating the state metric of each state j shares the same fourth adder.

7. A simplified turbo decoding circuit as claimed in claim 3, characterized in that: In the turbo decoding circuit, the second algebraic expressions with opposite signs in the preset expansion formula for calculating the state metric of each state j share the same second adder; For the second algebraic expression in the forward direction, the operation result output by the second adder is directly input into an input terminal of the corresponding first comparator; For the second algebraic expression which is opposite to the positive second algebraic expression, the operation result output by the second adder is inverted and then compared in the corresponding first comparator.

8. A simplified turbo decoding circuit as claimed in claim 2, characterized in that: The turbo decoding circuit omits an adder for adding branch metrics with a preset value of 0 in γ2, γ3, and γ4.

9. A simplified turbo decoder, characterized in that A simplified turbo decoding circuit comprising the method according to any one of claims 1 to 8.

10. A simplified turbo decoding method, characterized in that: A simplified turbo decoding circuit according to any one of claims 1 to 8, comprising: Step B1, when calculating the state metric of each state j at the 2i+2th moment, extracting data corresponding to each calculation item in the preset expansion formula according to the preset expansion formula for calculating the state metric; Step B2, inputting each of the data into a corresponding operation unit in the turbo decoding circuit, and the turbo decoding circuit outputs a calculation result of the state metric of each state j at the 2i+2th moment.

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