Radio frequency signal parallel test circuit and method

Abstract

The invention relates to a radio frequency signal parallel test circuit and method, and relates to the field of radio frequency chips. A 3.3 V power supply is provided for the MCU chip through the testing machine, so that the P6 end of the MCU chip sends a 1KHz waveform to the DI end of the wireless signal transmitter, then the wireless signal transmitter is powered to transmit a 1KHz radio signal, and the transmitting function of the wireless signal transmitter is verified; the radio frequency chip and the wireless signal transmitter are connected through the control relay, and whether the receiving function is normal or not is tested; driving current under a 5V power supply is measured, and output end testing is completed; the SHUT end of the radio frequency chip is set to be 5V high level, so that the chip is ensured to be in a non-working state, and the high-impedance current at the moment is measured. Under the condition, chips with wireless signals and poor receiving functions can be eliminated, the incapable influence of errors of test equipment on test results is avoided, the accuracy and reliability of test data are ensured, the test time is shortened, and the production efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency chips, and particularly relates to a radio frequency signal parallel test circuit and method. Background Art

[0002] In today's highly developed technological era, radio frequency chips, as the core components of modern wireless communication systems, are of great importance. From daily used smartphones, tablets to large communication infrastructures such as base stations and satellite communications, radio frequency chips are everywhere and play a crucial role. In the field of communication, it is the key to realizing wireless data transmission and signal transceiver, ensuring that people can make voice calls, download and upload data anytime and anywhere; in electronic products such as wireless earphones and smart home devices, radio frequency chips enable efficient wireless connection and interaction between devices; in the medical field, like remote medical devices and wearable health monitoring devices, radio frequency chips help in the real-time transmission of medical data, providing support for remote diagnosis and health management; in the military field, radio frequency chips are even applied to key equipment such as radars and communication countermeasures, which is related to national defense security and military combat capabilities.

[0003] However, when currently testing the radio frequency signals of a single radio frequency chip, the existing testing technologies expose many insurmountable defects: On the one hand, the error problem existing in the testing equipment itself has always been a difficult problem plaguing the industry; due to factors such as the accuracy limitation of the components of the testing equipment, the non-ideality of the circuit design, and the performance drift after long-term use, when the testing equipment measures various parameters of the radio frequency chip, it will inevitably introduce errors; these errors accumulate and amplify, ultimately having an ineliminable impact on the test results, leading to misjudgment of the true performance of the radio frequency chip.

[0004] On the other hand, the signal interference problem in the testing environment is also extremely serious; during the actual testing process, there are various wireless signals around, such as signals from other communication devices and electromagnetic interference generated by electronic devices; these interference signals will mix into the test signals and interfere with the test results; when testing the signal reception sensitivity of the radio frequency chip, the interference signals may cause fluctuations in the test results, unable to accurately reflect the true reception performance of the chip, thus greatly reducing the accuracy of the test results.

[0005] In addition, due to the cumbersome current test process, the complex operation of test equipment, and the need for multiple repeated tests to eliminate the influence of errors and interference, the testing of a single radio frequency chip often consumes a large amount of time and labor costs; this not only reduces production efficiency but also increases the manufacturing cost of products, seriously affecting the economic benefits and market competitiveness of enterprises in today's increasingly competitive market. Therefore, the existing radio frequency chip testing technology urgently needs to be improved to overcome these existing defects. Summary of the Invention

[0006] The purpose of the present invention is to provide a radio frequency signal parallel testing circuit and method to solve the problems existing in the above-mentioned prior art.

[0007] To achieve the above purpose, the technical solution adopted by the present invention is as follows: In the first aspect, the present invention provides a [circuit or device not specified in the original, needs to be adjusted according to the context], including: an MCU chip, a TR6836 tester J1, a wireless signal transmitter, a first test radio frequency chip, and a second test radio frequency chip. The VDD terminal of the MCU chip is connected to the DPSC terminal of the TR6836 tester J1 and the VCC terminal of the wireless signal transmitter. The ANT terminal of the wireless signal transmitter is connected to an antenna. The P6 terminal of the MCU chip is connected to the DI terminal of the wireless signal transmitter. The DPSA terminal of the TR6836 tester J1 is connected to the VDD terminal of the first test radio frequency chip. The DPSE terminal of the TR6836 tester J1 is connected to the VDD terminal of the second test radio frequency chip. The GND terminal of the TR6836 tester J1 is connected to the GND terminal of the wireless signal transmitter, the GND terminal of the MCU chip, the GND1 terminal of the first test radio frequency chip, and the GND1 terminal of the second test radio frequency chip. Among them, the first test radio frequency chip is connected to the TR6836 tester J1 through a first relay circuit, and the second test radio frequency chip is connected to the TR6836 tester J1 through a second relay circuit.

[0008] In a possible implementation manner, the radio frequency signal parallel testing circuit further includes: a capacitor C1, a capacitor C2, an inductor L1, and an inductor L2. The first end of the inductor L1 is connected to the first end of the capacitor C1, and the second end of the inductor L1 is connected to the GND1 terminal of the first test radio frequency chip. The first end of the inductor L2 is connected to the ANT terminal of the wireless signal transmitter, and the second end of the inductor L2 is connected to the GND1 terminal of the first test radio frequency chip. The second end of the capacitor C1 is connected to the ANT terminal of the wireless signal transmitter. The first end of the capacitor C2 is connected to the GND1 terminal of the first test radio frequency chip, and the second end of the capacitor C2 is connected to the ANT terminal of the wireless signal transmitter.

[0009] In a possible implementation, the RF signal parallel test circuit further includes: a capacitor C3 and a capacitor C4. A first end of the capacitor C3 is connected to the GND1 terminal of the first test RF chip, and a second end of the capacitor C3 is connected to the VDD terminal of the first test RF chip; a first end of the capacitor C4 is connected to the GND1 terminal of the first test RF chip, and a second end of the capacitor C4 is connected to the CAGC terminal of the first test RF chip.

[0010] In a possible implementation, the first relay circuit includes a relay UR2 and a relay UR4. A left 1 terminal of the relay UR2 is connected to the UR2 terminal of the TR6836 tester J1, a right 1 terminal of the relay UR2 is connected to the 5V power supply of the TR6836 tester J1, a right 2 terminal of the relay UR2 is connected to the T3 channel of the TR6836 tester J1, a right 3 terminal of the relay UR2 is connected to the SHUT terminal of the first test RF chip, and a right 4 terminal of the relay UR2 is connected to the GND1 terminal of the first test RF chip; A left 1 terminal of the relay UR4 is connected to the UR4 terminal of the TR6836 tester J1, a right 1 terminal of the relay UR4 is connected to the 5V power supply of the TR6836 tester J1, a right 2 terminal of the relay UR4 is connected to the T1 channel of the TR6836 tester J1, a right 3 terminal of the relay UR4 is connected to the XOSC terminal of the first test RF chip, and a right 4 terminal of the relay UR4 is connected to the GND1 terminal of the first test RF chip through a crystal oscillator U1.

[0011] In a possible implementation, the first relay circuit further includes a relay UR5 and a relay UR6. A left 1 terminal of the relay UR5 is connected to the UR5 terminal of the TR6836 tester J1, a right 1 terminal of the relay UR5 is connected to the 5V power supply of the TR6836 tester J1, a right 2 terminal of the relay UR5 is connected to the T15 channel of the TR6836 tester J1, a right 3 terminal of the relay UR5 is connected to the RFIN terminal of the first test RF chip, and a right 4 terminal of the relay UR5 is connected to a first end of an inductor L1; A left 1 terminal of the relay UR6 is connected to the UR6 terminal of the TR6836 tester J1, a right 1 terminal of the relay UR6 is connected to the 5V power supply of the TR6836 tester J1, a right 2 terminal of the relay UR6 is connected to the GND1 terminal of the first test RF chip, a right 3 terminal of the relay UR6 is connected to the GND terminal of the TR6836 tester J1, and a right 4 terminal of the relay UR6 is connected to the GND2 terminal of the first test RF chip.

[0012] In a possible implementation, the second relay circuit includes a relay UR8 and a relay UR10. The left end 1 of the relay UR8 is connected to the UR8 terminal of the TR6836 tester J1. The right end 1 of the relay UR8 is connected to the 5V power supply of the TR6836 tester J1. The right end 2 of the relay UR8 is connected to the T19 channel of the TR6836 tester J1. The right end 3 of the relay UR8 is connected to the SHUT terminal of the second test radio frequency chip. The right end 4 of the relay UR8 is connected to the GND1 terminal of the second test radio frequency chip. The left end 1 of the relay UR10 is connected to the UR10 terminal of the TR6836 tester J1. The right end 1 of the relay UR10 is connected to the 5V power supply of the TR6836 tester J1. The right end 2 of the relay UR10 is connected to the T17 channel of the TR6836 tester J1. The right end 3 of the relay UR10 is connected to the XOSC terminal of the second test radio frequency chip. The right end 4 of the relay UR10 is connected to the GND1 terminal of the second test radio frequency chip through a crystal oscillator U2.

[0013] In a possible implementation, the second relay circuit further includes a relay UR11 and a relay UR12. The left end 1 of the relay UR11 is connected to the UR11 terminal of the TR6836 tester J1. The right end 1 of the relay UR11 is connected to the 5V power supply of the TR6836 tester J1. The right end 2 of the relay UR11 is connected to the T31 channel of the TR6836 tester J1. The right end 3 of the relay UR11 is connected to the RFIN terminal of the second test radio frequency chip. The right end 4 of the relay UR11 is connected to the first end of the inductor L1. The left end 1 of the relay UR12 is connected to the UR12 terminal of the TR6836 tester J1. The right end 1 of the relay UR12 is connected to the 5V power supply of the TR6836 tester J1. The right end 2 of the relay UR12 is connected to the GND1 terminal of the second test radio frequency chip. The right end 3 of the relay UR12 is connected to the GND terminal of the TR6836 tester J1. The right end 4 of the relay UR12 is connected to the GND2 terminal of the second test radio frequency chip.

[0014] In a second aspect, the present invention provides a method for parallel testing of radio frequency signals. The method is applied to the radio frequency signal parallel testing circuit as described above. The method includes: S1. Supply 3.3V power to the VDD terminal of the MCU chip through the TR6836 tester J1. The MCU chip starts to work, and the P6 terminal of the MCU chip sends a 1KHZ waveform to the DI terminal of the wireless signal transmitter. The TR6836 tester J1 then supplies 3.3V power to the VCC terminal of the wireless signal transmitter. The wireless signal transmitter starts to work and emits a 1KHZ radio signal. At this time, connect to the DI port of the wireless signal transmitter through the channel of the TR6836 tester J1 to test whether the waveform frequency of the DI terminal of the wireless signal transmitter is 1KHZ to determine whether the transmission function is normal and complete the test of the transmission function. S2. Open the UR2 terminal and UR8 terminal of the TR6836 tester J1. The right 3 terminal and right 4 terminal of the relay UR2 and the relay UR8 are conducted, that is, the SHUT terminal of the first test radio frequency chip and the second test radio frequency chip is connected to GND1. Open the UR4 terminal and UR10 terminal of the TR6836 tester J1. The right 3 terminal and right 4 terminal of the relay UR4 and the relay UR10 are conducted, that is, the XSCO terminals of the first test radio frequency chip and the second test radio frequency chip are respectively connected to GND1 through the crystal oscillator U2 and the crystal oscillator U1. Open the UR5 terminal and UR11 terminal of the TR6836 tester J1. The right 3 terminal and right 4 terminal of the relay UR5 and the relay UR11 are conducted, that is, the RFIN terminals of the first test radio frequency chip and the second test radio frequency chip are connected to the ANT terminal of the wireless signal transmitter. When the VDD terminals of the first test radio frequency chip and the second test radio frequency chip are powered on with 5V, the IKHZ waveform signal emitted from the DI terminal of the wireless signal transmitter is received by the RFIN ports of the first test radio frequency chip and the second test radio frequency chip. Subsequently, it is output from the DOUT ports of the first test radio frequency chip and the second test radio frequency chip. At this time, connect to the DOUT terminals of the first test radio frequency chip and the second test radio frequency chip through the channel of the TR6836 tester J1 to test whether the waveform frequency of the DOUT terminal is 1KHZ to determine whether the receiving function is normal and complete the test of the receiving function. S3. Continuing from the previous step, test the magnitude of the current flowing through the 5V power supply, that is, the drive current of the DOUT terminals of the first test radio frequency chip and the second test radio frequency chip, and complete the test of the drive current function of the output terminal. S4. Continuing from the previous step, close the UR2 and UR8 terminals of the TR6836 tester J1. The right 3 and right 4 terminals of the relay UR2 and the relay UR8 are disconnected, that is, the SHUT terminals of the first test RF chip and the second test RF chip are disconnected from GND1. At this time, the SHUT terminal of the first test RF chip is connected to the T3 channel of the TR6836 tester J1, and the SHUT terminal of the second test RF chip is connected to the T19 channel of the TR6836 tester J1. The TR6836 tester J1 applies a 5V voltage through the T3 channel and the T19 channel, that is, the SHUT terminals of the first test RF chip and the second test RF chip are in a high level state of 5V. At this time, the first test RF chip and the second test RF chip do not receive wireless signals and the chips do not work, that is, the output terminal is in a high impedance state. Measure the magnitude of the current flowing through the 5V power supply, that is, the high impedance state current, to complete the test of the high impedance state function.

[0015] The beneficial effects brought by the technical solution provided by the present invention at least include: The RF signal parallel test circuit and method provided by this technical solution use a TR6836 tester to provide a 3.3V power supply for the MCU chip, enabling its P6 terminal to send a 1KHz waveform to the DI terminal of the wireless signal transmitter, and then powering the wireless signal transmitter to transmit a 1KHz radio signal and verifying its transmission function; by controlling the relay to connect the RF chip and the wireless signal transmitter, test whether the receiving function is normal; measure the drive current under the 5V power supply to complete the output terminal test; by setting the SHUT terminal of the RF chip to a 5V high level, ensure that the chip is in a non-working state and measure the high impedance state current at this time. In this case, it is possible to avoid the interference of other signals as much as possible, eliminate chips with poor wireless signal generation and reception functions, avoid the ineliminable influence of the errors of the test equipment on the test results, quickly confirm whether the chip function is good, ensure the accuracy and reliability of the test data, shorten the test time, improve production efficiency, and save production costs. Description of the Drawings

[0016] The drawings are used to provide a further understanding of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the present invention and do not constitute a limitation to the present invention.

[0017] Figure 1 Shows a schematic structural diagram of a RF signal parallel test circuit provided by an exemplary embodiment of the present invention.

[0018] Figure 2 Shows a schematic flow diagram of a RF signal parallel test method provided by an exemplary embodiment of the present invention. Detailed implementation mode

[0019] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0020] First, a brief introduction to the components involved in this application: The left 1 end of the relays UR2, UR4, UR5, UR6, UR8, UR10, UR11, and UR12 is the signal control end, and the right 1 end is the power supply port. The right 1 end starts and closes the relay according to the control signal of the left 1 end; the right 2 end and the right 3 end are in a normally closed relationship, and the right 3 end and the right 4 end are in a normally open relationship.

[0021] The functions of each port of the MCU chip mentioned in the text: The VDD end is the 2.3 - 5V power input; the GND end is the ground input; the P6 end is the waveform output port.

[0022] The functions of each port of the TR6836 tester J1 mentioned in the text: The UR2, UR4, UR5, UR6, UR8, UR10, UR11, and UR12 ends are the signal control ends of the corresponding relays, low level disconnects, high level closes; the T1, T3, T4, T13, T15, T17, T19, T20, T29, and T31 digital channels can supply voltages from -2V to 6V and currents of 32MA, and measure voltages from -2V to 6V and currents of 32MA; the DPSA, DPSC, DPSE, and DPSG ends can supply voltages from -16 to +16 and currents of 1A, and measure voltages from -16 to +16 and currents of 1A; the GND end is the grounding end.

[0023] The functions of each port of the wireless signal transmitter mentioned in the text: The GND end is the ground input; the DI end is the waveform receiving end; the VCC end is the 3.3V power input; the ANT end is the antenna end, outputting wireless radio frequency signals.

[0024] The functions of each port of the first test radio frequency chip and the second test radio frequency chip mentioned in the text: The RNIF end is the antenna pin, for radio frequency signal input, and a matching network needs to be externally connected; the GND1 and GND2 ends are the ground inputs; the VDD end is the 2.5V - 5.5V power input; the SHUT end is the shutdown control pin, connected to high level to shut down, connected to low level to work; the DOUT end is the data output; the CAGC end is the automatic gain control pin, externally connected with a filter capacitor; the XOSC end is the crystal oscillator input pin, externally connected with a crystal or a reference clock.

[0025] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0026] Figure 1 FIG. shows a schematic structural diagram of a radio frequency signal parallel test circuit provided by an exemplary embodiment of the present invention. The radio frequency signal parallel test circuit includes: an MCU chip, a TR6836 tester J1, a wireless signal transmitter, a first test radio frequency chip, and a second test radio frequency chip. The VDD terminal of the MCU chip is connected to the DPSC terminal of the TR6836 tester J1 and the VCC terminal of the wireless signal transmitter. The ANT terminal of the wireless signal transmitter is connected to an antenna. The P6 terminal of the MCU chip is connected to the DI terminal of the wireless signal transmitter. The DPSA terminal of the TR6836 tester J1 is connected to the VDD terminal of the first test radio frequency chip. The DPSE terminal of the TR6836 tester J1 is connected to the VDD terminal of the second test radio frequency chip. The GND terminal of the TR6836 tester J1 is connected to the GND terminal of the wireless signal transmitter, the GND terminal of the MCU chip, the GND1 terminal of the first test radio frequency chip, and the GND1 terminal of the second test radio frequency chip. Among them, the first test radio frequency chip is connected to the TR6836 tester J1 through a first relay circuit, and the second test radio frequency chip is connected to the TR6836 tester J1 through a second relay circuit.

[0027] In one example, the models of both the first test radio frequency chip and the second test radio frequency chip are JSC3090SO8B, which are represented as the first test radio frequency chip JSC3090SO8B① and the second test radio frequency chip JSC3090SO8B② in the figure.

[0028] In the embodiment of the present application, the VDD terminal of the MCU chip is connected to the DPSC terminal of J1 of the TR6836 tester and the VCC terminal of the wireless signal transmitter. This connection provides a stable power input for the entire system. The VDD terminal of the MCU chip can accept a power supply of 2.3 - 5V. The DPSC terminal of J1 of the TR6836 tester can provide a voltage of -16 - +16V and a current of 1A. The VCC terminal of the wireless signal transmitter requires a 3.3V power supply. Such a connection can ensure that the MCU chip, J1 of the TR6836 tester, and the wireless signal transmitter can all work under suitable power supply conditions. The ANT terminal of the wireless signal transmitter is connected to the antenna, which enables the wireless signal transmitter to convert the electrical signal into a wireless radio frequency signal and radiate it through the antenna, providing an actual working signal environment for testing the radio frequency chip. The P6 terminal of the MCU chip is connected to the DI terminal of the wireless signal transmitter as a waveform output port, and can transmit a specific waveform signal to the wireless signal transmitter, thereby controlling the characteristics of its transmitted signal, such as frequency, amplitude, etc. The DPSA terminal of J1 of the TR6836 tester is connected to the VDD terminal of the first test radio frequency chip, and the DPSE terminal is connected to the VDD terminal of the second test radio frequency chip, providing a power supply of 2.5V - 5.5V for the two test radio frequency chips to ensure the normal operation of the chips. The GND terminal of J1 of the TR6836 tester is connected to the ground terminals of the wireless signal transmitter, the MCU chip, the first test radio frequency chip, and the second test radio frequency chip, establishing a unified ground reference and reducing the influence of electromagnetic interference and noise on the test results.

[0029] Specifically, the parallel test circuit for radio frequency signals further includes: capacitor C1, capacitor C2, inductor L1, inductor L2, capacitor C3, and capacitor C4. The first end of inductor L1 is connected to the first end of capacitor C1, and the second end of inductor L1 is connected to the GND1 terminal of the first test radio frequency chip; the first end of inductor L2 is connected to the ANT terminal of the wireless signal transmitter, and the second end of inductor L2 is connected to the GND1 terminal of the first test radio frequency chip; the second end of capacitor C1 is connected to the ANT terminal of the wireless signal transmitter; the first end of capacitor C2 is connected to the GND1 terminal of the first test radio frequency chip, and the second end of capacitor C2 is connected to the ANT terminal of the wireless signal transmitter; the first end of capacitor C3 is connected to the GND1 terminal of the first test radio frequency chip, and the second end of capacitor C3 is connected to the VDD terminal of the first test radio frequency chip; the first end of capacitor C4 is connected to the GND1 terminal of the first test radio frequency chip, and the second end of capacitor C4 is connected to the CAGC terminal of the first test radio frequency chip.

[0030] In the embodiment of the present application, in the network formed by capacitors C1, C2, inductors L1, and L2, inductor L1 is connected to capacitor C1 and then connected to the GND1 terminal of the first test RF chip. Inductor L2 is connected to the ANT terminal of the wireless signal transmitter and the GND1 terminal of the chip. Capacitor C2 is also connected to the GND1 terminal of the chip and the ANT terminal of the wireless signal transmitter. This combination can achieve impedance matching and filtering functions, optimizing the transmission of RF signals. Capacitor C3 is connected across the GND1 terminal and the VDD terminal of the first test RF chip, playing a decoupling role to stabilize the chip power supply. Capacitor C4 is connected to the GND1 terminal and the CAGC terminal of the chip, providing a filtering function for the automatic gain control pin to ensure the stable operation of the chip's automatic gain control circuit.

[0031] Further, the first relay circuit includes relay UR2 and relay UR4. The left 1 terminal of relay UR2 is connected to the UR2 terminal of TR6836 tester J1. The right 1 terminal of relay UR2 is connected to the 5V power supply of TR6836 tester J1. The right 2 terminal of relay UR2 is connected to the T3 channel of TR6836 tester J1. The right 3 terminal of relay UR2 is connected to the SHUT terminal of the first test RF chip. The right 4 terminal of relay UR2 is connected to the GND1 terminal of the first test RF chip. The left 1 terminal of relay UR4 is connected to the UR4 terminal of TR6836 tester J1. The right 1 terminal of relay UR4 is connected to the 5V power supply of TR6836 tester J1. The right 2 terminal of relay UR4 is connected to the T1 channel of TR6836 tester J1. The right 3 terminal of relay UR4 is connected to the XOSC terminal of the first test RF chip. The right 4 terminal of relay UR4 is connected to the GND1 terminal of the first test RF chip through crystal oscillator U1.

[0032] Furthermore, the first relay circuit further includes relay UR5 and relay UR6. The left 1 terminal of relay UR5 is connected to the UR5 terminal of TR6836 tester J1. The right 1 terminal of relay UR5 is connected to the 5V power supply of TR6836 tester J1. The right 2 terminal of relay UR5 is connected to the T15 channel of TR6836 tester J1. The right 3 terminal of relay UR5 is connected to the RFIN terminal of the first test RF chip. The right 4 terminal of relay UR5 is connected to the first end of inductor L1. The left 1 terminal of relay UR6 is connected to the UR6 terminal of TR6836 tester J1. The right 1 terminal of relay UR6 is connected to the 5V power supply of TR6836 tester J1. The right 2 terminal of relay UR6 is connected to the GND1 terminal of the first test RF chip. The right 3 terminal of relay UR6 is connected to the GND terminal of TR6836 tester J1. The right 4 terminal of relay UR6 is connected to the GND2 terminal of the first test RF chip.

[0033] Specifically, the second relay circuit includes relay UR8 and relay UR10. The left end 1 of relay UR8 is connected to the UR8 terminal of tester J1 of TR6836. The right end 1 of relay UR8 is connected to the 5V power supply of tester J1 of TR6836. The right end 2 of relay UR8 is connected to channel T19 of tester J1 of TR6836. The right end 3 of relay UR8 is connected to the SHUT terminal of the second test radio frequency chip. The right end 4 of relay UR8 is connected to the GND1 terminal of the second test radio frequency chip. The left end 1 of relay UR10 is connected to the UR10 terminal of tester J1 of TR6836. The right end 1 of relay UR10 is connected to the 5V power supply of tester J1 of TR6836. The right end 2 of relay UR10 is connected to channel T17 of tester J1 of TR6836. The right end 3 of relay UR10 is connected to the XOSC terminal of the second test radio frequency chip. The right end 4 of relay UR10 is connected to the GND1 terminal of the second test radio frequency chip through crystal oscillator U2.

[0034] More specifically, the second relay circuit further includes relay UR11 and relay UR12. The left end 1 of relay UR11 is connected to the UR11 terminal of tester J1 of TR6836. The right end 1 of relay UR11 is connected to the 5V power supply of tester J1 of TR6836. The right end 2 of relay UR11 is connected to channel T31 of tester J1 of TR6836. The right end 3 of relay UR11 is connected to the RFIN terminal of the second test radio frequency chip. The right end 4 of relay UR11 is connected to the first end of inductor L1. The left end 1 of relay UR12 is connected to the UR12 terminal of tester J1 of TR6836. The right end 1 of relay UR12 is connected to the 5V power supply of tester J1 of TR6836. The right end 2 of relay UR12 is connected to the GND1 terminal of the second test radio frequency chip. The right end 3 of relay UR12 is connected to the GND terminal of tester J1 of TR6836. The right end 4 of relay UR12 is connected to the GND2 terminal of the second test radio frequency chip.

[0035] In the embodiment of the present application, taking the first relay circuit as an example, the left terminal 1 of the relay UR2 is connected to the UR2 terminal of the TR6836 tester J1. When a high level is output from the UR2 terminal, the 5V power supply at the right terminal 1 of the relay UR2 activates the relay, and the right terminal 2 and the right terminal 3 are closed, transmitting the T3 channel signal of the TR6836 tester J1 to the SHUT terminal of the first test radio frequency chip. If it is a high level, the chip can be turned off; the left terminal 1 of the relay UR4 is connected to the UR4 terminal of the TR6836 tester J1. Similarly, it controls the transmission of the T1 channel signal to the XOSC terminal of the chip to provide a crystal oscillator input signal for the chip; the relay UR5 can control the transmission of the T15 channel signal of the TR6836 tester J1 to the RFIN terminal of the chip as a radio frequency signal input; the relay UR6 can control the grounding state of the GND2 terminal of the chip. Similarly, the second relay circuit plays a similar control role for the second test radio frequency chip.

[0036] Figure 2 The flowchart of a radio frequency signal parallel testing method provided by an exemplary embodiment of the present invention is shown. This radio frequency signal parallel testing method is applied to the above radio frequency signal parallel testing circuit, and this method includes the following steps: Step S1: Supply a 3.3V power supply to the VDD terminal of the MCU chip through the TR6836 tester J1. The MCU chip starts to work, and the P6 terminal of the MCU chip sends a 1KHZ waveform to the DI terminal of the wireless signal transmitter; the TR6836 tester J1 then supplies a 3.3V power supply to the VCC terminal of the wireless signal transmitter. The wireless signal transmitter starts to work and emits a 1KHZ radio signal; at this time, connect to the DI port of the wireless signal transmitter through the channel of the TR6836 tester J1 to test whether the waveform frequency of the DI terminal of the wireless signal transmitter is 1KHZ to determine whether the transmission function is normal, and complete the test of the transmission function.

[0037] Specifically, in this step, the TR6836 tester J1 supplies a 3.3V power supply to the VDD terminal of the MCU chip, which provides a suitable operating voltage for the MCU chip. Since the MCU chip requires a stable power supply to operate properly, the VDD terminal is its power input port, and the 3.3V voltage can ensure the normal operation of the internal circuit of the chip, enabling the chip to start executing the preset programs and functions. After the MCU chip starts working, its P6 terminal sends a 1KHZ waveform to the DI terminal of the wireless signal transmitter. The P6 terminal, as a waveform output port, transmits the waveform signal of a specific frequency to the wireless signal transmitter. This waveform signal is the basic signal for subsequent wireless signal transmission and is used to control the characteristics such as the frequency of the wireless signal transmitted by the wireless signal transmitter. The TR6836 tester J1 then supplies a 3.3V power supply to the VCC terminal of the wireless signal transmitter, providing the energy required for the wireless signal transmitter to operate. The VCC terminal is the power input port of the wireless signal transmitter, and the 3.3V power supply causes the RF circuit inside the transmitter to start working, converting the received waveform signal at the DI terminal into a radio signal. After the wireless signal transmitter transmits a 1KHZ radio signal, it is connected to the DI port of the wireless signal transmitter through the channel of the TR6836 tester J1 to test whether the waveform frequency at the DI terminal is 1KHZ. If the measured frequency is 1KHZ, it indicates that the wireless signal transmitter can correctly receive and process the waveform signal from the MCU chip, and the frequency of the transmitted radio signal meets the expectation, and the transmission function is normal; if the frequency does not meet 1KHZ, it indicates that there is a problem in the signal processing or transmission process of the transmitter, and the transmission function may be abnormal. Through this step, the transmission function of the wireless signal transmitter can be quickly and effectively verified.

[0038] Step S2: Turn on the UR2 terminal and UR8 terminal of the TR6836 tester J1. The right 3 terminal and right 4 terminal of relay UR2 and relay UR8 are conducted, that is, the SHUT terminals of the first test radio frequency chip and the second test radio frequency chip are connected to GND1; turn on the UR4 terminal and UR10 terminal of the TR6836 tester J1. The right 3 terminal and right 4 terminal of relay UR4 and relay UR10 are conducted, that is, the XSCO terminals of the first test radio frequency chip and the second test radio frequency chip are respectively connected to GND1 through crystal oscillator U2 and crystal oscillator U1; turn on the UR5 terminal and UR11 terminal of the TR6836 tester J1. The right 3 terminal and right 4 terminal of relay UR5 and relay UR11 are conducted, that is, the RFIN terminals of the first test radio frequency chip and the second test radio frequency chip are connected to the ANT terminal of the wireless signal transmitter; when the VDD terminals of the first test radio frequency chip and the second test radio frequency chip are powered on with 5V, the IKHZ waveform signal emitted by the DI terminal of the wireless signal transmitter is received by the RFIN ports of the first test radio frequency chip and the second test radio frequency chip; then it is output from the DOUT ports of the first test radio frequency chip and the second test radio frequency chip. At this time, it is connected to the DOUT terminals of the first test radio frequency chip and the second test radio frequency chip through the channel of the TR6836 tester J1 to test whether the waveform frequency of the DOUT terminal is 1KHZ to judge whether the receiving function is normal, and complete the test of the receiving function.

[0039] Specifically, in this step, by opening the UR2 terminal and UR8 terminal of the TR6836 tester J1, the right 3 terminal and right 4 terminal of the relay UR2 and the relay UR8 are conducted, so that the SHUT terminals of the first test RF chip and the second test RF chip are connected to GND1. The SHUT terminal is a shutdown control pin. When connected to a low level (GND1 is the ground level, i.e., low level), the chip is in the working state. This step sets the chip to the working mode that can receive signals. Open the UR4 terminal and UR10 terminal of the TR6836 tester J1. The right 3 terminal and right 4 terminal of the relay UR4 and the relay UR10 are conducted, so that the XSCO terminals of the first test RF chip and the second test RF chip are respectively connected to GND1 through the crystal oscillator U2 and the crystal oscillator U1. The XSCO terminal is a crystal oscillator input pin. The crystal oscillator provides a stable clock signal to ensure that the internal circuit of the chip operates at an accurate clock frequency, guaranteeing the accuracy of signal processing and operation of the chip. Open the UR5 terminal and UR11 terminal of the TR6836 tester J1. The right 3 terminal and right 4 terminal of the relay UR5 and the relay UR11 are conducted, and the RFIN terminals of the first test RF chip and the second test RF chip are connected to the ANT terminal of the wireless signal transmitter. The RFIN terminal is an antenna pin for receiving RF signals, thus establishing a transmission path for wireless signals from the transmitter to the test chip. When the VDD terminal of the first test RF chip and the second test RF chip is powered on with 5V, the chip obtains sufficient energy to start normal operation. The 1KHZ waveform signal emitted by the DI terminal of the wireless signal transmitter is transmitted to the RFIN port of the chip through the ANT terminal. After the chip processes the signal, it is output from the DOUT port. Connect to the DOUT terminals of the first test RF chip and the second test RF chip through the channel of the TR6836 tester J1 to test whether the waveform frequency of the DOUT terminal is 1KHZ. If the frequency is 1KHZ, it indicates that the chip can correctly receive, process, and output a signal with the same frequency as the input, and the receiving function is normal; if the frequency does not meet 1KHZ, it indicates that there is a problem in the signal receiving or processing process of the chip, and the receiving function may have a fault.

[0040] Step S3: Continuing from the previous step, test the magnitude of the current flowing through the 5V power supply, that is, the drive current of the DOUT terminals of the first test RF chip and the second test RF chip, to complete the drive current function test of the output terminal.

[0041] Specifically, after the reception function test is completed in this step, the chip is in a normal working state and outputs a signal from the DOUT port. At this time, measure the magnitude of the current flowing through the 5V power supply, that is, the drive current at the DOUT terminals of the first test RF chip and the second test RF chip. The drive current reflects the ability of the chip's output terminal to drive an external load, and different application scenarios have different requirements for the drive current at the chip's output terminal. By measuring the drive current, it can be determined whether the drive ability of the chip's output terminal meets the design requirements. If the drive current is too large or too small, it may affect the normal connection and operation of the chip and the subsequent circuit. This step helps to evaluate the performance and reliability of the chip in actual applications.

[0042] Step S4: Continuing from the previous step, turn off the UR2 terminal and the UR8 terminal of the TR6836 tester J1. The right 3 terminal and the right 4 terminal of the relay UR2 and the relay UR8 are disconnected, that is, the SHUT terminals of the first test RF chip and the second test RF chip are disconnected from GND1. At this time, the SHUT terminal of the first test RF chip is connected to the T3 channel of the TR6836 tester J1, and the SHUT terminal of the second test RF chip is connected to the T19 channel of the TR6836 tester J1. The TR6836 tester J1 applies a 5V voltage through the T3 channel and the T19 channel, that is, the SHUT terminals of the first test RF chip and the second test RF chip are in a high-level state of 5V. At this time, the first test RF chip and the second test RF chip do not receive wireless signals, and the chip does not work, that is, the output terminal is in a high-impedance state. Measure the magnitude of the current flowing through the 5V power supply, that is, the high-impedance state current, and complete the test of the high-impedance state function.

[0043] Specifically, in this step, by turning off the UR2 terminal and the UR8 terminal of the TR6836 tester J1, the right 3 terminal and the right 4 terminal of the relay UR2 and the relay UR8 are disconnected, and the SHUT terminals of the first test RF chip and the second test RF chip are disconnected from GND1. Then, the TR6836 tester J1 applies a 5V voltage to the SHUT terminals of the first test RF chip and the second test RF chip through the T3 channel and the T19 channel, so that the SHUT terminals are in a high-level state of 5V. Since the SHUT terminal is a shutdown control pin, when a high level is connected, the chip does not receive wireless signals and is in a non-working state, and the output terminal presents a high-impedance state. When the chip is in a high-impedance state, measure the magnitude of the current flowing through the 5V power supply, that is, the high-impedance state current. The high-impedance state current reflects the power consumption of the chip in the non-working state. Ideally, the high-impedance state current should be very small. If the high-impedance state current is too large, it means that the chip still has a large energy consumption when it is not working, and there may be problems such as leakage, which will affect the overall power consumption and stability of the chip. Through this step, it can be verified whether the performance of the chip in the shutdown state meets the requirements.

[0044] In summary, for the RF signal parallel test circuit and method provided by this technical solution, the TR6836 tester provides a 3.3V power supply for the MCU chip, enabling its P6 terminal to send a 1KHz waveform to the DI terminal of the wireless signal transmitter. Then, power is supplied to the wireless signal transmitter to emit a 1KHz radio signal, and its emission function is verified. The relay is controlled to connect the RF chip and the wireless signal transmitter to test whether the receiving function is normal. The drive current under a 5V power supply is measured to complete the output terminal test. By setting the SHUT terminal of the RF chip to a 5V high level, it is ensured that the chip is in a non-operating state and the high-impedance state current is measured at this time. In this case, interference from other signals can be avoided as much as possible, chips with poor wireless signal generation and receiving functions can be eliminated, the influence of the errors of the test equipment on the test results that cannot be eliminated can be avoided, the chip function can be quickly confirmed to be good, the accuracy and reliability of the test data can be guaranteed, the test time can be shortened, the production efficiency can be improved, and the production cost can be saved.

[0045] It can be understood that the specific examples in this article are only to help those skilled in the art better understand the present disclosure, rather than limiting the scope of the present invention.

[0046] It can be understood that in various embodiments of this specification, the magnitude of the serial numbers of the various processes does not mean the sequence of execution, and the execution sequence of the various processes should be determined by their functions and internal logics, and should not constitute any limitation to the implementation process of the present disclosure.

[0047] It can be understood that the various embodiments described in this specification can be implemented alone or in combination, and the present disclosure does not limit this.

[0048] Unless otherwise specified, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by those skilled in the technical field of this specification. The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the scope of this specification. The term "and / or" used in this specification includes any and all combinations of one or more of the related listed items. The singular forms "a", "above", and "the" used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0049] As described above, this is only the specific embodiment of this specification, but the protection scope of the present invention is not limited thereto. Any person skilled in the technical field of this technology can easily think of changes or substitutions within the technical scope disclosed in this specification, and all should be covered by the protection scope of this specification. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A radio frequency signal parallel test circuit, characterized in that: include: MCU chip, TR6836 test machine J1, wireless signal transmitter, a first test RF chip, and a second test RF chip, the VDD end of the MCU chip is connected to the DPSC end of the TR6836 test machine J1 and the VCC end of the wireless signal transmitter, the ANT end of the wireless signal transmitter is connected to the antenna, the P6 end of the MCU chip is connected to the DI end of the wireless signal transmitter, the DPSA end of the TR6836 test machine J1 is connected to the VDD end of the first test RF chip, the DPSE end of the TR6836 test machine J1 is connected to the VDD end of the second test RF chip, and the GND end of the TR6836 test machine J1 is connected to the GND end of the wireless signal transmitter, the GND end of the MCU chip, the GND1 end of the first test RF chip, and the GND1 end of the second test RF chip; The first test RF chip is connected to the TR6836 test machine J1 through a first relay circuit, and the second test RF chip is connected to the TR6836 test machine J1 through a second relay circuit.

2. The radio frequency signal parallel test circuit according to claim 1, characterized in that: Also includes: Capacitor C1, capacitor C2, inductor L1, and inductor L2, the first end of the inductor L1 is connected to the first end of the capacitor C1, and the second end of the inductor L1 is connected to the GND1 end of the first test RF chip; the first end of the inductor L2 is connected to the ANT end of the wireless signal transmitter, and the second end of the inductor L2 is connected to the GND1 end of the first test RF chip; the second end of the capacitor C1 is connected to the ANT end of the wireless signal transmitter; the first end of the capacitor C2 is connected to the GND1 end of the first test RF chip, and the second end of the capacitor C2 is connected to the ANT end of the wireless signal transmitter.

3. The radio frequency signal parallel test circuit according to claim 1, characterized in that: Also includes: Capacitor C3 and capacitor C4, the first end of the capacitor C3 is connected to the GND1 end of the first test RF chip, and the second end of the capacitor C3 is connected to the VDD end of the first test RF chip; the first end of the capacitor C4 is connected to the GND1 end of the first test RF chip, and the second end of the capacitor C4 is connected to the CAGC end of the first test RF chip.

4. The radio frequency signal parallel test circuit according to claim 2, characterized in that: The first relay circuit includes a relay UR2 and a relay UR4, the left end 1 of the relay UR2 is connected to the UR2 end of the TR6836 tester J1, the right end 1 of the relay UR2 is connected to the 5V power supply of the TR6836 tester J1, the right end 2 of the relay UR2 is connected to the T3 channel of the TR6836 tester J1, the right end 3 of the relay UR2 is connected to the SHUT end of the first test RF chip, and the right end 4 of the relay UR2 is connected to the GND1 end of the first test RF chip; The left end 1 of the relay UR4 is connected to the UR4 end of the TR6836 test machine J1, the right end 1 of the relay UR4 is connected to the 5V power supply of the TR6836 test machine J1, the right end 2 of the relay UR4 is connected to the T1 channel of the TR6836 test machine J1, the right end 3 of the relay UR4 is connected to the XOSC end of the first test RF chip, and the right end 4 of the relay UR4 is connected to the GND1 end of the first test RF chip through the crystal oscillator U1.

5. The radio frequency signal parallel test circuit according to claim 4, characterized in that: The first relay circuit also includes a relay UR5 and a relay UR6, the left end 1 of the relay UR5 is connected to the UR5 end of the TR6836 test machine J1, the right end 1 of the relay UR5 is connected to the 5V power supply of the TR6836 test machine J1, the right end 2 of the relay UR5 is connected to the T15 channel of the TR6836 test machine J1, the right end 3 of the relay UR5 is connected to the RFIN end of the first test RF chip, and the right end 4 of the relay UR5 is connected to the first end of the inductor L1; The left end 1 of the relay UR6 is connected to the UR6 end of the TR6836 test machine J1, the right end 1 of the relay UR6 is connected to the 5V power supply of the TR6836 test machine J1, the right end 2 of the relay UR6 is connected to the GND1 end of the first test RF chip, the right end 3 of the relay UR6 is connected to the GND end of the TR6836 test machine J1, and the right end 4 of the relay UR6 is connected to the GND2 end of the first test RF chip.

6. The radio frequency signal parallel test circuit according to claim 2, characterized in that: The second relay circuit includes a relay UR8 and a relay UR10, the left end 1 of the relay UR8 is connected to the UR8 end of the TR6836 test machine J1, the right end 1 of the relay UR8 is connected to the 5V power supply of the TR6836 test machine J1, the right end 2 of the relay UR8 is connected to the T19 channel of the TR6836 test machine J1, the right end 3 of the relay UR8 is connected to the SHUT end of the second test RF chip, and the right end 4 of the relay UR8 is connected to the GND1 end of the second test RF chip; The left end 1 of the relay UR10 is connected to the UR10 end of the TR6836 test machine J1, the right end 1 of the relay UR10 is connected to the 5V power supply of the TR6836 test machine J1, the right end 2 of the relay UR10 is connected to the T17 channel of the TR6836 test machine J1, the right end 3 of the relay UR10 is connected to the XOSC end of the second test RF chip, and the right end 4 of the relay UR10 is connected to the GND1 end of the second test RF chip through the crystal oscillator U2.

7. The radio frequency signal parallel test circuit according to claim 6, characterized in that: The second relay circuit also includes a relay UR11 and a relay UR12, the left end 1 of the relay UR11 is connected to the UR11 end of the TR6836 test machine J1, the right end 1 of the relay UR11 is connected to the 5V power supply of the TR6836 test machine J1, the right end 2 of the relay UR11 is connected to the T31 channel of the TR6836 test machine J1, the right end 3 of the relay UR11 is connected to the RFIN end of the second test RF chip, and the right end 4 of the relay UR11 is connected to the first end of the inductor L1; The left end 1 of the relay UR12 is connected to the UR12 end of the TR6836 test machine J1, the right end 1 of the relay UR12 is connected to the 5V power supply of the TR6836 test machine J1, the right end 2 of the relay UR12 is connected to the GND1 end of the second test RF chip, the right end 3 of the relay UR12 is connected to the GND end of the TR6836 test machine J1, and the right end 4 of the relay UR12 is connected to the GND2 end of the second test RF chip.

8. A radio frequency signal parallel testing method, the method being applied to the radio frequency signal parallel testing circuit according to any one of claims 1 to 7, characterized in that: The method comprises: S1. Supply 3.3V power to the VDD terminal of the MCU chip through the TR6836 test machine J1, and the MCU chip starts to work. The P6 terminal of the MCU chip sends a 1KHZ waveform to the DI terminal of the wireless signal transmitter; The TR6836 tester J1 then supplies 3.3V power to the VCC terminal of the wireless signal transmitter, and the wireless signal transmitter starts to work and transmits a 1KHZ radio signal; At this time, the channel of the TR6836 test machine J1 is connected to the DI port of the wireless signal transmitter to test whether the waveform frequency of the DI end of the wireless signal transmitter is 1KHZ, so as to determine whether the transmission function is normal and complete the test of the transmission function; S2, open the UR2 terminal and the UR8 terminal of the TR6836 test machine J1, the right 3 terminal and the right 4 terminal of the relay UR2 and the relay UR8 are turned on, that is, the SHUT terminal of the first test RF chip and the second test RF chip is connected to GND1; Open the UR4 terminal and the UR10 terminal of the TR6836 test machine J1, and the right 3 terminal and the right 4 terminal of the relay UR4 and the relay UR10 are turned on, that is, the XSCO terminal of the first test RF chip and the second test RF chip are connected to GND1 through the crystal oscillator U2 and the crystal oscillator U1 respectively; Open the UR5 terminal and the UR11 terminal of the TR6836 test machine J1, and the right 3 terminal and the right 4 terminal of the relay UR5 and the relay UR11 are turned on, that is, the RFIN terminals of the first test RF chip and the second test RF chip are connected to the ANT terminal of the wireless signal transmitter; When the VDD terminals of the first test RF chip and the second test RF chip are powered on with 5V, the 1KHZ waveform signal emitted by the DI terminal of the wireless signal transmitter is received by the RFIN ports of the first test RF chip and the second test RF chip; Then, the DOUT ports of the first test RF chip and the second test RF chip are outputted, and at this time, the channel of the TR6836 test machine J1 is connected to the DOUT terminals of the first test RF chip and the second test RF chip to test whether the waveform frequency of the DOUT terminal is 1KHZ, so as to determine whether the receiving function is normal, and complete the test of the receiving function; S3, following the previous step, testing the current flowing through the 5V power supply, that is, the driving current of the DOUT terminal of the first test RF chip and the second test RF chip, and completing the driving current function test of the output terminal; S4, continuing from the previous step, close the UR2 terminal and the UR8 terminal of the TR6836 test machine J1, disconnect the right 3 terminal and the right 4 terminal of the relay UR2 and the relay UR8, that is, disconnect the SHUT terminal of the first test RF chip and the second test RF chip from GND1; At this time, the SHUT end of the first test RF chip is connected to the T3 channel of the TR6836 test machine J1, and the SHUT end of the second test RF chip is connected to the T19 channel of the TR6836 test machine J1. The TR6836 test machine J1 applies a 5V voltage through the T3 channel and the T19 channel, that is, the SHUT ends of the first test RF chip and the second test RF chip are in a high level state of 5V; At this time, the first test RF chip and the second test RF chip do not receive wireless signals, and the chips do not work, that is, the output end is in a high-impedance state; the current flowing through the 5V power supply is tested, that is, the high-impedance current, to complete the test of the high-impedance function.

Images