Video processing method, apparatus, device, storage medium and program product

Abstract

This application relates to a video processing method applied to a processor of a computer device. The computer device further includes an acquisition unit, a memory unit, a blocking unit, and an encoding unit. The memory unit contains pre-allocated cache space. The method includes: receiving a row interrupt instruction triggered by the acquisition unit after each row interrupt instruction, while the acquisition unit is cyclically filling the cache space with acquired source video data in a row-filling manner; updating the first cache address of the cache space to the blocking unit in response to the row interrupt instruction; and after the blocking unit receives a data read request sent by the encoding unit, and determines whether to allow the data read request based on the first cache address and a second cache address carried in the data read request, reading the source video data from the cache space based on the first cache address, and encoding the read source video data by the encoding unit. This method can reduce memory usage and reduce encoding latency.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a video processing method, apparatus, device, storage medium, and program product. Background Technology

[0002] In applications such as security monitoring or consumer cameras, the acquisition device receives video images from the camera and stores them in memory. Then, the encoding device reads the video images from memory for encoding. The encoded video is then transmitted to the cloud or a mobile device for viewing or storage via Wi-Fi or Ethernet. In traditional video processing solutions, the interaction between the acquisition and encoding devices regarding video data transmission primarily involves frame buffering. That is, after the acquisition device stores a complete frame of the video into memory, the encoding device starts, reads that frame, and encodes it. Simultaneously, the acquisition device stores the next frame in another memory space. The acquisition and encoding devices achieve video stream acquisition and encoding processing through a ping-pong operation between these two frame buffer spaces.

[0003] However, while traditional video processing methods involve simple hardware and software interaction and implementation, they require at least two frame buffers of memory, resulting in significant memory consumption. Furthermore, this method requires frame-by-frame video encoding, leading to substantial encoding latency. Summary of the Invention

[0004] Therefore, it is necessary to provide a video processing method, apparatus, device, storage medium, and program product that can reduce memory usage and lower encoding latency to address the aforementioned technical problems.

[0005] In a first aspect, this application provides a video processing method applied to a processor of a computer device; the computer device further includes an acquisition unit, a memory unit, a blocking unit, and an encoding unit; the memory unit includes pre-allocated cache space; the method includes:

[0006] When the acquisition unit cyclically fills the buffer space with the acquired source video data in a row-filling manner, the acquisition unit receives a row interruption command triggered by the acquisition unit each time the buffer space is filled.

[0007] In response to the line interrupt instruction, the first cache address of the cache space is updated to the blocking unit;

[0008] After the blocking unit receives the data read request sent by the encoding unit, and determines to allow the data read request based on the first cache address and the second cache address carried in the data read request, it reads the source video data from the cache space based on the first cache address, and encodes the read source video data by the encoding unit.

[0009] Secondly, this application provides a video processing apparatus applied to a processor of a computer device; the computer device further includes an acquisition unit, a memory unit, a blocking unit, and an encoding unit; the memory unit includes pre-allocated cache space; the apparatus includes:

[0010] The receiving module is used to receive a row interruption command generated by the acquisition unit each time the buffer space is filled, when the acquisition unit is filling the buffer space in a row-filling manner.

[0011] The update module is used to update the first cache address of the cache space to the blocking unit in response to the line interrupt instruction;

[0012] The reading module is configured to, after the blocking unit receives a data reading request sent by the encoding unit and determines whether to allow the data reading request based on the first cache address and the second cache address carried in the data reading request, read the source video data from the cache space based on the first cache address, and encode the read source video data by the encoding unit.

[0013] Thirdly, this application provides a video processing system, which includes a processor, a capture unit, a memory unit, a blocking unit, and an encoding unit; the memory unit includes pre-allocated cache space;

[0014] The acquisition unit is used to cyclically fill the buffer space with the acquired source video data in a row-filling manner, and trigger the generation of a row interruption instruction each time the buffer space is filled.

[0015] The processor is configured to receive the row interrupt instruction and, in response to the row interrupt instruction, update the first cache address of the cache space to the blocking unit;

[0016] The blocking unit is used to receive the data read request sent by the encoding unit, and determine whether to allow the data read request based on the first cache address and the second cache address carried in the data read request.

[0017] The processor is also configured to read the source video data from the cache space based on the first cache address;

[0018] The encoding unit is used to encode the read source video data.

[0019] Fourthly, this application provides a computer device, including a processor, a data acquisition unit, a memory unit, a blocking unit, and an encoding unit; the memory unit includes pre-allocated cache space; the memory unit stores a computer program, and the processor executes the computer program to implement the steps in the various method embodiments of this application.

[0020] Fifthly, this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in the various method embodiments of this application.

[0021] Sixthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the steps in the various method embodiments of this application.

[0022] The aforementioned video processing method, apparatus, device, storage medium, and program product, including the computer device, comprises a processor, an acquisition unit, a memory unit, a blocking unit, and an encoding unit. When the acquisition unit cyclically fills the buffer space with acquired source video data in a row-filling manner, the processor receives a row interrupt instruction triggered by the acquisition unit each time the buffer space is filled. In response to the row interrupt instruction, the processor updates the first cache address of the buffer space to the blocking unit. When the blocking unit receives a data read request from the encoding unit and, based on the first cache address and the second cache address carried in the data read request, determines whether to allow the data read request, the processor reads the source video data from the buffer space based on the first cache address and encodes the read source video data through the encoding unit. Compared to traditional video processing methods, this application uses an acquisition unit to cyclically fill the buffer space with acquired source video data in a row-filling manner. Each time the acquisition unit completes filling the buffer space, it triggers a row interrupt instruction, ensuring that the amount of source video data buffered in the buffer space is less than the amount of data in one frame. Then, the processor updates the first buffer address of the buffer space containing the prepared source video data to the blocking unit. The blocking unit then determines whether to allow the data read request based on the first buffer address and the second buffer address carried in the data read request sent by the encoding unit. Once the data read request is allowed, the source video data can be read from the buffer space and encoded by the encoding unit. This reduces memory usage during video processing, lowers video encoding latency, and improves video processing efficiency and real-time performance. Attached Figure Description

[0023] Figure 1 This is a flowchart illustrating a video processing method in one embodiment;

[0024] Figure 2 This is a schematic diagram illustrating the working principle of the blocking unit in one embodiment;

[0025] Figure 3 This is a schematic diagram illustrating the looping of cache spaces with different quantities and capacities in one embodiment;

[0026] Figure 4 This is a schematic diagram illustrating a loop between two cache spaces of different capacities in one embodiment;

[0027] Figure 5 This is a schematic diagram of the structure of a video processing system in one embodiment;

[0028] Figure 6 This is a structural block diagram of a video processing device in one embodiment;

[0029] Figure 7 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0031] In one embodiment, such as Figure 1 As shown, a video processing method is provided, applied to the processor of a computer device; the computer device further includes an acquisition unit, a memory unit, a blocking unit, and an encoding unit; the memory unit contains pre-allocated cache space; the method includes the following steps:

[0032] Step 102: When the acquisition unit fills the buffer space with the acquired source video data in a row-filling manner, the receiving unit triggers a row interruption command each time it finishes filling the buffer space.

[0033] The source video data contains multiple frames, each frame containing multiple rows of image data (i.e., multiple rows of pixel data). For example, a 1920×1080 frame in the source video data contains 1920 rows of image data. Filling the buffer space with source video data row-by-row means filling the buffer space with each frame of the source video data, using row-by-row image data as the granularity. It can be understood that the buffer space's capacity is smaller than the buffer space occupied by a single frame. Circularly filling the buffer space means that after the buffer space is full, source video data is continuously filled into the buffer space, with each round of filling directly overwriting the previous round's filling. The row interruption instruction is a computer instruction used to indicate that the buffer space currently being written to by the acquisition unit is full, temporarily stopping the writing of source video data into that buffer space.

[0034] In one embodiment, the computer device further includes a camera. The acquisition unit can receive source video data sent by the camera in real time and cyclically fill the buffer space with the acquired source video data in a row-filling manner. After each buffer space is filled, the acquisition unit can trigger the generation of a row interrupt instruction and send the row interrupt instruction to the processor, which can receive the row interrupt instruction.

[0035] In one embodiment, the memory unit includes at least one pre-allocated cache space. When the acquisition unit cyclically fills these cache spaces with acquired source video data in a row-filling manner, for each cache space, the processor may receive a row interrupt instruction triggered by the acquisition unit each time the cache space is filled.

[0036] In one embodiment, the processor, acquisition unit, memory unit, blocking unit, and encoding unit in the computer device are all hardware devices. The processor can be a central processing unit, the acquisition unit can be a video capture device, the memory unit can be internal memory, the blocking unit can be a hardware logic circuit, and the encoding unit can be a video encoder.

[0037] Step 104: In response to the line interrupt instruction, update the first cache address of the cache space to the blocking unit.

[0038] The first cache address of the cache space is the physical address of the cache space in the memory unit.

[0039] Specifically, in response to a line interrupt instruction, the processor can update the first cache address of the cache space to the blocking unit, which can record the first cache address. It can be understood that if the blocking unit records the first cache address of the cache space, it indicates that the cache space is full, the data writing by the acquisition unit to the cache space has been interrupted, and the source video data to be encoded is ready in the cache space.

[0040] Step 106: After the blocking unit receives the data read request sent by the encoding unit and determines to allow the data read request based on the first cache address and the second cache address carried in the data read request, the blocking unit reads the source video data from the cache space based on the first cache address and encodes the read source video data through the encoding unit.

[0041] Specifically, the blocking unit can receive data read requests sent by the encoding unit in real time. These requests carry a second buffer address corresponding to the source video data to be encoded. The blocking unit can determine whether to allow the data read request based on the first buffer address recorded in the blocking unit and the second buffer address carried in the data read request. After the blocking unit determines to allow the data read request, the processor can read the source video data from the buffer space indicated by the first buffer address and encode the read source video data through the encoding unit.

[0042] In one embodiment, the encoding unit reads the source video data from memory units sequentially according to a frame buffer method. Therefore, the encoding unit first generates the frame buffer address corresponding to the source video data to be encoded, i.e., the virtual address of the buffer space. The encoding unit then converts the virtual address of the buffer space into its actual physical address in the memory unit and appends this physical address to the data read request corresponding to the source video data to be encoded. It can be understood that in this embodiment, the address translation function is implemented by the encoding unit. Furthermore, the blocking unit can directly compare the consistency of the first buffer address recorded in the blocking unit with the second buffer address (i.e., the actual physical address of the buffer space) carried in the data read request. If the second buffer address matches the first buffer address, the blocking unit can determine to allow the data read request. If the second buffer address does not match the first buffer address, the blocking unit can determine to block the data read request.

[0043] In the aforementioned video processing method, the computer device includes a processor, an acquisition unit, a memory unit, a blocking unit, and an encoding unit. When the acquisition unit cyclically fills the buffer space with the acquired source video data in a row-filling manner, the processor receives a row interrupt instruction triggered by the acquisition unit each time the buffer space is filled. In response to the row interrupt instruction, the processor updates the first cache address of the buffer space to the blocking unit. When the blocking unit receives a data read request from the encoding unit and, based on the first cache address and the second cache address carried in the data read request, determines whether to allow the data read request, the processor reads the source video data from the buffer space based on the first cache address and encodes the read source video data through the encoding unit. Compared to traditional video processing methods, this application uses an acquisition unit to cyclically fill the buffer space with acquired source video data in a row-filling manner. Each time the acquisition unit completes filling the buffer space, it triggers a row interrupt instruction, ensuring that the amount of source video data buffered in the buffer space is less than the amount of data in one frame. Then, the processor updates the first buffer address of the buffer space containing the prepared source video data to the blocking unit. The blocking unit then determines whether to allow the data read request based on the first buffer address and the second buffer address carried in the data read request sent by the encoding unit. Once the data read request is allowed, the source video data can be read from the buffer space and encoded by the encoding unit. This reduces memory usage during video processing, lowers video encoding latency, and improves video processing efficiency and real-time performance.

[0044] Furthermore, compared to the traditional method of calculating the cache address of the circular buffer space accessed by the acquisition unit and encoding unit through the hardware processing logic of the blocking unit, and then performing the cache space empty / full judgment process, this application uses the processor to update the cache address of the buffer space with prepared source video data to the blocking unit through software management, in order to perform the cache space empty / full judgment. This software management method, instead of the traditional method of controlling the cache address update through the hardware processing logic in the blocking unit, simplifies the hardware structure design of the blocking unit and simplifies the control logic for cache address updates.

[0045] In one embodiment, the second cache address is a virtual address where the encoding unit reads source video data sequentially according to the frame buffering method; the step of the blocking unit determining to allow the data reading request based on the first cache address and the second cache address carried in the data reading request includes: the blocking unit performs address translation on the second cache address carried in the data reading request to obtain a third cache address; if the first cache address and the third cache address are consistent, the blocking unit determines to allow the data reading request.

[0046] The second cache address is the virtual address where the encoding unit reads the source video data sequentially according to the frame buffering method. It can be understood that the second cache address is not the actual physical address of the cache space in the memory unit.

[0047] In one embodiment, the encoding unit reads the source video data from memory units sequentially according to a frame buffer method. Therefore, the encoding unit generates a frame buffer address corresponding to the source video data to be encoded, i.e., a virtual address of the buffer space, also known as a second buffer address. The encoding unit can append the second buffer address to the data read request corresponding to the source video data to be encoded. It can be understood that in this embodiment, the address translation function is implemented by a blocking unit. Furthermore, as... Figure 2 As shown, the blocking unit can perform address translation on the second cache address carried in the data read request to obtain a third cache address. It can be understood that the third cache address obtained after address translation is the actual physical address of the cache space in the memory location. The blocking unit can compare the first cache address updated by the processor in the blocking unit with the third cache address obtained after address translation. If the first cache address and the third cache address match, the data read request is allowed. If the first cache address and the third cache address do not match, the data read request is blocked.

[0048] In the above embodiments, compared with the traditional method of address translation in the encoding unit, this embodiment transfers the address translation function to the blocking unit. In this way, the encoding unit does not need to make modifications to the hardware structure and hardware processing logic, and can directly read the source video data sequentially according to the original frame buffer method, which simplifies the design of the encoding unit and thus improves the video encoding performance.

[0049] In one embodiment, the blocking unit includes cache allocation information corresponding to the cache space; the cache allocation information includes the number of cache spaces, the cache capacity of each cache space, and the cache address; the step of the blocking unit performing address translation on the second cache address carried by the data read request to obtain the third cache address includes: the blocking unit performing address translation on the second cache address carried by the data read request based on the cache allocation information to obtain the third cache address.

[0050] Specifically, when the processor allocates cache space in a memory unit, it can generate cache allocation information corresponding to the cache space. This information includes the number of cache spaces, the cache capacity of each cache space, and the cache address. The processor can pre-configure this cache allocation information to the acquisition unit and the blocking unit, both of which contain the corresponding cache allocation information. It can be understood that the acquisition unit can cyclically fill the source video data into the cache space corresponding to the memory unit based on the cache allocation information. The blocking unit can perform address mapping based on the cache allocation information, that is, perform address translation on the virtual second cache address carried by the data read request to obtain the actual third cache address of the cache space.

[0051] In the above embodiments, by using the blocking unit to perform address translation on the second cache address carried by the data read request based on the cache allocation information to obtain the third cache address, the accuracy of address translation can be improved, thereby improving video encoding efficiency.

[0052] In one embodiment, the memory unit contains multiple cache spaces; the cache capacity of each cache space is obtained through custom configuration; when the acquisition unit fills the acquired source video data into the cache space in a row-filling manner, the receiving acquisition unit triggers a row interrupt instruction generated each time the cache space is filled, including: when the acquisition unit fills the acquired source video data into multiple cache spaces one by one in a row-filling manner, for each cache space, the receiving acquisition unit triggers a row interrupt instruction generated each time the cache space is filled.

[0053] Specifically, the memory unit contains multiple pre-allocated cache spaces, each with a customizable cache capacity, meaning the size (i.e., cache capacity) and number of cache spaces can be flexibly configured. When the acquisition unit fills the acquired source video data into the multiple cache spaces row-by-row, for each cache space, the processor can receive a row interrupt instruction triggered by the acquisition unit after filling that cache space. In response to the row interrupt instruction, the processor can update the first cache address of that cache space to the blocking unit. When the blocking unit receives a data read request from the encoding unit and, based on the first cache address and the second cache address carried in the data read request, determines whether to allow the data read request, the processor can read the source video data from that cache space based on the first cache address and encode the read source video data through the encoding unit.

[0054] In one embodiment, the size (i.e., cache capacity) and number of cache spaces in a memory unit can be flexibly configured. For example, ... Figure 3As shown, a memory unit can contain two cache spaces 1 and 2 with different cache sizes, three cache spaces 1, 2 and 3 with different cache sizes, or four cache spaces 1, 2, 3 and 4 with different cache sizes. It should be noted that the cache sizes of the multiple cache spaces within a memory unit can be the same or different.

[0055] In one embodiment, such as Figure 4 As shown, the memory unit can be configured with cache space 1 with a capacity of N1 and cache space 2 with a capacity of N2. It can be understood that cache space 1 can store N1 lines of source video data, and cache space 2 can store N2 lines of source video data. When the acquisition unit uploads N1 lines of source video data (lines 1 to N1) to cache space 1, it can trigger the generation of a line interrupt instruction. When it uploads N2 lines of source video data (lines N1+1 to N1+N2) to cache space 2, it can trigger the generation of a line interrupt instruction. The next N1 lines are uploaded to cache space 1, triggering the generation of a line interrupt instruction. The access process of these two cache spaces is repeated in this loop.

[0056] In the above embodiments, by flexibly configuring multiple cache spaces with the same or different cache capacities in the memory unit, the size and number of cache spaces can be flexibly configured. The processor can manage the cache space more flexibly through software management, and the fragmented storage space in the memory unit can also be used more rationally, thereby improving memory utilization.

[0057] In one embodiment, the computer device further includes a camera; the step of the acquisition unit cyclically filling the acquired source video data into the buffer space in a row-filling manner includes:

[0058] The acquisition unit receives raw source video data sent by the camera in real time, optimizes the raw source video data to obtain source video data, and fills the cache space with the source video data in a row-filling manner in a loop.

[0059] Specifically, the computer device includes a processor, a camera, an acquisition unit, a memory unit, a blocking unit, and an encoding unit. The memory unit contains pre-allocated cache space. The acquisition unit can receive raw source video data sent by the camera in real time, perform video quality optimization processing on the raw source video data to obtain source video data, and cyclically fill the cache space with the optimized source video data in a row-filling manner. Each time the acquisition unit completes filling the cache space, it can trigger the generation of a row interrupt instruction. The processor can receive the row interrupt instruction and, in response, update the first cache address of the cache space to the blocking unit. When the blocking unit receives a data read request sent by the encoding unit, and determines whether to allow the data read request based on the first cache address and the second cache address carried in the data read request, the processor can read the source video data from the cache space based on the first cache address, and the encoding unit encodes the read source video data.

[0060] In the above embodiments, before writing the video data into the buffer space, the acquisition unit can first optimize the image quality of the video data, thereby improving the quality of the subsequently encoded video.

[0061] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially, these steps are not necessarily executed in that order. Unless otherwise expressly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the above embodiments may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0062] In one embodiment, such as Figure 5 As shown, a video processing system is provided, which includes a processor, a capture unit, a memory unit, a blocking unit, and an encoding unit; the memory unit contains pre-allocated cache space;

[0063] The acquisition unit is used to fill the buffer space with the acquired source video data in a row-filling manner in a loop. Each time the buffer space is filled, a row interruption command is triggered.

[0064] The processor is used to receive line interrupt instructions and, in response to line interrupt instructions, update the first cache address of the cache space to the blocking unit;

[0065] The blocking unit is used to receive the data read request sent by the encoding unit, and determine whether to allow the data read request based on the first cache address and the second cache address carried in the data read request.

[0066] The processor is also used to read source video data from the cache space based on the first cache address;

[0067] The encoding unit is used to encode the read source video data.

[0068] In one embodiment, see continue to see Figure 5 In addition to a processor, acquisition unit, memory unit, blocking unit, and encoding unit, a video processing system may also include a camera. Specifically, the acquisition unit can receive source video data captured by the camera in real time. And, after encoding the read source video data, the encoding unit can store the encoded video data in the memory unit.

[0069] In one embodiment, such as Figure 6 As shown, a video processing apparatus 600 is provided, applied to a processor of a computer device; the computer device further includes an acquisition unit, a memory unit, a blocking unit, and an encoding unit; the memory unit includes pre-allocated cache space; the apparatus specifically includes:

[0070] The receiving module 602 is used to receive the line interrupt command generated by the acquisition unit after the acquisition unit has finished filling the buffer space, when the acquisition unit is cyclically filling the acquired source video data into the buffer space in a row-filling manner.

[0071] Update module 604 is used to update the first cache address of the cache space to the blocking unit in response to a line interrupt instruction;

[0072] The reading module 606 is used to read source video data from the cache space based on the first cache address after the blocking unit receives a data reading request sent by the encoding unit and determines to allow the data reading request based on the first cache address and the second cache address carried in the data reading request, and then encodes the read source video data through the encoding unit.

[0073] In one embodiment, the second cache address is the virtual address where the encoding unit reads the source video data sequentially according to the frame buffering method; the blocking unit performs address translation on the second cache address carried in the data read request to obtain the third cache address; if the first cache address and the third cache address are consistent, the data read request is allowed.

[0074] In one embodiment, the blocking unit includes cache allocation information corresponding to the cache space; the cache allocation information includes the number of cache spaces, the cache capacity of each cache space, and the cache address; based on the cache allocation information, the blocking unit performs address translation on the second cache address carried by the data read request to obtain the third cache address.

[0075] In one embodiment, the memory unit contains multiple cache spaces; the cache capacity of each cache space is obtained by custom configuration; the receiving module 602 is also used to receive the row interrupt instruction generated by the receiving unit after the cache space is filled, when the acquisition unit fills the acquired source video data into multiple cache spaces one by one in a row-filling manner.

[0076] In one embodiment, the computer device further includes a camera; the acquisition unit receives raw source video data sent by the camera in real time, optimizes the raw source video data to obtain source video data, and cyclically fills the cache space with the source video data in a row-filling manner.

[0077] The aforementioned video processing apparatus, a computer device, includes a processor, an acquisition unit, a memory unit, a blocking unit, and an encoding unit. When the acquisition unit cyclically fills the buffer space with acquired source video data in a row-filling manner, the processor receives a row interrupt instruction triggered by the acquisition unit each time the buffer space is filled. In response to the row interrupt instruction, the processor updates the first cache address of the buffer space to the blocking unit. When the blocking unit receives a data read request from the encoding unit, and determines whether to allow the data read request based on the first cache address and the second cache address carried in the data read request, the processor reads the source video data from the buffer space based on the first cache address, and the encoding unit encodes the read source video data. Compared to traditional video processing methods, this application uses an acquisition unit to cyclically fill the buffer space with acquired source video data in a row-filling manner. Each time the acquisition unit completes filling the buffer space, it triggers a row interrupt instruction, ensuring that the amount of source video data buffered in the buffer space is less than the amount of data in one frame. Then, the processor updates the first buffer address of the buffer space containing the prepared source video data to the blocking unit. The blocking unit then determines whether to allow the data read request based on the first buffer address and the second buffer address carried in the data read request sent by the encoding unit. Once the data read request is allowed, the source video data can be read from the buffer space and encoded by the encoding unit. This reduces memory usage during video processing, lowers video encoding latency, and improves video processing efficiency and real-time performance.

[0078] Each module in the aforementioned video processing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0079] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 7 As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements a video processing method. The display unit of the computer device is used to form a visually visible image. It can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0080] Those skilled in the art will understand that Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0081] In one embodiment, a computer device is also provided, including a processor, a acquisition unit, a memory unit, a blocking unit, and an encoding unit; the memory unit includes pre-allocated cache space; the memory unit stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0082] In one embodiment, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0083] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0084] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0085] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0086] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0087] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A video processing method, characterized in that, A processor used in computer equipment; the computer equipment further includes a data acquisition unit, a memory unit, a blocking unit, and an encoding unit; The memory unit contains pre-allocated cache space; the method includes: When the acquisition unit cyclically fills the buffer space with the acquired source video data in a row-filling manner, the acquisition unit receives a row interruption command triggered by the acquisition unit each time the buffer space is filled. In response to the line interrupt instruction, the first cache address of the cache space is updated to the blocking unit; After the blocking unit receives the data read request sent by the encoding unit, and determines to allow the data read request based on the first cache address and the second cache address carried in the data read request, it reads the source video data from the cache space based on the first cache address, and encodes the read source video data by the encoding unit. The second cache address is the virtual address where the encoding unit reads the source video data sequentially according to the frame buffering method; The step of the blocking unit determining whether to allow the data read request based on the first cache address and the second cache address carried in the data read request includes: The blocking unit performs address translation on the second cache address carried by the data read request to obtain a third cache address. If the first cache address and the third cache address are consistent, the data read request is allowed.

2. The method according to claim 1, characterized in that, The blocking unit contains cache allocation information corresponding to the cache space; the cache allocation information includes the number of cache spaces, the cache capacity of each cache space, and the cache address; The step of the blocking unit performing address translation on the second cache address carried in the data read request to obtain the third cache address includes: The blocking unit performs address translation on the second cache address carried in the data read request based on the cache allocation information to obtain the third cache address.

3. The method according to claim 1, characterized in that, The memory unit contains multiple cache spaces; the cache capacity of each cache space is obtained through custom configuration. When the acquisition unit cyclically fills the buffer space with the acquired source video data in a row-filling manner, receiving the row interruption instruction triggered by the acquisition unit each time the buffer space is filled includes: When the acquisition unit fills the acquired source video data into multiple buffer spaces one by one in a row-filling manner, for each buffer space, a row interruption instruction for the buffer space is received, which is triggered by the acquisition unit each time the buffer space is filled.

4. The method according to claim 1, characterized in that, The computer device also includes a camera; the step of the acquisition unit cyclically filling the cache space with the acquired source video data in a row-filling manner includes: The acquisition unit receives raw source video data sent by the camera in real time, optimizes the raw source video data to obtain source video data, and fills the cache space with the source video data in a row-filling manner in a loop.

5. A video processing apparatus, characterized in that, A processor used in a computer device; the computer device further includes a data acquisition unit, a memory unit, a blocking unit, and an encoding unit; the memory unit includes pre-allocated cache space; the device includes: The receiving module is used to receive a row interruption command generated by the acquisition unit each time the buffer space is filled, when the acquisition unit is filling the buffer space in a row-filling manner. The update module is used to update the first cache address of the cache space to the blocking unit in response to the line interrupt instruction; The reading module is configured to, after the blocking unit receives a data reading request sent by the encoding unit and determines whether to allow the data reading request based on the first cache address and the second cache address carried in the data reading request, read the source video data from the cache space based on the first cache address, and encode the read source video data by the encoding unit; the second cache address is a virtual address in which the encoding unit reads the source video data sequentially according to the frame buffering method; the blocking unit performs address translation on the second cache address carried in the data reading request to obtain a third cache address, and if the first cache address and the third cache address are consistent, then determines that the data reading request should be allowed.

6. A video processing system, characterized in that, The system includes a processor, a data acquisition unit, a memory unit, a blocking unit, and an encoding unit; the memory unit contains pre-allocated cache space. The acquisition unit is used to cyclically fill the buffer space with the acquired source video data in a row-filling manner, and trigger the generation of a row interruption instruction each time the buffer space is filled. The processor is configured to receive the row interrupt instruction and, in response to the row interrupt instruction, update the first cache address of the cache space to the blocking unit; The blocking unit is used to receive the data read request sent by the encoding unit, and determine whether to allow the data read request based on the first cache address and the second cache address carried in the data read request. The second cache address is the virtual address where the encoding unit reads the source video data sequentially according to the frame buffering method; the blocking unit performs address translation on the second cache address carried by the data read request to obtain the third cache address; if the first cache address and the third cache address are consistent, the data read request is allowed. The processor is also configured to read the source video data from the cache space based on the first cache address; The encoding unit is used to encode the read source video data.

7. A computer device, characterized in that, It includes a processor, a data acquisition unit, a memory unit, a blocking unit, and an encoding unit; the memory unit contains pre-allocated cache space; the memory unit stores a computer program, characterized in that the processor executes the computer program to implement the steps of the method according to any one of claims 1 to 4.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 4.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 4.

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