A method for manufacturing a semiconductor memory device

Abstract

The application provides a preparation method of a semiconductor storage device, and is applied to the technical field of semiconductor preparation. In the application, a photoresist layer and a photo mask are not arranged, a first ion implantation is performed on the whole substrate, the photo mask, photo etching and related processes for forming a first well region and a second well region are reduced, then a reverse ion neutralization is performed by subsequent ion implantation, a third well region and a fourth well region with opposite conductive types are formed, the process steps are reduced, the manufacturing cost of the embedded flash memory chip is reduced, and the product competitiveness is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor memory device. Background Technology

[0002] To reduce the production cost of individual chips, the critical dimensions of embedded flash memory are continuously shrinking to increase the number of chips per wafer. Currently, for small-size wafer fabs such as 8-inch wafers, the continuous shrinking of chip critical dimensions has reached its limit due to equipment capacity limitations. Therefore, optimizing processes to reduce the number of lithography layers has become an effective way to improve the competitiveness of small-size products such as 8-inch wafers. Summary of the Invention

[0003] The purpose of this invention is to provide a method for manufacturing a semiconductor memory device, thereby reducing the number of process steps, lowering the manufacturing cost of embedded flash memory chips, and improving product competitiveness.

[0004] To address the aforementioned technical problems, the present invention provides a method for fabricating a semiconductor memory device, comprising at least the following steps:

[0005] A substrate is provided, comprising a first CMOS device region and a second CMOS device region with different operating voltages, wherein each CMOS device region includes a PMOS region and an NMOS region;

[0006] A floating gate layer and a mask layer are formed and stacked sequentially from bottom to top, located on the substrate of the first CMOS device region and the second CMOS device region;

[0007] A first ion implantation process is performed on the entire substrate to form a first well region within the substrate corresponding to the NMOS region in the first CMOS device region;

[0008] The first photoresist layer is formed on the mask layer located in the PMOS region of the first CMOS device region and the second CMOS device region;

[0009] A second ion implantation process is performed on the substrate to form a second well region within the substrate corresponding to the NMOS region in the second CMOS device region.

[0010] In some optional examples, the dopant ions in the first well region and the second well region have the same conductivity type, and the dopant ions include P-type ions.

[0011] In some optional examples, the concentration of doped ions in the first well region is less than the concentration of doped ions in the second well region.

[0012] In some optional examples, the method for fabricating the semiconductor memory device further includes:

[0013] Remove the mask layer and the floating gate layer from the first CMOS device region and the second CMOS device region.

[0014] In some optional examples, after forming the second well region, the following steps are also included:

[0015] A second photoresist layer is formed on the substrate that is re-exposed in the NMOS region of the second CMOS device region and the first CMOS device region; and,

[0016] A third ion implantation process is performed on the substrate to form a third well region within the substrate corresponding to the PMOS region of the first CMOS device region.

[0017] In some optional examples, after forming the second well region, the following steps are also included:

[0018] A third photoresist layer is formed on the substrate that is re-exposed in the NMOS regions of the first CMOS device region and the second CMOS device region; and,

[0019] A fourth ion implantation process is performed on the substrate to form a fourth well region within the substrate corresponding to the PMOS region of the second CMOS device region.

[0020] In some optional examples, the operating voltage of the first CMOS device region is greater than the operating voltage of the second CMOS device region.

[0021] In some optional examples, the dopant ions in the third well region and the fourth well region have the same conductivity type, and the dopant ions include N-type ions.

[0022] In some optional examples, the concentration of doped ions in the third well region is less than the concentration of doped ions in the fourth well region.

[0023] In some optional examples, the method of fabricating the semiconductor memory device further includes: the substrate further includes a memory region, and the second photoresist layer and the third photoresist layer are further compressed and covered on the substrate of the memory region.

[0024] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0025] This invention provides a method for fabricating a semiconductor memory device, comprising: providing a substrate including a first CMOS device region and a second CMOS device region with different operating voltages, wherein each CMOS device region includes a PMOS region and an NMOS region; forming a floating gate layer and a mask layer stacked sequentially from bottom to top on the substrate of the first CMOS device region and the second CMOS device region; performing a first ion implantation process on the entire substrate to form a first well region in the substrate corresponding to the NMOS region in the first CMOS device region; forming a first photoresist layer on the mask layer in the PMOS region of the first CMOS device region and the second CMOS device region; and performing a second ion implantation process on the substrate to form a second well region in the substrate corresponding to the NMOS region in the second CMOS device region.

[0026] In this invention, firstly, without setting a photoresist layer and a photomask, a first ion implantation is performed on the entire substrate. This forms a first well region within the substrate corresponding to the NMOS region in the first CMOS device region, while simultaneously performing low-dose P-type ion implantation on other areas of the substrate. Then, a first photoresist layer is formed to shield a portion of the substrate. A second ion implantation of P-type ions is performed within the substrate corresponding to the NMOS region in the second CMOS device region, and the superposition of the first ion implantation of P-type ions forms a high-ion-concentration second well region. Next, a second and third photoresist layer are used to shield a portion of the substrate, and a third and fourth ion implantation of high-dose N-type ions are performed. This neutralizes the P-type ions (the ions implanted in the first ion implantation process) in the PMOS regions of both the first and second CMOS device regions, allowing for further N-type doping of the third and fourth well regions. This reduces the number of photomask and photolithography processes required to form the first and second well regions, thereby reducing process steps, lowering the manufacturing cost of embedded flash memory chips, and improving product competitiveness. Attached Figure Description

[0027] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:

[0028] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor memory device according to an embodiment of the present invention.

[0029] Figures 2 to 10 This is a schematic diagram of the semiconductor memory device provided in one embodiment of the present invention during the fabrication process.

[0030] Among them, Figures 2 to 10 middle:

[0031] 100 - Substrate; 101 - Memory region; 102 - Logic region; 102HN - High-voltage PMOS region; 102HP - High-voltage NMOS region; 102LN - Low-voltage PMOS region; 102LP - Low-voltage NMOS region; 110 - Coupling oxide layer; 120 - Floating gate layer; 130 - Mask layer; 140 - Shallow trench isolation structure; 150 - First photoresist layer; 160 - Memory cell; 170 - Second photoresist layer; HPW - First well region; 180 - Third photoresist layer; LPW - Second well region; HNW - Third well region; LNW - Fourth well region; 191 - Word line polysilicon layer; 192 - First dielectric layer; 201 - High-voltage gate oxide layer; 202 - High-voltage polysilicon layer; 210 - Fourth photoresist layer; 220 - Fifth photoresist layer.

[0032] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0033] To make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0034] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, intended only to facilitate and clarify the illustration of the embodiments of the invention. It is understood that the terms "on," "above," and "over" in this invention should be interpreted in the broadest sense, such that "on" means not only "on" something without any intervening feature or layer (i.e., directly on something), but also includes "on" something with an intervening feature or layer.

[0035] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0036] In the embodiments of the present invention, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present invention can be arbitrarily combined without conflict.

[0037] Please refer to Figure 1 The illustration shows a flowchart of a method for fabricating a semiconductor memory device according to an embodiment of the present invention. The semiconductor device of the present invention can be used to manufacture embedded flash memory devices, and without departing from the spirit of the present invention, it can also be applied to other types of memory.

[0038] like Figure 1 As shown, the method for fabricating the semiconductor memory device includes the following steps:

[0039] Step S101: Provide a substrate, including a first CMOS device region and a second CMOS device region with different operating voltages, wherein each CMOS device region includes a PMOS region and an NMOS region.

[0040] Step S102: A floating gate layer and a mask layer are formed, stacked sequentially from bottom to top, on the substrates of the first CMOS device region and the second CMOS device region.

[0041] Step S103: Perform a first ion implantation process on the entire substrate to form a first well region in the substrate corresponding to the NMOS region in the first CMOS device region.

[0042] Step S104: Form a first photoresist layer on the mask layer located in the PMOS region of the first CMOS device region and the second CMOS device region.

[0043] Step S105: Perform a second ion implantation process on the substrate to form a second well region in the substrate corresponding to the NMOS region in the second CMOS device region.

[0044] In the method for fabricating a semiconductor memory device according to the present invention, the storage region is used to fabricate the MOS transistors of the memory cells of a semiconductor memory device, such as an embedded flash memory device, and the logic region is used to fabricate the logic MOS devices of a semiconductor memory device, such as an embedded flash memory device. Furthermore, the logic region can be specifically divided into a high-voltage device region and a low-voltage region, etc., based on the actual operating voltage of the logic MOS device, but is not limited thereto. Therefore, the present invention can reduce the number of photomask and photolithography processes involved in forming the first and second well regions by performing a first ion implantation on the entire substrate without setting a photoresist layer and a photomask. Then, through the neutralization of inversion ions by subsequently implanted ions, a third and fourth well region with opposite conductivity types are formed, thereby reducing the number of process steps, lowering the manufacturing cost of the embedded flash memory chip, and improving product competitiveness.

[0045] To enable those skilled in the art to easily understand the fabrication method of the semiconductor memory device in the embodiments of this invention, the fabrication method of the semiconductor memory device proposed in this invention will be further described below with reference to various structural schematic diagrams during the fabrication process. Please refer to... Figures 2 to 10 As shown, the illustration is a structural schematic diagram of the fabrication process of the semiconductor memory device provided in the embodiment of the present invention.

[0046] To perform step S101 above, please refer to [link / reference]. Figure 2A substrate 100 is provided, which may include a storage region 101 and a logic region 102. In one embodiment, the substrate 100 may be, for example, a silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a glass substrate, or a III-V compound substrate (e.g., a silicon nitride substrate or a gallium arsenide substrate), a silicon carbide substrate or a stacked structure thereof, or a diamond substrate, or other semiconductor material substrates known to those skilled in the art. Exemplarily, the substrate 100 is a silicon substrate, but this is not a limitation. The storage region 101 and the logic region 102 may be arranged adjacent to each other, but this is not a limitation. The logic region 102 may specifically include a first CMOS device region and a second CMOS device region with different operating voltages. Each CMOS device region may include a PMOS region and an NMOS region. For example, the first CMOS device region may be a high-voltage device region and the second CMOS device region may be a low-voltage device region. The first CMOS device region may include a high-voltage PMOS region 102HN for forming PMOS transistors and a high-voltage NMOS region 102HP for forming NMOS transistors. Similarly, the second CMOS device region may also include a low-voltage PMOS region 102LN for forming PMOS transistors and a low-voltage NMOS region 102LP for forming NMOS transistors, but is not limited thereto.

[0047] To perform step S102 above, please refer to the following: Figure 2 Using at least one deposition process, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, a layer-coupled oxide layer 110, a floating gate layer 120, and a mask layer 130 are sequentially stacked from bottom to top on the entire surface of the substrate 100. Then, using photolithography and etching processes, the plurality of shallow trench isolation structures 140 are formed on the substrate 100. Finally, using a deposition process such as chemical vapor deposition, the substrate 100 is divided into the memory region 101 and the logic region 102. In one embodiment, the materials of the coupling oxide layer 110 and the shallow trench isolation structure 140 may be oxides, such as silicon dioxide; the material of the floating gate layer 120 may be a conductive material, such as polysilicon; the material of the mask layer 130 may be an insulating material, such as silicon nitride; and the top surface of the shallow trench isolation structure 140 may be flush with the top surface of the mask layer 130 (e.g., ...). Figure 2 (as shown), or its top surface may be slightly lower than the top surface of the mask layer 130 (not shown), but is not limited thereto.

[0048] To proceed with step S103 above, please refer to the following documentation. Figure 2Without any photomask or photoresist layer, a first ion implantation process is performed on the entire substrate 100 of the storage region 101 and the logic region 102, so that the first ion implantation is performed in each region of the substrate 100 isolated by the shallow trench isolation structure 140 in the storage region 101 and the logic region 102. In one embodiment, the ion type implanted in the first ion implantation process is P-type ions, such as phosphorus ions. Since the ion concentration required for the well region corresponding to the high-voltage NMOS region 102HP in the first CMOS device region in the logic region 102 is low, in this embodiment of the invention, the concentration of ions implanted in the first ion implantation process can be the same as the ion implantation concentration of the well region (i.e., the first well region HPW) of the high-voltage NMOS region in the logic region in the prior art. The difference between the present invention and the prior art is that: in the process of forming the first well region HPW of the high-voltage NMOS region in the logic region, the present invention simultaneously performs low-concentration or low-dose P-type ion implantation in the substrate 100 of the storage region 101 and the other regions of the logic region 102 of the substrate 100. Under this configuration, the fabrication method provided in this embodiment of the invention does not require any photomask, photolithography or other process technology to form the first well region HPW of the high voltage NMOS region in the logic region, thereby achieving the purpose of reducing the photomask, photolithography and other related processes for forming the first well region HPW of the high voltage NMOS region.

[0049] To perform steps S104 and S105 above, please refer to [link / reference]. Figure 3 A first photoresist layer 150 can be formed on the mask layer 130 below the PMOS region 102LN in the first CMOS device region and the second CMOS device region using a deposition process such as physical vapor deposition. Then, a second ion implantation process is used to perform a second ion implantation process on the corresponding area of ​​the substrate 100 that is not covered by the first photoresist layer 150 (or the area exposed by the first photoresist layer 150) to form a second well region LPW. In one embodiment, the first photoresist layer 150 exposes the low-voltage NMOS region 102LP of the memory region 101 and the logic region 102. The ions implanted in the second ion implantation process are P-type ions. Since the doping ion concentration of the low-voltage NMOS region 102LP in the logic region 102 needs to be greater than the ion concentration of the first well region HPW in the high-voltage NMOS region, after P-type ion implantation using the first and second ion implantation processes in this embodiment, the doping ion concentration can be formed to meet the well region requirements corresponding to the high-voltage and low-voltage NMOS transistors in the logic region of the embedded flash memory device.

[0050] It should be understood that the implantation dose, concentration, and other parameters of the P-type ions implanted in the second ion implantation process in this embodiment of the invention are related to the implantation dose, concentration, and other parameters of the P-type ions implanted in the first ion implantation process. That is, since the total ion concentration in the second well region LPW is accumulated through the above two ion implantation processes, in order to make the ion concentration of the well regions in each region of the logic region 102 formed on the substrate 100 meet the design requirements, the implantation dose, concentration, and other parameters of the P-type ions implanted in the second ion implantation process can be adaptively adjusted based on the implantation dose, concentration, and other parameters of the P-type ions implanted in the first ion implantation process, but this is not a limitation.

[0051] Following step S105 above, please refer to... Figure 4 First, the mask layer 130 and the floating gate layer 120 in the first CMOS device region and the second CMOS device region in the logic region 102 can be removed using an etching process, such as dry etching or wet etching, to re-expose the coupling oxide layer 110 in the logic region 102. Then, the memory cell 160 of the embedded flash memory device can be formed on the substrate of the memory region 101 by further etching and deposition processes. The memory cell 160 may include components and / or devices such as a floating gate layer (not shown), sidewalls (not shown), shared source lines (not shown), and tunneling oxide layer (not shown), but is not limited thereto. Then, using a deposition process such as chemical vapor deposition, a second photoresist layer 170 is formed on the substrate 100 that is exposed again in the second CMOS device region and the high voltage NMOS region 102HP of the first CMOS device region in the storage region 101 and the logic region 102. That is, the second photoresist layer 170 has an opening that exposes the substrate 100 corresponding to the high voltage PMOS region 102HN in the first CMOS device region in the logic region 102.

[0052] Next, a third ion implantation process is performed on the substrate 100 corresponding to the high-voltage PMOS region 102HN in the first CMOS device region exposed by the opening, to form a third well region HNW within the substrate 100 corresponding to the PMOS region 102HN in the first CMOS device region. In one embodiment, the type of ions implanted in the third ion implantation process is N-type ions, that is, the type of ions implanted in the third ion implantation process is opposite to the type of ions implanted in the first or second ion implantation process, and the concentration, dose, and other parameters of the N-type ions implanted in the third ion implantation process are related to the concentration, dose, and other parameters of the P-type ions implanted in the first ion implantation process. Because the first ion implantation process in this embodiment of the invention involves P-type ion implantation in each region of the substrate 100, during the formation of the N-type doped third well region HNW using the third ion implantation process, the N-type ions implanted in the third ion implantation process first neutralize the P-type ions in the substrate 100 corresponding to the PMOS region 102HN of the first CMOS device region. Then, the N-type ions continuously implanted in the third ion implantation process further form the third well region HNW in that region. Afterwards, the second photoresist layer 170 is removed using an etching process, such as a dry etching process.

[0053] Following step S105 above, please refer to... Figure 5 First, a third photoresist layer 180 can be formed on the substrate 100 exposed again in the low-voltage NMOS region 102LN of the first CMOS device region and the second CMOS device region using a deposition process such as chemical vapor deposition. Then, using the shielding of the third photoresist layer 180, a fourth ion implantation process is performed on the substrate 100 corresponding to the low-voltage PMOS region 102LN of the second CMOS device region in the logic region 102 exposed by the third photoresist layer 180, to form a fourth well region LNW in the substrate 100 corresponding to this region. Based on the same principle as forming the third well region HNW, the ion type implanted in the fourth ion implantation process in this embodiment of the invention is N-type, and the implantation dose, concentration, and other parameters of the N-type ions implanted in the fourth ion implantation process are related to the implantation dose, concentration, and other parameters of the P-type ions implanted in the first ion implantation process, which will not be described again here. In one embodiment, the concentration of N-type doped ions in the third well region HNW is less than the concentration of N-type doped ions in the fourth well region LNW.

[0054] Following step S105 above, please refer to... Figure 6Furthermore, using a deposition process such as chemical vapor deposition, a word line polysilicon layer 191 and a first dielectric layer 192 are conformally formed from bottom to top on the film structure corresponding to the storage region 101 and the logic region 102 of the substrate 100. In one embodiment, the word line polysilicon layer 191 is made of polysilicon, and the first dielectric layer 192 is made of an insulating material, such as silicon dioxide.

[0055] Following step S105 above, please refer to... Figure 7 First, a photoresist layer (not shown) is formed to shield the storage region 101 of the substrate 100 and part of the logic region 102. The portion of the logic region 102 exposed by the photoresist layer may be the first CMOS device region. Then, using the photoresist layer as a mask, an etching process, such as a dry etching process, is used to remove the first dielectric layer 192 and the word line polysilicon layer 191 located in the first CMOS device region that are not shielded by the photoresist layer, so as to re-expose the coupling oxide layer 110 in the first CMOS device region.

[0056] Following step S105 above, please refer to... Figure 8 Furthermore, by utilizing a deposition process such as chemical vapor deposition, a high-voltage gate oxide layer 201 and a high-voltage polysilicon layer 202 are sharedly formed on the substrate 100 of the storage region 101 and the logic region 102. The high-voltage gate oxide layer 201 is used as the gate oxide for high-voltage devices NMOS transistors and PMOS transistors, and the high-voltage polysilicon layer 202 is made of polysilicon and is used as the gate layer for high-voltage devices NMOS transistors and PMOS transistors.

[0057] Following step S105 above, please refer to... Figure 9 A fourth photoresist layer 210 can be formed on the substrate 100 using a deposition process such as chemical vapor deposition, and a portion of the high-voltage polysilicon layer 202 and a portion of the high-voltage gate oxide layer 201 can be etched away using an etching process such as dry etching to form at least one discrete gate structure on the substrate 100 of the logic region 102; and then the fourth photoresist layer 210 can be removed.

[0058] Following step S105 above, please refer to... Figure 10 A fifth photoresist layer 220 can be formed on the substrate 100 using a deposition process such as chemical vapor deposition, and a portion of the film layer in the second CMOS device region of the logic region 102 can be etched away using an etching process such as dry etching until multiple discrete gate structures are formed in the second CMOS device region; and then the fifth photoresist layer 220 is removed.

[0059] It should be understood that "common" in the embodiments of the present invention refers to the construction of a continuous structural shape by utilizing the morphological similarity and correlation between two or more shapes.

[0060] In summary, the present invention provides a method for fabricating a semiconductor memory device, comprising: providing a substrate including a first CMOS device region and a second CMOS device region with different operating voltages, wherein each CMOS device region includes a PMOS region and an NMOS region; forming a floating gate layer and a mask layer stacked sequentially from bottom to top on the substrate of the first CMOS device region and the second CMOS device region; performing a first ion implantation process on the entire substrate to form a first well region in the substrate corresponding to the NMOS region in the first CMOS device region; forming a first photoresist layer on the mask layer in the PMOS region of the first CMOS device region and the second CMOS device region; and performing a second ion implantation process on the substrate to form a second well region in the substrate corresponding to the NMOS region in the second CMOS device region.

[0061] In this invention, firstly, without setting a photoresist layer and a photomask, a first ion implantation is performed on the entire substrate. This forms a first well region within the substrate corresponding to the NMOS region in the first CMOS device region, while simultaneously performing low-dose P-type ion implantation on other areas of the substrate. Then, a first photoresist layer is formed to shield a portion of the substrate. A second ion implantation of P-type ions is performed within the substrate corresponding to the NMOS region in the second CMOS device region, and the superposition of the first ion implantation of P-type ions forms a high-ion-concentration second well region. Next, a second and third photoresist layer are used to shield a portion of the substrate, and a third and fourth ion implantation of high-dose N-type ions are performed. This neutralizes the P-type ions (the ions implanted in the first ion implantation process) in the PMOS regions of both the first and second CMOS device regions, allowing for further N-type doping of the third and fourth well regions. This reduces the number of photomask and photolithography processes required to form the first and second well regions, thereby reducing process steps, lowering the manufacturing cost of embedded flash memory chips, and improving product competitiveness.

[0062] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A method for manufacturing a semiconductor memory device, characterized by, The method comprises: providing a substrate comprising a first CMOS device region and a second CMOS device region having different working voltages, wherein each CMOS device region comprises a PMOS region and an NMOS region; forming a floating gate layer and a mask layer stacked in sequence from bottom to top on the substrate of the first CMOS device region and the second CMOS device region; performing a first ion implantation process on the entire substrate to form a first well region in the substrate corresponding to the NMOS region in the first CMOS device region; forming a first photoresist layer on the mask layer in the PMOS region of the first CMOS device region and the second CMOS device region; performing a second ion implantation process on the substrate to form a second well region in the substrate corresponding to the NMOS region in the second CMOS device region; removing the mask layer and the floating gate layer in the first CMOS device region and the second CMOS device region; after forming the second well region, further comprising: forming a second photoresist layer on the substrate re-exposed in the NMOS region of the second CMOS device region and the first CMOS device region; and performing a third ion implantation process on the substrate to form a third well region in the substrate corresponding to the PMOS region of the first CMOS device region. The first well region and the second well region have the same conductivity type of dopant ions, and the dopant ions include P-type ions.

2. The method of manufacturing a semiconductor memory device according to claim 1, wherein The concentration of the dopant ions in the first well region is less than the concentration of the dopant ions in the second well region.

3. The method of manufacturing a semiconductor memory device according to claim 1, wherein after forming the second well region, further comprising:

4. The method of producing a semiconductor memory device according to Claim 1, wherein forming a third photoresist layer on the substrate re-exposed in the NMOS region of the first CMOS device region and the second CMOS device region; and performing a fourth ion implantation process on the substrate to form a fourth well region in the substrate corresponding to the PMOS region of the second CMOS device region. The working voltage of the first CMOS device region is greater than the working voltage of the second CMOS device region.

5. The method of producing a semiconductor memory device according to any one of claims 1 to 4, wherein The third well region and the fourth well region have the same conductivity type of dopant ions, and the dopant ions include N-type ions.

6. The method of producing a semiconductor memory device according to Claim 4, wherein The concentration of the dopant ions in the third well region is less than the concentration of the dopant ions in the fourth well region.

7. The method of producing a semiconductor memory device according to Claim 4, wherein Further comprising:

8. The method of producing a semiconductor memory device according to Claim 4, wherein The substrate further comprises a storage region, and the second photoresist layer and the third photoresist layer further compressively cover the substrate of the storage region. ​

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